[AMDGPU] Qualify auto. NFC. (#110878)

Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)

[AMDGPU] Make more use of getWaveMaskRegClass. NFC. (#108186)

[CodeGen] Update a few places that were passing Register to raw_ostream::operator<< (#106877)

These would implicitly cast the register to `unsigned`. Switch most of
them to use printReg will give a

[CodeGen] Update a few places that were passing Register to raw_ostream::operator<< (#106877)

These would implicitly cast the register to `unsigned`. Switch most of
them to use printReg will give a more readable output. Change some
others to use Register::id() so we can eventually remove the implicit
cast to `unsigned`.

show more ...

AMDGPU/NewPM Port SILoadStoreOptimizer to NPM (#106362)

[AMDGPU] add missing checks in processBaseWithConstOffset (#102310)

fixes https://github.com/llvm/llvm-project/issues/102231 by inserting
missing checks.

[AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (#101619)

Use the constrained buffer load opcodes while combining under-aligned
loads for XNACK enabled subtargets.

[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)

Consider the constrained multi-dword loads while merging
individual loads to a single multi-dword load.

[AMDGPU] Promote immediate offset to atomics (#94043)

[AMDGPU] Enable constant offset promotion to immediate FLAT (#93884)

Currently it is only supported for FLAT Global.

[AMDGPU] Fix crash in the SILoadStoreOptimizer (#93862)

It does not properly handle situation when address calculation uses
V_ADDC_U32 0, 0, carry-in (i.e. with both src0 and src1 immediates).

[AMDGPU] Use some merging/unmerging helpers in SILoadStoreOptimizer (#90866)

Factor out copyToDestRegs and copyFromSrcRegs for merging store sources
and unmerging load results. NFC.

[AMDGPU] Modernize some syntax in SILoadStoreOptimizer. NFC.

Use structured bindings and similar.

[AMDGPU] Remove some pointless fallthrough annotations

[AMDPU] Add support for idxen and bothen buffer load/store merging in SILoadStoreOptimizer (#86285)

Added more buffer instruction merging support

[CodeGen] Use LocationSize for MMO getSize (#84751)

This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
const

[CodeGen] Use LocationSize for MMO getSize (#84751)

This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.

show more ...

[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)

[AMDGPU] CodeGen for GFX12 VIMAGE and VSAMPLE instructions (#75488)

[AMDGPU] CodeGen for SMEM instructions (#75579)

[AMDGPU] Add sanity check that fixes bad shift operation in AMD backend

There is a problem with the
SILoadStoreOptimizer::dmasksCanBeCombined() function that can lead to
UB.

This boolean function d

[AMDGPU] Add sanity check that fixes bad shift operation in AMD backend

There is a problem with the
SILoadStoreOptimizer::dmasksCanBeCombined() function that can lead to
UB.

This boolean function decides if two masks can be combined into 1. The
idea here is that the bits which are "on" in one mask, don't overlap
with the "on" bits of the other. Consider an example (10 bits for
simplicity):

Mask 1: 0101101000
Mask 2: 0000000110

Those can be combined into a single mask: 0101101110.

To check if such an operation is possible, the code takes the mask
which is greater and counts how many 0s there are, starting from the
LSB and stopping at the first 1. Then, it shifts 1u by this number and
compares it with the smaller mask. The problem is that when both masks
are 0, the counter will find 32 zeroes in the first mask and will try
to do a shift by 32 positions which leads to UB.

The fix is a simple sanity check, if the bigger mask is 0 or not.

https://reviews.llvm.org/D155051

show more ...

[AMDGPU] Minor refactoring in SILoadStoreOptimizer::offsetsCanBeCombined

[AMDGPU] Do not handle _SGPR SMEM instructions in SILoadStoreOptimizer

After D147334 we never select _SGPR forms of SMEM instructions on
subtargets that also support the _SGPR_IMM form, so there is

[AMDGPU] Do not handle _SGPR SMEM instructions in SILoadStoreOptimizer

After D147334 we never select _SGPR forms of SMEM instructions on
subtargets that also support the _SGPR_IMM form, so there is no need to
handle them here.

Differential Revision: https://reviews.llvm.org/D149139

show more ...

[AMDGPU] Extend tbuffer_load_format merge

Add support for merging _IDXEN and _BOTHEN variants of
TBUFFER_LOAD_FORMAT instruction.

[Target] Use *{Set,Map}::contains (NFC)

[Target] Use llvm::count{l,r}_{zero,one} (NFC)

Use llvm::popcount instead of llvm::countPopulation(NFC)