Lines Matching defs:Src0
2705 MachineOperand &Src0,
2783 // pre-gfx10 However, most test cases need literals in Src0 for VOP
2784 // FIXME: After gfx9, literal can be in place other than Src0
2830 MachineOperand &Src0 = MI.getOperand(Src0Idx);
2832 if (!isLegalToSwap(MI, Src0Idx, &Src0, Src1Idx, &Src1)) {
2836 if (Src0.isReg() && Src1.isReg()) {
2840 } else if (Src0.isReg() && !Src1.isReg()) {
2841 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2842 } else if (!Src0.isReg() && Src1.isReg()) {
2843 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2844 } else if (Src0.isImm() && Src1.isImm()) {
2845 CommutedMI = swapImmOperands(MI, Src0, Src1);
2852 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
2855 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_sel, Src1,
3556 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
3559 if (isInlineConstant(UseMI, *Src0, *ImmOp))
3572 if ((Src0->isReg() && Src0->getReg() == Reg) ||
3575 Src1->isReg() && Src1->getReg() == Reg ? Src0 : Src1;
3612 const int64_t Imm = getImmFor(RegSrc == Src1 ? *Src0 : *Src1);
3619 Src0->setReg(SrcReg);
3620 Src0->setSubReg(SrcSubReg);
3621 Src0->setIsKill(RegSrc->isKill());
3647 if (Src0->isReg()) {
3651 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
3654 MRI->hasOneUse(Src0->getReg())) {
3655 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3658 RI.isSGPRReg(*MRI, Src0->getReg())) {
3661 // VGPR is okay as Src0 - fallthrough
3670 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3992 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3993 if (!Src0->isReg() && !Src0->isImm())
3996 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
4005 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
4021 (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
4022 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
4068 .add(*Src0)
4088 .add(*Src0)
4100 if (Src0Literal || getFoldableImm(Src0, Imm, &DefMI)) {
4102 Imm = Src0->getImm();
4139 .add(*Src0)
5127 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
5130 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
5131 if (!compareMachineOp(Src0, Src1) &&
5132 !compareMachineOp(Src0, Src2)) {
5149 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
5152 if (!isRegOrFI(Src0) && !isRegOrFI(Src1) &&
5153 !isInlineConstant(Src0, Desc.operands()[Src0Idx]) &&
5155 !Src0.isIdenticalTo(Src1)) {
5218 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
5222 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
6028 MachineOperand &Src0 = MI.getOperand(Src0Idx);
6036 if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 && Src0.isReg() &&
6037 RI.isSGPRReg(MRI, Src0.getReg()))
6045 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
6048 .add(Src0);
6049 Src0.ChangeToRegister(Reg, false);
6062 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
6108 !isLegalRegOperand(MRI, InstrDesc.operands()[Src1Idx], Src0)) {
6121 Register Src0Reg = Src0.getReg();
6122 unsigned Src0SubReg = Src0.getSubReg();
6123 bool Src0Kill = Src0.isKill();
6126 Src0.ChangeToImmediate(Src1.getImm());
6128 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
6129 Src0.setSubReg(Src1.getSubReg());
6853 Register Src0 = MI.getOperand(1).getReg();
6855 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
6941 MachineOperand &Src0 = MI.getOperand(Src0Idx);
6943 .add(Src0);
6944 Src0.ChangeToRegister(Reg, false);
7407 MachineOperand &Src0 = Inst.getOperand(2);
7418 .add(Src0)
7784 MachineOperand &Src0 = Inst.getOperand(1);
7795 if (!IsSCC && Src0.isImm() && (Src0.getImm() == -1) && Src1.isImm() &&
7843 .add(Src0) // True
7849 .add(Src0) // True
7892 MachineOperand &Src0 = Inst.getOperand(1);
7897 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
7901 .add(Src0)
7911 bool Src0IsSGPR = Src0.isReg() &&
7912 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
7923 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
7930 .add(Src0)
7934 .add(Src0)
7958 MachineOperand &Src0 = Inst.getOperand(1);
7965 .add(Src0)
7987 MachineOperand &Src0 = Inst.getOperand(1);
7997 .add(Src0)
8014 MachineOperand &Src0 = Inst.getOperand(1);
8020 const TargetRegisterClass *Src0RC = Src0.isReg() ?
8021 MRI.getRegClass(Src0.getReg()) :
8027 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8038 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8079 MachineOperand &Src0 = Inst.getOperand(1);
8084 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
8098 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8102 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
8188 MachineOperand &Src0 = Inst.getOperand(1);
8193 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
8207 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8247 MachineOperand &Src0 = Inst.getOperand(1);
8254 const TargetRegisterClass *Src0RC = Src0.isReg() ?
8255 MRI.getRegClass(Src0.getReg()) :
8267 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8271 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8314 MachineOperand &Src0 = Inst.getOperand(1);
8327 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
8328 Op0 = &Src0;
8332 Op1 = &Src0;
8544 MachineOperand &Src0 = Inst.getOperand(1);
8560 .add(Src0);
8574 .add(Src0)
8582 .add(Src0);
8594 .add(Src0);