GlobalISel/MachineIRBuilder: Construct DstOp with VRegAttrs (#113581)

Allow construction of DstOp with VRegAttrs.
Also allow construction with register class or bank and LLT.
Intended to be used i

GlobalISel/MachineIRBuilder: Construct DstOp with VRegAttrs (#113581)

Allow construction of DstOp with VRegAttrs.
Also allow construction with register class or bank and LLT.
Intended to be used in lowering code for reg-bank-select where
new registers need to have both register bank and LLT.
Add support for new type of DstOp in CSEMIRBuilder.

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Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 8988148003

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 89881480030f48f83af668175b70a9798edca2fb.
This reverts commit 225d8fc8eb24fb797154c1ef6dcbe5ba033142da.

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Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AAr

Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AArch64/PowerPC: follow the IEEE754-2008's minNUM: return qNaN.
RISC-V/Hexagon follow the IEEE754-2019's minimumNumber: return NUM. X86:
Returns NUM but not same with IEEE754-2019's minimumNumber as
+0.0 is not always greater than -0.0.
MIPS/LoongArch/Generic: return NUM.
LIBCALL: returns qNaN.

So, let's introduce llvm.minmumnum/llvm.maximumnum, which always follow
IEEE754-2019's minimumNumber/maximumNumber.

Half-fix: #93033

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Merge sourcelocation in CSEMIRBuilder::getDominatingInstrForID. (#90922)

Make sure to merge the sourcelocation of the Dominating Instruction that
is hoisted in a basic block in the CSEMIRBuilder in

Merge sourcelocation in CSEMIRBuilder::getDominatingInstrForID. (#90922)

Make sure to merge the sourcelocation of the Dominating Instruction that
is hoisted in a basic block in the CSEMIRBuilder in the legalizer pass.

If this is not done, we can have a incorrect line table entry that makes
the instruction pointer jump around.

For example the line table without this patch looks like:

```
Address Line Column File ISA Discriminator OpIndex Flags
------------------ ------ ------ ------ --- ------------- ------- -------------
0x0000000000000000 0 0 1 0 0 0 is_stmt
0x0000000000000010 11 14 1 0 0 0 is_stmt prologue_end
0x0000000000000028 12 1 1 0 0 0 is_stmt
0x000000000000002c 12 15 1 0 0 0
0x000000000000004c 12 13 1 0 0 0
0x000000000000005c 13 1 1 0 0 0 is_stmt
0x0000000000000064 12 13 1 0 0 0 is_stmt
0x000000000000007c 13 7 1 0 0 0 is_stmt
0x00000000000000c8 13 1 1 0 0 0
0x00000000000000e8 13 1 1 0 0 0 epilogue_begin
0x00000000000000f8 13 1 1 0 0 0 end_sequence
```

The line table entry for 0x000000000000005c should be 0

After this patch, the line table looks like:

```
Address Line Column File ISA Discriminator OpIndex Flags
------------------ ------ ------ ------ --- ------------- ------- -------------
0x0000000000000000 0 0 1 0 0 0 is_stmt
0x0000000000000010 11 14 1 0 0 0 is_stmt prologue_end
0x0000000000000028 12 1 1 0 0 0 is_stmt
0x000000000000002c 12 15 1 0 0 0
0x000000000000004c 12 13 1 0 0 0
0x000000000000005c 0 0 1 0 0 0
0x0000000000000064 12 13 1 0 0 0
0x000000000000007c 13 7 1 0 0 0 is_stmt
0x00000000000000c8 13 1 1 0 0 0
0x00000000000000e8 13 1 1 0 0 0 epilogue_begin
0x00000000000000f8 13 1 1 0 0 0 end_sequence
```

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[GlobalISel] Fold G_ICMP if possible (#86357)

This patch tries to fold `G_ICMP` if possible.

[GlobalISel] Fold G_CTTZ if possible (#86224)

This patch tries to fold `G_CTTZ` if possible.

[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)

Recommits llvm/llvm-project#80378 which was reverted in
llvm/llvm-project#84330. The problem was that the change in
llvm

[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)

Recommits llvm/llvm-project#80378 which was reverted in
llvm/llvm-project#84330. The problem was that the change in
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir used
217 as an opcode instead of a regex.

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Revert "[GISEL] Add IRTranslation for shufflevector on scalable vector types" (#84330)

Reverts llvm/llvm-project#80378

causing Buildbot failures that did not show up with check-llvm or CI.

[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)

This patch is stacked on
https://github.com/llvm/llvm-project/pull/80372,
https://github.com/llvm/llvm-project/pull/80

[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)

This patch is stacked on
https://github.com/llvm/llvm-project/pull/80372,
https://github.com/llvm/llvm-project/pull/80307, and
https://github.com/llvm/llvm-project/pull/80306.

ShuffleVector on scalable vector types gets IRTranslate'd to
G_SPLAT_VECTOR since a ShuffleVector that has operates on scalable
vectors is a splat vector where the value of the splat vector is the 0th
element of the first operand, because the index mask operand is the
zeroinitializer (undef and poison are treated as zeroinitializer here).
This is analogous to what happens in SelectionDAG for ShuffleVector.

`buildSplatVector` is renamed to`buildBuildVectorSplatVector`. I did not
make this a separate patch because it would cause problems to revert
that change without reverting this change too.

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[CodeGen] llvm::Optional => std::optional

[GlobalISel] Change ConstantFoldVectorBinop to return vector of APInt

Previously it built MIR for the results and returned a Register.

This avoids building constants for earlier elements of the vec

[GlobalISel] Change ConstantFoldVectorBinop to return vector of APInt

Previously it built MIR for the results and returned a Register.

This avoids building constants for earlier elements of the vector if
later elements will fail to fold, and allows CSEMIRBuilder::buildInstr
to avoid unconditionally building a copy from the result.

Use a new helper function MachineIRBuilder::buildBuildVectorConstant
to build a G_BUILD_VECTOR of G_CONSTANTs.

Differential Revision: https://reviews.llvm.org/D117758

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Cleanup includes: DebugInfo & CodeGen

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332

GlobalISel: Constant fold G_PTR_ADD

Some globals lower to literal addresses on AMDGPU.

This may be wrong for non-integral address spaces. I'm wondering if we
should just allow regular G_ADD to use

GlobalISel: Constant fold G_PTR_ADD

Some globals lower to literal addresses on AMDGPU.

This may be wrong for non-integral address spaces. I'm wondering if we
should just allow regular G_ADD to use pointer types, and reserve
G_PTR_ADD for non-integral address spaces.

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GlobalISel: Constant fold FP bin ops in MIRBuilder

Might as well handle these if we're going to handle the integer ops
here.

GlobalISel: Constant fold integer min/max opcodes

GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors

This was ignoring the requested result register, resulting in a
missing def when this happened in the IRTranslator. Fixes some cra

GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors

This was ignoring the requested result register, resulting in a
missing def when this happened in the IRTranslator. Fixes some crashes
and verifier errors at -O0.

Alternatively we could pass DstOps to the constant fold functions.

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[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.

Differential Revision: https://reviews.llvm.org/D111524

[GlobalISel] Combine G_UMULH x, (1 << c)) -> x >> (bitwidth - c)

In order to not generate an unnecessary G_CTLZ, I extended the constant folder
in the CSEMIRBuilder to handle G_CTLZ. I also added so

[GlobalISel] Combine G_UMULH x, (1 << c)) -> x >> (bitwidth - c)

In order to not generate an unnecessary G_CTLZ, I extended the constant folder
in the CSEMIRBuilder to handle G_CTLZ. I also added some extra handing of
vector constants too. It seems we don't have any support for doing constant
folding of vector constants, so the tests show some other useless G_SUB
instructions too.

Differential Revision: https://reviews.llvm.org/D111036

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[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder

Differential Revision: https://reviews.llvm.org/D104528

GlobalISel: Avoid unnecessary truncation to i64

We can just directly pass through the APInt to create a new constant.

[llvm] Use llvm::all_of (NFC)

[GlobalISel] Fix CSEMIRBuilder silently allowing use-before-def.

If a CSEMIRBuilder query hits the instruction at the current insert point,
move insert point ahead one so that subsequent uses of the

[GlobalISel] Fix CSEMIRBuilder silently allowing use-before-def.

If a CSEMIRBuilder query hits the instruction at the current insert point,
move insert point ahead one so that subsequent uses of the builder don't end up with
uses before defs.

This fix also shows that AMDGPU was also affected by this bug often, but got away
with it because it was using a G_IMPLICIT_DEF before the use.

Differential Revision: https://reviews.llvm.org/D88605

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[GISel]: Fix one more CSE Non determinism

https://reviews.llvm.org/D86676

Sometimes we can have the following code

x:gpr(s32) = G_OP

Say we build G_OP2 to the same x and then delete the previous

[GISel]: Fix one more CSE Non determinism

https://reviews.llvm.org/D86676

Sometimes we can have the following code

x:gpr(s32) = G_OP

Say we build G_OP2 to the same x and then delete the previous instruction. Using something like

Register X = ...;
auto NewMIB = CSEBuilder.buildOp2(X, ... args);

Currently there's a mismatch in how NewMIB is profiled and inserted into the CSEMap (ie it doesn't consider register bank/register class along with type).Unify the profiling by refactoring and calling the common method.

This was found by turning on the CSEInfo::verify in at the end of each of our GISel passes which turns inconsistent state/non determinism in CSEing into crashes which likely usually indicates missing calls to Observer on mutations (the most common case). Here non determinism usually means not cseing sometimes, but almost never about producing incorrect code.
Also this patch adds this verification at the end of the combiners as well.

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[globalisel][cse] Merge debug locations when CSE'ing

Reviewed By: aditya_nandakumar

Differential Revision: https://reviews.llvm.org/D78388

[GISel: Add support for CSEing SrcOps which are immediates

https://reviews.llvm.org/D84072

Add G_EXTRACT to CSEConfigFull and add unit test as well.