| /llvm-project/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 249 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SwitchLoweringUtils.h | 217 MVT RegVT; global() member
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| /llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 220 EVT RegVT = VA.getLocVT(); LowerFormalArguments() local
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| /llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 523 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
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| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1409 EVT RegVT = VA.getLocVT(); LowerFormalArguments() local
1542 EVT RegVT = VA.getLocVT(); LowerCall() local
[all...] |
| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 351 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 1718 EVT RegVT = VA.getLocVT(); LowerFormalArguments() local
2162 EVT RegVT = VA.getLocVT(); LowerCall() local
[all...] |
| H A D | X86ISelLowering.cpp | 24781 MVT RegVT = Op.getSimpleValueType(); LowerLoad() local
51004 EVT RegVT = Ld->getValueType(0); combineConstantPoolLoads() local
51078 EVT RegVT = Ld->getValueType(0); combineLoad() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 1112 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); getReturnInfo() local
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| /llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 643 EVT RegVT = VA.getLocVT(); LowerCCCArguments() local
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| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 458 EVT RegVT = VA.getLocVT(); LowerCCCArguments() local
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| /llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 646 EVT RegVT = VA.getLocVT(); in LowerCall() local
947 EVT RegVT = VA.getLocVT(); LowerFormalArguments() local
[all...] |
| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1209 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 783 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
831 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
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| H A D | PPCISelLowering.cpp | 5666 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; prepareDescriptorIndirectCall() local
5718 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; buildCallOperands() local
6861 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; CC_AIX() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9653 EVT RegVT = Value.getValueType(); scalarizeVectorStore() local
9751 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); expandUnalignedLoad() local
9899 MVT RegVT = getRegisterType( expandUnalignedStore() local
[all...] |
| H A D | SelectionDAGBuilder.cpp | 9563 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); getRegistersForValue() local
9973 MVT RegVT = R->getSimpleValueType(0); visitInlineAsm() local
11588 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); LowerArguments() local
[all...] |
| H A D | LegalizeIntegerTypes.cpp | 1845 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); PromoteIntRes_VAARG() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 857 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3715 MVT RegVT = VA.getLocVT(); LowerFormalArguments() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 3127 EVT RegVT = VA.getLocVT(); IsEligibleForTailCallOptimization() local
4575 EVT RegVT = VA.getLocVT(); LowerFormalArguments() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 7253 EVT RegVT = VA.getLocVT(); LowerFormalArguments() local
[all...] |