Lines Matching defs:RegVT

25254   MVT RegVT = Op.getSimpleValueType();
25255   assert(RegVT.isVector() && "We only custom lower vector loads.");
25256   assert(RegVT.isInteger() &&
25263   if (RegVT.getVectorElementType() == MVT::i1) {
25264     assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load");
25265     assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT");
25277     Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT,
52334   EVT RegVT = Ld->getValueType(0);
52342   if (!(RegVT.is128BitVector() || RegVT.is256BitVector()))
52370             RegVT.getFixedSizeInBits()) {
52383           unsigned NumBits = std::min(RegVT.getScalarSizeInBits(),
52391                   SDValue(User, 0), 0, DAG, SDLoc(N), RegVT.getSizeInBits());
52392               Extract = DAG.getBitcast(RegVT, Extract);
52408   EVT RegVT = Ld->getValueType(0);
52418   if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
52422        (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
52425     unsigned NumElems = RegVT.getVectorNumElements();
52446     SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2);
52452   if (Ext == ISD::NON_EXTLOAD && !Subtarget.hasAVX512() && RegVT.isVector() &&
52453       RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) {
52454     unsigned NumElts = RegVT.getVectorNumElements();
52461       SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);
52469       (RegVT.is128BitVector() || RegVT.is256BitVector())) {
52480               RegVT.getFixedSizeInBits()) {
52482                                            RegVT.getSizeInBits());
52483         Extract = DAG.getBitcast(RegVT, Extract);
52500       return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,