Lines Matching defs:RegVT

183   const MVT RegVT = Subtarget.getScalarIntVT();
199 setOperationAction(ISD::UADDO, RegVT, Custom);
277 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1, RegVT);
279 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1, RegVT);
282 AddPromotedToType(ISD::SINT_TO_FP, MVT::i1, RegVT);
284 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, RegVT);
287 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1, RegVT);
289 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1, RegVT);
292 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, RegVT);
294 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1, RegVT);
5674 const MVT RegVT = Subtarget.getScalarIntVT();
5678 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5684 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5686 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5691 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5693 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5726 const MVT RegVT = Subtarget.getScalarIntVT();
5749 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5752 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5759 RegVT));
5764 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5782 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
6869 const MVT RegVT = Subtarget.getScalarIntVT();
6904 State.getStackSize(), RegVT, LocInfo));
6925 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
6948 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits())
6952 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
6954 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, RegVT, LocInfo));
6980 CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo));
7076 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo));
7078 CCValAssign::getCustomReg(ValNo, ValVT, SecondReg, RegVT, LocInfo));
7092 CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo));