MIRBuilder (definition) in projects: llvm-project

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Searched defs:MIRBuilder (Results 1 – 25 of 33) sorted by relevance

/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A D	IRTranslator.h	336 translateICmp(const User & U,MachineIRBuilder & MIRBuilder) translateICmp() argument 341 translateFCmp(const User & U,MachineIRBuilder & MIRBuilder) translateFCmp() argument 457 translateAdd(const User & U,MachineIRBuilder & MIRBuilder) translateAdd() argument 460 translateSub(const User & U,MachineIRBuilder & MIRBuilder) translateSub() argument 463 translateAnd(const User & U,MachineIRBuilder & MIRBuilder) translateAnd() argument 466 translateMul(const User & U,MachineIRBuilder & MIRBuilder) translateMul() argument 469 translateOr(const User & U,MachineIRBuilder & MIRBuilder) translateOr() argument 472 translateXor(const User & U,MachineIRBuilder & MIRBuilder) translateXor() argument 476 translateUDiv(const User & U,MachineIRBuilder & MIRBuilder) translateUDiv() argument 479 translateSDiv(const User & U,MachineIRBuilder & MIRBuilder) translateSDiv() argument 482 translateURem(const User & U,MachineIRBuilder & MIRBuilder) translateURem() argument 485 translateSRem(const User & U,MachineIRBuilder & MIRBuilder) translateSRem() argument 488 translateIntToPtr(const User & U,MachineIRBuilder & MIRBuilder) translateIntToPtr() argument 491 translatePtrToInt(const User & U,MachineIRBuilder & MIRBuilder) translatePtrToInt() argument 494 translateTrunc(const User & U,MachineIRBuilder & MIRBuilder) translateTrunc() argument 497 translateFPTrunc(const User & U,MachineIRBuilder & MIRBuilder) translateFPTrunc() argument 500 translateFPExt(const User & U,MachineIRBuilder & MIRBuilder) translateFPExt() argument 503 translateFPToUI(const User & U,MachineIRBuilder & MIRBuilder) translateFPToUI() argument 506 translateFPToSI(const User & U,MachineIRBuilder & MIRBuilder) translateFPToSI() argument 509 translateUIToFP(const User & U,MachineIRBuilder & MIRBuilder) translateUIToFP() argument 512 translateSIToFP(const User & U,MachineIRBuilder & MIRBuilder) translateSIToFP() argument 517 translateSExt(const User & U,MachineIRBuilder & MIRBuilder) translateSExt() argument 521 translateZExt(const User & U,MachineIRBuilder & MIRBuilder) translateZExt() argument 525 translateShl(const User & U,MachineIRBuilder & MIRBuilder) translateShl() argument 528 translateLShr(const User & U,MachineIRBuilder & MIRBuilder) translateLShr() argument 531 translateAShr(const User & U,MachineIRBuilder & MIRBuilder) translateAShr() argument 535 translateFAdd(const User & U,MachineIRBuilder & MIRBuilder) translateFAdd() argument 538 translateFSub(const User & U,MachineIRBuilder & MIRBuilder) translateFSub() argument 541 translateFMul(const User & U,MachineIRBuilder & MIRBuilder) translateFMul() argument 544 translateFDiv(const User & U,MachineIRBuilder & MIRBuilder) translateFDiv() argument 547 translateFRem(const User & U,MachineIRBuilder & MIRBuilder) translateFRem() argument 566 translateResume(const User & U,MachineIRBuilder & MIRBuilder) translateResume() argument 569 translateCleanupRet(const User & U,MachineIRBuilder & MIRBuilder) translateCleanupRet() argument 572 translateCatchRet(const User & U,MachineIRBuilder & MIRBuilder) translateCatchRet() argument 575 translateCatchSwitch(const User & U,MachineIRBuilder & MIRBuilder) translateCatchSwitch() argument 578 translateAddrSpaceCast(const User & U,MachineIRBuilder & MIRBuilder) translateAddrSpaceCast() argument 581 translateCleanupPad(const User & U,MachineIRBuilder & MIRBuilder) translateCleanupPad() argument 584 translateCatchPad(const User & U,MachineIRBuilder & MIRBuilder) translateCatchPad() argument 587 translateUserOp1(const User & U,MachineIRBuilder & MIRBuilder) translateUserOp1() argument 590 translateUserOp2(const User & U,MachineIRBuilder & MIRBuilder) translateUserOp2() argument [all...]
H A D	CallLowering.h	243 MachineIRBuilder &MIRBuilder; member 522 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI,Register SwiftErrorVReg) lowerReturn() argument 534 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI) lowerReturn() argument 554 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) lowerFormalArguments() argument 566 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) lowerCall() argument [all...]
/llvm-project/llvm/lib/Target/BPF/GISel/
H A D	BPFCallLowering.cpp	`26 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI,Register SwiftErrorVReg) const lowerReturn() argument 36 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 43 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument`
/llvm-project/llvm/lib/Target/SPIRV/
H A D	SPIRVGlobalRegistry.cpp	61 assignTypeToVReg(const Type * Type,Register VReg,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccessQual,bool EmitIR) assignTypeToVReg() argument 75 createTypeVReg(MachineIRBuilder & MIRBuilder) createTypeVReg() argument 88 getOpTypeBool(MachineIRBuilder & MIRBuilder) getOpTypeBool() argument 112 getOpTypeInt(unsigned Width,MachineIRBuilder & MIRBuilder,bool IsSigned) getOpTypeInt() argument 132 getOpTypeFloat(uint32_t Width,MachineIRBuilder & MIRBuilder) getOpTypeFloat() argument 139 getOpTypeVoid(MachineIRBuilder & MIRBuilder) getOpTypeVoid() argument 146 getOpTypeVector(uint32_t NumElems,SPIRVType * ElemType,MachineIRBuilder & MIRBuilder) getOpTypeVector() argument 162 getOrCreateConstIntReg(uint64_t Val,SPIRVType * SpvType,MachineIRBuilder * MIRBuilder,MachineInstr * I,const SPIRVInstrInfo * TII) getOrCreateConstIntReg() argument 193 getOrCreateConstFloatReg(APFloat Val,SPIRVType * SpvType,MachineIRBuilder * MIRBuilder,MachineInstr * I,const SPIRVInstrInfo * TII) getOrCreateConstFloatReg() argument 297 buildConstantInt(uint64_t Val,MachineIRBuilder & MIRBuilder,SPIRVType * SpvType,bool EmitIR) buildConstantInt() argument 344 buildConstantFP(APFloat Val,MachineIRBuilder & MIRBuilder,SPIRVType * SpvType) buildConstantFP() argument 503 getOrCreateIntCompositeOrNull(uint64_t Val,MachineIRBuilder & MIRBuilder,SPIRVType * SpvType,bool EmitIR,Constant * CA,unsigned BitWidth,unsigned ElemCnt) getOrCreateIntCompositeOrNull() argument 541 getOrCreateConsIntVector(uint64_t Val,MachineIRBuilder & MIRBuilder,SPIRVType * SpvType,bool EmitIR) getOrCreateConsIntVector() argument 557 getOrCreateConstNullPtr(MachineIRBuilder & MIRBuilder,SPIRVType * SpvType) getOrCreateConstNullPtr() argument 580 buildConstantSampler(Register ResReg,unsigned AddrMode,unsigned Param,unsigned FilerMode,MachineIRBuilder & MIRBuilder,SPIRVType * SpvType) buildConstantSampler() argument 606 buildGlobalVariable(Register ResVReg,SPIRVType * BaseType,StringRef Name,const GlobalValue * GV,SPIRV::StorageClass::StorageClass Storage,const MachineInstr * Init,bool IsConst,bool HasLinkageTy,SPIRV::LinkageType::LinkageType LinkageType,MachineIRBuilder & MIRBuilder,bool IsInstSelector) buildGlobalVariable() argument 706 getOpTypeArray(uint32_t NumElems,SPIRVType * ElemType,MachineIRBuilder & MIRBuilder,bool EmitIR) getOpTypeArray() argument 720 getOpTypeOpaque(const StructType * Ty,MachineIRBuilder & MIRBuilder) getOpTypeOpaque() argument 731 getOpTypeStruct(const StructType * Ty,MachineIRBuilder & MIRBuilder,bool EmitIR) getOpTypeStruct() argument 752 getOrCreateSpecialType(const Type * Ty,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccQual) getOrCreateSpecialType() argument 760 getOpTypePointer(SPIRV::StorageClass::StorageClass SC,SPIRVType * ElemType,MachineIRBuilder & MIRBuilder,Register Reg) getOpTypePointer() argument 770 getOpTypeForwardPointer(SPIRV::StorageClass::StorageClass SC,MachineIRBuilder & MIRBuilder) getOpTypeForwardPointer() argument 778 getOpTypeFunction(SPIRVType * RetType,const SmallVectorImpl<SPIRVType * > & ArgTypes,MachineIRBuilder & MIRBuilder) getOpTypeFunction() argument 790 getOrCreateOpTypeFunctionWithArgs(const Type * Ty,SPIRVType * RetType,const SmallVectorImpl<SPIRVType * > & ArgTypes,MachineIRBuilder & MIRBuilder) getOrCreateOpTypeFunctionWithArgs() argument 800 findSPIRVType(const Type * Ty,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccQual,bool EmitIR) findSPIRVType() argument 840 createSPIRVType(const Type * Ty,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccQual,bool EmitIR) createSPIRVType() argument 921 restOfCreateSPIRVType(const Type * Ty,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccessQual,bool EmitIR) restOfCreateSPIRVType() argument 963 getOrCreateSPIRVType(const Type * Ty,MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccessQual,bool EmitIR) getOrCreateSPIRVType() argument 1113 getOrCreateOpTypeImage(MachineIRBuilder & MIRBuilder,SPIRVType * SampledType,SPIRV::Dim::Dim Dim,uint32_t Depth,uint32_t Arrayed,uint32_t Multisampled,uint32_t Sampled,SPIRV::ImageFormat::ImageFormat ImageFormat,SPIRV::AccessQualifier::AccessQualifier AccessQual) getOrCreateOpTypeImage() argument 1137 getOrCreateOpTypeSampler(MachineIRBuilder & MIRBuilder) getOrCreateOpTypeSampler() argument 1147 getOrCreateOpTypePipe(MachineIRBuilder & MIRBuilder,SPIRV::AccessQualifier::AccessQualifier AccessQual) getOrCreateOpTypePipe() argument 1160 getOrCreateOpTypeDeviceEvent(MachineIRBuilder & MIRBuilder) getOrCreateOpTypeDeviceEvent() argument 1170 getOrCreateOpTypeSampledImage(SPIRVType * ImageType,MachineIRBuilder & MIRBuilder) getOrCreateOpTypeSampledImage() argument 1185 getOrCreateOpTypeCoopMatr(MachineIRBuilder & MIRBuilder,const TargetExtType * ExtensionType,const SPIRVType * ElemType,uint32_t Scope,uint32_t Rows,uint32_t Columns,uint32_t Use) getOrCreateOpTypeCoopMatr() argument 1205 getOrCreateOpTypeByOpcode(const Type * Ty,MachineIRBuilder & MIRBuilder,unsigned Opcode) getOrCreateOpTypeByOpcode() argument 1217 checkSpecialInstr(const SPIRV::SpecialTypeDescriptor & TD,MachineIRBuilder & MIRBuilder) checkSpecialInstr() argument 1226 getOrCreateSPIRVTypeByName(StringRef TypeStr,MachineIRBuilder & MIRBuilder,SPIRV::StorageClass::StorageClass SC,SPIRV::AccessQualifier::AccessQualifier AQ) getOrCreateSPIRVTypeByName() argument 1273 getOrCreateSPIRVIntegerType(unsigned BitWidth,MachineIRBuilder & MIRBuilder) getOrCreateSPIRVIntegerType() argument 1336 getOrCreateSPIRVBoolType(MachineIRBuilder & MIRBuilder) getOrCreateSPIRVBoolType() argument 1357 getOrCreateSPIRVVectorType(SPIRVType * BaseType,unsigned NumElements,MachineIRBuilder & MIRBuilder) getOrCreateSPIRVVectorType() argument 1401 getOrCreateSPIRVPointerType(SPIRVType * BaseType,MachineIRBuilder & MIRBuilder,SPIRV::StorageClass::StorageClass SC) getOrCreateSPIRVPointerType() argument 1425 MachineIRBuilder MIRBuilder(I); getOrCreateSPIRVPointerType() local [all...]
H A D	SPIRVBuiltins.cpp	384 buildBoolRegister(MachineIRBuilder & MIRBuilder,const SPIRVType * ResultType,SPIRVGlobalRegistry * GR) buildBoolRegister() argument 409 buildSelectInst(MachineIRBuilder & MIRBuilder,Register ReturnRegister,Register SourceRegister,const SPIRVType * ReturnType,SPIRVGlobalRegistry * GR) buildSelectInst() argument 431 buildLoadInst(SPIRVType * BaseType,Register PtrRegister,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR,LLT LowLevelType,Register DestinationReg=Register (0)) buildLoadInst() argument 450 buildBuiltinVariableLoad(MachineIRBuilder & MIRBuilder,SPIRVType * VariableType,SPIRVGlobalRegistry * GR,SPIRV::BuiltIn::BuiltIn BuiltinValue,LLT LLType,Register Reg=Register (0),bool isConst=true,bool hasLinkageTy=true) buildBuiltinVariableLoad() argument 520 buildConstantIntReg(uint64_t Val,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR,unsigned BitWidth=32) buildConstantIntReg() argument 529 buildScopeReg(Register CLScopeRegister,SPIRV::Scope::Scope Scope,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR,MachineRegisterInfo * MRI) buildScopeReg() argument 547 buildMemSemanticsReg(Register SemanticsRegister,Register PtrRegister,unsigned & Semantics,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildMemSemanticsReg() argument 565 buildOpFromWrapper(MachineIRBuilder & MIRBuilder,unsigned Opcode,const SPIRV::IncomingCall * Call,Register TypeReg,ArrayRef<uint32_t> ImmArgs={}) buildOpFromWrapper() argument 587 buildAtomicInitInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder) buildAtomicInitInst() argument 603 buildAtomicLoadInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildAtomicLoadInst() argument 644 buildAtomicStoreInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildAtomicStoreInst() argument 669 buildAtomicCompareExchangeInst(const SPIRV::IncomingCall * Call,const SPIRV::DemangledBuiltin * Builtin,unsigned Opcode,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildAtomicCompareExchangeInst() argument 776 buildAtomicRMWInst(const SPIRV::IncomingCall * Call,unsigned Opcode,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildAtomicRMWInst() argument 835 buildAtomicFloatingRMWInst(const SPIRV::IncomingCall * Call,unsigned Opcode,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildAtomicFloatingRMWInst() argument 867 buildAtomicFlagInst(const SPIRV::IncomingCall * Call,unsigned Opcode,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildAtomicFlagInst() argument 904 buildBarrierInst(const SPIRV::IncomingCall * Call,unsigned Opcode,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildBarrierInst() argument 1000 generateExtInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateExtInst() argument 1021 generateRelationalInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateRelationalInst() argument 1047 generateGroupInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateGroupInst() argument 1140 generateIntelSubgroupsInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateIntelSubgroupsInst() argument 1209 generateGroupUniformInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateGroupUniformInst() argument 1260 generateKernelClockInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateKernelClockInst() argument 1319 genWorkgroupQuery(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR,SPIRV::BuiltIn::BuiltIn BuiltinValue,uint64_t DefaultValue) genWorkgroupQuery() argument 1417 generateBuiltinVar(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateBuiltinVar() argument 1441 generateAtomicInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateAtomicInst() argument 1480 generateAtomicFloatingInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateAtomicFloatingInst() argument 1497 generateBarrierInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateBarrierInst() argument 1508 generateCastToPtrInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder) generateCastToPtrInst() argument 1516 generateDotOrFMulInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateDotOrFMulInst() argument 1533 generateWaveInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateWaveInst() argument 1549 generateGetQueryInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateGetQueryInst() argument 1561 generateImageSizeQueryInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateImageSizeQueryInst() argument 1636 generateImageMiscQueryInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateImageMiscQueryInst() argument 1707 generateReadImageInst(const StringRef DemangledCall,const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateReadImageInst() argument 1787 generateWriteImageInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateWriteImageInst() argument 1801 generateSampleImageInst(const StringRef DemangledCall,const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateSampleImageInst() argument 1863 generateSelectInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder) generateSelectInst() argument 1870 generateConstructInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateConstructInst() argument 1877 generateCoopMatrInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateCoopMatrInst() argument 1909 generateSpecConstantInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateSpecConstantInst() argument 1965 buildNDRange(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildNDRange() argument 2038 getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getOrCreateSPIRVDeviceEventPointer() argument 2053 buildEnqueueKernel(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) buildEnqueueKernel() argument 2138 generateEnqueueInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateEnqueueInst() argument 2185 generateAsyncCopy(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateAsyncCopy() argument 2237 generateConvertInst(const StringRef DemangledCall,const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateConvertInst() argument 2341 generateVectorLoadStoreInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateVectorLoadStoreInst() argument 2367 generateLoadStoreInst(const SPIRV::IncomingCall * Call,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) generateLoadStoreInst() argument 2478 lowerBuiltin(const StringRef DemangledCall,SPIRV::InstructionSet::InstructionSet Set,MachineIRBuilder & MIRBuilder,const Register OrigRet,const Type * OrigRetTy,const SmallVectorImpl<Register> & Args,SPIRVGlobalRegistry * GR) lowerBuiltin() argument 2670 getNonParameterizedType(const TargetExtType * ExtensionType,const SPIRV::BuiltinType * TypeRecord,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getNonParameterizedType() argument 2677 getSamplerType(MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getSamplerType() argument 2684 getPipeType(const TargetExtType * ExtensionType,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getPipeType() argument 2695 getCoopMatrType(const TargetExtType * ExtensionType,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getCoopMatrType() argument 2713 getImageType(const TargetExtType * ExtensionType,const SPIRV::AccessQualifier::AccessQualifier Qualifier,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getImageType() argument 2734 getSampledImageType(const TargetExtType * OpaqueType,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) getSampledImageType() argument 2794 lowerBuiltinType(const Type * OpaqueType,SPIRV::AccessQualifier::AccessQualifier AccessQual,MachineIRBuilder & MIRBuilder,SPIRVGlobalRegistry * GR) lowerBuiltinType() argument [all...]
H A D	SPIRVCallLowering.cpp	35 bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn() argument 191 getArgSPIRVType(const Function & F,unsigned ArgIdx,SPIRVGlobalRegistry * GR,MachineIRBuilder & MIRBuilder,const SPIRVSubtarget & ST) getArgSPIRVType() argument 279 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 488 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument [all...]
H A D	SPIRVUtils.cpp	`101 buildOpName(Register Target,const StringRef & Name,MachineIRBuilder & MIRBuilder) buildOpName() argument 117 buildOpDecorate(Register Reg,MachineIRBuilder & MIRBuilder,SPIRV::Decoration::Decoration Dec,const std::vector<uint32_t> & DecArgs,StringRef StrImm) buildOpDecorate() argument 136 buildOpSpirvDecorations(Register Reg,MachineIRBuilder & MIRBuilder,const MDNode * GVarMD) buildOpSpirvDecorations() argument [all...]`
/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A D	PPCCallLowering.h	`41 PPCIncomingValueHandler(MachineIRBuilder &MIRBuilder, in PPCIncomingValueHandler() 67 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in FormalArgHandler()`
H A D	PPCCallLowering.cpp	74 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI,Register SwiftErrorVReg) const lowerReturn() argument 109 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument 114 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 158 __anon928913910202(MachineIRBuilder &MIRBuilder, const MachinePointerInfo &MPO, LLT MemTy, const DstOp &Res, Register Addr) assignValueToAddress() argument [all...]
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A D	IRTranslator.cpp	332 MachineIRBuilder &MIRBuilder) { in translateFNeg() argument 301 translateBinaryOp(unsigned Opcode,const User & U,MachineIRBuilder & MIRBuilder) translateBinaryOp() argument 320 translateUnaryOp(unsigned Opcode,const User & U,MachineIRBuilder & MIRBuilder) translateUnaryOp() argument 337 translateCompare(const User & U,MachineIRBuilder & MIRBuilder) translateCompare() argument 361 translateRet(const User & U,MachineIRBuilder & MIRBuilder) translateRet() argument 577 translateBr(const User & U,MachineIRBuilder & MIRBuilder) translateBr() argument 1333 translateIndirectBr(const User & U,MachineIRBuilder & MIRBuilder) translateIndirectBr() argument 1362 translateLoad(const User & U,MachineIRBuilder & MIRBuilder) translateLoad() argument 1412 translateStore(const User & U,MachineIRBuilder & MIRBuilder) translateStore() argument 1475 translateExtractValue(const User & U,MachineIRBuilder & MIRBuilder) translateExtractValue() argument 1490 translateInsertValue(const User & U,MachineIRBuilder & MIRBuilder) translateInsertValue() argument 1510 translateSelect(const User & U,MachineIRBuilder & MIRBuilder) translateSelect() argument 1528 translateCopy(const User & U,const Value & V,MachineIRBuilder & MIRBuilder) translateCopy() argument 1543 translateBitCast(const User & U,MachineIRBuilder & MIRBuilder) translateBitCast() argument 1559 translateCast(unsigned Opcode,const User & U,MachineIRBuilder & MIRBuilder) translateCast() argument 1575 translateGetElementPtr(const User & U,MachineIRBuilder & MIRBuilder) translateGetElementPtr() argument 1685 translateMemFunc(const CallInst & CI,MachineIRBuilder & MIRBuilder,unsigned Opcode) translateMemFunc() argument 1776 translateTrap(const CallInst & CI,MachineIRBuilder & MIRBuilder,unsigned Opcode) translateTrap() argument 1802 translateVectorInterleave2Intrinsic(const CallInst & CI,MachineIRBuilder & MIRBuilder) translateVectorInterleave2Intrinsic() argument 1818 translateVectorDeinterleave2Intrinsic(const CallInst & CI,MachineIRBuilder & MIRBuilder) translateVectorDeinterleave2Intrinsic() argument 1837 getStackGuard(Register DstReg,MachineIRBuilder & MIRBuilder) getStackGuard() argument 1859 translateOverflowIntrinsic(const CallInst & CI,unsigned Op,MachineIRBuilder & MIRBuilder) translateOverflowIntrinsic() argument 1869 translateFixedPointIntrinsic(unsigned Op,const CallInst & CI,MachineIRBuilder & MIRBuilder) translateFixedPointIntrinsic() argument 2011 translateSimpleIntrinsic(const CallInst & CI,Intrinsic::ID ID,MachineIRBuilder & MIRBuilder) translateSimpleIntrinsic() argument 2054 translateConstrainedFPIntrinsic(const ConstrainedFPIntrinsic & FPI,MachineIRBuilder & MIRBuilder) translateConstrainedFPIntrinsic() argument 2089 translateIfEntryValueArgument(bool isDeclare,Value * Val,const DILocalVariable * Var,const DIExpression * Expr,const DebugLoc & DL,MachineIRBuilder & MIRBuilder) translateIfEntryValueArgument() argument 2131 translateConvergenceControlIntrinsic(const CallInst & CI,Intrinsic::ID ID,MachineIRBuilder & MIRBuilder) translateConvergenceControlIntrinsic() argument 2148 translateKnownIntrinsic(const CallInst & CI,Intrinsic::ID ID,MachineIRBuilder & MIRBuilder) translateKnownIntrinsic() argument 2606 translateInlineAsm(const CallBase & CB,MachineIRBuilder & MIRBuilder) translateInlineAsm() argument 2621 translateCallBase(const CallBase & CB,MachineIRBuilder & MIRBuilder) translateCallBase() argument 2688 translateCall(const User & U,MachineIRBuilder & MIRBuilder) translateCall() argument 2858 translateInvoke(const User & U,MachineIRBuilder & MIRBuilder) translateInvoke() argument 2945 translateCallBr(const User & U,MachineIRBuilder & MIRBuilder) translateCallBr() argument 2951 translateLandingPad(const User & U,MachineIRBuilder & MIRBuilder) translateLandingPad() argument 3014 translateAlloca(const User & U,MachineIRBuilder & MIRBuilder) translateAlloca() argument 3069 translateVAArg(const User & U,MachineIRBuilder & MIRBuilder) translateVAArg() argument 3080 translateUnreachable(const User & U,MachineIRBuilder & MIRBuilder) translateUnreachable() argument 3101 translateInsertElement(const User & U,MachineIRBuilder & MIRBuilder) translateInsertElement() argument 3131 translateExtractElement(const User & U,MachineIRBuilder & MIRBuilder) translateExtractElement() argument 3159 translateShuffleVector(const User & U,MachineIRBuilder & MIRBuilder) translateShuffleVector() argument 3187 translatePHI(const User & U,MachineIRBuilder & MIRBuilder) translatePHI() argument 3201 translateAtomicCmpXchg(const User & U,MachineIRBuilder & MIRBuilder) translateAtomicCmpXchg() argument 3223 translateAtomicRMW(const User & U,MachineIRBuilder & MIRBuilder) translateAtomicRMW() argument 3298 translateFence(const User & U,MachineIRBuilder & MIRBuilder) translateFence() argument 3306 translateFreeze(const User & U,MachineIRBuilder & MIRBuilder) translateFreeze() argument 3359 translateDbgValueRecord(Value * V,bool HasArgList,const DILocalVariable * Variable,const DIExpression * Expression,const DebugLoc & DL,MachineIRBuilder & MIRBuilder) translateDbgValueRecord() argument 3406 translateDbgDeclareRecord(Value * Address,bool HasArgList,const DILocalVariable * Variable,const DIExpression * Expression,const DebugLoc & DL,MachineIRBuilder & MIRBuilder) translateDbgDeclareRecord() argument 3437 translateDbgInfo(const Instruction & Inst,MachineIRBuilder & MIRBuilder) translateDbgInfo() argument [all...]
H A D	InlineAsmLowering.cpp	`81 MachineIRBuilder &MIRBuilder, in getRegistersForValue() 183 MachineIRBuilder &MIRBuilder) { in buildAnyextOrCopy() 216 MachineIRBuilder &MIRBuilder, const CallBase &Call, in lowerInlineAsm()`
H A D	Legalizer.cpp	`180 legalizeMachineFunction(MachineFunction & MF,const LegalizerInfo & LI,ArrayRef<GISelChangeObserver * > AuxObservers,LostDebugLocObserver & LocObserver,MachineIRBuilder & MIRBuilder,GISelKnownBits * KB) legalizeMachineFunction() argument 322 std::unique_ptr<MachineIRBuilder> MIRBuilder; runOnMachineFunction() local [all...]`
H A D	CallLowering.cpp	94 lowerCall(MachineIRBuilder & MIRBuilder,const CallBase & CB,ArrayRef<Register> ResRegs,ArrayRef<ArrayRef<Register>> ArgRegs,Register SwiftErrorVReg,std::optional<PtrAuthInfo> PAI,Register ConvergenceCtrlToken,std::function<unsigned ()> GetCalleeReg) const lowerCall() argument 643 determineAndHandleAssignments(ValueHandler & Handler,ValueAssigner & Assigner,SmallVectorImpl<ArgInfo> & Args,MachineIRBuilder & MIRBuilder,CallingConv::ID CallConv,bool IsVarArg,ArrayRef<Register> ThisReturnRegs) const determineAndHandleAssignments() argument 731 handleAssignments(ValueHandler & Handler,SmallVectorImpl<ArgInfo> & Args,CCState & CCInfo,SmallVectorImpl<CCValAssign> & ArgLocs,MachineIRBuilder & MIRBuilder,ArrayRef<Register> ThisReturnRegs) const handleAssignments() argument 982 insertSRetLoads(MachineIRBuilder & MIRBuilder,Type * RetTy,ArrayRef<Register> VRegs,Register DemoteReg,int FI) const insertSRetLoads() argument 1013 insertSRetStores(MachineIRBuilder & MIRBuilder,Type * RetTy,ArrayRef<Register> VRegs,Register DemoteReg) const insertSRetStores() argument 1065 insertSRetOutgoingArgument(MachineIRBuilder & MIRBuilder,const CallBase & CB,CallLoweringInfo & Info) const insertSRetOutgoingArgument() argument [all...]
/llvm-project/llvm/lib/Target/Mips/
H A D	MipsLegalizerInfo.cpp	`338 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; in legalizeCustom() local 470 MachineIRBuilder &MIRBuilder, in SelectMSA3OpIntrinsic() 485 MachineIRBuilder &MIRBuilder, in MSA3OpIntrinsicToGeneric() 497 MachineIRBuilder &MIRBuilder, in MSA2OpIntrinsicToGeneric() 509 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; in legalizeIntrinsic() local`
H A D	MipsCallLowering.cpp	89 MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder, in MipsIncomingValueHandler() 117 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler() 196 MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder, in MipsOutgoingValueHandler() 315 bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn() 358 bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, in lowerFormalArguments() 445 bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()
/llvm-project/llvm/lib/Target/ARM/
H A D	ARMCallLowering.cpp	183 lowerReturnVal(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,MachineInstrBuilder & Ret) const lowerReturnVal() argument 214 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI) const lowerReturn() argument 365 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 456 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument [all...]
H A D	ARMLegalizerInfo.cpp	`341 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeCustom() local [all...]`
/llvm-project/llvm/lib/Target/RISCV/GISel/
H A D	RISCVCallLowering.cpp	391 lowerReturnVal(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,MachineInstrBuilder & Ret) const lowerReturnVal() argument 424 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI) const lowerReturn() argument 440 saveVarArgRegisters(MachineIRBuilder & MIRBuilder,CallLowering::IncomingValueHandler & Handler,IncomingValueAssigner & Assigner,CCState & CCInfo) const saveVarArgRegisters() argument 505 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 563 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument [all...]
H A D	RISCVLegalizerInfo.cpp	`485 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeIntrinsic() local 512 legalizeShlAshrLshr(MachineInstr & MI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer) const legalizeShlAshrLshr() argument 769 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeCustom() local [all...]`
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A D	AArch64LegalizerInfo.cpp	1264 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeCustom() local 1318 legalizeFunnelShift(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer,LegalizerHelper & Helper) const legalizeFunnelShift() argument 1417 legalizeSmallCMGlobalValue(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer) const legalizeSmallCMGlobalValue() argument 1656 legalizeShlAshrLshr(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer) const legalizeShlAshrLshr() argument 1695 legalizeLoadStore(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIRBuilder,GISelChangeObserver & Observer) const legalizeLoadStore() argument 1865 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeCTPOP() local 1980 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeAtomicCmpxchg128() local 2077 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeCTTZ() local 2088 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeMemOps() local 2118 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; legalizeDynStackAlloc() local [all...]
H A D	AArch64CallLowering.cpp	355 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI,Register SwiftErrorVReg) const lowerReturn() argument 487 handleMustTailForwardedRegisters(MachineIRBuilder & MIRBuilder,CCAssignFn * AssignFn) handleMustTailForwardedRegisters() argument 550 saveVarArgRegisters(MachineIRBuilder & MIRBuilder,CallLowering::IncomingValueHandler & Handler,CCState & CCInfo) const saveVarArgRegisters() argument 637 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 917 isEligibleForTailCallOptimization(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info,SmallVectorImpl<ArgInfo> & InArgs,SmallVectorImpl<ArgInfo> & OutArgs) const isEligibleForTailCallOptimization() argument 1078 lowerTailCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info,SmallVectorImpl<ArgInfo> & OutArgs) const lowerTailCall() argument 1255 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument [all...]
H A D	AArch64GlobalISelUtils.cpp	`64 tryEmitBZero(MachineInstr & MI,MachineIRBuilder & MIRBuilder,bool MinSize) tryEmitBZero() argument`
/llvm-project/llvm/lib/Target/M68k/GISel/
H A D	M68kCallLowering.cpp	`93 bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn() 122 bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, in lowerFormalArguments() 189 bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall()`
/llvm-project/llvm/lib/Target/X86/GISel/
H A D	X86CallLowering.cpp	`144 lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI) const lowerReturn() argument 260 lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const lowerFormalArguments() argument 319 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument [all...]`
/llvm-project/llvm/lib/Target/AMDGPU/
H A D	AMDGPUCallLowering.cpp	750 passSpecialInputs(MachineIRBuilder & MIRBuilder,CCState & CCInfo,SmallVectorImpl<std::pair<MCRegister,Register>> & ArgRegs,CallLoweringInfo & Info) const passSpecialInputs() argument 977 addCallTargetOperands(MachineInstrBuilder & CallInst,MachineIRBuilder & MIRBuilder,AMDGPUCallLowering::CallLoweringInfo & Info) addCallTargetOperands() argument 1156 handleImplicitCallArguments(MachineIRBuilder & MIRBuilder,MachineInstrBuilder & CallInst,const GCNSubtarget & ST,const SIMachineFunctionInfo & FuncInfo,CallingConv::ID CalleeCC,ArrayRef<std::pair<MCRegister,Register>> ImplicitArgRegs) const handleImplicitCallArguments() argument 1181 lowerTailCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info,SmallVectorImpl<ArgInfo> & OutArgs) const lowerTailCall() argument 1343 lowerChainCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerChainCall() argument 1389 lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const lowerCall() argument [all...]