Lines Matching defs:MIRBuilder
38 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
80 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0);
82 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0);
85 auto ToSGPR = MIRBuilder
92 MIRBuilder.buildCopy(PhysReg, ExtReg);
106 auto &MFI = MIRBuilder.getMF().getFrameInfo();
112 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
113 auto AddrReg = MIRBuilder.buildFrameIndex(
126 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
132 MIRBuilder.buildTrunc(ValVReg, Extended);
142 MachineFunction &MF = MIRBuilder.getMF();
147 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
161 MIRBuilder.getMBB().addLiveIn(PhysReg);
166 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
168 : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
187 AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,
190 : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff),
196 MachineFunction &MF = MIRBuilder.getMF();
203 auto FIReg = MIRBuilder.buildFrameIndex(PtrTy, FI);
211 const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>();
214 SPReg = MIRBuilder.buildCopy(PtrTy,
220 SPReg = MIRBuilder.buildInstr(AMDGPU::G_AMDGPU_WAVE_ADDRESS, {PtrTy},
225 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
227 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
235 MachineFunction &MF = MIRBuilder.getMF();
242 MIRBuilder.buildStore(ValVReg, Addr, *MMO);
746 bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
750 MachineFunction &MF = MIRBuilder.getMF();
819 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
821 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);
826 MIRBuilder.buildConstant(InputReg, *Id);
828 MIRBuilder.buildUndef(InputReg);
833 MIRBuilder.buildUndef(InputReg);
886 LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
889 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0);
896 LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
899 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
900 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
906 LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
909 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
910 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
921 MIRBuilder.buildUndef(InputReg);
928 LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
973 MachineIRBuilder &MIRBuilder,
982 auto Ptr = MIRBuilder.buildGlobalValue(
1155 MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst,
1162 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32),
1169 MIRBuilder.buildCopy(CalleeRSrcReg, ScratchRSrcReg);
1174 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);
1180 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1182 MachineFunction &MF = MIRBuilder.getMF();
1200 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
1204 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1205 if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1289 if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1299 AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff);
1300 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1306 handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, CalleeCC,
1318 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
1322 MIRBuilder.insertInstr(MIB);
1342 bool AMDGPUCallLowering::lowerChainCall(MachineIRBuilder &MIRBuilder,
1353 MachineFunction &MF = MIRBuilder.getMF();
1385 return lowerTailCall(MIRBuilder, Info, OutArgs);
1388 bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
1394 return lowerChainCall(MIRBuilder, Info);
1402 MachineFunction &MF = MIRBuilder.getMF();
1421 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1431 return lowerTailCall(MIRBuilder, Info, OutArgs);
1439 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)
1448 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1454 if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1471 if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1482 AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false);
1483 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1491 handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, Info.CallConv,
1511 MIRBuilder.insertInstr(MIB);
1520 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1521 if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
1528 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
1533 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,