Lines Matching defs:MIRBuilder
310 MachineIRBuilder &MIRBuilder) {
327 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
332 MachineIRBuilder &MIRBuilder) {
343 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags);
347 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
348 return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder);
352 MachineIRBuilder &MIRBuilder) {
363 MIRBuilder.buildICmp(Pred, Res, Op0, Op1, Flags);
365 MIRBuilder.buildCopy(
368 MIRBuilder.buildCopy(
371 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags);
376 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
389 &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
395 return CLI->lowerReturn(MIRBuilder, Ret, VRegs, FuncInfo, SwiftErrorVReg);
592 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
594 auto &CurMBB = MIRBuilder.getMBB();
601 MIRBuilder.buildBr(*Succ0MBB);
1348 MachineIRBuilder &MIRBuilder) {
1352 MIRBuilder.buildBrIndirect(Tgt);
1356 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
1377 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
1395 SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(), Ptr);
1396 MIRBuilder.buildCopy(Regs[0], VReg);
1413 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
1421 MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
1427 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
1442 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
1444 MIRBuilder.buildCopy(VReg, Vals[0]);
1452 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
1460 MIRBuilder.buildStore(Vals[i], Addr, *MMO);
1490 MachineIRBuilder &MIRBuilder) {
1505 MachineIRBuilder &MIRBuilder) {
1525 MachineIRBuilder &MIRBuilder) {
1536 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags);
1543 MachineIRBuilder &MIRBuilder) {
1552 MIRBuilder.buildCopy(Regs[0], Src);
1558 MachineIRBuilder &MIRBuilder) {
1566 MIRBuilder);
1567 return translateCopy(U, *U.getOperand(0), MIRBuilder);
1570 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
1574 MachineIRBuilder &MIRBuilder) {
1584 MIRBuilder.buildInstr(Opcode, {Res}, {Op}, Flags);
1589 MachineIRBuilder &MIRBuilder) {
1617 BaseReg = MIRBuilder
1648 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1649 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0))
1658 IdxReg = MIRBuilder
1664 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
1671 auto ElementSizeMIB = MIRBuilder.buildConstant(
1674 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0);
1678 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
1684 MIRBuilder.buildConstant(OffsetTy, Offset);
1689 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0),
1694 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
1699 MachineIRBuilder &MIRBuilder,
1722 SizeOpReg = MIRBuilder.buildZExtOrTrunc(SizeTy, SizeOpReg).getReg(0);
1724 auto ICall = MIRBuilder.buildInstr(Opcode);
1790 MachineIRBuilder &MIRBuilder,
1797 MIRBuilder.buildInstr(Opcode, {}, ArrayRef<llvm::SrcOp>{Code});
1799 MIRBuilder.buildInstr(Opcode);
1812 return CLI->lowerCall(MIRBuilder, Info);
1816 const CallInst &CI, MachineIRBuilder &MIRBuilder) {
1825 MIRBuilder.buildShuffleVector(Res, Op0, Op1,
1832 const CallInst &CI, MachineIRBuilder &MIRBuilder) {
1838 auto Undef = MIRBuilder.buildUndef(MRI->getType(Op));
1842 MIRBuilder.buildShuffleVector(Res[0], Op, Undef,
1844 MIRBuilder.buildShuffleVector(Res[1], Op, Undef,
1851 MachineIRBuilder &MIRBuilder) {
1855 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
1873 MachineIRBuilder &MIRBuilder) {
1875 MIRBuilder.buildInstr(
1883 MachineIRBuilder &MIRBuilder) {
1888 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale });
2029 MachineIRBuilder &MIRBuilder) {
2042 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
2072 const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) {
2087 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);
2107 MachineIRBuilder &MIRBuilder) {
2129 MIRBuilder.buildDirectDbgValue(*PhysReg, Var, Expr);
2149 const CallInst &CI, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder) {
2150 MachineInstrBuilder MIB = MIRBuilder.buildInstr(getConvOpcode(ID));
2166 MachineIRBuilder &MIRBuilder) {
2178 if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
2209 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));
2218 MIRBuilder.buildInstr(TargetOpcode::FAKE_USE, {}, VRegs);
2226 DI.getExpression(), DI.getDebugLoc(), MIRBuilder);
2234 MIRBuilder.getDebugLoc()) &&
2237 MIRBuilder.buildDbgLabel(DI.getLabel());
2249 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)})
2266 DI.getExpression(), DI.getDebugLoc(), MIRBuilder);
2270 return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
2272 return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
2274 return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
2276 return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
2278 return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
2280 return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
2282 return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);
2284 return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);
2286 return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
2288 return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
2290 return translateBinaryOp(TargetOpcode::G_USHLSAT, CI, MIRBuilder);
2292 return translateBinaryOp(TargetOpcode::G_SSHLSAT, CI, MIRBuilder);
2294 return translateBinaryOp(TargetOpcode::G_UMIN, CI, MIRBuilder);
2296 return translateBinaryOp(TargetOpcode::G_UMAX, CI, MIRBuilder);
2298 return translateBinaryOp(TargetOpcode::G_SMIN, CI, MIRBuilder);
2300 return translateBinaryOp(TargetOpcode::G_SMAX, CI, MIRBuilder);
2303 return translateUnaryOp(TargetOpcode::G_ABS, CI, MIRBuilder);
2305 return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIX, CI, MIRBuilder);
2307 return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIX, CI, MIRBuilder);
2309 return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIXSAT, CI, MIRBuilder);
2311 return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIXSAT, CI, MIRBuilder);
2313 return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIX, CI, MIRBuilder);
2315 return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIX, CI, MIRBuilder);
2317 return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIXSAT, CI, MIRBuilder);
2319 return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder);
2331 MIRBuilder.buildFMA(Dst, Op0, Op1, Op2,
2335 auto FMul = MIRBuilder.buildFMul(
2337 MIRBuilder.buildFAdd(Dst, FMul, Op2,
2344 MIRBuilder.buildFPExt(getOrCreateVReg(CI),
2350 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI),
2356 MIRBuilder.buildFFrexp(VRegs[0], VRegs[1],
2363 MIRBuilder.buildFSincos(VRegs[0], VRegs[1],
2369 MIRBuilder.buildFPTOSI_SAT(getOrCreateVReg(CI),
2373 MIRBuilder.buildFPTOUI_SAT(getOrCreateVReg(CI),
2377 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY_INLINE);
2379 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY);
2381 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMMOVE);
2383 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMSET);
2388 MIRBuilder.buildConstant(Reg, TypeID);
2398 getStackGuard(getOrCreateVReg(CI), MIRBuilder);
2405 getStackGuard(GuardVal, MIRBuilder);
2413 MIRBuilder.buildStore(
2422 MIRBuilder.buildInstr(TargetOpcode::G_STACKSAVE, {getOrCreateVReg(CI)}, {});
2426 MIRBuilder.buildInstr(TargetOpcode::G_STACKRESTORE, {},
2439 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},
2446 MIRBuilder.buildUndef(Undef);
2458 MIRBuilder.buildCopy(getOrCreateVReg(CI),
2471 MIRBuilder
2478 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)
2500 MIRBuilder.buildInstrNoInsert(TargetOpcode::LOCAL_ESCAPE)
2522 MIRBuilder.buildInstr(Opc, {Dst}, {ScalarSrc, VecSrc},
2537 auto Rdx = MIRBuilder.buildInstr(
2539 MIRBuilder.buildInstr(ScalarOpc, {Dst}, {ScalarSrc, Rdx},
2545 return translateTrap(CI, MIRBuilder, TargetOpcode::G_TRAP);
2547 return translateTrap(CI, MIRBuilder, TargetOpcode::G_DEBUGTRAP);
2549 return translateTrap(CI, MIRBuilder, TargetOpcode::G_UBSANTRAP);
2552 MIRBuilder.buildCopy(getOrCreateVReg(CI),
2556 return translateCallBase(CI, MIRBuilder);
2566 MIRBuilder
2578 MIRBuilder
2587 MIRBuilder.buildSetFPEnv(getOrCreateVReg(*FPEnv));
2591 MIRBuilder.buildResetFPEnv();
2595 MIRBuilder.buildSetFPMode(getOrCreateVReg(*FPState));
2599 MIRBuilder.buildResetFPMode();
2602 MIRBuilder.buildVScale(getOrCreateVReg(CI), 1);
2606 MIRBuilder.buildSCmp(getOrCreateVReg(CI),
2611 MIRBuilder.buildUCmp(getOrCreateVReg(CI),
2616 return translateExtractVector(CI, MIRBuilder);
2618 return translateInsertVector(CI, MIRBuilder);
2620 MIRBuilder.buildStepVector(getOrCreateVReg(CI), 1);
2633 MIRBuilder.buildPrefetch(getOrCreateVReg(*Addr), RW, Locality, CacheType,
2643 LLT ResTy = getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout());
2648 return translateVectorInterleave2Intrinsic(CI, MIRBuilder);
2650 return translateVectorDeinterleave2Intrinsic(CI, MIRBuilder);
2657 MIRBuilder);
2661 return translateConvergenceControlIntrinsic(CI, ID, MIRBuilder);
2667 MachineIRBuilder &MIRBuilder) {
2680 MIRBuilder, CB, [&](const Value &Val) { return getOrCreateVRegs(Val); });
2684 MachineIRBuilder &MIRBuilder) {
2695 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
2696 &CB, &MIRBuilder.getMBB(), Arg));
2699 SwiftError.getOrCreateVRegDefAt(&CB, &MIRBuilder.getMBB(), Arg);
2745 MIRBuilder, CB, Res, Args, SwiftErrorVReg, PAI, ConvergenceCtrlToken,
2752 HasTailCall = TII->isTailCall(*std::prev(MIRBuilder.getInsertPt()));
2758 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
2782 return translateInlineAsm(CI, MIRBuilder);
2794 return translateCallBase(CI, MIRBuilder);
2798 if (translateKnownIntrinsic(CI, ID, MIRBuilder))
2807 MachineInstrBuilder MIB = MIRBuilder.buildIntrinsic(ID, ResultRegs);
2931 MachineIRBuilder &MIRBuilder) {
2970 MIRBuilder.buildInstr(TargetOpcode::G_INVOKE_REGION_START);
2972 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
2976 if (!translateInlineAsm(I, MIRBuilder))
2978 } else if (!translateCallBase(I, MIRBuilder))
2984 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
2989 MachineBasicBlock *InvokeMBB = &MIRBuilder.getMBB();
3013 MIRBuilder.buildBr(ReturnMBB);
3018 MachineIRBuilder &MIRBuilder) {
3024 MachineIRBuilder &MIRBuilder) {
3027 MachineBasicBlock &MBB = MIRBuilder.getMBB();
3047 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
3058 MIRBuilder.buildUndef(Undef);
3072 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
3080 MIRBuilder.buildCopy(PtrVReg, SelectorReg);
3081 MIRBuilder.buildCast(ResRegs[1], PtrVReg);
3087 MachineIRBuilder &MIRBuilder) {
3096 MIRBuilder.buildFrameIndex(Res, FI);
3110 MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
3119 MIRBuilder.buildMul(AllocSize, NumElts, TySize);
3125 auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign.value() - 1);
3126 auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne,
3129 MIRBuilder.buildConstant(IntPtrTy, ~(uint64_t)(StackAlign.value() - 1));
3130 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst);
3135 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment);
3142 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
3147 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},
3153 bool IRTranslator::translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
3169 MIRBuilder.buildTrap();
3174 MachineIRBuilder &MIRBuilder) {
3179 return translateCopy(U, *U.getOperand(1), MIRBuilder);
3197 Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
3199 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
3204 MachineIRBuilder &MIRBuilder) {
3226 return translateCopy(U, *U.getOperand(0), MIRBuilder);
3233 MIRBuilder.buildInsertVectorElement(Dst, Vec, Elt, Idx);
3241 auto ScaledIndex = MIRBuilder.buildMul(
3242 VecIdxTy, MIRBuilder.buildVScale(VecIdxTy, 1), Idx);
3243 MIRBuilder.buildInsertVectorElement(Dst, Vec, Elt, ScaledIndex);
3248 MIRBuilder.buildInsertSubvector(
3255 MachineIRBuilder &MIRBuilder) {
3261 return translateCopy(U, *U.getOperand(0), MIRBuilder);
3278 Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
3280 MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
3285 MachineIRBuilder &MIRBuilder) {
3304 return translateCopy(U, *U.getOperand(0), MIRBuilder);
3311 MIRBuilder.buildExtractVectorElement(Res, Vec, Idx);
3319 auto ScaledIndex = MIRBuilder.buildMul(
3320 VecIdxTy, MIRBuilder.buildVScale(VecIdxTy, 1), Idx);
3321 MIRBuilder.buildExtractVectorElement(Res, Vec, ScaledIndex);
3326 MIRBuilder.buildExtractSubvector(getOrCreateVReg(U),
3333 MachineIRBuilder &MIRBuilder) {
3340 auto SplatVal = MIRBuilder.buildExtractVectorElementConstant(
3342 MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal);
3352 MIRBuilder
3360 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
3365 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
3374 MachineIRBuilder &MIRBuilder) {
3386 MIRBuilder.buildAtomicCmpXchgWithSuccess(
3396 MachineIRBuilder &MIRBuilder) {
3470 MIRBuilder.buildAtomicRMW(
3480 MachineIRBuilder &MIRBuilder) {
3482 MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
3488 MachineIRBuilder &MIRBuilder) {
3496 MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]);
3541 MachineIRBuilder &MIRBuilder) {
3545 MIRBuilder.setDebugLoc(DL);
3550 MIRBuilder.buildIndirectDbgValue(0, Variable, Expression);
3555 MIRBuilder.buildConstDbgValue(*CI, Variable, Expression);
3567 MIRBuilder.buildFIDbgValue(getOrCreateFrameIndex(*AI), Variable,
3572 MIRBuilder))
3579 MIRBuilder.buildDirectDbgValue(Reg, Variable, Expression);
3587 MachineIRBuilder &MIRBuilder) {
3606 MIRBuilder))
3611 MIRBuilder.setDebugLoc(DL);
3612 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
3618 MachineIRBuilder &MIRBuilder) {
3621 MIRBuilder.setDebugLoc(DLR->getDebugLoc());
3624 MIRBuilder.getDebugLoc()) &&
3626 MIRBuilder.buildDbgLabel(DLR->getLabel());
3635 DVR.getDebugLoc(), MIRBuilder);
3638 DVR.getDebugLoc(), MIRBuilder);
3898 if (!CLI->lowerCall(MIRBuilder, Info)) {