Lines Matching defs:MIRBuilder
139 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
140 : IncomingValueHandler(MIRBuilder, MRI) {}
145 auto &MFI = MIRBuilder.getMF().getFrameInfo();
152 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
153 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
175 MachineFunction &MF = MIRBuilder.getMF();
196 MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, ValVReg, Addr, *MMO);
199 MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, ValVReg, Addr, *MMO);
202 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
214 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
215 : IncomingArgHandler(MIRBuilder, MRI) {}
218 MIRBuilder.getMRI()->addLiveIn(Reg.asMCReg());
219 MIRBuilder.getMBB().addLiveIn(Reg.asMCReg());
224 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
226 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
237 ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
240 : CallReturnHandler(MIRBuilder, MRI, MIB) {}
246 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
249 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall),
251 Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
256 MachineFunction &MF = MIRBuilder.getMF();
265 auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
271 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
273 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
275 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
296 MIRBuilder.buildCopy(PhysReg, ExtReg);
302 MachineFunction &MF = MIRBuilder.getMF();
305 MIRBuilder.buildStore(ValVReg, Addr, *MMO);
357 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
362 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
368 insertSRetStores(MIRBuilder, Val->getType(), VRegs, FLI.DemoteRegister);
370 MachineFunction &MF = MIRBuilder.getMF();
398 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
419 MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
423 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
432 MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
444 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
460 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
462 MIRBuilder, CC, F.isVarArg());
467 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
470 MIRBuilder.insertInstr(MIB);
489 static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder,
491 MachineBasicBlock &MBB = MIRBuilder.getMBB();
492 MachineFunction &MF = MIRBuilder.getMF();
525 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
552 MachineIRBuilder &MIRBuilder, CallLowering::IncomingValueHandler &Handler,
557 MachineFunction &MF = MIRBuilder.getMF();
584 auto FIN = MIRBuilder.buildFrameIndex(p0, GPRIdx);
586 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 8);
597 MIRBuilder.buildStore(Val, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
599 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
614 auto FIN = MIRBuilder.buildFrameIndex(p0, FPRIdx);
616 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 16);
627 MIRBuilder.buildStore(Val, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
629 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
639 MachineIRBuilder &MIRBuilder, const Function &F,
641 MachineFunction &MF = MIRBuilder.getMF();
642 MachineBasicBlock &MBB = MIRBuilder.getMBB();
703 MIRBuilder.setInstr(*MBB.begin());
709 FormalArgHandler Handler(MIRBuilder, MRI);
713 !handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, MIRBuilder))
723 MIRBuilder.buildTrunc(
724 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0));
737 saveVarArgRegisters(MIRBuilder, Handler, CCInfo);
745 auto &MFI = MIRBuilder.getMF().getFrameInfo();
772 handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
775 MIRBuilder.setMBB(MBB);
921 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
930 MachineFunction &MF = MIRBuilder.getMF();
1082 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1084 MachineFunction &MF = MIRBuilder.getMF();
1103 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1106 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1203 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB,
1205 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1227 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
1241 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0);
1245 MIRBuilder.insertInstr(MIB);
1259 bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
1261 MachineFunction &MF = MIRBuilder.getMF();
1295 MIRBuilder.buildZExt(LLT::scalar(8), OutArg.Regs[0]).getReg(0);
1307 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1320 return lowerTailCall(MIRBuilder, Info, OutArgs);
1329 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1350 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_GLOBAL_VALUE);
1358 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1380 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, /*IsReturn*/ false);
1381 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1417 MIRBuilder.insertInstr(MIB);
1426 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1443 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1449 ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB);
1452 MIRBuilder, Info.CallConv, Info.IsVarArg,
1460 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1464 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,