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Searched defs:LIS (Results 1 – 25 of 70) sorted by relevance

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/llvm-project/llvm/unittests/MI/
H A DLiveIntervalTest.cpp135 testHandleMove(MachineFunction & MF,LiveIntervals & LIS,unsigned From,unsigned To,unsigned BlockNum=0) testHandleMove() argument
150 testHandleMoveIntoNewBundle(MachineFunction & MF,LiveIntervals & LIS,unsigned From,unsigned To,unsigned BlockNum=0) testHandleMoveIntoNewBundle() argument
171 testSplitAt(MachineFunction & MF,LiveIntervals & LIS,unsigned SplitAt,unsigned BlockNum) testSplitAt() argument
184 checkRegUnitInterference(LiveIntervals & LIS,const TargetRegisterInfo & TRI,const LiveInterval & VirtReg,MCRegister PhysReg) checkRegUnitInterference() argument
266 __anon6e8c89990202(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
277 __anon6e8c89990302(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
288 __anon6e8c89990402(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
299 __anon6e8c89990502(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
309 __anon6e8c89990602(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
320 __anon6e8c89990702(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
335 __anon6e8c89990802(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
346 __anon6e8c89990902(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
357 __anon6e8c89990a02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
368 __anon6e8c89990b02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
378 __anon6e8c89990c02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
389 __anon6e8c89990d02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
400 __anon6e8c89990e02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
422 __anon6e8c89990f02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
434 __anon6e8c89991002(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
446 __anon6e8c89991102(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
468 __anon6e8c89991202(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
489 __anon6e8c89991302(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
514 __anon6e8c89991402(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
529 __anon6e8c89991502(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
546 __anon6e8c89991602(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
567 __anon6e8c89991702(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
587 __anon6e8c89991802(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
602 __anon6e8c89991902(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
614 __anon6e8c89991a02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
625 __anon6e8c89991b02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
636 __anon6e8c89991c02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
647 __anon6e8c89991d02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
658 __anon6e8c89991e02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
675 __anon6e8c89991f02(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
692 __anon6e8c89992002(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
704 __anon6e8c89992102(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
720 __anon6e8c89992202(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
731 __anon6e8c89992302(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
768 __anon6e8c89992402(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
793 __anon6e8c89992502(MachineFunction &MF, LiveIntervals &LIS) TEST() argument
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/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h175 LiveIntervals &LIS; variable
266 LiveIntervals &LIS, InstrChangesTy InstrChanges) in ModuloScheduleExpander() argument
286 LiveIntervals *LIS) in PeelingModuloScheduleExpander() argument
302 LiveIntervals *LIS = nullptr; variable
386 LiveIntervals &LIS; variable
437 LiveIntervals &LIS) in ModuloScheduleExpanderMVE() argument
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H A DCalcSpillWeights.h47 LiveIntervals &LIS; global() variable
57 VirtRegAuxInfo(MachineFunction & MF,LiveIntervals & LIS,const VirtRegMap & VRM,const MachineLoopInfo & Loops,const MachineBlockFrequencyInfo & MBFI) VirtRegAuxInfo() argument
H A DLiveRegMatrix.h42 LiveIntervals *LIS = nullptr; global() variable
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMemIntrinsicResults.cpp88 LiveIntervals &LIS) { in replaceDominatedUses() argument
150 MachineDominatorTree &MDT, LiveIntervals &LIS, in optimizeCall() argument
188 auto &LIS in runOnMachineFunction() local
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H A DWebAssemblyRegStackify.cpp102 convertImplicitDefToConstZero(MachineInstr * MI,MachineRegisterInfo & MRI,const TargetInstrInfo * TII,MachineFunction & MF,LiveIntervals & LIS) convertImplicitDefToConstZero() argument
267 getVRegDef(unsigned Reg,const MachineInstr * Insert,const MachineRegisterInfo & MRI,const LiveIntervals & LIS) getVRegDef() argument
285 hasOneNonDBGUse(unsigned Reg,MachineInstr * Def,MachineRegisterInfo & MRI,MachineDominatorTree & MDT,LiveIntervals & LIS) hasOneNonDBGUse() argument
439 oneUseDominatesOtherUses(unsigned Reg,const MachineOperand & OneUse,const MachineBasicBlock & MBB,const MachineRegisterInfo & MRI,const MachineDominatorTree & MDT,LiveIntervals & LIS,WebAssemblyFunctionInfo & MFI) oneUseDominatesOtherUses() argument
514 shrinkToUses(LiveInterval & LI,LiveIntervals & LIS) shrinkToUses() argument
525 moveForSingleUse(unsigned Reg,MachineOperand & Op,MachineInstr * Def,MachineBasicBlock & MBB,MachineInstr * Insert,LiveIntervals & LIS,WebAssemblyFunctionInfo & MFI,MachineRegisterInfo & MRI) moveForSingleUse() argument
574 rematerializeCheapDef(unsigned Reg,MachineOperand & Op,MachineInstr & Def,MachineBasicBlock & MBB,MachineBasicBlock::instr_iterator Insert,LiveIntervals & LIS,WebAssemblyFunctionInfo & MFI,MachineRegisterInfo & MRI,const WebAssemblyInstrInfo * TII,const WebAssemblyRegisterInfo * TRI) rematerializeCheapDef() argument
637 moveAndTeeForMultiUse(unsigned Reg,MachineOperand & Op,MachineInstr * Def,MachineBasicBlock & MBB,MachineInstr * Insert,LiveIntervals & LIS,WebAssemblyFunctionInfo & MFI,MachineRegisterInfo & MRI,const WebAssemblyInstrInfo * TII) moveAndTeeForMultiUse() argument
818 auto &LIS = getAnalysis<LiveIntervals>(); runOnMachineFunction() local
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H A DWebAssemblyOptimizeLiveIntervals.cpp80 auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); in runOnMachineFunction() local
/llvm-project/llvm/lib/CodeGen/
H A DRegAllocPBQP.cpp193 LiveIntervals &LIS = G.getMetadata().LIS; apply() local
310 LiveIntervals &LIS = G.getMetadata().LIS; apply() local
529 PBQPVirtRegAuxInfo(MachineFunction & MF,LiveIntervals & LIS,VirtRegMap & VRM,const MachineLoopInfo & Loops,const MachineBlockFrequencyInfo & MBFI) PBQPVirtRegAuxInfo() argument
568 findVRegIntervalsToAlloc(const MachineFunction & MF,LiveIntervals & LIS) findVRegIntervalsToAlloc() argument
594 LiveIntervals &LIS = G.getMetadata().LIS; initializeGraph() local
692 spillVReg(Register VReg,SmallVectorImpl<Register> & NewIntervals,MachineFunction & MF,LiveIntervals & LIS,VirtRegMap & VRM,Spiller & VRegSpiller) spillVReg() argument
721 LiveIntervals &LIS = G.getMetadata().LIS; mapPBQPToRegAlloc() local
756 finalizeAlloc(MachineFunction & MF,LiveIntervals & LIS,VirtRegMap & VRM) const finalizeAlloc() argument
783 postOptimization(Spiller & VRegSpiller,LiveIntervals & LIS) postOptimization() argument
794 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); runOnMachineFunction() local
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H A DLiveDebugVariables.cpp536 LiveIntervals *LIS; global() member in __anon69e74b370411::LDVImpl
965 extendDef(SlotIndex Idx,DbgVariableValue DbgValue,SmallDenseMap<unsigned,std::pair<LiveRange *,const VNInfo * >> & LiveIntervalInfo,std::optional<std::pair<SlotIndex,SmallVector<unsigned>>> & Kills,LiveIntervals & LIS) extendDef() argument
1019 addDefsFromCopies(DbgVariableValue DbgValue,SmallVectorImpl<std::pair<unsigned,LiveInterval * >> & LocIntervals,SlotIndex KilledAt,SmallVectorImpl<std::pair<SlotIndex,DbgVariableValue>> & NewDefs,MachineRegisterInfo & MRI,LiveIntervals & LIS) addDefsFromCopies() argument
1105 computeIntervals(MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,LiveIntervals & LIS,LexicalScopes & LS) computeIntervals() argument
1334 splitLocation(unsigned OldLocNo,ArrayRef<Register> NewRegs,LiveIntervals & LIS) splitLocation() argument
1434 splitRegister(Register OldReg,ArrayRef<Register> NewRegs,LiveIntervals & LIS) splitRegister() argument
1506 splitRegister(Register OldReg,ArrayRef<Register> NewRegs,LiveIntervals & LIS) splitRegister() argument
1590 findInsertLocation(MachineBasicBlock * MBB,SlotIndex Idx,LiveIntervals & LIS,BlockSkipInstsMap & BBSkipInstsMap) findInsertLocation() argument
1638 findNextInsertLocation(MachineBasicBlock * MBB,MachineBasicBlock::iterator I,SlotIndex StopIdx,ArrayRef<MachineOperand> LocMOs,LiveIntervals & LIS,const TargetRegisterInfo & TRI) findNextInsertLocation() argument
1665 insertDebugValue(MachineBasicBlock * MBB,SlotIndex StartIdx,SlotIndex StopIdx,DbgVariableValue DbgValue,ArrayRef<bool> LocSpills,ArrayRef<unsigned> SpillOffsets,LiveIntervals & LIS,const TargetInstrInfo & TII,const TargetRegisterInfo & TRI,BlockSkipInstsMap & BBSkipInstsMap) insertDebugValue() argument
1734 insertDebugLabel(MachineBasicBlock * MBB,SlotIndex Idx,LiveIntervals & LIS,const TargetInstrInfo & TII,BlockSkipInstsMap & BBSkipInstsMap) insertDebugLabel() argument
1743 emitDebugValues(VirtRegMap * VRM,LiveIntervals & LIS,const TargetInstrInfo & TII,const TargetRegisterInfo & TRI,const SpillOffsetMap & SpillOffsets,BlockSkipInstsMap & BBSkipInstsMap) emitDebugValues() argument
1799 emitDebugLabel(LiveIntervals & LIS,const TargetInstrInfo & TII,BlockSkipInstsMap & BBSkipInstsMap) emitDebugLabel() argument
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H A DRegAllocBase.h69 LiveIntervals *LIS = nullptr; variable
H A DRegAllocPriorityAdvisor.h39 LiveIntervals *const LIS; variable
H A DSplitKit.h100 const LiveIntervals &LIS; variable
265 LiveIntervals &LIS; variable
H A DRegisterPressure.cpp237 getLiveRange(const LiveIntervals & LIS,unsigned Reg) getLiveRange() argument
421 getLanesWithProperty(const LiveIntervals & LIS,const MachineRegisterInfo & MRI,bool TrackLaneMasks,Register RegUnit,SlotIndex Pos,LaneBitmask SafeDefault,bool (* Property)(const LiveRange & LR,SlotIndex Pos)) getLanesWithProperty() argument
449 getLiveLanesAt(const LiveIntervals & LIS,const MachineRegisterInfo & MRI,bool TrackLaneMasks,Register RegUnit,SlotIndex Pos) getLiveLanesAt() argument
579 detectDeadDefs(const MachineInstr & MI,const LiveIntervals & LIS) detectDeadDefs() argument
598 adjustLaneLiveness(const LiveIntervals & LIS,const MachineRegisterInfo & MRI,SlotIndex Pos,MachineInstr * AddFlagsMI) adjustLaneLiveness() argument
1227 findUseBetween(unsigned Reg,LaneBitmask LastUseMask,SlotIndex PriorUseIdx,SlotIndex NextUseIdx,const MachineRegisterInfo & MRI,const LiveIntervals * LIS) findUseBetween() argument
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerSGPRSpills.cpp39 LiveIntervals *LIS = nullptr; global() member in __anonb9093ebe0111::SILowerSGPRSpills
88 insertCSRSaves(MachineBasicBlock & SaveBlock,ArrayRef<CalleeSavedInfo> CSI,SlotIndexes * Indexes,LiveIntervals * LIS) insertCSRSaves() argument
131 insertCSRRestores(MachineBasicBlock & RestoreBlock,MutableArrayRef<CalleeSavedInfo> CSI,SlotIndexes * Indexes,LiveIntervals * LIS) insertCSRRestores() argument
263 extendWWMVirtRegLiveness(MachineFunction & MF,LiveIntervals * LIS) extendWWMVirtRegLiveness() argument
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H A DGCNRegPressure.h280 getLiveRegMap(Range && R,bool After,LiveIntervals & LIS) getLiveRegMap() argument
318 getLiveRegsAfter(const MachineInstr & MI,const LiveIntervals & LIS) getLiveRegsAfter() argument
324 getLiveRegsBefore(const MachineInstr & MI,const LiveIntervals & LIS) getLiveRegsBefore() argument
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H A DGCNRegPressure.cpp259 collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> & RegMaskPairs,const MachineInstr & MI,const LiveIntervals & LIS,const MachineRegisterInfo & MRI) collectVirtualRegUses() argument
295 getLiveLaneMask(unsigned Reg,SlotIndex SI,const LiveIntervals & LIS,const MachineRegisterInfo & MRI) getLiveLaneMask() argument
316 getLiveRegs(SlotIndex SI,const LiveIntervals & LIS,const MachineRegisterInfo & MRI) getLiveRegs() argument
603 getRegLiveThroughMask(const MachineRegisterInfo & MRI,const LiveIntervals & LIS,Register Reg,SlotIndex Begin,SlotIndex End,LaneBitmask Mask=LaneBitmask::getAll ()) getRegLiveThroughMask() argument
631 const LiveIntervals &LIS = getAnalysis<LiveIntervals>(); runOnMachineFunction() local
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H A DAMDGPUMarkLastScratchLoad.cpp31 LiveIntervals *LIS = nullptr; member in __anon9abdfecb0111::AMDGPUMarkLastScratchLoad
H A DSILowerWWMCopies.cpp54 LiveIntervals *LIS; global() member in __anon143300290111::SILowerWWMCopies
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H A DGCNPreRAOptimizations.cpp45 LiveIntervals *LIS; member in __anon6dbc05520111::GCNPreRAOptimizations
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H A DSIPreAllocateWWMRegs.cpp42 LiveIntervals *LIS; member in __anon6057c6da0111::SIPreAllocateWWMRegs
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H A DSIOptimizeExecMaskingPreRA.cpp33 LiveIntervals *LIS; member in __anon8f09429c0111::SIOptimizeExecMaskingPreRA
91 LiveIntervals *LIS, Register Reg, in isDefBetween() argument
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PostCoalescerPass.cpp29 LiveIntervals *LIS; global() member
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchDeadRegisterDefinitions.cpp66 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); runOnMachineFunction() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVDeadRegisterDefinitions.cpp65 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); runOnMachineFunction() local
/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp89 LiveIntervals &LIS = getAnalysis<LiveIntervals>(); INITIALIZE_PASS_DEPENDENCY() local

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