xref: /llvm-project/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp (revision 2c7ece2e8cf58d607f870ca9f02302df8aaa75d4)
1 //===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 //
9 // This pass rewrites Rd to x0 for instrs whose return values are unused.
10 //
11 //===---------------------------------------------------------------------===//
12 
13 #include "RISCV.h"
14 #include "RISCVSubtarget.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/CodeGen/LiveDebugVariables.h"
17 #include "llvm/CodeGen/LiveIntervals.h"
18 #include "llvm/CodeGen/LiveStacks.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 
21 using namespace llvm;
22 #define DEBUG_TYPE "riscv-dead-defs"
23 #define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"
24 
25 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
26 
27 namespace {
28 class RISCVDeadRegisterDefinitions : public MachineFunctionPass {
29 public:
30   static char ID;
31 
32   RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {}
33   bool runOnMachineFunction(MachineFunction &MF) override;
34   void getAnalysisUsage(AnalysisUsage &AU) const override {
35     AU.setPreservesCFG();
36     AU.addRequired<LiveIntervalsWrapperPass>();
37     AU.addPreserved<LiveIntervalsWrapperPass>();
38     AU.addRequired<LiveIntervalsWrapperPass>();
39     AU.addPreserved<SlotIndexesWrapperPass>();
40     AU.addPreserved<LiveDebugVariablesWrapperLegacy>();
41     AU.addPreserved<LiveStacksWrapperLegacy>();
42     MachineFunctionPass::getAnalysisUsage(AU);
43   }
44 
45   StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; }
46 };
47 } // end anonymous namespace
48 
49 char RISCVDeadRegisterDefinitions::ID = 0;
50 INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE,
51                 RISCV_DEAD_REG_DEF_NAME, false, false)
52 
53 FunctionPass *llvm::createRISCVDeadRegisterDefinitionsPass() {
54   return new RISCVDeadRegisterDefinitions();
55 }
56 
57 bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
58   if (skipFunction(MF.getFunction()))
59     return false;
60 
61   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
62   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
63   LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
64   LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");
65 
66   bool MadeChange = false;
67   for (MachineBasicBlock &MBB : MF) {
68     for (MachineInstr &MI : MBB) {
69       // We only handle non-computational instructions since some NOP encodings
70       // are reserved for HINT instructions.
71       const MCInstrDesc &Desc = MI.getDesc();
72       if (!Desc.mayLoad() && !Desc.mayStore() &&
73           !Desc.hasUnmodeledSideEffects() &&
74           MI.getOpcode() != RISCV::PseudoVSETVLI &&
75           MI.getOpcode() != RISCV::PseudoVSETIVLI)
76         continue;
77       // For PseudoVSETVLIX0, Rd = X0 has special meaning.
78       if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
79         continue;
80       for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
81         MachineOperand &MO = MI.getOperand(I);
82         if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())
83           continue;
84         // Be careful not to change the register if it's a tied operand.
85         if (MI.isRegTiedToUseOperand(I)) {
86           LLVM_DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
87           continue;
88         }
89         Register Reg = MO.getReg();
90         if (!Reg.isVirtual() || !MO.isDead())
91           continue;
92         LLVM_DEBUG(dbgs() << "    Dead def operand #" << I << " in:\n      ";
93                    MI.print(dbgs()));
94         Register X0Reg;
95         const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
96         if (RC && RC->contains(RISCV::X0)) {
97           X0Reg = RISCV::X0;
98         } else if (RC && RC->contains(RISCV::X0_W)) {
99           X0Reg = RISCV::X0_W;
100         } else if (RC && RC->contains(RISCV::X0_H)) {
101           X0Reg = RISCV::X0_H;
102         } else {
103           LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
104           continue;
105         }
106         assert(LIS.hasInterval(Reg));
107         LIS.removeInterval(Reg);
108         MO.setReg(X0Reg);
109         LLVM_DEBUG(dbgs() << "    Replacing with zero register. New:\n      ";
110                    MI.print(dbgs()));
111         ++NumDeadDefsReplaced;
112         MadeChange = true;
113       }
114     }
115   }
116 
117   return MadeChange;
118 }
119