[AMDGPU] Qualify auto. NFC. (#110878)

Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.

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[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

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[MC] Add MCRegisterInfo::regunits for iteration over register units

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D152098

[AMDGPU] Recompute liveness in SIOptimizeExecMaskingPreRA

Instead of ad-hoc updating liveness, recompute it completely for the affected register.

This does not affect any existing test and fixes an

[AMDGPU] Recompute liveness in SIOptimizeExecMaskingPreRA

Instead of ad-hoc updating liveness, recompute it completely for the affected register.

This does not affect any existing test and fixes an edge case that
caused a "Non-empty but used interval" error in the register allocator
due to how the pass updated liveranges. It created a "isolated" live-through
segment.

Overall this change just seems to be a net positive with no side effect observed. There may be a compile time impact but it's expected to be minimal.

Fixes SWDEV-388279

Reviewed By: critson

Differential Revision: https://reviews.llvm.org/D150105

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[AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

LLVM :: CodeGe

[AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

Differential Revision: https://reviews.llvm.org/D147721

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[AMDGPU] Fix comment in SIOptimizeExecMaskingPreRA

[AMDGPU] Fix liveness in the SIOptimizeExecMaskingPreRA.cpp

If a condition register def happens past the newly created use
we do not properly update LIS. It has two problems:

1) We do not extend de

[AMDGPU] Fix liveness in the SIOptimizeExecMaskingPreRA.cpp

If a condition register def happens past the newly created use
we do not properly update LIS. It has two problems:

1) We do not extend defining segment to the end of its block
marking it a live-out (this is regression after
https://reviews.llvm.org/rG09d38dd7704a52e8ad2d5f8f39aaeccf107f4c56)

2) We do not extend use segment to the beginning of the use block
marking it a live-in.

Fixes: SWDEV-379563

Differential Revision: https://reviews.llvm.org/D143302

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AMDGPU: Fix assert when trying to overextend liverange

This was trying to add segments beyond the new and use,
so skip additional segments.

This would hit (S < E && "Cannot create empty or backward

AMDGPU: Fix assert when trying to overextend liverange

This was trying to add segments beyond the new and use,
so skip additional segments.

This would hit (S < E && "Cannot create empty or backwards segment").

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[AMDGPU] Improve liveness copying in si-optimize-exec-masking-pre-ra

Further improve liveness copying for CC register post optimization
by mirroring live internal splits.
The fixes a bug in register

[AMDGPU] Improve liveness copying in si-optimize-exec-masking-pre-ra

Further improve liveness copying for CC register post optimization
by mirroring live internal splits.
The fixes a bug in register allocation when CC register liveness
is extended across a branches instead of split.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D129557

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[AMDGPU] Additional liveness tests for si-optimize-exec-masking-pre-ra

Merge tests and fixes from D128110 and D128315 on top of already
committed D128800.

Original author: arsenm

Reviewed By: arse

[AMDGPU] Additional liveness tests for si-optimize-exec-masking-pre-ra

Merge tests and fixes from D128110 and D128315 on top of already
committed D128800.

Original author: arsenm

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D128882

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[AMDGPU] Fix liveness for loops in si-optimize-exec-masking-pre-ra

Follow up to D127894, new liveness update code needs to handle
the case where S_ANDN2 input must be extended through loops when
V_C

[AMDGPU] Fix liveness for loops in si-optimize-exec-masking-pre-ra

Follow up to D127894, new liveness update code needs to handle
the case where S_ANDN2 input must be extended through loops when
V_CNDMASK_B32 has been hoisted.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D128800

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AMDGPU: Fix invalid liveness after si-optimize-exec-masking-pre-ra

This was leaving behind a use at the deleted instruction which the
verifier would fail during allocation.

[AMDGPU][NFC] Fix typos

Fix some typos in the amdgpu backend.

Differential Revision: https://reviews.llvm.org/D119235

[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy

Folding EXEC copy into it's single use may lead to constant bus constraint violation as it adds one more

[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy

Folding EXEC copy into it's single use may lead to constant bus constraint violation as it adds one more SGPR operand.
This change makes it validate the user instruction with the new SGPR operand and only fold it if it is legal.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D98888

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[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets

... to reduce headers dependency.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D95036

[NFC][AMDGPU] Reduce include files dependency.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813

[NFC] Use Register/MCRegister

Differential Revision: https://reviews.llvm.org/D90724

[AMDGPU] Remove fix up operand from SI_ELSE

Remove immediate operand from SI_ELSE which indicates if EXEC has
been modified. Instead always emit code that handles EXEC and
remove unnecessary instru

[AMDGPU] Remove fix up operand from SI_ELSE

Remove immediate operand from SI_ELSE which indicates if EXEC has
been modified. Instead always emit code that handles EXEC and
remove unnecessary instructions during pre-RA optimisation.

This facilitates passes (i.e. SIWholeQuadMode) adding exec mask
manipulation post control flow lowering, and pre control flow
lower passes do not need to be aware of SI_ELSE handling.

Reviewed By: nhaehnle

Differential Revision: https://reviews.llvm.org/D89644

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[AMDGPU][NFC] Tidy SIOptimizeExecMaskingPreRA for extensibility

Remove duplicate code and move things around to make it easier to
add additional optimisations to the pass.

Reviewed By: rampitec

Di

[AMDGPU][NFC] Tidy SIOptimizeExecMaskingPreRA for extensibility

Remove duplicate code and move things around to make it easier to
add additional optimisations to the pass.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D89619

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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister

... in favour of the isPhysical/isVirtual methods.

AMDGPU: Check for other defs when folding conditions into s_andn2_b64

We can't fold the masked compare value through the select if the
select condition is re-defed after the and instruction. Fixes a

AMDGPU: Check for other defs when folding conditions into s_andn2_b64

We can't fold the masked compare value through the select if the
select condition is re-defed after the and instruction. Fixes a
verifier error and trying to use the outgoing value defined in the
block.

I'm not sure why this pass is bothering to handle physregs. It's
making this more complex and forces extra liveness computation.

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[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations

Preserve SCC dead flags in SIOptimizeExecMaskingPreRA.
This helps with removing redundant s_andn2 instructions later.

Reviewed By:

[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations

Preserve SCC dead flags in SIOptimizeExecMaskingPreRA.
This helps with removing redundant s_andn2 instructions later.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D83637

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[AMDGPU] Don't assert on partial exec copy

After Machine CSE and coalescing we can end up with copies of exec to
subregister SGPRs.

Differential Revision: https://reviews.llvm.org/D77992

[AMDGPU] Simplify exec copies

The patch removes late endcf handling and only leaves the
related portion with redundant exec mask copy elimination.

Differential Revision: https://reviews.llvm.org/D7

[AMDGPU] Simplify exec copies

The patch removes late endcf handling and only leaves the
related portion with redundant exec mask copy elimination.

Differential Revision: https://reviews.llvm.org/D76095

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