/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64StorePairSuppress.cpp | 162 const MachineOperand *BaseOp; in runOnMachineFunction() local
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H A D | AArch64InstrInfo.cpp | 2706 const MachineOperand *BaseOp; getMemOperandsWithOffsetWidth() local 3491 getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,TypeSize & Width,const TargetRegisterInfo * TRI) const getMemOperandWithOffsetWidth() argument
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenMemAbsolute.cpp | 131 TII->getMemOperandWithOffset(*NextMI, BaseOp, Offset, Scalable, TRI); in runOnMachineFunction() local
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H A D | HexagonOptAddrMode.cpp | 432 MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI)); processAddUses() local 498 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); updateAddUses() local
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H A D | HexagonInstrInfo.cpp | 1173 const MachineOperand &BaseOp = MI.getOperand(1); expandPostRAPseudo() local 1188 const MachineOperand &BaseOp = MI.getOperand(1); expandPostRAPseudo() local 1211 const MachineOperand &BaseOp = MI.getOperand(0); expandPostRAPseudo() local 1227 const MachineOperand &BaseOp = MI.getOperand(0); expandPostRAPseudo() local 3077 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); getMemOperandsWithOffsetWidth() local 3316 const MachineOperand &BaseOp = MI.getOperand(BasePos); getBaseAndOffset() local [all...] |
/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.cpp | 755 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 811 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 109 getBaseOffset(const MachineInstr & MI,const MachineOperand * & BaseOp,int64_t & Offset) getBaseOffset() argument
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H A D | ARMLoadStoreOptimizer.cpp | 1624 const MachineOperand &BaseOp = MI.getOperand(2); MergeBaseUpdateLSDouble() local 1770 const MachineOperand &BaseOp = MI->getOperand(2); FixInvalidRegPairOp() local 3019 unsigned BaseOp = getBaseOperandIndex(*MI); AdjustBaseAndOffset() local 3160 int BaseOp = getBaseOperandIndex(Use); DistributeIncrements() local 3218 int BaseOp = getBaseOperandIndex(*PrePostInc); DistributeIncrements() local 3239 unsigned BaseOp = getBaseOperandIndex(*Use); DistributeIncrements() local 3289 int BaseOp = getBaseOperandIndex(MI); DistributeIncrements() local [all...] |
/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 133 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
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/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 1425 getMemOperandWithOffset(const MachineInstr & MI,const MachineOperand * & BaseOp,int64_t & Offset,bool & OffsetIsScalable,const TargetRegisterInfo * TRI) const getMemOperandWithOffset() argument 1593 const MachineOperand *BaseOp; describeLoadedValue() local
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H A D | MachineSink.cpp | 1306 const MachineOperand *BaseOp; SinkingPreventsImplicitNullCheck() local
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H A D | ModuloSchedule.cpp | 926 const MachineOperand *BaseOp; computeDelta() local
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H A D | MachinePipeliner.cpp | 2560 const MachineOperand *BaseOp; computeDelta() local
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/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 4283 unsigned BaseOp = 0; lowerXALUO() local 4309 unsigned BaseOp = 0; lowerXALUO() local 4376 unsigned BaseOp = 0; lowerUADDSUBO_CARRY() local 4406 unsigned BaseOp = 0; lowerUADDSUBO_CARRY() local [all...] |
/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 4498 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); getAddrModeFromMemoryOp() local 4625 const MachineOperand *BaseOp = getMemOperandsWithOffsetWidth() local
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H A D | X86ISelLowering.cpp | 23985 unsigned BaseOp = 0; getX86XALUOOp() local 54154 SDValue BaseOp = LHS.getOperand(0); combineSetCC() local [all...] |
/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 2637 const MachineOperand *BaseOp; getMemOperandsWithOffsetWidth() local
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/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 1574 unsigned BaseOp = 0; in lowerOverflowArithmetic() local
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/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 2841 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth() local
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/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 5808 const MCOperand &BaseOp = Inst.getOperand(2); expandSaaAddr() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 368 const MachineOperand *BaseOp, *OffsetOp; getMemOperandsWithOffsetWidth() local [all...] |
/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 7782 unsigned BaseOp; lowerAddSubSatToMinMax() local
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