Lines Matching defs:BaseOp

1176       const MachineOperand &BaseOp = MI.getOperand(1);
1177       assert(BaseOp.getSubReg() == 0);
1183           .addReg(BaseOp.getReg(), getRegState(BaseOp))
1191       const MachineOperand &BaseOp = MI.getOperand(1);
1192       assert(BaseOp.getSubReg() == 0);
1200           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1205           .addReg(BaseOp.getReg(), getRegState(BaseOp))
1214       const MachineOperand &BaseOp = MI.getOperand(0);
1215       assert(BaseOp.getSubReg() == 0);
1221           .addReg(BaseOp.getReg(), getRegState(BaseOp))
1230       const MachineOperand &BaseOp = MI.getOperand(0);
1231       assert(BaseOp.getSubReg() == 0);
1238           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1243           .addReg(BaseOp.getReg(), getRegState(BaseOp))
3080   const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
3081   if (!BaseOp || !BaseOp->isReg())
3083   BaseOps.push_back(BaseOp);
3319   const MachineOperand &BaseOp = MI.getOperand(BasePos);
3320   if (BaseOp.getSubReg() != 0)
3322   return &const_cast<MachineOperand&>(BaseOp);