Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can aga

Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129

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ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.

Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the re

ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.

Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834

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ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.

llvm-svn: 140560

Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.

llvm-svn: 140415

Revert r140412. This affects more instructions than intended.

llvm-svn: 140413

Thumb2 register-shifted-register loads cannot target the PC or the SP.

llvm-svn: 140412

tMOVSr is not allowed in an IT block either.

llvm-svn: 140104

CPS instructions are UNPREDICTABLE inside IT blocks.

llvm-svn: 140102

Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.

llvm-svn: 140079

Thumb2 assembly parsing and encoding for TBB/TBH.

llvm-svn: 140078

Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.

llvm-svn: 140032

Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.

llvm-svn: 139972

Fix bitfield decoding based on Eli's feedback.

llvm-svn: 139969

Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.

llvm-svn: 139965

Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).

llvm-svn: 139964

Fix disassembly of Thumb2 LDRSH with a #-0 offset.

llvm-svn: 139943

Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.

llvm-svn

Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.

llvm-svn: 139876

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Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.

llvm-svn: 139736

Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.

llvm-svn: 139522

LDM writeback is not allowed if Rn is in the target register list.

llvm-svn: 139432

Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.

llvm-svn: 139422

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.

llvm-svn: 139381

All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.

llvm-svn: 139329

Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.

llvm-svn: 139328