1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 EDInstInfo *getEDInfo() const; 55 private: 56 }; 57 58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59 class ThumbDisassembler : public MCDisassembler { 60 public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 EDInstInfo *getEDInfo() const; 80 private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84 }; 85 } 86 87 static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 return false; 100 } 101 102 103 // Forward declare these because the autogenerated code will reference them. 104 // Definitions are further down. 105 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128 129 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 142 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 147 unsigned Insn, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 159 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 160 unsigned Insn, 161 uint64_t Adddress, 162 const void *Decoder); 163 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 250 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 313 314 315 #include "ARMGenDisassemblerTables.inc" 316 #include "ARMGenInstrInfo.inc" 317 #include "ARMGenEDInfo.inc" 318 319 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 320 return new ARMDisassembler(STI); 321 } 322 323 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 324 return new ThumbDisassembler(STI); 325 } 326 327 EDInstInfo *ARMDisassembler::getEDInfo() const { 328 return instInfoARM; 329 } 330 331 EDInstInfo *ThumbDisassembler::getEDInfo() const { 332 return instInfoARM; 333 } 334 335 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 336 const MemoryObject &Region, 337 uint64_t Address, 338 raw_ostream &os, 339 raw_ostream &cs) const { 340 uint8_t bytes[4]; 341 342 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 343 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 344 345 // We want to read exactly 4 bytes of data. 346 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 347 Size = 0; 348 return MCDisassembler::Fail; 349 } 350 351 // Encoded as a small-endian 32-bit word in the stream. 352 uint32_t insn = (bytes[3] << 24) | 353 (bytes[2] << 16) | 354 (bytes[1] << 8) | 355 (bytes[0] << 0); 356 357 // Calling the auto-generated decoder function. 358 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 359 if (result != MCDisassembler::Fail) { 360 Size = 4; 361 return result; 362 } 363 364 // VFP and NEON instructions, similarly, are shared between ARM 365 // and Thumb modes. 366 MI.clear(); 367 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 368 if (result != MCDisassembler::Fail) { 369 Size = 4; 370 return result; 371 } 372 373 MI.clear(); 374 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 375 if (result != MCDisassembler::Fail) { 376 Size = 4; 377 // Add a fake predicate operand, because we share these instruction 378 // definitions with Thumb2 where these instructions are predicable. 379 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 380 return MCDisassembler::Fail; 381 return result; 382 } 383 384 MI.clear(); 385 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 386 if (result != MCDisassembler::Fail) { 387 Size = 4; 388 // Add a fake predicate operand, because we share these instruction 389 // definitions with Thumb2 where these instructions are predicable. 390 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 391 return MCDisassembler::Fail; 392 return result; 393 } 394 395 MI.clear(); 396 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 397 if (result != MCDisassembler::Fail) { 398 Size = 4; 399 // Add a fake predicate operand, because we share these instruction 400 // definitions with Thumb2 where these instructions are predicable. 401 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 402 return MCDisassembler::Fail; 403 return result; 404 } 405 406 MI.clear(); 407 408 Size = 0; 409 return MCDisassembler::Fail; 410 } 411 412 namespace llvm { 413 extern MCInstrDesc ARMInsts[]; 414 } 415 416 // Thumb1 instructions don't have explicit S bits. Rather, they 417 // implicitly set CPSR. Since it's not represented in the encoding, the 418 // auto-generated decoder won't inject the CPSR operand. We need to fix 419 // that as a post-pass. 420 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 421 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 422 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 423 MCInst::iterator I = MI.begin(); 424 for (unsigned i = 0; i < NumOps; ++i, ++I) { 425 if (I == MI.end()) break; 426 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 427 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 428 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 429 return; 430 } 431 } 432 433 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 434 } 435 436 // Most Thumb instructions don't have explicit predicates in the 437 // encoding, but rather get their predicates from IT context. We need 438 // to fix up the predicate operands using this context information as a 439 // post-pass. 440 MCDisassembler::DecodeStatus 441 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 442 MCDisassembler::DecodeStatus S = Success; 443 444 // A few instructions actually have predicates encoded in them. Don't 445 // try to overwrite it if we're seeing one of those. 446 switch (MI.getOpcode()) { 447 case ARM::tBcc: 448 case ARM::t2Bcc: 449 case ARM::tCBZ: 450 case ARM::tCBNZ: 451 case ARM::tCPS: 452 case ARM::t2CPS3p: 453 case ARM::t2CPS2p: 454 case ARM::t2CPS1p: 455 case ARM::tMOVSr: 456 // Some instructions (mostly conditional branches) are not 457 // allowed in IT blocks. 458 if (!ITBlock.empty()) 459 S = SoftFail; 460 else 461 return Success; 462 break; 463 case ARM::tB: 464 case ARM::t2B: 465 case ARM::t2TBB: 466 case ARM::t2TBH: 467 // Some instructions (mostly unconditional branches) can 468 // only appears at the end of, or outside of, an IT. 469 if (ITBlock.size() > 1) 470 S = SoftFail; 471 break; 472 default: 473 break; 474 } 475 476 // If we're in an IT block, base the predicate on that. Otherwise, 477 // assume a predicate of AL. 478 unsigned CC; 479 if (!ITBlock.empty()) { 480 CC = ITBlock.back(); 481 if (CC == 0xF) 482 CC = ARMCC::AL; 483 ITBlock.pop_back(); 484 } else 485 CC = ARMCC::AL; 486 487 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 488 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 489 MCInst::iterator I = MI.begin(); 490 for (unsigned i = 0; i < NumOps; ++i, ++I) { 491 if (I == MI.end()) break; 492 if (OpInfo[i].isPredicate()) { 493 I = MI.insert(I, MCOperand::CreateImm(CC)); 494 ++I; 495 if (CC == ARMCC::AL) 496 MI.insert(I, MCOperand::CreateReg(0)); 497 else 498 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 499 return S; 500 } 501 } 502 503 I = MI.insert(I, MCOperand::CreateImm(CC)); 504 ++I; 505 if (CC == ARMCC::AL) 506 MI.insert(I, MCOperand::CreateReg(0)); 507 else 508 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 509 510 return S; 511 } 512 513 // Thumb VFP instructions are a special case. Because we share their 514 // encodings between ARM and Thumb modes, and they are predicable in ARM 515 // mode, the auto-generated decoder will give them an (incorrect) 516 // predicate operand. We need to rewrite these operands based on the IT 517 // context as a post-pass. 518 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 519 unsigned CC; 520 if (!ITBlock.empty()) { 521 CC = ITBlock.back(); 522 ITBlock.pop_back(); 523 } else 524 CC = ARMCC::AL; 525 526 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 527 MCInst::iterator I = MI.begin(); 528 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 529 for (unsigned i = 0; i < NumOps; ++i, ++I) { 530 if (OpInfo[i].isPredicate() ) { 531 I->setImm(CC); 532 ++I; 533 if (CC == ARMCC::AL) 534 I->setReg(0); 535 else 536 I->setReg(ARM::CPSR); 537 return; 538 } 539 } 540 } 541 542 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 543 const MemoryObject &Region, 544 uint64_t Address, 545 raw_ostream &os, 546 raw_ostream &cs) const { 547 uint8_t bytes[4]; 548 549 assert((STI.getFeatureBits() & ARM::ModeThumb) && 550 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 551 552 // We want to read exactly 2 bytes of data. 553 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 554 Size = 0; 555 return MCDisassembler::Fail; 556 } 557 558 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 559 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 560 if (result != MCDisassembler::Fail) { 561 Size = 2; 562 Check(result, AddThumbPredicate(MI)); 563 return result; 564 } 565 566 MI.clear(); 567 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 568 if (result) { 569 Size = 2; 570 bool InITBlock = !ITBlock.empty(); 571 Check(result, AddThumbPredicate(MI)); 572 AddThumb1SBit(MI, InITBlock); 573 return result; 574 } 575 576 MI.clear(); 577 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 578 if (result != MCDisassembler::Fail) { 579 Size = 2; 580 Check(result, AddThumbPredicate(MI)); 581 582 // If we find an IT instruction, we need to parse its condition 583 // code and mask operands so that we can apply them correctly 584 // to the subsequent instructions. 585 if (MI.getOpcode() == ARM::t2IT) { 586 // Nested IT blocks are UNPREDICTABLE. 587 if (!ITBlock.empty()) 588 return MCDisassembler::SoftFail; 589 590 // (3 - the number of trailing zeros) is the number of then / else. 591 unsigned firstcond = MI.getOperand(0).getImm(); 592 unsigned Mask = MI.getOperand(1).getImm(); 593 unsigned CondBit0 = Mask >> 4 & 1; 594 unsigned NumTZ = CountTrailingZeros_32(Mask); 595 assert(NumTZ <= 3 && "Invalid IT mask!"); 596 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 597 bool T = ((Mask >> Pos) & 1) == CondBit0; 598 if (T) 599 ITBlock.insert(ITBlock.begin(), firstcond); 600 else 601 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 602 } 603 604 ITBlock.push_back(firstcond); 605 } 606 607 return result; 608 } 609 610 // We want to read exactly 4 bytes of data. 611 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 612 Size = 0; 613 return MCDisassembler::Fail; 614 } 615 616 uint32_t insn32 = (bytes[3] << 8) | 617 (bytes[2] << 0) | 618 (bytes[1] << 24) | 619 (bytes[0] << 16); 620 MI.clear(); 621 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 622 if (result != MCDisassembler::Fail) { 623 Size = 4; 624 bool InITBlock = ITBlock.size(); 625 Check(result, AddThumbPredicate(MI)); 626 AddThumb1SBit(MI, InITBlock); 627 return result; 628 } 629 630 MI.clear(); 631 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 632 if (result != MCDisassembler::Fail) { 633 Size = 4; 634 Check(result, AddThumbPredicate(MI)); 635 return result; 636 } 637 638 MI.clear(); 639 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 640 if (result != MCDisassembler::Fail) { 641 Size = 4; 642 UpdateThumbVFPPredicate(MI); 643 return result; 644 } 645 646 MI.clear(); 647 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 648 if (result != MCDisassembler::Fail) { 649 Size = 4; 650 Check(result, AddThumbPredicate(MI)); 651 return result; 652 } 653 654 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 655 MI.clear(); 656 uint32_t NEONLdStInsn = insn32; 657 NEONLdStInsn &= 0xF0FFFFFF; 658 NEONLdStInsn |= 0x04000000; 659 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 660 if (result != MCDisassembler::Fail) { 661 Size = 4; 662 Check(result, AddThumbPredicate(MI)); 663 return result; 664 } 665 } 666 667 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 668 MI.clear(); 669 uint32_t NEONDataInsn = insn32; 670 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 671 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 672 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 673 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 674 if (result != MCDisassembler::Fail) { 675 Size = 4; 676 Check(result, AddThumbPredicate(MI)); 677 return result; 678 } 679 } 680 681 Size = 0; 682 return MCDisassembler::Fail; 683 } 684 685 686 extern "C" void LLVMInitializeARMDisassembler() { 687 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 688 createARMDisassembler); 689 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 690 createThumbDisassembler); 691 } 692 693 static const unsigned GPRDecoderTable[] = { 694 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 695 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 696 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 697 ARM::R12, ARM::SP, ARM::LR, ARM::PC 698 }; 699 700 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 701 uint64_t Address, const void *Decoder) { 702 if (RegNo > 15) 703 return MCDisassembler::Fail; 704 705 unsigned Register = GPRDecoderTable[RegNo]; 706 Inst.addOperand(MCOperand::CreateReg(Register)); 707 return MCDisassembler::Success; 708 } 709 710 static DecodeStatus 711 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 712 uint64_t Address, const void *Decoder) { 713 if (RegNo == 15) return MCDisassembler::Fail; 714 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 715 } 716 717 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 718 uint64_t Address, const void *Decoder) { 719 if (RegNo > 7) 720 return MCDisassembler::Fail; 721 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 722 } 723 724 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 725 uint64_t Address, const void *Decoder) { 726 unsigned Register = 0; 727 switch (RegNo) { 728 case 0: 729 Register = ARM::R0; 730 break; 731 case 1: 732 Register = ARM::R1; 733 break; 734 case 2: 735 Register = ARM::R2; 736 break; 737 case 3: 738 Register = ARM::R3; 739 break; 740 case 9: 741 Register = ARM::R9; 742 break; 743 case 12: 744 Register = ARM::R12; 745 break; 746 default: 747 return MCDisassembler::Fail; 748 } 749 750 Inst.addOperand(MCOperand::CreateReg(Register)); 751 return MCDisassembler::Success; 752 } 753 754 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 755 uint64_t Address, const void *Decoder) { 756 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 757 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 758 } 759 760 static const unsigned SPRDecoderTable[] = { 761 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 762 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 763 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 764 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 765 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 766 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 767 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 768 ARM::S28, ARM::S29, ARM::S30, ARM::S31 769 }; 770 771 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 772 uint64_t Address, const void *Decoder) { 773 if (RegNo > 31) 774 return MCDisassembler::Fail; 775 776 unsigned Register = SPRDecoderTable[RegNo]; 777 Inst.addOperand(MCOperand::CreateReg(Register)); 778 return MCDisassembler::Success; 779 } 780 781 static const unsigned DPRDecoderTable[] = { 782 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 783 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 784 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 785 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 786 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 787 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 788 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 789 ARM::D28, ARM::D29, ARM::D30, ARM::D31 790 }; 791 792 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 793 uint64_t Address, const void *Decoder) { 794 if (RegNo > 31) 795 return MCDisassembler::Fail; 796 797 unsigned Register = DPRDecoderTable[RegNo]; 798 Inst.addOperand(MCOperand::CreateReg(Register)); 799 return MCDisassembler::Success; 800 } 801 802 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 803 uint64_t Address, const void *Decoder) { 804 if (RegNo > 7) 805 return MCDisassembler::Fail; 806 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 807 } 808 809 static DecodeStatus 810 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 811 uint64_t Address, const void *Decoder) { 812 if (RegNo > 15) 813 return MCDisassembler::Fail; 814 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 815 } 816 817 static const unsigned QPRDecoderTable[] = { 818 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 819 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 820 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 821 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 822 }; 823 824 825 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 826 uint64_t Address, const void *Decoder) { 827 if (RegNo > 31) 828 return MCDisassembler::Fail; 829 RegNo >>= 1; 830 831 unsigned Register = QPRDecoderTable[RegNo]; 832 Inst.addOperand(MCOperand::CreateReg(Register)); 833 return MCDisassembler::Success; 834 } 835 836 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 837 uint64_t Address, const void *Decoder) { 838 if (Val == 0xF) return MCDisassembler::Fail; 839 // AL predicate is not allowed on Thumb1 branches. 840 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 841 return MCDisassembler::Fail; 842 Inst.addOperand(MCOperand::CreateImm(Val)); 843 if (Val == ARMCC::AL) { 844 Inst.addOperand(MCOperand::CreateReg(0)); 845 } else 846 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 847 return MCDisassembler::Success; 848 } 849 850 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 851 uint64_t Address, const void *Decoder) { 852 if (Val) 853 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 854 else 855 Inst.addOperand(MCOperand::CreateReg(0)); 856 return MCDisassembler::Success; 857 } 858 859 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 860 uint64_t Address, const void *Decoder) { 861 uint32_t imm = Val & 0xFF; 862 uint32_t rot = (Val & 0xF00) >> 7; 863 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 864 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 865 return MCDisassembler::Success; 866 } 867 868 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 869 uint64_t Address, const void *Decoder) { 870 DecodeStatus S = MCDisassembler::Success; 871 872 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 873 unsigned type = fieldFromInstruction32(Val, 5, 2); 874 unsigned imm = fieldFromInstruction32(Val, 7, 5); 875 876 // Register-immediate 877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 878 return MCDisassembler::Fail; 879 880 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 881 switch (type) { 882 case 0: 883 Shift = ARM_AM::lsl; 884 break; 885 case 1: 886 Shift = ARM_AM::lsr; 887 break; 888 case 2: 889 Shift = ARM_AM::asr; 890 break; 891 case 3: 892 Shift = ARM_AM::ror; 893 break; 894 } 895 896 if (Shift == ARM_AM::ror && imm == 0) 897 Shift = ARM_AM::rrx; 898 899 unsigned Op = Shift | (imm << 3); 900 Inst.addOperand(MCOperand::CreateImm(Op)); 901 902 return S; 903 } 904 905 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 906 uint64_t Address, const void *Decoder) { 907 DecodeStatus S = MCDisassembler::Success; 908 909 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 910 unsigned type = fieldFromInstruction32(Val, 5, 2); 911 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 912 913 // Register-register 914 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 915 return MCDisassembler::Fail; 916 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 917 return MCDisassembler::Fail; 918 919 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 920 switch (type) { 921 case 0: 922 Shift = ARM_AM::lsl; 923 break; 924 case 1: 925 Shift = ARM_AM::lsr; 926 break; 927 case 2: 928 Shift = ARM_AM::asr; 929 break; 930 case 3: 931 Shift = ARM_AM::ror; 932 break; 933 } 934 935 Inst.addOperand(MCOperand::CreateImm(Shift)); 936 937 return S; 938 } 939 940 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 941 uint64_t Address, const void *Decoder) { 942 DecodeStatus S = MCDisassembler::Success; 943 944 bool writebackLoad = false; 945 unsigned writebackReg = 0; 946 switch (Inst.getOpcode()) { 947 default: 948 break; 949 case ARM::LDMIA_UPD: 950 case ARM::LDMDB_UPD: 951 case ARM::LDMIB_UPD: 952 case ARM::LDMDA_UPD: 953 case ARM::t2LDMIA_UPD: 954 case ARM::t2LDMDB_UPD: 955 writebackLoad = true; 956 writebackReg = Inst.getOperand(0).getReg(); 957 break; 958 } 959 960 // Empty register lists are not allowed. 961 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 962 for (unsigned i = 0; i < 16; ++i) { 963 if (Val & (1 << i)) { 964 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 965 return MCDisassembler::Fail; 966 // Writeback not allowed if Rn is in the target list. 967 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 968 Check(S, MCDisassembler::SoftFail); 969 } 970 } 971 972 return S; 973 } 974 975 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 976 uint64_t Address, const void *Decoder) { 977 DecodeStatus S = MCDisassembler::Success; 978 979 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 980 unsigned regs = Val & 0xFF; 981 982 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 983 return MCDisassembler::Fail; 984 for (unsigned i = 0; i < (regs - 1); ++i) { 985 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 986 return MCDisassembler::Fail; 987 } 988 989 return S; 990 } 991 992 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 993 uint64_t Address, const void *Decoder) { 994 DecodeStatus S = MCDisassembler::Success; 995 996 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 997 unsigned regs = (Val & 0xFF) / 2; 998 999 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1000 return MCDisassembler::Fail; 1001 for (unsigned i = 0; i < (regs - 1); ++i) { 1002 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1003 return MCDisassembler::Fail; 1004 } 1005 1006 return S; 1007 } 1008 1009 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1010 uint64_t Address, const void *Decoder) { 1011 // This operand encodes a mask of contiguous zeros between a specified MSB 1012 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1013 // the mask of all bits LSB-and-lower, and then xor them to create 1014 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1015 // create the final mask. 1016 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1017 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1018 1019 DecodeStatus S = MCDisassembler::Success; 1020 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1021 1022 uint32_t msb_mask = 0xFFFFFFFF; 1023 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1024 uint32_t lsb_mask = (1U << lsb) - 1; 1025 1026 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1027 return S; 1028 } 1029 1030 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1031 uint64_t Address, const void *Decoder) { 1032 DecodeStatus S = MCDisassembler::Success; 1033 1034 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1035 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1036 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1037 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1038 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1039 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1040 1041 switch (Inst.getOpcode()) { 1042 case ARM::LDC_OFFSET: 1043 case ARM::LDC_PRE: 1044 case ARM::LDC_POST: 1045 case ARM::LDC_OPTION: 1046 case ARM::LDCL_OFFSET: 1047 case ARM::LDCL_PRE: 1048 case ARM::LDCL_POST: 1049 case ARM::LDCL_OPTION: 1050 case ARM::STC_OFFSET: 1051 case ARM::STC_PRE: 1052 case ARM::STC_POST: 1053 case ARM::STC_OPTION: 1054 case ARM::STCL_OFFSET: 1055 case ARM::STCL_PRE: 1056 case ARM::STCL_POST: 1057 case ARM::STCL_OPTION: 1058 case ARM::t2LDC_OFFSET: 1059 case ARM::t2LDC_PRE: 1060 case ARM::t2LDC_POST: 1061 case ARM::t2LDC_OPTION: 1062 case ARM::t2LDCL_OFFSET: 1063 case ARM::t2LDCL_PRE: 1064 case ARM::t2LDCL_POST: 1065 case ARM::t2LDCL_OPTION: 1066 case ARM::t2STC_OFFSET: 1067 case ARM::t2STC_PRE: 1068 case ARM::t2STC_POST: 1069 case ARM::t2STC_OPTION: 1070 case ARM::t2STCL_OFFSET: 1071 case ARM::t2STCL_PRE: 1072 case ARM::t2STCL_POST: 1073 case ARM::t2STCL_OPTION: 1074 if (coproc == 0xA || coproc == 0xB) 1075 return MCDisassembler::Fail; 1076 break; 1077 default: 1078 break; 1079 } 1080 1081 Inst.addOperand(MCOperand::CreateImm(coproc)); 1082 Inst.addOperand(MCOperand::CreateImm(CRd)); 1083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1084 return MCDisassembler::Fail; 1085 switch (Inst.getOpcode()) { 1086 case ARM::LDC_OPTION: 1087 case ARM::LDCL_OPTION: 1088 case ARM::LDC2_OPTION: 1089 case ARM::LDC2L_OPTION: 1090 case ARM::STC_OPTION: 1091 case ARM::STCL_OPTION: 1092 case ARM::STC2_OPTION: 1093 case ARM::STC2L_OPTION: 1094 case ARM::LDCL_POST: 1095 case ARM::STCL_POST: 1096 case ARM::LDC2L_POST: 1097 case ARM::STC2L_POST: 1098 case ARM::t2LDC_OPTION: 1099 case ARM::t2LDCL_OPTION: 1100 case ARM::t2STC_OPTION: 1101 case ARM::t2STCL_OPTION: 1102 case ARM::t2LDCL_POST: 1103 case ARM::t2STCL_POST: 1104 break; 1105 default: 1106 Inst.addOperand(MCOperand::CreateReg(0)); 1107 break; 1108 } 1109 1110 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1111 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1112 1113 bool writeback = (P == 0) || (W == 1); 1114 unsigned idx_mode = 0; 1115 if (P && writeback) 1116 idx_mode = ARMII::IndexModePre; 1117 else if (!P && writeback) 1118 idx_mode = ARMII::IndexModePost; 1119 1120 switch (Inst.getOpcode()) { 1121 case ARM::LDCL_POST: 1122 case ARM::STCL_POST: 1123 case ARM::t2LDCL_POST: 1124 case ARM::t2STCL_POST: 1125 case ARM::LDC2L_POST: 1126 case ARM::STC2L_POST: 1127 imm |= U << 8; 1128 case ARM::LDC_OPTION: 1129 case ARM::LDCL_OPTION: 1130 case ARM::LDC2_OPTION: 1131 case ARM::LDC2L_OPTION: 1132 case ARM::STC_OPTION: 1133 case ARM::STCL_OPTION: 1134 case ARM::STC2_OPTION: 1135 case ARM::STC2L_OPTION: 1136 case ARM::t2LDC_OPTION: 1137 case ARM::t2LDCL_OPTION: 1138 case ARM::t2STC_OPTION: 1139 case ARM::t2STCL_OPTION: 1140 Inst.addOperand(MCOperand::CreateImm(imm)); 1141 break; 1142 default: 1143 if (U) 1144 Inst.addOperand(MCOperand::CreateImm( 1145 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1146 else 1147 Inst.addOperand(MCOperand::CreateImm( 1148 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1149 break; 1150 } 1151 1152 switch (Inst.getOpcode()) { 1153 case ARM::LDC_OFFSET: 1154 case ARM::LDC_PRE: 1155 case ARM::LDC_POST: 1156 case ARM::LDC_OPTION: 1157 case ARM::LDCL_OFFSET: 1158 case ARM::LDCL_PRE: 1159 case ARM::LDCL_POST: 1160 case ARM::LDCL_OPTION: 1161 case ARM::STC_OFFSET: 1162 case ARM::STC_PRE: 1163 case ARM::STC_POST: 1164 case ARM::STC_OPTION: 1165 case ARM::STCL_OFFSET: 1166 case ARM::STCL_PRE: 1167 case ARM::STCL_POST: 1168 case ARM::STCL_OPTION: 1169 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1170 return MCDisassembler::Fail; 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 return S; 1177 } 1178 1179 static DecodeStatus 1180 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1181 uint64_t Address, const void *Decoder) { 1182 DecodeStatus S = MCDisassembler::Success; 1183 1184 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1185 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1186 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1187 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1188 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1189 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1190 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1191 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1192 1193 // On stores, the writeback operand precedes Rt. 1194 switch (Inst.getOpcode()) { 1195 case ARM::STR_POST_IMM: 1196 case ARM::STR_POST_REG: 1197 case ARM::STRB_POST_IMM: 1198 case ARM::STRB_POST_REG: 1199 case ARM::STRT_POST_REG: 1200 case ARM::STRT_POST_IMM: 1201 case ARM::STRBT_POST_REG: 1202 case ARM::STRBT_POST_IMM: 1203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1204 return MCDisassembler::Fail; 1205 break; 1206 default: 1207 break; 1208 } 1209 1210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1211 return MCDisassembler::Fail; 1212 1213 // On loads, the writeback operand comes after Rt. 1214 switch (Inst.getOpcode()) { 1215 case ARM::LDR_POST_IMM: 1216 case ARM::LDR_POST_REG: 1217 case ARM::LDRB_POST_IMM: 1218 case ARM::LDRB_POST_REG: 1219 case ARM::LDRBT_POST_REG: 1220 case ARM::LDRBT_POST_IMM: 1221 case ARM::LDRT_POST_REG: 1222 case ARM::LDRT_POST_IMM: 1223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1224 return MCDisassembler::Fail; 1225 break; 1226 default: 1227 break; 1228 } 1229 1230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 1233 ARM_AM::AddrOpc Op = ARM_AM::add; 1234 if (!fieldFromInstruction32(Insn, 23, 1)) 1235 Op = ARM_AM::sub; 1236 1237 bool writeback = (P == 0) || (W == 1); 1238 unsigned idx_mode = 0; 1239 if (P && writeback) 1240 idx_mode = ARMII::IndexModePre; 1241 else if (!P && writeback) 1242 idx_mode = ARMII::IndexModePost; 1243 1244 if (writeback && (Rn == 15 || Rn == Rt)) 1245 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1246 1247 if (reg) { 1248 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1249 return MCDisassembler::Fail; 1250 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1251 switch( fieldFromInstruction32(Insn, 5, 2)) { 1252 case 0: 1253 Opc = ARM_AM::lsl; 1254 break; 1255 case 1: 1256 Opc = ARM_AM::lsr; 1257 break; 1258 case 2: 1259 Opc = ARM_AM::asr; 1260 break; 1261 case 3: 1262 Opc = ARM_AM::ror; 1263 break; 1264 default: 1265 return MCDisassembler::Fail; 1266 } 1267 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1268 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1269 1270 Inst.addOperand(MCOperand::CreateImm(imm)); 1271 } else { 1272 Inst.addOperand(MCOperand::CreateReg(0)); 1273 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1274 Inst.addOperand(MCOperand::CreateImm(tmp)); 1275 } 1276 1277 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1278 return MCDisassembler::Fail; 1279 1280 return S; 1281 } 1282 1283 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1284 uint64_t Address, const void *Decoder) { 1285 DecodeStatus S = MCDisassembler::Success; 1286 1287 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1288 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1289 unsigned type = fieldFromInstruction32(Val, 5, 2); 1290 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1291 unsigned U = fieldFromInstruction32(Val, 12, 1); 1292 1293 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1294 switch (type) { 1295 case 0: 1296 ShOp = ARM_AM::lsl; 1297 break; 1298 case 1: 1299 ShOp = ARM_AM::lsr; 1300 break; 1301 case 2: 1302 ShOp = ARM_AM::asr; 1303 break; 1304 case 3: 1305 ShOp = ARM_AM::ror; 1306 break; 1307 } 1308 1309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1310 return MCDisassembler::Fail; 1311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1312 return MCDisassembler::Fail; 1313 unsigned shift; 1314 if (U) 1315 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1316 else 1317 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1318 Inst.addOperand(MCOperand::CreateImm(shift)); 1319 1320 return S; 1321 } 1322 1323 static DecodeStatus 1324 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1325 uint64_t Address, const void *Decoder) { 1326 DecodeStatus S = MCDisassembler::Success; 1327 1328 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1329 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1330 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1331 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1332 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1333 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1334 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1335 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1336 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1337 1338 bool writeback = (W == 1) | (P == 0); 1339 1340 // For {LD,ST}RD, Rt must be even, else undefined. 1341 switch (Inst.getOpcode()) { 1342 case ARM::STRD: 1343 case ARM::STRD_PRE: 1344 case ARM::STRD_POST: 1345 case ARM::LDRD: 1346 case ARM::LDRD_PRE: 1347 case ARM::LDRD_POST: 1348 if (Rt & 0x1) return MCDisassembler::Fail; 1349 break; 1350 default: 1351 break; 1352 } 1353 1354 if (writeback) { // Writeback 1355 if (P) 1356 U |= ARMII::IndexModePre << 9; 1357 else 1358 U |= ARMII::IndexModePost << 9; 1359 1360 // On stores, the writeback operand precedes Rt. 1361 switch (Inst.getOpcode()) { 1362 case ARM::STRD: 1363 case ARM::STRD_PRE: 1364 case ARM::STRD_POST: 1365 case ARM::STRH: 1366 case ARM::STRH_PRE: 1367 case ARM::STRH_POST: 1368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1369 return MCDisassembler::Fail; 1370 break; 1371 default: 1372 break; 1373 } 1374 } 1375 1376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1377 return MCDisassembler::Fail; 1378 switch (Inst.getOpcode()) { 1379 case ARM::STRD: 1380 case ARM::STRD_PRE: 1381 case ARM::STRD_POST: 1382 case ARM::LDRD: 1383 case ARM::LDRD_PRE: 1384 case ARM::LDRD_POST: 1385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1386 return MCDisassembler::Fail; 1387 break; 1388 default: 1389 break; 1390 } 1391 1392 if (writeback) { 1393 // On loads, the writeback operand comes after Rt. 1394 switch (Inst.getOpcode()) { 1395 case ARM::LDRD: 1396 case ARM::LDRD_PRE: 1397 case ARM::LDRD_POST: 1398 case ARM::LDRH: 1399 case ARM::LDRH_PRE: 1400 case ARM::LDRH_POST: 1401 case ARM::LDRSH: 1402 case ARM::LDRSH_PRE: 1403 case ARM::LDRSH_POST: 1404 case ARM::LDRSB: 1405 case ARM::LDRSB_PRE: 1406 case ARM::LDRSB_POST: 1407 case ARM::LDRHTr: 1408 case ARM::LDRSBTr: 1409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1410 return MCDisassembler::Fail; 1411 break; 1412 default: 1413 break; 1414 } 1415 } 1416 1417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1418 return MCDisassembler::Fail; 1419 1420 if (type) { 1421 Inst.addOperand(MCOperand::CreateReg(0)); 1422 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1423 } else { 1424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1425 return MCDisassembler::Fail; 1426 Inst.addOperand(MCOperand::CreateImm(U)); 1427 } 1428 1429 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1430 return MCDisassembler::Fail; 1431 1432 return S; 1433 } 1434 1435 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1436 uint64_t Address, const void *Decoder) { 1437 DecodeStatus S = MCDisassembler::Success; 1438 1439 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1440 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1441 1442 switch (mode) { 1443 case 0: 1444 mode = ARM_AM::da; 1445 break; 1446 case 1: 1447 mode = ARM_AM::ia; 1448 break; 1449 case 2: 1450 mode = ARM_AM::db; 1451 break; 1452 case 3: 1453 mode = ARM_AM::ib; 1454 break; 1455 } 1456 1457 Inst.addOperand(MCOperand::CreateImm(mode)); 1458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1459 return MCDisassembler::Fail; 1460 1461 return S; 1462 } 1463 1464 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1465 unsigned Insn, 1466 uint64_t Address, const void *Decoder) { 1467 DecodeStatus S = MCDisassembler::Success; 1468 1469 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1470 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1471 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1472 1473 if (pred == 0xF) { 1474 switch (Inst.getOpcode()) { 1475 case ARM::LDMDA: 1476 Inst.setOpcode(ARM::RFEDA); 1477 break; 1478 case ARM::LDMDA_UPD: 1479 Inst.setOpcode(ARM::RFEDA_UPD); 1480 break; 1481 case ARM::LDMDB: 1482 Inst.setOpcode(ARM::RFEDB); 1483 break; 1484 case ARM::LDMDB_UPD: 1485 Inst.setOpcode(ARM::RFEDB_UPD); 1486 break; 1487 case ARM::LDMIA: 1488 Inst.setOpcode(ARM::RFEIA); 1489 break; 1490 case ARM::LDMIA_UPD: 1491 Inst.setOpcode(ARM::RFEIA_UPD); 1492 break; 1493 case ARM::LDMIB: 1494 Inst.setOpcode(ARM::RFEIB); 1495 break; 1496 case ARM::LDMIB_UPD: 1497 Inst.setOpcode(ARM::RFEIB_UPD); 1498 break; 1499 case ARM::STMDA: 1500 Inst.setOpcode(ARM::SRSDA); 1501 break; 1502 case ARM::STMDA_UPD: 1503 Inst.setOpcode(ARM::SRSDA_UPD); 1504 break; 1505 case ARM::STMDB: 1506 Inst.setOpcode(ARM::SRSDB); 1507 break; 1508 case ARM::STMDB_UPD: 1509 Inst.setOpcode(ARM::SRSDB_UPD); 1510 break; 1511 case ARM::STMIA: 1512 Inst.setOpcode(ARM::SRSIA); 1513 break; 1514 case ARM::STMIA_UPD: 1515 Inst.setOpcode(ARM::SRSIA_UPD); 1516 break; 1517 case ARM::STMIB: 1518 Inst.setOpcode(ARM::SRSIB); 1519 break; 1520 case ARM::STMIB_UPD: 1521 Inst.setOpcode(ARM::SRSIB_UPD); 1522 break; 1523 default: 1524 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1525 } 1526 1527 // For stores (which become SRS's, the only operand is the mode. 1528 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1529 Inst.addOperand( 1530 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1531 return S; 1532 } 1533 1534 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1535 } 1536 1537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1538 return MCDisassembler::Fail; 1539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1540 return MCDisassembler::Fail; // Tied 1541 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1542 return MCDisassembler::Fail; 1543 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1544 return MCDisassembler::Fail; 1545 1546 return S; 1547 } 1548 1549 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1550 uint64_t Address, const void *Decoder) { 1551 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1552 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1553 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1554 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1555 1556 DecodeStatus S = MCDisassembler::Success; 1557 1558 // imod == '01' --> UNPREDICTABLE 1559 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1560 // return failure here. The '01' imod value is unprintable, so there's 1561 // nothing useful we could do even if we returned UNPREDICTABLE. 1562 1563 if (imod == 1) return MCDisassembler::Fail; 1564 1565 if (imod && M) { 1566 Inst.setOpcode(ARM::CPS3p); 1567 Inst.addOperand(MCOperand::CreateImm(imod)); 1568 Inst.addOperand(MCOperand::CreateImm(iflags)); 1569 Inst.addOperand(MCOperand::CreateImm(mode)); 1570 } else if (imod && !M) { 1571 Inst.setOpcode(ARM::CPS2p); 1572 Inst.addOperand(MCOperand::CreateImm(imod)); 1573 Inst.addOperand(MCOperand::CreateImm(iflags)); 1574 if (mode) S = MCDisassembler::SoftFail; 1575 } else if (!imod && M) { 1576 Inst.setOpcode(ARM::CPS1p); 1577 Inst.addOperand(MCOperand::CreateImm(mode)); 1578 if (iflags) S = MCDisassembler::SoftFail; 1579 } else { 1580 // imod == '00' && M == '0' --> UNPREDICTABLE 1581 Inst.setOpcode(ARM::CPS1p); 1582 Inst.addOperand(MCOperand::CreateImm(mode)); 1583 S = MCDisassembler::SoftFail; 1584 } 1585 1586 return S; 1587 } 1588 1589 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1590 uint64_t Address, const void *Decoder) { 1591 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1592 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1593 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1594 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1595 1596 DecodeStatus S = MCDisassembler::Success; 1597 1598 // imod == '01' --> UNPREDICTABLE 1599 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1600 // return failure here. The '01' imod value is unprintable, so there's 1601 // nothing useful we could do even if we returned UNPREDICTABLE. 1602 1603 if (imod == 1) return MCDisassembler::Fail; 1604 1605 if (imod && M) { 1606 Inst.setOpcode(ARM::t2CPS3p); 1607 Inst.addOperand(MCOperand::CreateImm(imod)); 1608 Inst.addOperand(MCOperand::CreateImm(iflags)); 1609 Inst.addOperand(MCOperand::CreateImm(mode)); 1610 } else if (imod && !M) { 1611 Inst.setOpcode(ARM::t2CPS2p); 1612 Inst.addOperand(MCOperand::CreateImm(imod)); 1613 Inst.addOperand(MCOperand::CreateImm(iflags)); 1614 if (mode) S = MCDisassembler::SoftFail; 1615 } else if (!imod && M) { 1616 Inst.setOpcode(ARM::t2CPS1p); 1617 Inst.addOperand(MCOperand::CreateImm(mode)); 1618 if (iflags) S = MCDisassembler::SoftFail; 1619 } else { 1620 // imod == '00' && M == '0' --> UNPREDICTABLE 1621 Inst.setOpcode(ARM::t2CPS1p); 1622 Inst.addOperand(MCOperand::CreateImm(mode)); 1623 S = MCDisassembler::SoftFail; 1624 } 1625 1626 return S; 1627 } 1628 1629 1630 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1631 uint64_t Address, const void *Decoder) { 1632 DecodeStatus S = MCDisassembler::Success; 1633 1634 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1635 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1636 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1637 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1638 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1639 1640 if (pred == 0xF) 1641 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1642 1643 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1644 return MCDisassembler::Fail; 1645 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1646 return MCDisassembler::Fail; 1647 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1648 return MCDisassembler::Fail; 1649 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1650 return MCDisassembler::Fail; 1651 1652 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1653 return MCDisassembler::Fail; 1654 1655 return S; 1656 } 1657 1658 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1659 uint64_t Address, const void *Decoder) { 1660 DecodeStatus S = MCDisassembler::Success; 1661 1662 unsigned add = fieldFromInstruction32(Val, 12, 1); 1663 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1664 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1665 1666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1667 return MCDisassembler::Fail; 1668 1669 if (!add) imm *= -1; 1670 if (imm == 0 && !add) imm = INT32_MIN; 1671 Inst.addOperand(MCOperand::CreateImm(imm)); 1672 1673 return S; 1674 } 1675 1676 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1677 uint64_t Address, const void *Decoder) { 1678 DecodeStatus S = MCDisassembler::Success; 1679 1680 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1681 unsigned U = fieldFromInstruction32(Val, 8, 1); 1682 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1683 1684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1685 return MCDisassembler::Fail; 1686 1687 if (U) 1688 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1689 else 1690 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1691 1692 return S; 1693 } 1694 1695 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1696 uint64_t Address, const void *Decoder) { 1697 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1698 } 1699 1700 static DecodeStatus 1701 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1702 uint64_t Address, const void *Decoder) { 1703 DecodeStatus S = MCDisassembler::Success; 1704 1705 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1706 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1707 1708 if (pred == 0xF) { 1709 Inst.setOpcode(ARM::BLXi); 1710 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1711 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1712 return S; 1713 } 1714 1715 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1716 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1717 return MCDisassembler::Fail; 1718 1719 return S; 1720 } 1721 1722 1723 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1724 uint64_t Address, const void *Decoder) { 1725 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1726 return MCDisassembler::Success; 1727 } 1728 1729 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1730 uint64_t Address, const void *Decoder) { 1731 DecodeStatus S = MCDisassembler::Success; 1732 1733 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1734 unsigned align = fieldFromInstruction32(Val, 4, 2); 1735 1736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1737 return MCDisassembler::Fail; 1738 if (!align) 1739 Inst.addOperand(MCOperand::CreateImm(0)); 1740 else 1741 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1742 1743 return S; 1744 } 1745 1746 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1747 uint64_t Address, const void *Decoder) { 1748 DecodeStatus S = MCDisassembler::Success; 1749 1750 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1751 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1752 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1753 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1754 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1755 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1756 1757 // First output register 1758 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1759 return MCDisassembler::Fail; 1760 1761 // Second output register 1762 switch (Inst.getOpcode()) { 1763 case ARM::VLD1q8: 1764 case ARM::VLD1q16: 1765 case ARM::VLD1q32: 1766 case ARM::VLD1q64: 1767 case ARM::VLD1q8_UPD: 1768 case ARM::VLD1q16_UPD: 1769 case ARM::VLD1q32_UPD: 1770 case ARM::VLD1q64_UPD: 1771 case ARM::VLD1d8T: 1772 case ARM::VLD1d16T: 1773 case ARM::VLD1d32T: 1774 case ARM::VLD1d64T: 1775 case ARM::VLD1d8T_UPD: 1776 case ARM::VLD1d16T_UPD: 1777 case ARM::VLD1d32T_UPD: 1778 case ARM::VLD1d64T_UPD: 1779 case ARM::VLD1d8Q: 1780 case ARM::VLD1d16Q: 1781 case ARM::VLD1d32Q: 1782 case ARM::VLD1d64Q: 1783 case ARM::VLD1d8Q_UPD: 1784 case ARM::VLD1d16Q_UPD: 1785 case ARM::VLD1d32Q_UPD: 1786 case ARM::VLD1d64Q_UPD: 1787 case ARM::VLD2d8: 1788 case ARM::VLD2d16: 1789 case ARM::VLD2d32: 1790 case ARM::VLD2d8_UPD: 1791 case ARM::VLD2d16_UPD: 1792 case ARM::VLD2d32_UPD: 1793 case ARM::VLD2q8: 1794 case ARM::VLD2q16: 1795 case ARM::VLD2q32: 1796 case ARM::VLD2q8_UPD: 1797 case ARM::VLD2q16_UPD: 1798 case ARM::VLD2q32_UPD: 1799 case ARM::VLD3d8: 1800 case ARM::VLD3d16: 1801 case ARM::VLD3d32: 1802 case ARM::VLD3d8_UPD: 1803 case ARM::VLD3d16_UPD: 1804 case ARM::VLD3d32_UPD: 1805 case ARM::VLD4d8: 1806 case ARM::VLD4d16: 1807 case ARM::VLD4d32: 1808 case ARM::VLD4d8_UPD: 1809 case ARM::VLD4d16_UPD: 1810 case ARM::VLD4d32_UPD: 1811 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1812 return MCDisassembler::Fail; 1813 break; 1814 case ARM::VLD2b8: 1815 case ARM::VLD2b16: 1816 case ARM::VLD2b32: 1817 case ARM::VLD2b8_UPD: 1818 case ARM::VLD2b16_UPD: 1819 case ARM::VLD2b32_UPD: 1820 case ARM::VLD3q8: 1821 case ARM::VLD3q16: 1822 case ARM::VLD3q32: 1823 case ARM::VLD3q8_UPD: 1824 case ARM::VLD3q16_UPD: 1825 case ARM::VLD3q32_UPD: 1826 case ARM::VLD4q8: 1827 case ARM::VLD4q16: 1828 case ARM::VLD4q32: 1829 case ARM::VLD4q8_UPD: 1830 case ARM::VLD4q16_UPD: 1831 case ARM::VLD4q32_UPD: 1832 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1833 return MCDisassembler::Fail; 1834 default: 1835 break; 1836 } 1837 1838 // Third output register 1839 switch(Inst.getOpcode()) { 1840 case ARM::VLD1d8T: 1841 case ARM::VLD1d16T: 1842 case ARM::VLD1d32T: 1843 case ARM::VLD1d64T: 1844 case ARM::VLD1d8T_UPD: 1845 case ARM::VLD1d16T_UPD: 1846 case ARM::VLD1d32T_UPD: 1847 case ARM::VLD1d64T_UPD: 1848 case ARM::VLD1d8Q: 1849 case ARM::VLD1d16Q: 1850 case ARM::VLD1d32Q: 1851 case ARM::VLD1d64Q: 1852 case ARM::VLD1d8Q_UPD: 1853 case ARM::VLD1d16Q_UPD: 1854 case ARM::VLD1d32Q_UPD: 1855 case ARM::VLD1d64Q_UPD: 1856 case ARM::VLD2q8: 1857 case ARM::VLD2q16: 1858 case ARM::VLD2q32: 1859 case ARM::VLD2q8_UPD: 1860 case ARM::VLD2q16_UPD: 1861 case ARM::VLD2q32_UPD: 1862 case ARM::VLD3d8: 1863 case ARM::VLD3d16: 1864 case ARM::VLD3d32: 1865 case ARM::VLD3d8_UPD: 1866 case ARM::VLD3d16_UPD: 1867 case ARM::VLD3d32_UPD: 1868 case ARM::VLD4d8: 1869 case ARM::VLD4d16: 1870 case ARM::VLD4d32: 1871 case ARM::VLD4d8_UPD: 1872 case ARM::VLD4d16_UPD: 1873 case ARM::VLD4d32_UPD: 1874 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1875 return MCDisassembler::Fail; 1876 break; 1877 case ARM::VLD3q8: 1878 case ARM::VLD3q16: 1879 case ARM::VLD3q32: 1880 case ARM::VLD3q8_UPD: 1881 case ARM::VLD3q16_UPD: 1882 case ARM::VLD3q32_UPD: 1883 case ARM::VLD4q8: 1884 case ARM::VLD4q16: 1885 case ARM::VLD4q32: 1886 case ARM::VLD4q8_UPD: 1887 case ARM::VLD4q16_UPD: 1888 case ARM::VLD4q32_UPD: 1889 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1890 return MCDisassembler::Fail; 1891 break; 1892 default: 1893 break; 1894 } 1895 1896 // Fourth output register 1897 switch (Inst.getOpcode()) { 1898 case ARM::VLD1d8Q: 1899 case ARM::VLD1d16Q: 1900 case ARM::VLD1d32Q: 1901 case ARM::VLD1d64Q: 1902 case ARM::VLD1d8Q_UPD: 1903 case ARM::VLD1d16Q_UPD: 1904 case ARM::VLD1d32Q_UPD: 1905 case ARM::VLD1d64Q_UPD: 1906 case ARM::VLD2q8: 1907 case ARM::VLD2q16: 1908 case ARM::VLD2q32: 1909 case ARM::VLD2q8_UPD: 1910 case ARM::VLD2q16_UPD: 1911 case ARM::VLD2q32_UPD: 1912 case ARM::VLD4d8: 1913 case ARM::VLD4d16: 1914 case ARM::VLD4d32: 1915 case ARM::VLD4d8_UPD: 1916 case ARM::VLD4d16_UPD: 1917 case ARM::VLD4d32_UPD: 1918 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1919 return MCDisassembler::Fail; 1920 break; 1921 case ARM::VLD4q8: 1922 case ARM::VLD4q16: 1923 case ARM::VLD4q32: 1924 case ARM::VLD4q8_UPD: 1925 case ARM::VLD4q16_UPD: 1926 case ARM::VLD4q32_UPD: 1927 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1928 return MCDisassembler::Fail; 1929 break; 1930 default: 1931 break; 1932 } 1933 1934 // Writeback operand 1935 switch (Inst.getOpcode()) { 1936 case ARM::VLD1d8_UPD: 1937 case ARM::VLD1d16_UPD: 1938 case ARM::VLD1d32_UPD: 1939 case ARM::VLD1d64_UPD: 1940 case ARM::VLD1q8_UPD: 1941 case ARM::VLD1q16_UPD: 1942 case ARM::VLD1q32_UPD: 1943 case ARM::VLD1q64_UPD: 1944 case ARM::VLD1d8T_UPD: 1945 case ARM::VLD1d16T_UPD: 1946 case ARM::VLD1d32T_UPD: 1947 case ARM::VLD1d64T_UPD: 1948 case ARM::VLD1d8Q_UPD: 1949 case ARM::VLD1d16Q_UPD: 1950 case ARM::VLD1d32Q_UPD: 1951 case ARM::VLD1d64Q_UPD: 1952 case ARM::VLD2d8_UPD: 1953 case ARM::VLD2d16_UPD: 1954 case ARM::VLD2d32_UPD: 1955 case ARM::VLD2q8_UPD: 1956 case ARM::VLD2q16_UPD: 1957 case ARM::VLD2q32_UPD: 1958 case ARM::VLD2b8_UPD: 1959 case ARM::VLD2b16_UPD: 1960 case ARM::VLD2b32_UPD: 1961 case ARM::VLD3d8_UPD: 1962 case ARM::VLD3d16_UPD: 1963 case ARM::VLD3d32_UPD: 1964 case ARM::VLD3q8_UPD: 1965 case ARM::VLD3q16_UPD: 1966 case ARM::VLD3q32_UPD: 1967 case ARM::VLD4d8_UPD: 1968 case ARM::VLD4d16_UPD: 1969 case ARM::VLD4d32_UPD: 1970 case ARM::VLD4q8_UPD: 1971 case ARM::VLD4q16_UPD: 1972 case ARM::VLD4q32_UPD: 1973 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 break; 1976 default: 1977 break; 1978 } 1979 1980 // AddrMode6 Base (register+alignment) 1981 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 1984 // AddrMode6 Offset (register) 1985 if (Rm == 0xD) 1986 Inst.addOperand(MCOperand::CreateReg(0)); 1987 else if (Rm != 0xF) { 1988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 } 1991 1992 return S; 1993 } 1994 1995 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1996 uint64_t Address, const void *Decoder) { 1997 DecodeStatus S = MCDisassembler::Success; 1998 1999 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2000 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2001 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2002 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2003 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2004 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2005 2006 // Writeback Operand 2007 switch (Inst.getOpcode()) { 2008 case ARM::VST1d8_UPD: 2009 case ARM::VST1d16_UPD: 2010 case ARM::VST1d32_UPD: 2011 case ARM::VST1d64_UPD: 2012 case ARM::VST1q8_UPD: 2013 case ARM::VST1q16_UPD: 2014 case ARM::VST1q32_UPD: 2015 case ARM::VST1q64_UPD: 2016 case ARM::VST1d8T_UPD: 2017 case ARM::VST1d16T_UPD: 2018 case ARM::VST1d32T_UPD: 2019 case ARM::VST1d64T_UPD: 2020 case ARM::VST1d8Q_UPD: 2021 case ARM::VST1d16Q_UPD: 2022 case ARM::VST1d32Q_UPD: 2023 case ARM::VST1d64Q_UPD: 2024 case ARM::VST2d8_UPD: 2025 case ARM::VST2d16_UPD: 2026 case ARM::VST2d32_UPD: 2027 case ARM::VST2q8_UPD: 2028 case ARM::VST2q16_UPD: 2029 case ARM::VST2q32_UPD: 2030 case ARM::VST2b8_UPD: 2031 case ARM::VST2b16_UPD: 2032 case ARM::VST2b32_UPD: 2033 case ARM::VST3d8_UPD: 2034 case ARM::VST3d16_UPD: 2035 case ARM::VST3d32_UPD: 2036 case ARM::VST3q8_UPD: 2037 case ARM::VST3q16_UPD: 2038 case ARM::VST3q32_UPD: 2039 case ARM::VST4d8_UPD: 2040 case ARM::VST4d16_UPD: 2041 case ARM::VST4d32_UPD: 2042 case ARM::VST4q8_UPD: 2043 case ARM::VST4q16_UPD: 2044 case ARM::VST4q32_UPD: 2045 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2046 return MCDisassembler::Fail; 2047 break; 2048 default: 2049 break; 2050 } 2051 2052 // AddrMode6 Base (register+alignment) 2053 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 2056 // AddrMode6 Offset (register) 2057 if (Rm == 0xD) 2058 Inst.addOperand(MCOperand::CreateReg(0)); 2059 else if (Rm != 0xF) { 2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 } 2063 2064 // First input register 2065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2066 return MCDisassembler::Fail; 2067 2068 // Second input register 2069 switch (Inst.getOpcode()) { 2070 case ARM::VST1q8: 2071 case ARM::VST1q16: 2072 case ARM::VST1q32: 2073 case ARM::VST1q64: 2074 case ARM::VST1q8_UPD: 2075 case ARM::VST1q16_UPD: 2076 case ARM::VST1q32_UPD: 2077 case ARM::VST1q64_UPD: 2078 case ARM::VST1d8T: 2079 case ARM::VST1d16T: 2080 case ARM::VST1d32T: 2081 case ARM::VST1d64T: 2082 case ARM::VST1d8T_UPD: 2083 case ARM::VST1d16T_UPD: 2084 case ARM::VST1d32T_UPD: 2085 case ARM::VST1d64T_UPD: 2086 case ARM::VST1d8Q: 2087 case ARM::VST1d16Q: 2088 case ARM::VST1d32Q: 2089 case ARM::VST1d64Q: 2090 case ARM::VST1d8Q_UPD: 2091 case ARM::VST1d16Q_UPD: 2092 case ARM::VST1d32Q_UPD: 2093 case ARM::VST1d64Q_UPD: 2094 case ARM::VST2d8: 2095 case ARM::VST2d16: 2096 case ARM::VST2d32: 2097 case ARM::VST2d8_UPD: 2098 case ARM::VST2d16_UPD: 2099 case ARM::VST2d32_UPD: 2100 case ARM::VST2q8: 2101 case ARM::VST2q16: 2102 case ARM::VST2q32: 2103 case ARM::VST2q8_UPD: 2104 case ARM::VST2q16_UPD: 2105 case ARM::VST2q32_UPD: 2106 case ARM::VST3d8: 2107 case ARM::VST3d16: 2108 case ARM::VST3d32: 2109 case ARM::VST3d8_UPD: 2110 case ARM::VST3d16_UPD: 2111 case ARM::VST3d32_UPD: 2112 case ARM::VST4d8: 2113 case ARM::VST4d16: 2114 case ARM::VST4d32: 2115 case ARM::VST4d8_UPD: 2116 case ARM::VST4d16_UPD: 2117 case ARM::VST4d32_UPD: 2118 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 break; 2121 case ARM::VST2b8: 2122 case ARM::VST2b16: 2123 case ARM::VST2b32: 2124 case ARM::VST2b8_UPD: 2125 case ARM::VST2b16_UPD: 2126 case ARM::VST2b32_UPD: 2127 case ARM::VST3q8: 2128 case ARM::VST3q16: 2129 case ARM::VST3q32: 2130 case ARM::VST3q8_UPD: 2131 case ARM::VST3q16_UPD: 2132 case ARM::VST3q32_UPD: 2133 case ARM::VST4q8: 2134 case ARM::VST4q16: 2135 case ARM::VST4q32: 2136 case ARM::VST4q8_UPD: 2137 case ARM::VST4q16_UPD: 2138 case ARM::VST4q32_UPD: 2139 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 break; 2142 default: 2143 break; 2144 } 2145 2146 // Third input register 2147 switch (Inst.getOpcode()) { 2148 case ARM::VST1d8T: 2149 case ARM::VST1d16T: 2150 case ARM::VST1d32T: 2151 case ARM::VST1d64T: 2152 case ARM::VST1d8T_UPD: 2153 case ARM::VST1d16T_UPD: 2154 case ARM::VST1d32T_UPD: 2155 case ARM::VST1d64T_UPD: 2156 case ARM::VST1d8Q: 2157 case ARM::VST1d16Q: 2158 case ARM::VST1d32Q: 2159 case ARM::VST1d64Q: 2160 case ARM::VST1d8Q_UPD: 2161 case ARM::VST1d16Q_UPD: 2162 case ARM::VST1d32Q_UPD: 2163 case ARM::VST1d64Q_UPD: 2164 case ARM::VST2q8: 2165 case ARM::VST2q16: 2166 case ARM::VST2q32: 2167 case ARM::VST2q8_UPD: 2168 case ARM::VST2q16_UPD: 2169 case ARM::VST2q32_UPD: 2170 case ARM::VST3d8: 2171 case ARM::VST3d16: 2172 case ARM::VST3d32: 2173 case ARM::VST3d8_UPD: 2174 case ARM::VST3d16_UPD: 2175 case ARM::VST3d32_UPD: 2176 case ARM::VST4d8: 2177 case ARM::VST4d16: 2178 case ARM::VST4d32: 2179 case ARM::VST4d8_UPD: 2180 case ARM::VST4d16_UPD: 2181 case ARM::VST4d32_UPD: 2182 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2183 return MCDisassembler::Fail; 2184 break; 2185 case ARM::VST3q8: 2186 case ARM::VST3q16: 2187 case ARM::VST3q32: 2188 case ARM::VST3q8_UPD: 2189 case ARM::VST3q16_UPD: 2190 case ARM::VST3q32_UPD: 2191 case ARM::VST4q8: 2192 case ARM::VST4q16: 2193 case ARM::VST4q32: 2194 case ARM::VST4q8_UPD: 2195 case ARM::VST4q16_UPD: 2196 case ARM::VST4q32_UPD: 2197 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 break; 2200 default: 2201 break; 2202 } 2203 2204 // Fourth input register 2205 switch (Inst.getOpcode()) { 2206 case ARM::VST1d8Q: 2207 case ARM::VST1d16Q: 2208 case ARM::VST1d32Q: 2209 case ARM::VST1d64Q: 2210 case ARM::VST1d8Q_UPD: 2211 case ARM::VST1d16Q_UPD: 2212 case ARM::VST1d32Q_UPD: 2213 case ARM::VST1d64Q_UPD: 2214 case ARM::VST2q8: 2215 case ARM::VST2q16: 2216 case ARM::VST2q32: 2217 case ARM::VST2q8_UPD: 2218 case ARM::VST2q16_UPD: 2219 case ARM::VST2q32_UPD: 2220 case ARM::VST4d8: 2221 case ARM::VST4d16: 2222 case ARM::VST4d32: 2223 case ARM::VST4d8_UPD: 2224 case ARM::VST4d16_UPD: 2225 case ARM::VST4d32_UPD: 2226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2227 return MCDisassembler::Fail; 2228 break; 2229 case ARM::VST4q8: 2230 case ARM::VST4q16: 2231 case ARM::VST4q32: 2232 case ARM::VST4q8_UPD: 2233 case ARM::VST4q16_UPD: 2234 case ARM::VST4q32_UPD: 2235 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2236 return MCDisassembler::Fail; 2237 break; 2238 default: 2239 break; 2240 } 2241 2242 return S; 2243 } 2244 2245 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2246 uint64_t Address, const void *Decoder) { 2247 DecodeStatus S = MCDisassembler::Success; 2248 2249 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2250 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2251 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2252 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2253 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2254 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2255 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2256 2257 align *= (1 << size); 2258 2259 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2260 return MCDisassembler::Fail; 2261 if (regs == 2) { 2262 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 } 2265 if (Rm != 0xF) { 2266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2267 return MCDisassembler::Fail; 2268 } 2269 2270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 Inst.addOperand(MCOperand::CreateImm(align)); 2273 2274 if (Rm == 0xD) 2275 Inst.addOperand(MCOperand::CreateReg(0)); 2276 else if (Rm != 0xF) { 2277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2278 return MCDisassembler::Fail; 2279 } 2280 2281 return S; 2282 } 2283 2284 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2285 uint64_t Address, const void *Decoder) { 2286 DecodeStatus S = MCDisassembler::Success; 2287 2288 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2289 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2290 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2291 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2292 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2293 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2294 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2295 align *= 2*size; 2296 2297 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2300 return MCDisassembler::Fail; 2301 if (Rm != 0xF) { 2302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2303 return MCDisassembler::Fail; 2304 } 2305 2306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2307 return MCDisassembler::Fail; 2308 Inst.addOperand(MCOperand::CreateImm(align)); 2309 2310 if (Rm == 0xD) 2311 Inst.addOperand(MCOperand::CreateReg(0)); 2312 else if (Rm != 0xF) { 2313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2314 return MCDisassembler::Fail; 2315 } 2316 2317 return S; 2318 } 2319 2320 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2321 uint64_t Address, const void *Decoder) { 2322 DecodeStatus S = MCDisassembler::Success; 2323 2324 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2325 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2326 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2327 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2328 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2329 2330 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2331 return MCDisassembler::Fail; 2332 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2333 return MCDisassembler::Fail; 2334 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2335 return MCDisassembler::Fail; 2336 if (Rm != 0xF) { 2337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2338 return MCDisassembler::Fail; 2339 } 2340 2341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2342 return MCDisassembler::Fail; 2343 Inst.addOperand(MCOperand::CreateImm(0)); 2344 2345 if (Rm == 0xD) 2346 Inst.addOperand(MCOperand::CreateReg(0)); 2347 else if (Rm != 0xF) { 2348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2349 return MCDisassembler::Fail; 2350 } 2351 2352 return S; 2353 } 2354 2355 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2356 uint64_t Address, const void *Decoder) { 2357 DecodeStatus S = MCDisassembler::Success; 2358 2359 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2360 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2361 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2362 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2363 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2364 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2365 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2366 2367 if (size == 0x3) { 2368 size = 4; 2369 align = 16; 2370 } else { 2371 if (size == 2) { 2372 size = 1 << size; 2373 align *= 8; 2374 } else { 2375 size = 1 << size; 2376 align *= 4*size; 2377 } 2378 } 2379 2380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2381 return MCDisassembler::Fail; 2382 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2383 return MCDisassembler::Fail; 2384 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2385 return MCDisassembler::Fail; 2386 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2387 return MCDisassembler::Fail; 2388 if (Rm != 0xF) { 2389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2390 return MCDisassembler::Fail; 2391 } 2392 2393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2394 return MCDisassembler::Fail; 2395 Inst.addOperand(MCOperand::CreateImm(align)); 2396 2397 if (Rm == 0xD) 2398 Inst.addOperand(MCOperand::CreateReg(0)); 2399 else if (Rm != 0xF) { 2400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2401 return MCDisassembler::Fail; 2402 } 2403 2404 return S; 2405 } 2406 2407 static DecodeStatus 2408 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2409 uint64_t Address, const void *Decoder) { 2410 DecodeStatus S = MCDisassembler::Success; 2411 2412 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2413 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2414 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2415 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2416 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2417 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2418 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2419 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2420 2421 if (Q) { 2422 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2423 return MCDisassembler::Fail; 2424 } else { 2425 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2426 return MCDisassembler::Fail; 2427 } 2428 2429 Inst.addOperand(MCOperand::CreateImm(imm)); 2430 2431 switch (Inst.getOpcode()) { 2432 case ARM::VORRiv4i16: 2433 case ARM::VORRiv2i32: 2434 case ARM::VBICiv4i16: 2435 case ARM::VBICiv2i32: 2436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 break; 2439 case ARM::VORRiv8i16: 2440 case ARM::VORRiv4i32: 2441 case ARM::VBICiv8i16: 2442 case ARM::VBICiv4i32: 2443 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2444 return MCDisassembler::Fail; 2445 break; 2446 default: 2447 break; 2448 } 2449 2450 return S; 2451 } 2452 2453 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2454 uint64_t Address, const void *Decoder) { 2455 DecodeStatus S = MCDisassembler::Success; 2456 2457 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2458 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2459 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2460 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2461 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2462 2463 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2466 return MCDisassembler::Fail; 2467 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2468 2469 return S; 2470 } 2471 2472 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2473 uint64_t Address, const void *Decoder) { 2474 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2475 return MCDisassembler::Success; 2476 } 2477 2478 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2479 uint64_t Address, const void *Decoder) { 2480 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2481 return MCDisassembler::Success; 2482 } 2483 2484 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2485 uint64_t Address, const void *Decoder) { 2486 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2487 return MCDisassembler::Success; 2488 } 2489 2490 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2491 uint64_t Address, const void *Decoder) { 2492 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2493 return MCDisassembler::Success; 2494 } 2495 2496 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2497 uint64_t Address, const void *Decoder) { 2498 DecodeStatus S = MCDisassembler::Success; 2499 2500 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2501 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2502 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2503 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2504 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2505 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2506 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2507 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2508 2509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 if (op) { 2512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2513 return MCDisassembler::Fail; // Writeback 2514 } 2515 2516 for (unsigned i = 0; i < length; ++i) { 2517 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2518 return MCDisassembler::Fail; 2519 } 2520 2521 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2522 return MCDisassembler::Fail; 2523 2524 return S; 2525 } 2526 2527 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2528 uint64_t Address, const void *Decoder) { 2529 // The immediate needs to be a fully instantiated float. However, the 2530 // auto-generated decoder is only able to fill in some of the bits 2531 // necessary. For instance, the 'b' bit is replicated multiple times, 2532 // and is even present in inverted form in one bit. We do a little 2533 // binary parsing here to fill in those missing bits, and then 2534 // reinterpret it all as a float. 2535 union { 2536 uint32_t integer; 2537 float fp; 2538 } fp_conv; 2539 2540 fp_conv.integer = Val; 2541 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2542 fp_conv.integer |= b << 26; 2543 fp_conv.integer |= b << 27; 2544 fp_conv.integer |= b << 28; 2545 fp_conv.integer |= b << 29; 2546 fp_conv.integer |= (~b & 0x1) << 30; 2547 2548 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2549 return MCDisassembler::Success; 2550 } 2551 2552 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2553 uint64_t Address, const void *Decoder) { 2554 DecodeStatus S = MCDisassembler::Success; 2555 2556 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2557 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2558 2559 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2560 return MCDisassembler::Fail; 2561 2562 switch(Inst.getOpcode()) { 2563 default: 2564 return MCDisassembler::Fail; 2565 case ARM::tADR: 2566 break; // tADR does not explicitly represent the PC as an operand. 2567 case ARM::tADDrSPi: 2568 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2569 break; 2570 } 2571 2572 Inst.addOperand(MCOperand::CreateImm(imm)); 2573 return S; 2574 } 2575 2576 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2577 uint64_t Address, const void *Decoder) { 2578 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2579 return MCDisassembler::Success; 2580 } 2581 2582 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2583 uint64_t Address, const void *Decoder) { 2584 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2585 return MCDisassembler::Success; 2586 } 2587 2588 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2589 uint64_t Address, const void *Decoder) { 2590 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2591 return MCDisassembler::Success; 2592 } 2593 2594 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2595 uint64_t Address, const void *Decoder) { 2596 DecodeStatus S = MCDisassembler::Success; 2597 2598 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2599 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2600 2601 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2602 return MCDisassembler::Fail; 2603 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2604 return MCDisassembler::Fail; 2605 2606 return S; 2607 } 2608 2609 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2610 uint64_t Address, const void *Decoder) { 2611 DecodeStatus S = MCDisassembler::Success; 2612 2613 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2614 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2615 2616 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2617 return MCDisassembler::Fail; 2618 Inst.addOperand(MCOperand::CreateImm(imm)); 2619 2620 return S; 2621 } 2622 2623 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2624 uint64_t Address, const void *Decoder) { 2625 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2626 2627 return MCDisassembler::Success; 2628 } 2629 2630 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2631 uint64_t Address, const void *Decoder) { 2632 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2633 Inst.addOperand(MCOperand::CreateImm(Val)); 2634 2635 return MCDisassembler::Success; 2636 } 2637 2638 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2639 uint64_t Address, const void *Decoder) { 2640 DecodeStatus S = MCDisassembler::Success; 2641 2642 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2643 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2644 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2645 2646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2647 return MCDisassembler::Fail; 2648 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2649 return MCDisassembler::Fail; 2650 Inst.addOperand(MCOperand::CreateImm(imm)); 2651 2652 return S; 2653 } 2654 2655 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2656 uint64_t Address, const void *Decoder) { 2657 DecodeStatus S = MCDisassembler::Success; 2658 2659 switch (Inst.getOpcode()) { 2660 case ARM::t2PLDs: 2661 case ARM::t2PLDWs: 2662 case ARM::t2PLIs: 2663 break; 2664 default: { 2665 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2666 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2667 return MCDisassembler::Fail; 2668 } 2669 } 2670 2671 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2672 if (Rn == 0xF) { 2673 switch (Inst.getOpcode()) { 2674 case ARM::t2LDRBs: 2675 Inst.setOpcode(ARM::t2LDRBpci); 2676 break; 2677 case ARM::t2LDRHs: 2678 Inst.setOpcode(ARM::t2LDRHpci); 2679 break; 2680 case ARM::t2LDRSHs: 2681 Inst.setOpcode(ARM::t2LDRSHpci); 2682 break; 2683 case ARM::t2LDRSBs: 2684 Inst.setOpcode(ARM::t2LDRSBpci); 2685 break; 2686 case ARM::t2PLDs: 2687 Inst.setOpcode(ARM::t2PLDi12); 2688 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2689 break; 2690 default: 2691 return MCDisassembler::Fail; 2692 } 2693 2694 int imm = fieldFromInstruction32(Insn, 0, 12); 2695 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2696 Inst.addOperand(MCOperand::CreateImm(imm)); 2697 2698 return S; 2699 } 2700 2701 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2702 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2703 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2704 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 2707 return S; 2708 } 2709 2710 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2711 uint64_t Address, const void *Decoder) { 2712 int imm = Val & 0xFF; 2713 if (!(Val & 0x100)) imm *= -1; 2714 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2715 2716 return MCDisassembler::Success; 2717 } 2718 2719 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2720 uint64_t Address, const void *Decoder) { 2721 DecodeStatus S = MCDisassembler::Success; 2722 2723 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2724 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2725 2726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 2731 return S; 2732 } 2733 2734 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2735 uint64_t Address, const void *Decoder) { 2736 DecodeStatus S = MCDisassembler::Success; 2737 2738 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2739 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2740 2741 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 2744 Inst.addOperand(MCOperand::CreateImm(imm)); 2745 2746 return S; 2747 } 2748 2749 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2750 uint64_t Address, const void *Decoder) { 2751 int imm = Val & 0xFF; 2752 if (Val == 0) 2753 imm = INT32_MIN; 2754 else if (!(Val & 0x100)) 2755 imm *= -1; 2756 Inst.addOperand(MCOperand::CreateImm(imm)); 2757 2758 return MCDisassembler::Success; 2759 } 2760 2761 2762 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2763 uint64_t Address, const void *Decoder) { 2764 DecodeStatus S = MCDisassembler::Success; 2765 2766 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2767 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2768 2769 // Some instructions always use an additive offset. 2770 switch (Inst.getOpcode()) { 2771 case ARM::t2LDRT: 2772 case ARM::t2LDRBT: 2773 case ARM::t2LDRHT: 2774 case ARM::t2LDRSBT: 2775 case ARM::t2LDRSHT: 2776 case ARM::t2STRT: 2777 case ARM::t2STRBT: 2778 case ARM::t2STRHT: 2779 imm |= 0x100; 2780 break; 2781 default: 2782 break; 2783 } 2784 2785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 2790 return S; 2791 } 2792 2793 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2794 uint64_t Address, const void *Decoder) { 2795 DecodeStatus S = MCDisassembler::Success; 2796 2797 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2798 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2799 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2800 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2801 addr |= Rn << 9; 2802 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2803 2804 if (!load) { 2805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 } 2808 2809 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 2812 if (load) { 2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 } 2816 2817 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2818 return MCDisassembler::Fail; 2819 2820 return S; 2821 } 2822 2823 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2824 uint64_t Address, const void *Decoder) { 2825 DecodeStatus S = MCDisassembler::Success; 2826 2827 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2828 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2829 2830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 Inst.addOperand(MCOperand::CreateImm(imm)); 2833 2834 return S; 2835 } 2836 2837 2838 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2839 uint64_t Address, const void *Decoder) { 2840 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2841 2842 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2843 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2844 Inst.addOperand(MCOperand::CreateImm(imm)); 2845 2846 return MCDisassembler::Success; 2847 } 2848 2849 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2850 uint64_t Address, const void *Decoder) { 2851 DecodeStatus S = MCDisassembler::Success; 2852 2853 if (Inst.getOpcode() == ARM::tADDrSP) { 2854 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2855 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2856 2857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2862 } else if (Inst.getOpcode() == ARM::tADDspr) { 2863 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2864 2865 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2866 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2868 return MCDisassembler::Fail; 2869 } 2870 2871 return S; 2872 } 2873 2874 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2875 uint64_t Address, const void *Decoder) { 2876 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2877 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2878 2879 Inst.addOperand(MCOperand::CreateImm(imod)); 2880 Inst.addOperand(MCOperand::CreateImm(flags)); 2881 2882 return MCDisassembler::Success; 2883 } 2884 2885 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2886 uint64_t Address, const void *Decoder) { 2887 DecodeStatus S = MCDisassembler::Success; 2888 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2889 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2890 2891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 Inst.addOperand(MCOperand::CreateImm(add)); 2894 2895 return S; 2896 } 2897 2898 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2899 uint64_t Address, const void *Decoder) { 2900 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2901 return MCDisassembler::Success; 2902 } 2903 2904 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2905 uint64_t Address, const void *Decoder) { 2906 if (Val == 0xA || Val == 0xB) 2907 return MCDisassembler::Fail; 2908 2909 Inst.addOperand(MCOperand::CreateImm(Val)); 2910 return MCDisassembler::Success; 2911 } 2912 2913 static DecodeStatus 2914 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 2915 uint64_t Address, const void *Decoder) { 2916 DecodeStatus S = MCDisassembler::Success; 2917 2918 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2919 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2920 2921 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 2922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2923 return MCDisassembler::Fail; 2924 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 return S; 2927 } 2928 2929 static DecodeStatus 2930 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2931 uint64_t Address, const void *Decoder) { 2932 DecodeStatus S = MCDisassembler::Success; 2933 2934 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2935 if (pred == 0xE || pred == 0xF) { 2936 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2937 switch (opc) { 2938 default: 2939 return MCDisassembler::Fail; 2940 case 0xf3bf8f4: 2941 Inst.setOpcode(ARM::t2DSB); 2942 break; 2943 case 0xf3bf8f5: 2944 Inst.setOpcode(ARM::t2DMB); 2945 break; 2946 case 0xf3bf8f6: 2947 Inst.setOpcode(ARM::t2ISB); 2948 break; 2949 } 2950 2951 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2952 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2953 } 2954 2955 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2956 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2957 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2958 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2959 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2960 2961 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2964 return MCDisassembler::Fail; 2965 2966 return S; 2967 } 2968 2969 // Decode a shifted immediate operand. These basically consist 2970 // of an 8-bit value, and a 4-bit directive that specifies either 2971 // a splat operation or a rotation. 2972 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2973 uint64_t Address, const void *Decoder) { 2974 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2975 if (ctrl == 0) { 2976 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2977 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2978 switch (byte) { 2979 case 0: 2980 Inst.addOperand(MCOperand::CreateImm(imm)); 2981 break; 2982 case 1: 2983 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2984 break; 2985 case 2: 2986 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2987 break; 2988 case 3: 2989 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2990 (imm << 8) | imm)); 2991 break; 2992 } 2993 } else { 2994 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2995 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2996 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2997 Inst.addOperand(MCOperand::CreateImm(imm)); 2998 } 2999 3000 return MCDisassembler::Success; 3001 } 3002 3003 static DecodeStatus 3004 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3005 uint64_t Address, const void *Decoder){ 3006 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3007 return MCDisassembler::Success; 3008 } 3009 3010 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3011 uint64_t Address, const void *Decoder){ 3012 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3013 return MCDisassembler::Success; 3014 } 3015 3016 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3017 uint64_t Address, const void *Decoder) { 3018 switch (Val) { 3019 default: 3020 return MCDisassembler::Fail; 3021 case 0xF: // SY 3022 case 0xE: // ST 3023 case 0xB: // ISH 3024 case 0xA: // ISHST 3025 case 0x7: // NSH 3026 case 0x6: // NSHST 3027 case 0x3: // OSH 3028 case 0x2: // OSHST 3029 break; 3030 } 3031 3032 Inst.addOperand(MCOperand::CreateImm(Val)); 3033 return MCDisassembler::Success; 3034 } 3035 3036 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3037 uint64_t Address, const void *Decoder) { 3038 if (!Val) return MCDisassembler::Fail; 3039 Inst.addOperand(MCOperand::CreateImm(Val)); 3040 return MCDisassembler::Success; 3041 } 3042 3043 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3044 uint64_t Address, const void *Decoder) { 3045 DecodeStatus S = MCDisassembler::Success; 3046 3047 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3048 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3049 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3050 3051 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3052 3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3056 return MCDisassembler::Fail; 3057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3058 return MCDisassembler::Fail; 3059 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3060 return MCDisassembler::Fail; 3061 3062 return S; 3063 } 3064 3065 3066 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3067 uint64_t Address, const void *Decoder){ 3068 DecodeStatus S = MCDisassembler::Success; 3069 3070 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3071 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3072 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3073 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3074 3075 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 3078 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3079 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3080 3081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3086 return MCDisassembler::Fail; 3087 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 3090 return S; 3091 } 3092 3093 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3094 uint64_t Address, const void *Decoder) { 3095 DecodeStatus S = MCDisassembler::Success; 3096 3097 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3098 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3099 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3100 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3101 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3102 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3103 3104 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3105 3106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3107 return MCDisassembler::Fail; 3108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3111 return MCDisassembler::Fail; 3112 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3113 return MCDisassembler::Fail; 3114 3115 return S; 3116 } 3117 3118 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3119 uint64_t Address, const void *Decoder) { 3120 DecodeStatus S = MCDisassembler::Success; 3121 3122 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3123 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3124 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3125 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3126 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3127 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3128 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3129 3130 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3131 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3132 3133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3134 return MCDisassembler::Fail; 3135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3136 return MCDisassembler::Fail; 3137 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3138 return MCDisassembler::Fail; 3139 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3140 return MCDisassembler::Fail; 3141 3142 return S; 3143 } 3144 3145 3146 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3147 uint64_t Address, const void *Decoder) { 3148 DecodeStatus S = MCDisassembler::Success; 3149 3150 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3151 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3152 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3153 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3154 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3155 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3156 3157 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3158 3159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3160 return MCDisassembler::Fail; 3161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3162 return MCDisassembler::Fail; 3163 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3164 return MCDisassembler::Fail; 3165 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 3168 return S; 3169 } 3170 3171 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3172 uint64_t Address, const void *Decoder) { 3173 DecodeStatus S = MCDisassembler::Success; 3174 3175 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3176 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3177 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3178 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3179 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3180 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3181 3182 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3183 3184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3191 return MCDisassembler::Fail; 3192 3193 return S; 3194 } 3195 3196 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3197 uint64_t Address, const void *Decoder) { 3198 DecodeStatus S = MCDisassembler::Success; 3199 3200 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3201 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3202 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3203 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3204 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3205 3206 unsigned align = 0; 3207 unsigned index = 0; 3208 switch (size) { 3209 default: 3210 return MCDisassembler::Fail; 3211 case 0: 3212 if (fieldFromInstruction32(Insn, 4, 1)) 3213 return MCDisassembler::Fail; // UNDEFINED 3214 index = fieldFromInstruction32(Insn, 5, 3); 3215 break; 3216 case 1: 3217 if (fieldFromInstruction32(Insn, 5, 1)) 3218 return MCDisassembler::Fail; // UNDEFINED 3219 index = fieldFromInstruction32(Insn, 6, 2); 3220 if (fieldFromInstruction32(Insn, 4, 1)) 3221 align = 2; 3222 break; 3223 case 2: 3224 if (fieldFromInstruction32(Insn, 6, 1)) 3225 return MCDisassembler::Fail; // UNDEFINED 3226 index = fieldFromInstruction32(Insn, 7, 1); 3227 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3228 align = 4; 3229 } 3230 3231 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3232 return MCDisassembler::Fail; 3233 if (Rm != 0xF) { // Writeback 3234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 } 3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3238 return MCDisassembler::Fail; 3239 Inst.addOperand(MCOperand::CreateImm(align)); 3240 if (Rm != 0xF) { 3241 if (Rm != 0xD) { 3242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3243 return MCDisassembler::Fail; 3244 } else 3245 Inst.addOperand(MCOperand::CreateReg(0)); 3246 } 3247 3248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 Inst.addOperand(MCOperand::CreateImm(index)); 3251 3252 return S; 3253 } 3254 3255 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3256 uint64_t Address, const void *Decoder) { 3257 DecodeStatus S = MCDisassembler::Success; 3258 3259 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3260 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3261 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3262 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3263 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3264 3265 unsigned align = 0; 3266 unsigned index = 0; 3267 switch (size) { 3268 default: 3269 return MCDisassembler::Fail; 3270 case 0: 3271 if (fieldFromInstruction32(Insn, 4, 1)) 3272 return MCDisassembler::Fail; // UNDEFINED 3273 index = fieldFromInstruction32(Insn, 5, 3); 3274 break; 3275 case 1: 3276 if (fieldFromInstruction32(Insn, 5, 1)) 3277 return MCDisassembler::Fail; // UNDEFINED 3278 index = fieldFromInstruction32(Insn, 6, 2); 3279 if (fieldFromInstruction32(Insn, 4, 1)) 3280 align = 2; 3281 break; 3282 case 2: 3283 if (fieldFromInstruction32(Insn, 6, 1)) 3284 return MCDisassembler::Fail; // UNDEFINED 3285 index = fieldFromInstruction32(Insn, 7, 1); 3286 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3287 align = 4; 3288 } 3289 3290 if (Rm != 0xF) { // Writeback 3291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 } 3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 Inst.addOperand(MCOperand::CreateImm(align)); 3297 if (Rm != 0xF) { 3298 if (Rm != 0xD) { 3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 } else 3302 Inst.addOperand(MCOperand::CreateReg(0)); 3303 } 3304 3305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 Inst.addOperand(MCOperand::CreateImm(index)); 3308 3309 return S; 3310 } 3311 3312 3313 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3314 uint64_t Address, const void *Decoder) { 3315 DecodeStatus S = MCDisassembler::Success; 3316 3317 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3318 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3319 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3320 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3321 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3322 3323 unsigned align = 0; 3324 unsigned index = 0; 3325 unsigned inc = 1; 3326 switch (size) { 3327 default: 3328 return MCDisassembler::Fail; 3329 case 0: 3330 index = fieldFromInstruction32(Insn, 5, 3); 3331 if (fieldFromInstruction32(Insn, 4, 1)) 3332 align = 2; 3333 break; 3334 case 1: 3335 index = fieldFromInstruction32(Insn, 6, 2); 3336 if (fieldFromInstruction32(Insn, 4, 1)) 3337 align = 4; 3338 if (fieldFromInstruction32(Insn, 5, 1)) 3339 inc = 2; 3340 break; 3341 case 2: 3342 if (fieldFromInstruction32(Insn, 5, 1)) 3343 return MCDisassembler::Fail; // UNDEFINED 3344 index = fieldFromInstruction32(Insn, 7, 1); 3345 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3346 align = 8; 3347 if (fieldFromInstruction32(Insn, 6, 1)) 3348 inc = 2; 3349 break; 3350 } 3351 3352 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3353 return MCDisassembler::Fail; 3354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (Rm != 0xF) { // Writeback 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 } 3360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 Inst.addOperand(MCOperand::CreateImm(align)); 3363 if (Rm != 0xF) { 3364 if (Rm != 0xD) { 3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 } else 3368 Inst.addOperand(MCOperand::CreateReg(0)); 3369 } 3370 3371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3372 return MCDisassembler::Fail; 3373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 Inst.addOperand(MCOperand::CreateImm(index)); 3376 3377 return S; 3378 } 3379 3380 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3381 uint64_t Address, const void *Decoder) { 3382 DecodeStatus S = MCDisassembler::Success; 3383 3384 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3385 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3386 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3387 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3388 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3389 3390 unsigned align = 0; 3391 unsigned index = 0; 3392 unsigned inc = 1; 3393 switch (size) { 3394 default: 3395 return MCDisassembler::Fail; 3396 case 0: 3397 index = fieldFromInstruction32(Insn, 5, 3); 3398 if (fieldFromInstruction32(Insn, 4, 1)) 3399 align = 2; 3400 break; 3401 case 1: 3402 index = fieldFromInstruction32(Insn, 6, 2); 3403 if (fieldFromInstruction32(Insn, 4, 1)) 3404 align = 4; 3405 if (fieldFromInstruction32(Insn, 5, 1)) 3406 inc = 2; 3407 break; 3408 case 2: 3409 if (fieldFromInstruction32(Insn, 5, 1)) 3410 return MCDisassembler::Fail; // UNDEFINED 3411 index = fieldFromInstruction32(Insn, 7, 1); 3412 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3413 align = 8; 3414 if (fieldFromInstruction32(Insn, 6, 1)) 3415 inc = 2; 3416 break; 3417 } 3418 3419 if (Rm != 0xF) { // Writeback 3420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3421 return MCDisassembler::Fail; 3422 } 3423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3424 return MCDisassembler::Fail; 3425 Inst.addOperand(MCOperand::CreateImm(align)); 3426 if (Rm != 0xF) { 3427 if (Rm != 0xD) { 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 } else 3431 Inst.addOperand(MCOperand::CreateReg(0)); 3432 } 3433 3434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3435 return MCDisassembler::Fail; 3436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3437 return MCDisassembler::Fail; 3438 Inst.addOperand(MCOperand::CreateImm(index)); 3439 3440 return S; 3441 } 3442 3443 3444 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3445 uint64_t Address, const void *Decoder) { 3446 DecodeStatus S = MCDisassembler::Success; 3447 3448 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3449 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3450 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3451 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3452 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3453 3454 unsigned align = 0; 3455 unsigned index = 0; 3456 unsigned inc = 1; 3457 switch (size) { 3458 default: 3459 return MCDisassembler::Fail; 3460 case 0: 3461 if (fieldFromInstruction32(Insn, 4, 1)) 3462 return MCDisassembler::Fail; // UNDEFINED 3463 index = fieldFromInstruction32(Insn, 5, 3); 3464 break; 3465 case 1: 3466 if (fieldFromInstruction32(Insn, 4, 1)) 3467 return MCDisassembler::Fail; // UNDEFINED 3468 index = fieldFromInstruction32(Insn, 6, 2); 3469 if (fieldFromInstruction32(Insn, 5, 1)) 3470 inc = 2; 3471 break; 3472 case 2: 3473 if (fieldFromInstruction32(Insn, 4, 2)) 3474 return MCDisassembler::Fail; // UNDEFINED 3475 index = fieldFromInstruction32(Insn, 7, 1); 3476 if (fieldFromInstruction32(Insn, 6, 1)) 3477 inc = 2; 3478 break; 3479 } 3480 3481 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3484 return MCDisassembler::Fail; 3485 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 3488 if (Rm != 0xF) { // Writeback 3489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 } 3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 Inst.addOperand(MCOperand::CreateImm(align)); 3495 if (Rm != 0xF) { 3496 if (Rm != 0xD) { 3497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3498 return MCDisassembler::Fail; 3499 } else 3500 Inst.addOperand(MCOperand::CreateReg(0)); 3501 } 3502 3503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 Inst.addOperand(MCOperand::CreateImm(index)); 3510 3511 return S; 3512 } 3513 3514 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3515 uint64_t Address, const void *Decoder) { 3516 DecodeStatus S = MCDisassembler::Success; 3517 3518 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3519 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3520 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3521 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3522 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3523 3524 unsigned align = 0; 3525 unsigned index = 0; 3526 unsigned inc = 1; 3527 switch (size) { 3528 default: 3529 return MCDisassembler::Fail; 3530 case 0: 3531 if (fieldFromInstruction32(Insn, 4, 1)) 3532 return MCDisassembler::Fail; // UNDEFINED 3533 index = fieldFromInstruction32(Insn, 5, 3); 3534 break; 3535 case 1: 3536 if (fieldFromInstruction32(Insn, 4, 1)) 3537 return MCDisassembler::Fail; // UNDEFINED 3538 index = fieldFromInstruction32(Insn, 6, 2); 3539 if (fieldFromInstruction32(Insn, 5, 1)) 3540 inc = 2; 3541 break; 3542 case 2: 3543 if (fieldFromInstruction32(Insn, 4, 2)) 3544 return MCDisassembler::Fail; // UNDEFINED 3545 index = fieldFromInstruction32(Insn, 7, 1); 3546 if (fieldFromInstruction32(Insn, 6, 1)) 3547 inc = 2; 3548 break; 3549 } 3550 3551 if (Rm != 0xF) { // Writeback 3552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3553 return MCDisassembler::Fail; 3554 } 3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 Inst.addOperand(MCOperand::CreateImm(align)); 3558 if (Rm != 0xF) { 3559 if (Rm != 0xD) { 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 } else 3563 Inst.addOperand(MCOperand::CreateReg(0)); 3564 } 3565 3566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 Inst.addOperand(MCOperand::CreateImm(index)); 3573 3574 return S; 3575 } 3576 3577 3578 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3579 uint64_t Address, const void *Decoder) { 3580 DecodeStatus S = MCDisassembler::Success; 3581 3582 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3583 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3584 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3585 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3586 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3587 3588 unsigned align = 0; 3589 unsigned index = 0; 3590 unsigned inc = 1; 3591 switch (size) { 3592 default: 3593 return MCDisassembler::Fail; 3594 case 0: 3595 if (fieldFromInstruction32(Insn, 4, 1)) 3596 align = 4; 3597 index = fieldFromInstruction32(Insn, 5, 3); 3598 break; 3599 case 1: 3600 if (fieldFromInstruction32(Insn, 4, 1)) 3601 align = 8; 3602 index = fieldFromInstruction32(Insn, 6, 2); 3603 if (fieldFromInstruction32(Insn, 5, 1)) 3604 inc = 2; 3605 break; 3606 case 2: 3607 if (fieldFromInstruction32(Insn, 4, 2)) 3608 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3609 index = fieldFromInstruction32(Insn, 7, 1); 3610 if (fieldFromInstruction32(Insn, 6, 1)) 3611 inc = 2; 3612 break; 3613 } 3614 3615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 3624 if (Rm != 0xF) { // Writeback 3625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 } 3628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3629 return MCDisassembler::Fail; 3630 Inst.addOperand(MCOperand::CreateImm(align)); 3631 if (Rm != 0xF) { 3632 if (Rm != 0xD) { 3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 } else 3636 Inst.addOperand(MCOperand::CreateReg(0)); 3637 } 3638 3639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3640 return MCDisassembler::Fail; 3641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3644 return MCDisassembler::Fail; 3645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 Inst.addOperand(MCOperand::CreateImm(index)); 3648 3649 return S; 3650 } 3651 3652 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3653 uint64_t Address, const void *Decoder) { 3654 DecodeStatus S = MCDisassembler::Success; 3655 3656 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3657 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3658 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3659 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3660 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3661 3662 unsigned align = 0; 3663 unsigned index = 0; 3664 unsigned inc = 1; 3665 switch (size) { 3666 default: 3667 return MCDisassembler::Fail; 3668 case 0: 3669 if (fieldFromInstruction32(Insn, 4, 1)) 3670 align = 4; 3671 index = fieldFromInstruction32(Insn, 5, 3); 3672 break; 3673 case 1: 3674 if (fieldFromInstruction32(Insn, 4, 1)) 3675 align = 8; 3676 index = fieldFromInstruction32(Insn, 6, 2); 3677 if (fieldFromInstruction32(Insn, 5, 1)) 3678 inc = 2; 3679 break; 3680 case 2: 3681 if (fieldFromInstruction32(Insn, 4, 2)) 3682 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3683 index = fieldFromInstruction32(Insn, 7, 1); 3684 if (fieldFromInstruction32(Insn, 6, 1)) 3685 inc = 2; 3686 break; 3687 } 3688 3689 if (Rm != 0xF) { // Writeback 3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 } 3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3694 return MCDisassembler::Fail; 3695 Inst.addOperand(MCOperand::CreateImm(align)); 3696 if (Rm != 0xF) { 3697 if (Rm != 0xD) { 3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 } else 3701 Inst.addOperand(MCOperand::CreateReg(0)); 3702 } 3703 3704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3707 return MCDisassembler::Fail; 3708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 Inst.addOperand(MCOperand::CreateImm(index)); 3713 3714 return S; 3715 } 3716 3717 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3718 uint64_t Address, const void *Decoder) { 3719 DecodeStatus S = MCDisassembler::Success; 3720 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3721 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3722 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3723 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3724 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3725 3726 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3727 S = MCDisassembler::SoftFail; 3728 3729 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3734 return MCDisassembler::Fail; 3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3736 return MCDisassembler::Fail; 3737 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3738 return MCDisassembler::Fail; 3739 3740 return S; 3741 } 3742 3743 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3744 uint64_t Address, const void *Decoder) { 3745 DecodeStatus S = MCDisassembler::Success; 3746 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3747 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3748 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3749 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3750 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3751 3752 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3753 S = MCDisassembler::SoftFail; 3754 3755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3756 return MCDisassembler::Fail; 3757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3764 return MCDisassembler::Fail; 3765 3766 return S; 3767 } 3768 3769 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3770 uint64_t Address, const void *Decoder) { 3771 DecodeStatus S = MCDisassembler::Success; 3772 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3773 // The InstPrinter needs to have the low bit of the predicate in 3774 // the mask operand to be able to print it properly. 3775 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3776 3777 if (pred == 0xF) { 3778 pred = 0xE; 3779 S = MCDisassembler::SoftFail; 3780 } 3781 3782 if ((mask & 0xF) == 0) { 3783 // Preserve the high bit of the mask, which is the low bit of 3784 // the predicate. 3785 mask &= 0x10; 3786 mask |= 0x8; 3787 S = MCDisassembler::SoftFail; 3788 } 3789 3790 Inst.addOperand(MCOperand::CreateImm(pred)); 3791 Inst.addOperand(MCOperand::CreateImm(mask)); 3792 return S; 3793 } 3794 3795 static DecodeStatus 3796 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3797 uint64_t Address, const void *Decoder) { 3798 DecodeStatus S = MCDisassembler::Success; 3799 3800 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3801 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3802 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3803 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3804 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3805 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3806 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3807 bool writeback = (W == 1) | (P == 0); 3808 3809 addr |= (U << 8) | (Rn << 9); 3810 3811 if (writeback && (Rn == Rt || Rn == Rt2)) 3812 Check(S, MCDisassembler::SoftFail); 3813 if (Rt == Rt2) 3814 Check(S, MCDisassembler::SoftFail); 3815 3816 // Rt 3817 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 // Rt2 3820 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3821 return MCDisassembler::Fail; 3822 // Writeback operand 3823 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3824 return MCDisassembler::Fail; 3825 // addr 3826 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3827 return MCDisassembler::Fail; 3828 3829 return S; 3830 } 3831 3832 static DecodeStatus 3833 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3834 uint64_t Address, const void *Decoder) { 3835 DecodeStatus S = MCDisassembler::Success; 3836 3837 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3838 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3839 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3840 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3841 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3842 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3843 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3844 bool writeback = (W == 1) | (P == 0); 3845 3846 addr |= (U << 8) | (Rn << 9); 3847 3848 if (writeback && (Rn == Rt || Rn == Rt2)) 3849 Check(S, MCDisassembler::SoftFail); 3850 3851 // Writeback operand 3852 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3853 return MCDisassembler::Fail; 3854 // Rt 3855 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 // Rt2 3858 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 // addr 3861 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3862 return MCDisassembler::Fail; 3863 3864 return S; 3865 } 3866 3867 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 3868 uint64_t Address, const void *Decoder) { 3869 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 3870 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 3871 if (sign1 != sign2) return MCDisassembler::Fail; 3872 3873 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 3874 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 3875 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 3876 Val |= sign1 << 12; 3877 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 3878 3879 return MCDisassembler::Success; 3880 } 3881 3882 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 3883 uint64_t Address, 3884 const void *Decoder) { 3885 DecodeStatus S = MCDisassembler::Success; 3886 3887 // Shift of "asr #32" is not allowed in Thumb2 mode. 3888 if (Val == 0x20) S = MCDisassembler::SoftFail; 3889 Inst.addOperand(MCOperand::CreateImm(Val)); 3890 return S; 3891 } 3892 3893