1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 EDInstInfo *getEDInfo() const; 55 private: 56 }; 57 58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59 class ThumbDisassembler : public MCDisassembler { 60 public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 EDInstInfo *getEDInfo() const; 80 private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84 }; 85 } 86 87 static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 return false; 100 } 101 102 103 // Forward declare these because the autogenerated code will reference them. 104 // Definitions are further down. 105 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128 129 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 142 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 147 unsigned Insn, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 159 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 160 unsigned Insn, 161 uint64_t Adddress, 162 const void *Decoder); 163 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 250 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 311 312 #include "ARMGenDisassemblerTables.inc" 313 #include "ARMGenInstrInfo.inc" 314 #include "ARMGenEDInfo.inc" 315 316 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 317 return new ARMDisassembler(STI); 318 } 319 320 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 321 return new ThumbDisassembler(STI); 322 } 323 324 EDInstInfo *ARMDisassembler::getEDInfo() const { 325 return instInfoARM; 326 } 327 328 EDInstInfo *ThumbDisassembler::getEDInfo() const { 329 return instInfoARM; 330 } 331 332 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 333 const MemoryObject &Region, 334 uint64_t Address, 335 raw_ostream &os, 336 raw_ostream &cs) const { 337 uint8_t bytes[4]; 338 339 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 340 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 341 342 // We want to read exactly 4 bytes of data. 343 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 344 Size = 0; 345 return MCDisassembler::Fail; 346 } 347 348 // Encoded as a small-endian 32-bit word in the stream. 349 uint32_t insn = (bytes[3] << 24) | 350 (bytes[2] << 16) | 351 (bytes[1] << 8) | 352 (bytes[0] << 0); 353 354 // Calling the auto-generated decoder function. 355 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 356 if (result != MCDisassembler::Fail) { 357 Size = 4; 358 return result; 359 } 360 361 // VFP and NEON instructions, similarly, are shared between ARM 362 // and Thumb modes. 363 MI.clear(); 364 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 365 if (result != MCDisassembler::Fail) { 366 Size = 4; 367 return result; 368 } 369 370 MI.clear(); 371 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 372 if (result != MCDisassembler::Fail) { 373 Size = 4; 374 // Add a fake predicate operand, because we share these instruction 375 // definitions with Thumb2 where these instructions are predicable. 376 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 377 return MCDisassembler::Fail; 378 return result; 379 } 380 381 MI.clear(); 382 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 // Add a fake predicate operand, because we share these instruction 386 // definitions with Thumb2 where these instructions are predicable. 387 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 388 return MCDisassembler::Fail; 389 return result; 390 } 391 392 MI.clear(); 393 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 394 if (result != MCDisassembler::Fail) { 395 Size = 4; 396 // Add a fake predicate operand, because we share these instruction 397 // definitions with Thumb2 where these instructions are predicable. 398 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 399 return MCDisassembler::Fail; 400 return result; 401 } 402 403 MI.clear(); 404 405 Size = 0; 406 return MCDisassembler::Fail; 407 } 408 409 namespace llvm { 410 extern MCInstrDesc ARMInsts[]; 411 } 412 413 // Thumb1 instructions don't have explicit S bits. Rather, they 414 // implicitly set CPSR. Since it's not represented in the encoding, the 415 // auto-generated decoder won't inject the CPSR operand. We need to fix 416 // that as a post-pass. 417 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 418 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 419 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 420 MCInst::iterator I = MI.begin(); 421 for (unsigned i = 0; i < NumOps; ++i, ++I) { 422 if (I == MI.end()) break; 423 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 424 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 426 return; 427 } 428 } 429 430 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 431 } 432 433 // Most Thumb instructions don't have explicit predicates in the 434 // encoding, but rather get their predicates from IT context. We need 435 // to fix up the predicate operands using this context information as a 436 // post-pass. 437 MCDisassembler::DecodeStatus 438 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 439 MCDisassembler::DecodeStatus S = Success; 440 441 // A few instructions actually have predicates encoded in them. Don't 442 // try to overwrite it if we're seeing one of those. 443 switch (MI.getOpcode()) { 444 case ARM::tBcc: 445 case ARM::t2Bcc: 446 case ARM::tCBZ: 447 case ARM::tCBNZ: 448 // Some instructions (mostly conditional branches) are not 449 // allowed in IT blocks. 450 if (!ITBlock.empty()) 451 S = SoftFail; 452 else 453 return Success; 454 break; 455 case ARM::tB: 456 case ARM::t2B: 457 case ARM::t2TBB: 458 case ARM::t2TBH: 459 // Some instructions (mostly unconditional branches) can 460 // only appears at the end of, or outside of, an IT. 461 if (ITBlock.size() > 1) 462 S = SoftFail; 463 break; 464 default: 465 break; 466 } 467 468 // If we're in an IT block, base the predicate on that. Otherwise, 469 // assume a predicate of AL. 470 unsigned CC; 471 if (!ITBlock.empty()) { 472 CC = ITBlock.back(); 473 if (CC == 0xF) 474 CC = ARMCC::AL; 475 ITBlock.pop_back(); 476 } else 477 CC = ARMCC::AL; 478 479 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 480 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 481 MCInst::iterator I = MI.begin(); 482 for (unsigned i = 0; i < NumOps; ++i, ++I) { 483 if (I == MI.end()) break; 484 if (OpInfo[i].isPredicate()) { 485 I = MI.insert(I, MCOperand::CreateImm(CC)); 486 ++I; 487 if (CC == ARMCC::AL) 488 MI.insert(I, MCOperand::CreateReg(0)); 489 else 490 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 491 return S; 492 } 493 } 494 495 I = MI.insert(I, MCOperand::CreateImm(CC)); 496 ++I; 497 if (CC == ARMCC::AL) 498 MI.insert(I, MCOperand::CreateReg(0)); 499 else 500 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 501 502 return S; 503 } 504 505 // Thumb VFP instructions are a special case. Because we share their 506 // encodings between ARM and Thumb modes, and they are predicable in ARM 507 // mode, the auto-generated decoder will give them an (incorrect) 508 // predicate operand. We need to rewrite these operands based on the IT 509 // context as a post-pass. 510 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 511 unsigned CC; 512 if (!ITBlock.empty()) { 513 CC = ITBlock.back(); 514 ITBlock.pop_back(); 515 } else 516 CC = ARMCC::AL; 517 518 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 519 MCInst::iterator I = MI.begin(); 520 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 521 for (unsigned i = 0; i < NumOps; ++i, ++I) { 522 if (OpInfo[i].isPredicate() ) { 523 I->setImm(CC); 524 ++I; 525 if (CC == ARMCC::AL) 526 I->setReg(0); 527 else 528 I->setReg(ARM::CPSR); 529 return; 530 } 531 } 532 } 533 534 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 535 const MemoryObject &Region, 536 uint64_t Address, 537 raw_ostream &os, 538 raw_ostream &cs) const { 539 uint8_t bytes[4]; 540 541 assert((STI.getFeatureBits() & ARM::ModeThumb) && 542 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 543 544 // We want to read exactly 2 bytes of data. 545 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 546 Size = 0; 547 return MCDisassembler::Fail; 548 } 549 550 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 551 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 552 if (result != MCDisassembler::Fail) { 553 Size = 2; 554 Check(result, AddThumbPredicate(MI)); 555 return result; 556 } 557 558 MI.clear(); 559 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 560 if (result) { 561 Size = 2; 562 bool InITBlock = !ITBlock.empty(); 563 Check(result, AddThumbPredicate(MI)); 564 AddThumb1SBit(MI, InITBlock); 565 return result; 566 } 567 568 MI.clear(); 569 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 570 if (result != MCDisassembler::Fail) { 571 Size = 2; 572 Check(result, AddThumbPredicate(MI)); 573 574 // If we find an IT instruction, we need to parse its condition 575 // code and mask operands so that we can apply them correctly 576 // to the subsequent instructions. 577 if (MI.getOpcode() == ARM::t2IT) { 578 // Nested IT blocks are UNPREDICTABLE. 579 if (!ITBlock.empty()) 580 return MCDisassembler::SoftFail; 581 582 // (3 - the number of trailing zeros) is the number of then / else. 583 unsigned firstcond = MI.getOperand(0).getImm(); 584 unsigned Mask = MI.getOperand(1).getImm(); 585 unsigned CondBit0 = Mask >> 4 & 1; 586 unsigned NumTZ = CountTrailingZeros_32(Mask); 587 assert(NumTZ <= 3 && "Invalid IT mask!"); 588 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 589 bool T = ((Mask >> Pos) & 1) == CondBit0; 590 if (T) 591 ITBlock.insert(ITBlock.begin(), firstcond); 592 else 593 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 594 } 595 596 ITBlock.push_back(firstcond); 597 } 598 599 return result; 600 } 601 602 // We want to read exactly 4 bytes of data. 603 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 604 Size = 0; 605 return MCDisassembler::Fail; 606 } 607 608 uint32_t insn32 = (bytes[3] << 8) | 609 (bytes[2] << 0) | 610 (bytes[1] << 24) | 611 (bytes[0] << 16); 612 MI.clear(); 613 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 614 if (result != MCDisassembler::Fail) { 615 Size = 4; 616 bool InITBlock = ITBlock.size(); 617 Check(result, AddThumbPredicate(MI)); 618 AddThumb1SBit(MI, InITBlock); 619 return result; 620 } 621 622 MI.clear(); 623 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 624 if (result != MCDisassembler::Fail) { 625 Size = 4; 626 Check(result, AddThumbPredicate(MI)); 627 return result; 628 } 629 630 MI.clear(); 631 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 632 if (result != MCDisassembler::Fail) { 633 Size = 4; 634 UpdateThumbVFPPredicate(MI); 635 return result; 636 } 637 638 MI.clear(); 639 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 640 if (result != MCDisassembler::Fail) { 641 Size = 4; 642 Check(result, AddThumbPredicate(MI)); 643 return result; 644 } 645 646 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 647 MI.clear(); 648 uint32_t NEONLdStInsn = insn32; 649 NEONLdStInsn &= 0xF0FFFFFF; 650 NEONLdStInsn |= 0x04000000; 651 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 652 if (result != MCDisassembler::Fail) { 653 Size = 4; 654 Check(result, AddThumbPredicate(MI)); 655 return result; 656 } 657 } 658 659 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 660 MI.clear(); 661 uint32_t NEONDataInsn = insn32; 662 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 663 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 664 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 665 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 666 if (result != MCDisassembler::Fail) { 667 Size = 4; 668 Check(result, AddThumbPredicate(MI)); 669 return result; 670 } 671 } 672 673 Size = 0; 674 return MCDisassembler::Fail; 675 } 676 677 678 extern "C" void LLVMInitializeARMDisassembler() { 679 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 680 createARMDisassembler); 681 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 682 createThumbDisassembler); 683 } 684 685 static const unsigned GPRDecoderTable[] = { 686 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 687 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 688 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 689 ARM::R12, ARM::SP, ARM::LR, ARM::PC 690 }; 691 692 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 693 uint64_t Address, const void *Decoder) { 694 if (RegNo > 15) 695 return MCDisassembler::Fail; 696 697 unsigned Register = GPRDecoderTable[RegNo]; 698 Inst.addOperand(MCOperand::CreateReg(Register)); 699 return MCDisassembler::Success; 700 } 701 702 static DecodeStatus 703 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 704 uint64_t Address, const void *Decoder) { 705 if (RegNo == 15) return MCDisassembler::Fail; 706 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 707 } 708 709 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 710 uint64_t Address, const void *Decoder) { 711 if (RegNo > 7) 712 return MCDisassembler::Fail; 713 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 714 } 715 716 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 717 uint64_t Address, const void *Decoder) { 718 unsigned Register = 0; 719 switch (RegNo) { 720 case 0: 721 Register = ARM::R0; 722 break; 723 case 1: 724 Register = ARM::R1; 725 break; 726 case 2: 727 Register = ARM::R2; 728 break; 729 case 3: 730 Register = ARM::R3; 731 break; 732 case 9: 733 Register = ARM::R9; 734 break; 735 case 12: 736 Register = ARM::R12; 737 break; 738 default: 739 return MCDisassembler::Fail; 740 } 741 742 Inst.addOperand(MCOperand::CreateReg(Register)); 743 return MCDisassembler::Success; 744 } 745 746 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 747 uint64_t Address, const void *Decoder) { 748 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 749 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 750 } 751 752 static const unsigned SPRDecoderTable[] = { 753 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 754 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 755 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 756 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 757 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 758 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 759 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 760 ARM::S28, ARM::S29, ARM::S30, ARM::S31 761 }; 762 763 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 764 uint64_t Address, const void *Decoder) { 765 if (RegNo > 31) 766 return MCDisassembler::Fail; 767 768 unsigned Register = SPRDecoderTable[RegNo]; 769 Inst.addOperand(MCOperand::CreateReg(Register)); 770 return MCDisassembler::Success; 771 } 772 773 static const unsigned DPRDecoderTable[] = { 774 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 775 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 776 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 777 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 778 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 779 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 780 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 781 ARM::D28, ARM::D29, ARM::D30, ARM::D31 782 }; 783 784 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 785 uint64_t Address, const void *Decoder) { 786 if (RegNo > 31) 787 return MCDisassembler::Fail; 788 789 unsigned Register = DPRDecoderTable[RegNo]; 790 Inst.addOperand(MCOperand::CreateReg(Register)); 791 return MCDisassembler::Success; 792 } 793 794 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 795 uint64_t Address, const void *Decoder) { 796 if (RegNo > 7) 797 return MCDisassembler::Fail; 798 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 799 } 800 801 static DecodeStatus 802 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 803 uint64_t Address, const void *Decoder) { 804 if (RegNo > 15) 805 return MCDisassembler::Fail; 806 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 807 } 808 809 static const unsigned QPRDecoderTable[] = { 810 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 811 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 812 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 813 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 814 }; 815 816 817 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 818 uint64_t Address, const void *Decoder) { 819 if (RegNo > 31) 820 return MCDisassembler::Fail; 821 RegNo >>= 1; 822 823 unsigned Register = QPRDecoderTable[RegNo]; 824 Inst.addOperand(MCOperand::CreateReg(Register)); 825 return MCDisassembler::Success; 826 } 827 828 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 829 uint64_t Address, const void *Decoder) { 830 if (Val == 0xF) return MCDisassembler::Fail; 831 // AL predicate is not allowed on Thumb1 branches. 832 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 833 return MCDisassembler::Fail; 834 Inst.addOperand(MCOperand::CreateImm(Val)); 835 if (Val == ARMCC::AL) { 836 Inst.addOperand(MCOperand::CreateReg(0)); 837 } else 838 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 839 return MCDisassembler::Success; 840 } 841 842 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 843 uint64_t Address, const void *Decoder) { 844 if (Val) 845 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 846 else 847 Inst.addOperand(MCOperand::CreateReg(0)); 848 return MCDisassembler::Success; 849 } 850 851 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 852 uint64_t Address, const void *Decoder) { 853 uint32_t imm = Val & 0xFF; 854 uint32_t rot = (Val & 0xF00) >> 7; 855 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 856 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 857 return MCDisassembler::Success; 858 } 859 860 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 861 uint64_t Address, const void *Decoder) { 862 DecodeStatus S = MCDisassembler::Success; 863 864 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 865 unsigned type = fieldFromInstruction32(Val, 5, 2); 866 unsigned imm = fieldFromInstruction32(Val, 7, 5); 867 868 // Register-immediate 869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 870 return MCDisassembler::Fail; 871 872 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 873 switch (type) { 874 case 0: 875 Shift = ARM_AM::lsl; 876 break; 877 case 1: 878 Shift = ARM_AM::lsr; 879 break; 880 case 2: 881 Shift = ARM_AM::asr; 882 break; 883 case 3: 884 Shift = ARM_AM::ror; 885 break; 886 } 887 888 if (Shift == ARM_AM::ror && imm == 0) 889 Shift = ARM_AM::rrx; 890 891 unsigned Op = Shift | (imm << 3); 892 Inst.addOperand(MCOperand::CreateImm(Op)); 893 894 return S; 895 } 896 897 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 898 uint64_t Address, const void *Decoder) { 899 DecodeStatus S = MCDisassembler::Success; 900 901 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 902 unsigned type = fieldFromInstruction32(Val, 5, 2); 903 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 904 905 // Register-register 906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 907 return MCDisassembler::Fail; 908 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 909 return MCDisassembler::Fail; 910 911 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 912 switch (type) { 913 case 0: 914 Shift = ARM_AM::lsl; 915 break; 916 case 1: 917 Shift = ARM_AM::lsr; 918 break; 919 case 2: 920 Shift = ARM_AM::asr; 921 break; 922 case 3: 923 Shift = ARM_AM::ror; 924 break; 925 } 926 927 Inst.addOperand(MCOperand::CreateImm(Shift)); 928 929 return S; 930 } 931 932 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 933 uint64_t Address, const void *Decoder) { 934 DecodeStatus S = MCDisassembler::Success; 935 936 bool writebackLoad = false; 937 unsigned writebackReg = 0; 938 switch (Inst.getOpcode()) { 939 default: 940 break; 941 case ARM::LDMIA_UPD: 942 case ARM::LDMDB_UPD: 943 case ARM::LDMIB_UPD: 944 case ARM::LDMDA_UPD: 945 case ARM::t2LDMIA_UPD: 946 case ARM::t2LDMDB_UPD: 947 writebackLoad = true; 948 writebackReg = Inst.getOperand(0).getReg(); 949 break; 950 } 951 952 // Empty register lists are not allowed. 953 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 954 for (unsigned i = 0; i < 16; ++i) { 955 if (Val & (1 << i)) { 956 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 957 return MCDisassembler::Fail; 958 // Writeback not allowed if Rn is in the target list. 959 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 960 Check(S, MCDisassembler::SoftFail); 961 } 962 } 963 964 return S; 965 } 966 967 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 968 uint64_t Address, const void *Decoder) { 969 DecodeStatus S = MCDisassembler::Success; 970 971 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 972 unsigned regs = Val & 0xFF; 973 974 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 975 return MCDisassembler::Fail; 976 for (unsigned i = 0; i < (regs - 1); ++i) { 977 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 978 return MCDisassembler::Fail; 979 } 980 981 return S; 982 } 983 984 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 985 uint64_t Address, const void *Decoder) { 986 DecodeStatus S = MCDisassembler::Success; 987 988 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 989 unsigned regs = (Val & 0xFF) / 2; 990 991 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 992 return MCDisassembler::Fail; 993 for (unsigned i = 0; i < (regs - 1); ++i) { 994 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 995 return MCDisassembler::Fail; 996 } 997 998 return S; 999 } 1000 1001 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1002 uint64_t Address, const void *Decoder) { 1003 // This operand encodes a mask of contiguous zeros between a specified MSB 1004 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1005 // the mask of all bits LSB-and-lower, and then xor them to create 1006 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1007 // create the final mask. 1008 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1009 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1010 1011 DecodeStatus S = MCDisassembler::Success; 1012 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1013 1014 uint32_t msb_mask = 0xFFFFFFFF; 1015 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1016 uint32_t lsb_mask = (1U << lsb) - 1; 1017 1018 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1019 return S; 1020 } 1021 1022 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1023 uint64_t Address, const void *Decoder) { 1024 DecodeStatus S = MCDisassembler::Success; 1025 1026 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1027 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1028 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1029 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1030 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1031 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1032 1033 switch (Inst.getOpcode()) { 1034 case ARM::LDC_OFFSET: 1035 case ARM::LDC_PRE: 1036 case ARM::LDC_POST: 1037 case ARM::LDC_OPTION: 1038 case ARM::LDCL_OFFSET: 1039 case ARM::LDCL_PRE: 1040 case ARM::LDCL_POST: 1041 case ARM::LDCL_OPTION: 1042 case ARM::STC_OFFSET: 1043 case ARM::STC_PRE: 1044 case ARM::STC_POST: 1045 case ARM::STC_OPTION: 1046 case ARM::STCL_OFFSET: 1047 case ARM::STCL_PRE: 1048 case ARM::STCL_POST: 1049 case ARM::STCL_OPTION: 1050 case ARM::t2LDC_OFFSET: 1051 case ARM::t2LDC_PRE: 1052 case ARM::t2LDC_POST: 1053 case ARM::t2LDC_OPTION: 1054 case ARM::t2LDCL_OFFSET: 1055 case ARM::t2LDCL_PRE: 1056 case ARM::t2LDCL_POST: 1057 case ARM::t2LDCL_OPTION: 1058 case ARM::t2STC_OFFSET: 1059 case ARM::t2STC_PRE: 1060 case ARM::t2STC_POST: 1061 case ARM::t2STC_OPTION: 1062 case ARM::t2STCL_OFFSET: 1063 case ARM::t2STCL_PRE: 1064 case ARM::t2STCL_POST: 1065 case ARM::t2STCL_OPTION: 1066 if (coproc == 0xA || coproc == 0xB) 1067 return MCDisassembler::Fail; 1068 break; 1069 default: 1070 break; 1071 } 1072 1073 Inst.addOperand(MCOperand::CreateImm(coproc)); 1074 Inst.addOperand(MCOperand::CreateImm(CRd)); 1075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1076 return MCDisassembler::Fail; 1077 switch (Inst.getOpcode()) { 1078 case ARM::LDC_OPTION: 1079 case ARM::LDCL_OPTION: 1080 case ARM::LDC2_OPTION: 1081 case ARM::LDC2L_OPTION: 1082 case ARM::STC_OPTION: 1083 case ARM::STCL_OPTION: 1084 case ARM::STC2_OPTION: 1085 case ARM::STC2L_OPTION: 1086 case ARM::LDCL_POST: 1087 case ARM::STCL_POST: 1088 case ARM::LDC2L_POST: 1089 case ARM::STC2L_POST: 1090 case ARM::t2LDC_OPTION: 1091 case ARM::t2LDCL_OPTION: 1092 case ARM::t2STC_OPTION: 1093 case ARM::t2STCL_OPTION: 1094 case ARM::t2LDCL_POST: 1095 case ARM::t2STCL_POST: 1096 break; 1097 default: 1098 Inst.addOperand(MCOperand::CreateReg(0)); 1099 break; 1100 } 1101 1102 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1103 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1104 1105 bool writeback = (P == 0) || (W == 1); 1106 unsigned idx_mode = 0; 1107 if (P && writeback) 1108 idx_mode = ARMII::IndexModePre; 1109 else if (!P && writeback) 1110 idx_mode = ARMII::IndexModePost; 1111 1112 switch (Inst.getOpcode()) { 1113 case ARM::LDCL_POST: 1114 case ARM::STCL_POST: 1115 case ARM::t2LDCL_POST: 1116 case ARM::t2STCL_POST: 1117 case ARM::LDC2L_POST: 1118 case ARM::STC2L_POST: 1119 imm |= U << 8; 1120 case ARM::LDC_OPTION: 1121 case ARM::LDCL_OPTION: 1122 case ARM::LDC2_OPTION: 1123 case ARM::LDC2L_OPTION: 1124 case ARM::STC_OPTION: 1125 case ARM::STCL_OPTION: 1126 case ARM::STC2_OPTION: 1127 case ARM::STC2L_OPTION: 1128 case ARM::t2LDC_OPTION: 1129 case ARM::t2LDCL_OPTION: 1130 case ARM::t2STC_OPTION: 1131 case ARM::t2STCL_OPTION: 1132 Inst.addOperand(MCOperand::CreateImm(imm)); 1133 break; 1134 default: 1135 if (U) 1136 Inst.addOperand(MCOperand::CreateImm( 1137 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1138 else 1139 Inst.addOperand(MCOperand::CreateImm( 1140 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1141 break; 1142 } 1143 1144 switch (Inst.getOpcode()) { 1145 case ARM::LDC_OFFSET: 1146 case ARM::LDC_PRE: 1147 case ARM::LDC_POST: 1148 case ARM::LDC_OPTION: 1149 case ARM::LDCL_OFFSET: 1150 case ARM::LDCL_PRE: 1151 case ARM::LDCL_POST: 1152 case ARM::LDCL_OPTION: 1153 case ARM::STC_OFFSET: 1154 case ARM::STC_PRE: 1155 case ARM::STC_POST: 1156 case ARM::STC_OPTION: 1157 case ARM::STCL_OFFSET: 1158 case ARM::STCL_PRE: 1159 case ARM::STCL_POST: 1160 case ARM::STCL_OPTION: 1161 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1162 return MCDisassembler::Fail; 1163 break; 1164 default: 1165 break; 1166 } 1167 1168 return S; 1169 } 1170 1171 static DecodeStatus 1172 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1173 uint64_t Address, const void *Decoder) { 1174 DecodeStatus S = MCDisassembler::Success; 1175 1176 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1177 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1178 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1179 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1180 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1181 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1182 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1183 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1184 1185 // On stores, the writeback operand precedes Rt. 1186 switch (Inst.getOpcode()) { 1187 case ARM::STR_POST_IMM: 1188 case ARM::STR_POST_REG: 1189 case ARM::STRB_POST_IMM: 1190 case ARM::STRB_POST_REG: 1191 case ARM::STRT_POST_REG: 1192 case ARM::STRT_POST_IMM: 1193 case ARM::STRBT_POST_REG: 1194 case ARM::STRBT_POST_IMM: 1195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1196 return MCDisassembler::Fail; 1197 break; 1198 default: 1199 break; 1200 } 1201 1202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1203 return MCDisassembler::Fail; 1204 1205 // On loads, the writeback operand comes after Rt. 1206 switch (Inst.getOpcode()) { 1207 case ARM::LDR_POST_IMM: 1208 case ARM::LDR_POST_REG: 1209 case ARM::LDRB_POST_IMM: 1210 case ARM::LDRB_POST_REG: 1211 case ARM::LDRBT_POST_REG: 1212 case ARM::LDRBT_POST_IMM: 1213 case ARM::LDRT_POST_REG: 1214 case ARM::LDRT_POST_IMM: 1215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1216 return MCDisassembler::Fail; 1217 break; 1218 default: 1219 break; 1220 } 1221 1222 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1223 return MCDisassembler::Fail; 1224 1225 ARM_AM::AddrOpc Op = ARM_AM::add; 1226 if (!fieldFromInstruction32(Insn, 23, 1)) 1227 Op = ARM_AM::sub; 1228 1229 bool writeback = (P == 0) || (W == 1); 1230 unsigned idx_mode = 0; 1231 if (P && writeback) 1232 idx_mode = ARMII::IndexModePre; 1233 else if (!P && writeback) 1234 idx_mode = ARMII::IndexModePost; 1235 1236 if (writeback && (Rn == 15 || Rn == Rt)) 1237 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1238 1239 if (reg) { 1240 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1241 return MCDisassembler::Fail; 1242 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1243 switch( fieldFromInstruction32(Insn, 5, 2)) { 1244 case 0: 1245 Opc = ARM_AM::lsl; 1246 break; 1247 case 1: 1248 Opc = ARM_AM::lsr; 1249 break; 1250 case 2: 1251 Opc = ARM_AM::asr; 1252 break; 1253 case 3: 1254 Opc = ARM_AM::ror; 1255 break; 1256 default: 1257 return MCDisassembler::Fail; 1258 } 1259 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1260 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1261 1262 Inst.addOperand(MCOperand::CreateImm(imm)); 1263 } else { 1264 Inst.addOperand(MCOperand::CreateReg(0)); 1265 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1266 Inst.addOperand(MCOperand::CreateImm(tmp)); 1267 } 1268 1269 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1270 return MCDisassembler::Fail; 1271 1272 return S; 1273 } 1274 1275 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1276 uint64_t Address, const void *Decoder) { 1277 DecodeStatus S = MCDisassembler::Success; 1278 1279 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1280 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1281 unsigned type = fieldFromInstruction32(Val, 5, 2); 1282 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1283 unsigned U = fieldFromInstruction32(Val, 12, 1); 1284 1285 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1286 switch (type) { 1287 case 0: 1288 ShOp = ARM_AM::lsl; 1289 break; 1290 case 1: 1291 ShOp = ARM_AM::lsr; 1292 break; 1293 case 2: 1294 ShOp = ARM_AM::asr; 1295 break; 1296 case 3: 1297 ShOp = ARM_AM::ror; 1298 break; 1299 } 1300 1301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1302 return MCDisassembler::Fail; 1303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1304 return MCDisassembler::Fail; 1305 unsigned shift; 1306 if (U) 1307 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1308 else 1309 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1310 Inst.addOperand(MCOperand::CreateImm(shift)); 1311 1312 return S; 1313 } 1314 1315 static DecodeStatus 1316 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1317 uint64_t Address, const void *Decoder) { 1318 DecodeStatus S = MCDisassembler::Success; 1319 1320 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1321 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1322 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1323 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1324 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1325 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1326 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1327 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1328 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1329 1330 bool writeback = (W == 1) | (P == 0); 1331 1332 // For {LD,ST}RD, Rt must be even, else undefined. 1333 switch (Inst.getOpcode()) { 1334 case ARM::STRD: 1335 case ARM::STRD_PRE: 1336 case ARM::STRD_POST: 1337 case ARM::LDRD: 1338 case ARM::LDRD_PRE: 1339 case ARM::LDRD_POST: 1340 if (Rt & 0x1) return MCDisassembler::Fail; 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 if (writeback) { // Writeback 1347 if (P) 1348 U |= ARMII::IndexModePre << 9; 1349 else 1350 U |= ARMII::IndexModePost << 9; 1351 1352 // On stores, the writeback operand precedes Rt. 1353 switch (Inst.getOpcode()) { 1354 case ARM::STRD: 1355 case ARM::STRD_PRE: 1356 case ARM::STRD_POST: 1357 case ARM::STRH: 1358 case ARM::STRH_PRE: 1359 case ARM::STRH_POST: 1360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1361 return MCDisassembler::Fail; 1362 break; 1363 default: 1364 break; 1365 } 1366 } 1367 1368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1369 return MCDisassembler::Fail; 1370 switch (Inst.getOpcode()) { 1371 case ARM::STRD: 1372 case ARM::STRD_PRE: 1373 case ARM::STRD_POST: 1374 case ARM::LDRD: 1375 case ARM::LDRD_PRE: 1376 case ARM::LDRD_POST: 1377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1378 return MCDisassembler::Fail; 1379 break; 1380 default: 1381 break; 1382 } 1383 1384 if (writeback) { 1385 // On loads, the writeback operand comes after Rt. 1386 switch (Inst.getOpcode()) { 1387 case ARM::LDRD: 1388 case ARM::LDRD_PRE: 1389 case ARM::LDRD_POST: 1390 case ARM::LDRH: 1391 case ARM::LDRH_PRE: 1392 case ARM::LDRH_POST: 1393 case ARM::LDRSH: 1394 case ARM::LDRSH_PRE: 1395 case ARM::LDRSH_POST: 1396 case ARM::LDRSB: 1397 case ARM::LDRSB_PRE: 1398 case ARM::LDRSB_POST: 1399 case ARM::LDRHTr: 1400 case ARM::LDRSBTr: 1401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1402 return MCDisassembler::Fail; 1403 break; 1404 default: 1405 break; 1406 } 1407 } 1408 1409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1410 return MCDisassembler::Fail; 1411 1412 if (type) { 1413 Inst.addOperand(MCOperand::CreateReg(0)); 1414 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1415 } else { 1416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1417 return MCDisassembler::Fail; 1418 Inst.addOperand(MCOperand::CreateImm(U)); 1419 } 1420 1421 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1422 return MCDisassembler::Fail; 1423 1424 return S; 1425 } 1426 1427 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1428 uint64_t Address, const void *Decoder) { 1429 DecodeStatus S = MCDisassembler::Success; 1430 1431 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1432 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1433 1434 switch (mode) { 1435 case 0: 1436 mode = ARM_AM::da; 1437 break; 1438 case 1: 1439 mode = ARM_AM::ia; 1440 break; 1441 case 2: 1442 mode = ARM_AM::db; 1443 break; 1444 case 3: 1445 mode = ARM_AM::ib; 1446 break; 1447 } 1448 1449 Inst.addOperand(MCOperand::CreateImm(mode)); 1450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1451 return MCDisassembler::Fail; 1452 1453 return S; 1454 } 1455 1456 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1457 unsigned Insn, 1458 uint64_t Address, const void *Decoder) { 1459 DecodeStatus S = MCDisassembler::Success; 1460 1461 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1462 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1463 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1464 1465 if (pred == 0xF) { 1466 switch (Inst.getOpcode()) { 1467 case ARM::LDMDA: 1468 Inst.setOpcode(ARM::RFEDA); 1469 break; 1470 case ARM::LDMDA_UPD: 1471 Inst.setOpcode(ARM::RFEDA_UPD); 1472 break; 1473 case ARM::LDMDB: 1474 Inst.setOpcode(ARM::RFEDB); 1475 break; 1476 case ARM::LDMDB_UPD: 1477 Inst.setOpcode(ARM::RFEDB_UPD); 1478 break; 1479 case ARM::LDMIA: 1480 Inst.setOpcode(ARM::RFEIA); 1481 break; 1482 case ARM::LDMIA_UPD: 1483 Inst.setOpcode(ARM::RFEIA_UPD); 1484 break; 1485 case ARM::LDMIB: 1486 Inst.setOpcode(ARM::RFEIB); 1487 break; 1488 case ARM::LDMIB_UPD: 1489 Inst.setOpcode(ARM::RFEIB_UPD); 1490 break; 1491 case ARM::STMDA: 1492 Inst.setOpcode(ARM::SRSDA); 1493 break; 1494 case ARM::STMDA_UPD: 1495 Inst.setOpcode(ARM::SRSDA_UPD); 1496 break; 1497 case ARM::STMDB: 1498 Inst.setOpcode(ARM::SRSDB); 1499 break; 1500 case ARM::STMDB_UPD: 1501 Inst.setOpcode(ARM::SRSDB_UPD); 1502 break; 1503 case ARM::STMIA: 1504 Inst.setOpcode(ARM::SRSIA); 1505 break; 1506 case ARM::STMIA_UPD: 1507 Inst.setOpcode(ARM::SRSIA_UPD); 1508 break; 1509 case ARM::STMIB: 1510 Inst.setOpcode(ARM::SRSIB); 1511 break; 1512 case ARM::STMIB_UPD: 1513 Inst.setOpcode(ARM::SRSIB_UPD); 1514 break; 1515 default: 1516 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1517 } 1518 1519 // For stores (which become SRS's, the only operand is the mode. 1520 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1521 Inst.addOperand( 1522 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1523 return S; 1524 } 1525 1526 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1527 } 1528 1529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1530 return MCDisassembler::Fail; 1531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1532 return MCDisassembler::Fail; // Tied 1533 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1534 return MCDisassembler::Fail; 1535 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1536 return MCDisassembler::Fail; 1537 1538 return S; 1539 } 1540 1541 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1542 uint64_t Address, const void *Decoder) { 1543 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1544 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1545 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1546 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1547 1548 DecodeStatus S = MCDisassembler::Success; 1549 1550 // imod == '01' --> UNPREDICTABLE 1551 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1552 // return failure here. The '01' imod value is unprintable, so there's 1553 // nothing useful we could do even if we returned UNPREDICTABLE. 1554 1555 if (imod == 1) return MCDisassembler::Fail; 1556 1557 if (imod && M) { 1558 Inst.setOpcode(ARM::CPS3p); 1559 Inst.addOperand(MCOperand::CreateImm(imod)); 1560 Inst.addOperand(MCOperand::CreateImm(iflags)); 1561 Inst.addOperand(MCOperand::CreateImm(mode)); 1562 } else if (imod && !M) { 1563 Inst.setOpcode(ARM::CPS2p); 1564 Inst.addOperand(MCOperand::CreateImm(imod)); 1565 Inst.addOperand(MCOperand::CreateImm(iflags)); 1566 if (mode) S = MCDisassembler::SoftFail; 1567 } else if (!imod && M) { 1568 Inst.setOpcode(ARM::CPS1p); 1569 Inst.addOperand(MCOperand::CreateImm(mode)); 1570 if (iflags) S = MCDisassembler::SoftFail; 1571 } else { 1572 // imod == '00' && M == '0' --> UNPREDICTABLE 1573 Inst.setOpcode(ARM::CPS1p); 1574 Inst.addOperand(MCOperand::CreateImm(mode)); 1575 S = MCDisassembler::SoftFail; 1576 } 1577 1578 return S; 1579 } 1580 1581 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1582 uint64_t Address, const void *Decoder) { 1583 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1584 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1585 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1586 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1587 1588 DecodeStatus S = MCDisassembler::Success; 1589 1590 // imod == '01' --> UNPREDICTABLE 1591 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1592 // return failure here. The '01' imod value is unprintable, so there's 1593 // nothing useful we could do even if we returned UNPREDICTABLE. 1594 1595 if (imod == 1) return MCDisassembler::Fail; 1596 1597 if (imod && M) { 1598 Inst.setOpcode(ARM::t2CPS3p); 1599 Inst.addOperand(MCOperand::CreateImm(imod)); 1600 Inst.addOperand(MCOperand::CreateImm(iflags)); 1601 Inst.addOperand(MCOperand::CreateImm(mode)); 1602 } else if (imod && !M) { 1603 Inst.setOpcode(ARM::t2CPS2p); 1604 Inst.addOperand(MCOperand::CreateImm(imod)); 1605 Inst.addOperand(MCOperand::CreateImm(iflags)); 1606 if (mode) S = MCDisassembler::SoftFail; 1607 } else if (!imod && M) { 1608 Inst.setOpcode(ARM::t2CPS1p); 1609 Inst.addOperand(MCOperand::CreateImm(mode)); 1610 if (iflags) S = MCDisassembler::SoftFail; 1611 } else { 1612 // imod == '00' && M == '0' --> UNPREDICTABLE 1613 Inst.setOpcode(ARM::t2CPS1p); 1614 Inst.addOperand(MCOperand::CreateImm(mode)); 1615 S = MCDisassembler::SoftFail; 1616 } 1617 1618 return S; 1619 } 1620 1621 1622 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1623 uint64_t Address, const void *Decoder) { 1624 DecodeStatus S = MCDisassembler::Success; 1625 1626 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1627 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1628 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1629 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1630 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1631 1632 if (pred == 0xF) 1633 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1634 1635 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1636 return MCDisassembler::Fail; 1637 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1638 return MCDisassembler::Fail; 1639 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1640 return MCDisassembler::Fail; 1641 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1642 return MCDisassembler::Fail; 1643 1644 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1645 return MCDisassembler::Fail; 1646 1647 return S; 1648 } 1649 1650 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1651 uint64_t Address, const void *Decoder) { 1652 DecodeStatus S = MCDisassembler::Success; 1653 1654 unsigned add = fieldFromInstruction32(Val, 12, 1); 1655 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1656 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1657 1658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1659 return MCDisassembler::Fail; 1660 1661 if (!add) imm *= -1; 1662 if (imm == 0 && !add) imm = INT32_MIN; 1663 Inst.addOperand(MCOperand::CreateImm(imm)); 1664 1665 return S; 1666 } 1667 1668 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1669 uint64_t Address, const void *Decoder) { 1670 DecodeStatus S = MCDisassembler::Success; 1671 1672 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1673 unsigned U = fieldFromInstruction32(Val, 8, 1); 1674 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1675 1676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1677 return MCDisassembler::Fail; 1678 1679 if (U) 1680 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1681 else 1682 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1683 1684 return S; 1685 } 1686 1687 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1688 uint64_t Address, const void *Decoder) { 1689 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1690 } 1691 1692 static DecodeStatus 1693 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1694 uint64_t Address, const void *Decoder) { 1695 DecodeStatus S = MCDisassembler::Success; 1696 1697 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1698 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1699 1700 if (pred == 0xF) { 1701 Inst.setOpcode(ARM::BLXi); 1702 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1703 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1704 return S; 1705 } 1706 1707 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1708 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1709 return MCDisassembler::Fail; 1710 1711 return S; 1712 } 1713 1714 1715 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1716 uint64_t Address, const void *Decoder) { 1717 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1718 return MCDisassembler::Success; 1719 } 1720 1721 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1722 uint64_t Address, const void *Decoder) { 1723 DecodeStatus S = MCDisassembler::Success; 1724 1725 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1726 unsigned align = fieldFromInstruction32(Val, 4, 2); 1727 1728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1729 return MCDisassembler::Fail; 1730 if (!align) 1731 Inst.addOperand(MCOperand::CreateImm(0)); 1732 else 1733 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1734 1735 return S; 1736 } 1737 1738 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1739 uint64_t Address, const void *Decoder) { 1740 DecodeStatus S = MCDisassembler::Success; 1741 1742 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1743 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1744 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1745 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1746 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1747 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1748 1749 // First output register 1750 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1751 return MCDisassembler::Fail; 1752 1753 // Second output register 1754 switch (Inst.getOpcode()) { 1755 case ARM::VLD1q8: 1756 case ARM::VLD1q16: 1757 case ARM::VLD1q32: 1758 case ARM::VLD1q64: 1759 case ARM::VLD1q8_UPD: 1760 case ARM::VLD1q16_UPD: 1761 case ARM::VLD1q32_UPD: 1762 case ARM::VLD1q64_UPD: 1763 case ARM::VLD1d8T: 1764 case ARM::VLD1d16T: 1765 case ARM::VLD1d32T: 1766 case ARM::VLD1d64T: 1767 case ARM::VLD1d8T_UPD: 1768 case ARM::VLD1d16T_UPD: 1769 case ARM::VLD1d32T_UPD: 1770 case ARM::VLD1d64T_UPD: 1771 case ARM::VLD1d8Q: 1772 case ARM::VLD1d16Q: 1773 case ARM::VLD1d32Q: 1774 case ARM::VLD1d64Q: 1775 case ARM::VLD1d8Q_UPD: 1776 case ARM::VLD1d16Q_UPD: 1777 case ARM::VLD1d32Q_UPD: 1778 case ARM::VLD1d64Q_UPD: 1779 case ARM::VLD2d8: 1780 case ARM::VLD2d16: 1781 case ARM::VLD2d32: 1782 case ARM::VLD2d8_UPD: 1783 case ARM::VLD2d16_UPD: 1784 case ARM::VLD2d32_UPD: 1785 case ARM::VLD2q8: 1786 case ARM::VLD2q16: 1787 case ARM::VLD2q32: 1788 case ARM::VLD2q8_UPD: 1789 case ARM::VLD2q16_UPD: 1790 case ARM::VLD2q32_UPD: 1791 case ARM::VLD3d8: 1792 case ARM::VLD3d16: 1793 case ARM::VLD3d32: 1794 case ARM::VLD3d8_UPD: 1795 case ARM::VLD3d16_UPD: 1796 case ARM::VLD3d32_UPD: 1797 case ARM::VLD4d8: 1798 case ARM::VLD4d16: 1799 case ARM::VLD4d32: 1800 case ARM::VLD4d8_UPD: 1801 case ARM::VLD4d16_UPD: 1802 case ARM::VLD4d32_UPD: 1803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1804 return MCDisassembler::Fail; 1805 break; 1806 case ARM::VLD2b8: 1807 case ARM::VLD2b16: 1808 case ARM::VLD2b32: 1809 case ARM::VLD2b8_UPD: 1810 case ARM::VLD2b16_UPD: 1811 case ARM::VLD2b32_UPD: 1812 case ARM::VLD3q8: 1813 case ARM::VLD3q16: 1814 case ARM::VLD3q32: 1815 case ARM::VLD3q8_UPD: 1816 case ARM::VLD3q16_UPD: 1817 case ARM::VLD3q32_UPD: 1818 case ARM::VLD4q8: 1819 case ARM::VLD4q16: 1820 case ARM::VLD4q32: 1821 case ARM::VLD4q8_UPD: 1822 case ARM::VLD4q16_UPD: 1823 case ARM::VLD4q32_UPD: 1824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 default: 1827 break; 1828 } 1829 1830 // Third output register 1831 switch(Inst.getOpcode()) { 1832 case ARM::VLD1d8T: 1833 case ARM::VLD1d16T: 1834 case ARM::VLD1d32T: 1835 case ARM::VLD1d64T: 1836 case ARM::VLD1d8T_UPD: 1837 case ARM::VLD1d16T_UPD: 1838 case ARM::VLD1d32T_UPD: 1839 case ARM::VLD1d64T_UPD: 1840 case ARM::VLD1d8Q: 1841 case ARM::VLD1d16Q: 1842 case ARM::VLD1d32Q: 1843 case ARM::VLD1d64Q: 1844 case ARM::VLD1d8Q_UPD: 1845 case ARM::VLD1d16Q_UPD: 1846 case ARM::VLD1d32Q_UPD: 1847 case ARM::VLD1d64Q_UPD: 1848 case ARM::VLD2q8: 1849 case ARM::VLD2q16: 1850 case ARM::VLD2q32: 1851 case ARM::VLD2q8_UPD: 1852 case ARM::VLD2q16_UPD: 1853 case ARM::VLD2q32_UPD: 1854 case ARM::VLD3d8: 1855 case ARM::VLD3d16: 1856 case ARM::VLD3d32: 1857 case ARM::VLD3d8_UPD: 1858 case ARM::VLD3d16_UPD: 1859 case ARM::VLD3d32_UPD: 1860 case ARM::VLD4d8: 1861 case ARM::VLD4d16: 1862 case ARM::VLD4d32: 1863 case ARM::VLD4d8_UPD: 1864 case ARM::VLD4d16_UPD: 1865 case ARM::VLD4d32_UPD: 1866 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 break; 1869 case ARM::VLD3q8: 1870 case ARM::VLD3q16: 1871 case ARM::VLD3q32: 1872 case ARM::VLD3q8_UPD: 1873 case ARM::VLD3q16_UPD: 1874 case ARM::VLD3q32_UPD: 1875 case ARM::VLD4q8: 1876 case ARM::VLD4q16: 1877 case ARM::VLD4q32: 1878 case ARM::VLD4q8_UPD: 1879 case ARM::VLD4q16_UPD: 1880 case ARM::VLD4q32_UPD: 1881 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1882 return MCDisassembler::Fail; 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 // Fourth output register 1889 switch (Inst.getOpcode()) { 1890 case ARM::VLD1d8Q: 1891 case ARM::VLD1d16Q: 1892 case ARM::VLD1d32Q: 1893 case ARM::VLD1d64Q: 1894 case ARM::VLD1d8Q_UPD: 1895 case ARM::VLD1d16Q_UPD: 1896 case ARM::VLD1d32Q_UPD: 1897 case ARM::VLD1d64Q_UPD: 1898 case ARM::VLD2q8: 1899 case ARM::VLD2q16: 1900 case ARM::VLD2q32: 1901 case ARM::VLD2q8_UPD: 1902 case ARM::VLD2q16_UPD: 1903 case ARM::VLD2q32_UPD: 1904 case ARM::VLD4d8: 1905 case ARM::VLD4d16: 1906 case ARM::VLD4d32: 1907 case ARM::VLD4d8_UPD: 1908 case ARM::VLD4d16_UPD: 1909 case ARM::VLD4d32_UPD: 1910 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1911 return MCDisassembler::Fail; 1912 break; 1913 case ARM::VLD4q8: 1914 case ARM::VLD4q16: 1915 case ARM::VLD4q32: 1916 case ARM::VLD4q8_UPD: 1917 case ARM::VLD4q16_UPD: 1918 case ARM::VLD4q32_UPD: 1919 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1920 return MCDisassembler::Fail; 1921 break; 1922 default: 1923 break; 1924 } 1925 1926 // Writeback operand 1927 switch (Inst.getOpcode()) { 1928 case ARM::VLD1d8_UPD: 1929 case ARM::VLD1d16_UPD: 1930 case ARM::VLD1d32_UPD: 1931 case ARM::VLD1d64_UPD: 1932 case ARM::VLD1q8_UPD: 1933 case ARM::VLD1q16_UPD: 1934 case ARM::VLD1q32_UPD: 1935 case ARM::VLD1q64_UPD: 1936 case ARM::VLD1d8T_UPD: 1937 case ARM::VLD1d16T_UPD: 1938 case ARM::VLD1d32T_UPD: 1939 case ARM::VLD1d64T_UPD: 1940 case ARM::VLD1d8Q_UPD: 1941 case ARM::VLD1d16Q_UPD: 1942 case ARM::VLD1d32Q_UPD: 1943 case ARM::VLD1d64Q_UPD: 1944 case ARM::VLD2d8_UPD: 1945 case ARM::VLD2d16_UPD: 1946 case ARM::VLD2d32_UPD: 1947 case ARM::VLD2q8_UPD: 1948 case ARM::VLD2q16_UPD: 1949 case ARM::VLD2q32_UPD: 1950 case ARM::VLD2b8_UPD: 1951 case ARM::VLD2b16_UPD: 1952 case ARM::VLD2b32_UPD: 1953 case ARM::VLD3d8_UPD: 1954 case ARM::VLD3d16_UPD: 1955 case ARM::VLD3d32_UPD: 1956 case ARM::VLD3q8_UPD: 1957 case ARM::VLD3q16_UPD: 1958 case ARM::VLD3q32_UPD: 1959 case ARM::VLD4d8_UPD: 1960 case ARM::VLD4d16_UPD: 1961 case ARM::VLD4d32_UPD: 1962 case ARM::VLD4q8_UPD: 1963 case ARM::VLD4q16_UPD: 1964 case ARM::VLD4q32_UPD: 1965 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1966 return MCDisassembler::Fail; 1967 break; 1968 default: 1969 break; 1970 } 1971 1972 // AddrMode6 Base (register+alignment) 1973 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 1976 // AddrMode6 Offset (register) 1977 if (Rm == 0xD) 1978 Inst.addOperand(MCOperand::CreateReg(0)); 1979 else if (Rm != 0xF) { 1980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 } 1983 1984 return S; 1985 } 1986 1987 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1988 uint64_t Address, const void *Decoder) { 1989 DecodeStatus S = MCDisassembler::Success; 1990 1991 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1992 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1993 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1994 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1995 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1996 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1997 1998 // Writeback Operand 1999 switch (Inst.getOpcode()) { 2000 case ARM::VST1d8_UPD: 2001 case ARM::VST1d16_UPD: 2002 case ARM::VST1d32_UPD: 2003 case ARM::VST1d64_UPD: 2004 case ARM::VST1q8_UPD: 2005 case ARM::VST1q16_UPD: 2006 case ARM::VST1q32_UPD: 2007 case ARM::VST1q64_UPD: 2008 case ARM::VST1d8T_UPD: 2009 case ARM::VST1d16T_UPD: 2010 case ARM::VST1d32T_UPD: 2011 case ARM::VST1d64T_UPD: 2012 case ARM::VST1d8Q_UPD: 2013 case ARM::VST1d16Q_UPD: 2014 case ARM::VST1d32Q_UPD: 2015 case ARM::VST1d64Q_UPD: 2016 case ARM::VST2d8_UPD: 2017 case ARM::VST2d16_UPD: 2018 case ARM::VST2d32_UPD: 2019 case ARM::VST2q8_UPD: 2020 case ARM::VST2q16_UPD: 2021 case ARM::VST2q32_UPD: 2022 case ARM::VST2b8_UPD: 2023 case ARM::VST2b16_UPD: 2024 case ARM::VST2b32_UPD: 2025 case ARM::VST3d8_UPD: 2026 case ARM::VST3d16_UPD: 2027 case ARM::VST3d32_UPD: 2028 case ARM::VST3q8_UPD: 2029 case ARM::VST3q16_UPD: 2030 case ARM::VST3q32_UPD: 2031 case ARM::VST4d8_UPD: 2032 case ARM::VST4d16_UPD: 2033 case ARM::VST4d32_UPD: 2034 case ARM::VST4q8_UPD: 2035 case ARM::VST4q16_UPD: 2036 case ARM::VST4q32_UPD: 2037 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2038 return MCDisassembler::Fail; 2039 break; 2040 default: 2041 break; 2042 } 2043 2044 // AddrMode6 Base (register+alignment) 2045 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2046 return MCDisassembler::Fail; 2047 2048 // AddrMode6 Offset (register) 2049 if (Rm == 0xD) 2050 Inst.addOperand(MCOperand::CreateReg(0)); 2051 else if (Rm != 0xF) { 2052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2053 return MCDisassembler::Fail; 2054 } 2055 2056 // First input register 2057 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2058 return MCDisassembler::Fail; 2059 2060 // Second input register 2061 switch (Inst.getOpcode()) { 2062 case ARM::VST1q8: 2063 case ARM::VST1q16: 2064 case ARM::VST1q32: 2065 case ARM::VST1q64: 2066 case ARM::VST1q8_UPD: 2067 case ARM::VST1q16_UPD: 2068 case ARM::VST1q32_UPD: 2069 case ARM::VST1q64_UPD: 2070 case ARM::VST1d8T: 2071 case ARM::VST1d16T: 2072 case ARM::VST1d32T: 2073 case ARM::VST1d64T: 2074 case ARM::VST1d8T_UPD: 2075 case ARM::VST1d16T_UPD: 2076 case ARM::VST1d32T_UPD: 2077 case ARM::VST1d64T_UPD: 2078 case ARM::VST1d8Q: 2079 case ARM::VST1d16Q: 2080 case ARM::VST1d32Q: 2081 case ARM::VST1d64Q: 2082 case ARM::VST1d8Q_UPD: 2083 case ARM::VST1d16Q_UPD: 2084 case ARM::VST1d32Q_UPD: 2085 case ARM::VST1d64Q_UPD: 2086 case ARM::VST2d8: 2087 case ARM::VST2d16: 2088 case ARM::VST2d32: 2089 case ARM::VST2d8_UPD: 2090 case ARM::VST2d16_UPD: 2091 case ARM::VST2d32_UPD: 2092 case ARM::VST2q8: 2093 case ARM::VST2q16: 2094 case ARM::VST2q32: 2095 case ARM::VST2q8_UPD: 2096 case ARM::VST2q16_UPD: 2097 case ARM::VST2q32_UPD: 2098 case ARM::VST3d8: 2099 case ARM::VST3d16: 2100 case ARM::VST3d32: 2101 case ARM::VST3d8_UPD: 2102 case ARM::VST3d16_UPD: 2103 case ARM::VST3d32_UPD: 2104 case ARM::VST4d8: 2105 case ARM::VST4d16: 2106 case ARM::VST4d32: 2107 case ARM::VST4d8_UPD: 2108 case ARM::VST4d16_UPD: 2109 case ARM::VST4d32_UPD: 2110 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2111 return MCDisassembler::Fail; 2112 break; 2113 case ARM::VST2b8: 2114 case ARM::VST2b16: 2115 case ARM::VST2b32: 2116 case ARM::VST2b8_UPD: 2117 case ARM::VST2b16_UPD: 2118 case ARM::VST2b32_UPD: 2119 case ARM::VST3q8: 2120 case ARM::VST3q16: 2121 case ARM::VST3q32: 2122 case ARM::VST3q8_UPD: 2123 case ARM::VST3q16_UPD: 2124 case ARM::VST3q32_UPD: 2125 case ARM::VST4q8: 2126 case ARM::VST4q16: 2127 case ARM::VST4q32: 2128 case ARM::VST4q8_UPD: 2129 case ARM::VST4q16_UPD: 2130 case ARM::VST4q32_UPD: 2131 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 break; 2134 default: 2135 break; 2136 } 2137 2138 // Third input register 2139 switch (Inst.getOpcode()) { 2140 case ARM::VST1d8T: 2141 case ARM::VST1d16T: 2142 case ARM::VST1d32T: 2143 case ARM::VST1d64T: 2144 case ARM::VST1d8T_UPD: 2145 case ARM::VST1d16T_UPD: 2146 case ARM::VST1d32T_UPD: 2147 case ARM::VST1d64T_UPD: 2148 case ARM::VST1d8Q: 2149 case ARM::VST1d16Q: 2150 case ARM::VST1d32Q: 2151 case ARM::VST1d64Q: 2152 case ARM::VST1d8Q_UPD: 2153 case ARM::VST1d16Q_UPD: 2154 case ARM::VST1d32Q_UPD: 2155 case ARM::VST1d64Q_UPD: 2156 case ARM::VST2q8: 2157 case ARM::VST2q16: 2158 case ARM::VST2q32: 2159 case ARM::VST2q8_UPD: 2160 case ARM::VST2q16_UPD: 2161 case ARM::VST2q32_UPD: 2162 case ARM::VST3d8: 2163 case ARM::VST3d16: 2164 case ARM::VST3d32: 2165 case ARM::VST3d8_UPD: 2166 case ARM::VST3d16_UPD: 2167 case ARM::VST3d32_UPD: 2168 case ARM::VST4d8: 2169 case ARM::VST4d16: 2170 case ARM::VST4d32: 2171 case ARM::VST4d8_UPD: 2172 case ARM::VST4d16_UPD: 2173 case ARM::VST4d32_UPD: 2174 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2175 return MCDisassembler::Fail; 2176 break; 2177 case ARM::VST3q8: 2178 case ARM::VST3q16: 2179 case ARM::VST3q32: 2180 case ARM::VST3q8_UPD: 2181 case ARM::VST3q16_UPD: 2182 case ARM::VST3q32_UPD: 2183 case ARM::VST4q8: 2184 case ARM::VST4q16: 2185 case ARM::VST4q32: 2186 case ARM::VST4q8_UPD: 2187 case ARM::VST4q16_UPD: 2188 case ARM::VST4q32_UPD: 2189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2190 return MCDisassembler::Fail; 2191 break; 2192 default: 2193 break; 2194 } 2195 2196 // Fourth input register 2197 switch (Inst.getOpcode()) { 2198 case ARM::VST1d8Q: 2199 case ARM::VST1d16Q: 2200 case ARM::VST1d32Q: 2201 case ARM::VST1d64Q: 2202 case ARM::VST1d8Q_UPD: 2203 case ARM::VST1d16Q_UPD: 2204 case ARM::VST1d32Q_UPD: 2205 case ARM::VST1d64Q_UPD: 2206 case ARM::VST2q8: 2207 case ARM::VST2q16: 2208 case ARM::VST2q32: 2209 case ARM::VST2q8_UPD: 2210 case ARM::VST2q16_UPD: 2211 case ARM::VST2q32_UPD: 2212 case ARM::VST4d8: 2213 case ARM::VST4d16: 2214 case ARM::VST4d32: 2215 case ARM::VST4d8_UPD: 2216 case ARM::VST4d16_UPD: 2217 case ARM::VST4d32_UPD: 2218 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2219 return MCDisassembler::Fail; 2220 break; 2221 case ARM::VST4q8: 2222 case ARM::VST4q16: 2223 case ARM::VST4q32: 2224 case ARM::VST4q8_UPD: 2225 case ARM::VST4q16_UPD: 2226 case ARM::VST4q32_UPD: 2227 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 break; 2230 default: 2231 break; 2232 } 2233 2234 return S; 2235 } 2236 2237 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2238 uint64_t Address, const void *Decoder) { 2239 DecodeStatus S = MCDisassembler::Success; 2240 2241 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2242 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2243 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2244 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2245 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2246 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2247 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2248 2249 align *= (1 << size); 2250 2251 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2252 return MCDisassembler::Fail; 2253 if (regs == 2) { 2254 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2255 return MCDisassembler::Fail; 2256 } 2257 if (Rm != 0xF) { 2258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2259 return MCDisassembler::Fail; 2260 } 2261 2262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 Inst.addOperand(MCOperand::CreateImm(align)); 2265 2266 if (Rm == 0xD) 2267 Inst.addOperand(MCOperand::CreateReg(0)); 2268 else if (Rm != 0xF) { 2269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2270 return MCDisassembler::Fail; 2271 } 2272 2273 return S; 2274 } 2275 2276 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2277 uint64_t Address, const void *Decoder) { 2278 DecodeStatus S = MCDisassembler::Success; 2279 2280 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2281 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2282 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2283 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2284 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2285 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2286 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2287 align *= 2*size; 2288 2289 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2290 return MCDisassembler::Fail; 2291 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2292 return MCDisassembler::Fail; 2293 if (Rm != 0xF) { 2294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2295 return MCDisassembler::Fail; 2296 } 2297 2298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2299 return MCDisassembler::Fail; 2300 Inst.addOperand(MCOperand::CreateImm(align)); 2301 2302 if (Rm == 0xD) 2303 Inst.addOperand(MCOperand::CreateReg(0)); 2304 else if (Rm != 0xF) { 2305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2306 return MCDisassembler::Fail; 2307 } 2308 2309 return S; 2310 } 2311 2312 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2313 uint64_t Address, const void *Decoder) { 2314 DecodeStatus S = MCDisassembler::Success; 2315 2316 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2317 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2318 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2319 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2320 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2321 2322 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2323 return MCDisassembler::Fail; 2324 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2325 return MCDisassembler::Fail; 2326 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2327 return MCDisassembler::Fail; 2328 if (Rm != 0xF) { 2329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2330 return MCDisassembler::Fail; 2331 } 2332 2333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2334 return MCDisassembler::Fail; 2335 Inst.addOperand(MCOperand::CreateImm(0)); 2336 2337 if (Rm == 0xD) 2338 Inst.addOperand(MCOperand::CreateReg(0)); 2339 else if (Rm != 0xF) { 2340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2341 return MCDisassembler::Fail; 2342 } 2343 2344 return S; 2345 } 2346 2347 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2348 uint64_t Address, const void *Decoder) { 2349 DecodeStatus S = MCDisassembler::Success; 2350 2351 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2352 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2353 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2354 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2355 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2356 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2357 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2358 2359 if (size == 0x3) { 2360 size = 4; 2361 align = 16; 2362 } else { 2363 if (size == 2) { 2364 size = 1 << size; 2365 align *= 8; 2366 } else { 2367 size = 1 << size; 2368 align *= 4*size; 2369 } 2370 } 2371 2372 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2373 return MCDisassembler::Fail; 2374 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2375 return MCDisassembler::Fail; 2376 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 if (Rm != 0xF) { 2381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2382 return MCDisassembler::Fail; 2383 } 2384 2385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2386 return MCDisassembler::Fail; 2387 Inst.addOperand(MCOperand::CreateImm(align)); 2388 2389 if (Rm == 0xD) 2390 Inst.addOperand(MCOperand::CreateReg(0)); 2391 else if (Rm != 0xF) { 2392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2393 return MCDisassembler::Fail; 2394 } 2395 2396 return S; 2397 } 2398 2399 static DecodeStatus 2400 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2401 uint64_t Address, const void *Decoder) { 2402 DecodeStatus S = MCDisassembler::Success; 2403 2404 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2405 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2406 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2407 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2408 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2409 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2410 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2411 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2412 2413 if (Q) { 2414 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2415 return MCDisassembler::Fail; 2416 } else { 2417 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2418 return MCDisassembler::Fail; 2419 } 2420 2421 Inst.addOperand(MCOperand::CreateImm(imm)); 2422 2423 switch (Inst.getOpcode()) { 2424 case ARM::VORRiv4i16: 2425 case ARM::VORRiv2i32: 2426 case ARM::VBICiv4i16: 2427 case ARM::VBICiv2i32: 2428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2429 return MCDisassembler::Fail; 2430 break; 2431 case ARM::VORRiv8i16: 2432 case ARM::VORRiv4i32: 2433 case ARM::VBICiv8i16: 2434 case ARM::VBICiv4i32: 2435 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2436 return MCDisassembler::Fail; 2437 break; 2438 default: 2439 break; 2440 } 2441 2442 return S; 2443 } 2444 2445 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2446 uint64_t Address, const void *Decoder) { 2447 DecodeStatus S = MCDisassembler::Success; 2448 2449 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2450 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2451 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2452 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2453 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2454 2455 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2456 return MCDisassembler::Fail; 2457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2460 2461 return S; 2462 } 2463 2464 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2465 uint64_t Address, const void *Decoder) { 2466 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2467 return MCDisassembler::Success; 2468 } 2469 2470 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2471 uint64_t Address, const void *Decoder) { 2472 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2473 return MCDisassembler::Success; 2474 } 2475 2476 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2477 uint64_t Address, const void *Decoder) { 2478 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2479 return MCDisassembler::Success; 2480 } 2481 2482 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2483 uint64_t Address, const void *Decoder) { 2484 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2485 return MCDisassembler::Success; 2486 } 2487 2488 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2489 uint64_t Address, const void *Decoder) { 2490 DecodeStatus S = MCDisassembler::Success; 2491 2492 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2493 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2494 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2495 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2496 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2497 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2498 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2499 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2500 2501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2502 return MCDisassembler::Fail; 2503 if (op) { 2504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2505 return MCDisassembler::Fail; // Writeback 2506 } 2507 2508 for (unsigned i = 0; i < length; ++i) { 2509 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 } 2512 2513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2514 return MCDisassembler::Fail; 2515 2516 return S; 2517 } 2518 2519 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2520 uint64_t Address, const void *Decoder) { 2521 // The immediate needs to be a fully instantiated float. However, the 2522 // auto-generated decoder is only able to fill in some of the bits 2523 // necessary. For instance, the 'b' bit is replicated multiple times, 2524 // and is even present in inverted form in one bit. We do a little 2525 // binary parsing here to fill in those missing bits, and then 2526 // reinterpret it all as a float. 2527 union { 2528 uint32_t integer; 2529 float fp; 2530 } fp_conv; 2531 2532 fp_conv.integer = Val; 2533 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2534 fp_conv.integer |= b << 26; 2535 fp_conv.integer |= b << 27; 2536 fp_conv.integer |= b << 28; 2537 fp_conv.integer |= b << 29; 2538 fp_conv.integer |= (~b & 0x1) << 30; 2539 2540 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2541 return MCDisassembler::Success; 2542 } 2543 2544 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2545 uint64_t Address, const void *Decoder) { 2546 DecodeStatus S = MCDisassembler::Success; 2547 2548 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2549 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2550 2551 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2552 return MCDisassembler::Fail; 2553 2554 switch(Inst.getOpcode()) { 2555 default: 2556 return MCDisassembler::Fail; 2557 case ARM::tADR: 2558 break; // tADR does not explicitly represent the PC as an operand. 2559 case ARM::tADDrSPi: 2560 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2561 break; 2562 } 2563 2564 Inst.addOperand(MCOperand::CreateImm(imm)); 2565 return S; 2566 } 2567 2568 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2569 uint64_t Address, const void *Decoder) { 2570 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2571 return MCDisassembler::Success; 2572 } 2573 2574 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2575 uint64_t Address, const void *Decoder) { 2576 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2577 return MCDisassembler::Success; 2578 } 2579 2580 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2581 uint64_t Address, const void *Decoder) { 2582 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2583 return MCDisassembler::Success; 2584 } 2585 2586 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2587 uint64_t Address, const void *Decoder) { 2588 DecodeStatus S = MCDisassembler::Success; 2589 2590 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2591 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2592 2593 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2594 return MCDisassembler::Fail; 2595 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 2598 return S; 2599 } 2600 2601 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2602 uint64_t Address, const void *Decoder) { 2603 DecodeStatus S = MCDisassembler::Success; 2604 2605 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2606 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2607 2608 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2609 return MCDisassembler::Fail; 2610 Inst.addOperand(MCOperand::CreateImm(imm)); 2611 2612 return S; 2613 } 2614 2615 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2616 uint64_t Address, const void *Decoder) { 2617 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2618 2619 return MCDisassembler::Success; 2620 } 2621 2622 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2623 uint64_t Address, const void *Decoder) { 2624 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2625 Inst.addOperand(MCOperand::CreateImm(Val)); 2626 2627 return MCDisassembler::Success; 2628 } 2629 2630 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2631 uint64_t Address, const void *Decoder) { 2632 DecodeStatus S = MCDisassembler::Success; 2633 2634 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2635 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2636 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2637 2638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2639 return MCDisassembler::Fail; 2640 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2641 return MCDisassembler::Fail; 2642 Inst.addOperand(MCOperand::CreateImm(imm)); 2643 2644 return S; 2645 } 2646 2647 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2648 uint64_t Address, const void *Decoder) { 2649 DecodeStatus S = MCDisassembler::Success; 2650 2651 switch (Inst.getOpcode()) { 2652 case ARM::t2PLDs: 2653 case ARM::t2PLDWs: 2654 case ARM::t2PLIs: 2655 break; 2656 default: { 2657 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 } 2661 } 2662 2663 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2664 if (Rn == 0xF) { 2665 switch (Inst.getOpcode()) { 2666 case ARM::t2LDRBs: 2667 Inst.setOpcode(ARM::t2LDRBpci); 2668 break; 2669 case ARM::t2LDRHs: 2670 Inst.setOpcode(ARM::t2LDRHpci); 2671 break; 2672 case ARM::t2LDRSHs: 2673 Inst.setOpcode(ARM::t2LDRSHpci); 2674 break; 2675 case ARM::t2LDRSBs: 2676 Inst.setOpcode(ARM::t2LDRSBpci); 2677 break; 2678 case ARM::t2PLDs: 2679 Inst.setOpcode(ARM::t2PLDi12); 2680 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2681 break; 2682 default: 2683 return MCDisassembler::Fail; 2684 } 2685 2686 int imm = fieldFromInstruction32(Insn, 0, 12); 2687 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2688 Inst.addOperand(MCOperand::CreateImm(imm)); 2689 2690 return S; 2691 } 2692 2693 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2694 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2695 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2696 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 2699 return S; 2700 } 2701 2702 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2703 uint64_t Address, const void *Decoder) { 2704 int imm = Val & 0xFF; 2705 if (!(Val & 0x100)) imm *= -1; 2706 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2707 2708 return MCDisassembler::Success; 2709 } 2710 2711 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2712 uint64_t Address, const void *Decoder) { 2713 DecodeStatus S = MCDisassembler::Success; 2714 2715 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2716 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2717 2718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2721 return MCDisassembler::Fail; 2722 2723 return S; 2724 } 2725 2726 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2727 uint64_t Address, const void *Decoder) { 2728 DecodeStatus S = MCDisassembler::Success; 2729 2730 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2731 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2732 2733 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 2736 Inst.addOperand(MCOperand::CreateImm(imm)); 2737 2738 return S; 2739 } 2740 2741 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2742 uint64_t Address, const void *Decoder) { 2743 int imm = Val & 0xFF; 2744 if (Val == 0) 2745 imm = INT32_MIN; 2746 else if (!(Val & 0x100)) 2747 imm *= -1; 2748 Inst.addOperand(MCOperand::CreateImm(imm)); 2749 2750 return MCDisassembler::Success; 2751 } 2752 2753 2754 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2755 uint64_t Address, const void *Decoder) { 2756 DecodeStatus S = MCDisassembler::Success; 2757 2758 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2759 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2760 2761 // Some instructions always use an additive offset. 2762 switch (Inst.getOpcode()) { 2763 case ARM::t2LDRT: 2764 case ARM::t2LDRBT: 2765 case ARM::t2LDRHT: 2766 case ARM::t2LDRSBT: 2767 case ARM::t2LDRSHT: 2768 case ARM::t2STRT: 2769 case ARM::t2STRBT: 2770 case ARM::t2STRHT: 2771 imm |= 0x100; 2772 break; 2773 default: 2774 break; 2775 } 2776 2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 2782 return S; 2783 } 2784 2785 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2786 uint64_t Address, const void *Decoder) { 2787 DecodeStatus S = MCDisassembler::Success; 2788 2789 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2790 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2791 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2792 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2793 addr |= Rn << 9; 2794 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2795 2796 if (!load) { 2797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2798 return MCDisassembler::Fail; 2799 } 2800 2801 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 2804 if (load) { 2805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 } 2808 2809 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 2812 return S; 2813 } 2814 2815 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2816 uint64_t Address, const void *Decoder) { 2817 DecodeStatus S = MCDisassembler::Success; 2818 2819 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2820 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2821 2822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 Inst.addOperand(MCOperand::CreateImm(imm)); 2825 2826 return S; 2827 } 2828 2829 2830 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2831 uint64_t Address, const void *Decoder) { 2832 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2833 2834 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2835 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2836 Inst.addOperand(MCOperand::CreateImm(imm)); 2837 2838 return MCDisassembler::Success; 2839 } 2840 2841 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2842 uint64_t Address, const void *Decoder) { 2843 DecodeStatus S = MCDisassembler::Success; 2844 2845 if (Inst.getOpcode() == ARM::tADDrSP) { 2846 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2847 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2848 2849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2850 return MCDisassembler::Fail; 2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2852 return MCDisassembler::Fail; 2853 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2854 } else if (Inst.getOpcode() == ARM::tADDspr) { 2855 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2856 2857 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2858 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 } 2862 2863 return S; 2864 } 2865 2866 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2867 uint64_t Address, const void *Decoder) { 2868 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2869 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2870 2871 Inst.addOperand(MCOperand::CreateImm(imod)); 2872 Inst.addOperand(MCOperand::CreateImm(flags)); 2873 2874 return MCDisassembler::Success; 2875 } 2876 2877 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2878 uint64_t Address, const void *Decoder) { 2879 DecodeStatus S = MCDisassembler::Success; 2880 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2881 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2882 2883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 Inst.addOperand(MCOperand::CreateImm(add)); 2886 2887 return S; 2888 } 2889 2890 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2891 uint64_t Address, const void *Decoder) { 2892 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2893 return MCDisassembler::Success; 2894 } 2895 2896 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2897 uint64_t Address, const void *Decoder) { 2898 if (Val == 0xA || Val == 0xB) 2899 return MCDisassembler::Fail; 2900 2901 Inst.addOperand(MCOperand::CreateImm(Val)); 2902 return MCDisassembler::Success; 2903 } 2904 2905 static DecodeStatus 2906 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 2907 uint64_t Address, const void *Decoder) { 2908 DecodeStatus S = MCDisassembler::Success; 2909 2910 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2911 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2912 2913 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 2914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2915 return MCDisassembler::Fail; 2916 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 return S; 2919 } 2920 2921 static DecodeStatus 2922 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2923 uint64_t Address, const void *Decoder) { 2924 DecodeStatus S = MCDisassembler::Success; 2925 2926 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2927 if (pred == 0xE || pred == 0xF) { 2928 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2929 switch (opc) { 2930 default: 2931 return MCDisassembler::Fail; 2932 case 0xf3bf8f4: 2933 Inst.setOpcode(ARM::t2DSB); 2934 break; 2935 case 0xf3bf8f5: 2936 Inst.setOpcode(ARM::t2DMB); 2937 break; 2938 case 0xf3bf8f6: 2939 Inst.setOpcode(ARM::t2ISB); 2940 break; 2941 } 2942 2943 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2944 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2945 } 2946 2947 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2948 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2949 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2950 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2951 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2952 2953 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2954 return MCDisassembler::Fail; 2955 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2956 return MCDisassembler::Fail; 2957 2958 return S; 2959 } 2960 2961 // Decode a shifted immediate operand. These basically consist 2962 // of an 8-bit value, and a 4-bit directive that specifies either 2963 // a splat operation or a rotation. 2964 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2965 uint64_t Address, const void *Decoder) { 2966 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2967 if (ctrl == 0) { 2968 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2969 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2970 switch (byte) { 2971 case 0: 2972 Inst.addOperand(MCOperand::CreateImm(imm)); 2973 break; 2974 case 1: 2975 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2976 break; 2977 case 2: 2978 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2979 break; 2980 case 3: 2981 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2982 (imm << 8) | imm)); 2983 break; 2984 } 2985 } else { 2986 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2987 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2988 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2989 Inst.addOperand(MCOperand::CreateImm(imm)); 2990 } 2991 2992 return MCDisassembler::Success; 2993 } 2994 2995 static DecodeStatus 2996 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2997 uint64_t Address, const void *Decoder){ 2998 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2999 return MCDisassembler::Success; 3000 } 3001 3002 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3003 uint64_t Address, const void *Decoder){ 3004 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3005 return MCDisassembler::Success; 3006 } 3007 3008 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3009 uint64_t Address, const void *Decoder) { 3010 switch (Val) { 3011 default: 3012 return MCDisassembler::Fail; 3013 case 0xF: // SY 3014 case 0xE: // ST 3015 case 0xB: // ISH 3016 case 0xA: // ISHST 3017 case 0x7: // NSH 3018 case 0x6: // NSHST 3019 case 0x3: // OSH 3020 case 0x2: // OSHST 3021 break; 3022 } 3023 3024 Inst.addOperand(MCOperand::CreateImm(Val)); 3025 return MCDisassembler::Success; 3026 } 3027 3028 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3029 uint64_t Address, const void *Decoder) { 3030 if (!Val) return MCDisassembler::Fail; 3031 Inst.addOperand(MCOperand::CreateImm(Val)); 3032 return MCDisassembler::Success; 3033 } 3034 3035 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3036 uint64_t Address, const void *Decoder) { 3037 DecodeStatus S = MCDisassembler::Success; 3038 3039 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3040 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3041 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3042 3043 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3044 3045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3046 return MCDisassembler::Fail; 3047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3048 return MCDisassembler::Fail; 3049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3050 return MCDisassembler::Fail; 3051 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3052 return MCDisassembler::Fail; 3053 3054 return S; 3055 } 3056 3057 3058 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3059 uint64_t Address, const void *Decoder){ 3060 DecodeStatus S = MCDisassembler::Success; 3061 3062 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3063 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3064 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3065 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3066 3067 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3068 return MCDisassembler::Fail; 3069 3070 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3071 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3072 3073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 3082 return S; 3083 } 3084 3085 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3086 uint64_t Address, const void *Decoder) { 3087 DecodeStatus S = MCDisassembler::Success; 3088 3089 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3090 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3091 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3092 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3093 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3094 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3095 3096 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3097 3098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3099 return MCDisassembler::Fail; 3100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3101 return MCDisassembler::Fail; 3102 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3105 return MCDisassembler::Fail; 3106 3107 return S; 3108 } 3109 3110 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3111 uint64_t Address, const void *Decoder) { 3112 DecodeStatus S = MCDisassembler::Success; 3113 3114 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3115 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3116 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3117 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3118 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3119 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3120 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3121 3122 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3123 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3124 3125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3126 return MCDisassembler::Fail; 3127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 3134 return S; 3135 } 3136 3137 3138 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3139 uint64_t Address, const void *Decoder) { 3140 DecodeStatus S = MCDisassembler::Success; 3141 3142 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3143 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3144 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3145 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3146 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3147 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3148 3149 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3150 3151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3152 return MCDisassembler::Fail; 3153 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3154 return MCDisassembler::Fail; 3155 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3156 return MCDisassembler::Fail; 3157 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3158 return MCDisassembler::Fail; 3159 3160 return S; 3161 } 3162 3163 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3164 uint64_t Address, const void *Decoder) { 3165 DecodeStatus S = MCDisassembler::Success; 3166 3167 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3168 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3169 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3170 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3171 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3172 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3173 3174 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3175 3176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3177 return MCDisassembler::Fail; 3178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3179 return MCDisassembler::Fail; 3180 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3181 return MCDisassembler::Fail; 3182 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3183 return MCDisassembler::Fail; 3184 3185 return S; 3186 } 3187 3188 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3189 uint64_t Address, const void *Decoder) { 3190 DecodeStatus S = MCDisassembler::Success; 3191 3192 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3193 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3194 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3195 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3196 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3197 3198 unsigned align = 0; 3199 unsigned index = 0; 3200 switch (size) { 3201 default: 3202 return MCDisassembler::Fail; 3203 case 0: 3204 if (fieldFromInstruction32(Insn, 4, 1)) 3205 return MCDisassembler::Fail; // UNDEFINED 3206 index = fieldFromInstruction32(Insn, 5, 3); 3207 break; 3208 case 1: 3209 if (fieldFromInstruction32(Insn, 5, 1)) 3210 return MCDisassembler::Fail; // UNDEFINED 3211 index = fieldFromInstruction32(Insn, 6, 2); 3212 if (fieldFromInstruction32(Insn, 4, 1)) 3213 align = 2; 3214 break; 3215 case 2: 3216 if (fieldFromInstruction32(Insn, 6, 1)) 3217 return MCDisassembler::Fail; // UNDEFINED 3218 index = fieldFromInstruction32(Insn, 7, 1); 3219 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3220 align = 4; 3221 } 3222 3223 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 if (Rm != 0xF) { // Writeback 3226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 } 3229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 Inst.addOperand(MCOperand::CreateImm(align)); 3232 if (Rm != 0xF) { 3233 if (Rm != 0xD) { 3234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 } else 3237 Inst.addOperand(MCOperand::CreateReg(0)); 3238 } 3239 3240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 Inst.addOperand(MCOperand::CreateImm(index)); 3243 3244 return S; 3245 } 3246 3247 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3248 uint64_t Address, const void *Decoder) { 3249 DecodeStatus S = MCDisassembler::Success; 3250 3251 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3252 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3253 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3254 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3255 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3256 3257 unsigned align = 0; 3258 unsigned index = 0; 3259 switch (size) { 3260 default: 3261 return MCDisassembler::Fail; 3262 case 0: 3263 if (fieldFromInstruction32(Insn, 4, 1)) 3264 return MCDisassembler::Fail; // UNDEFINED 3265 index = fieldFromInstruction32(Insn, 5, 3); 3266 break; 3267 case 1: 3268 if (fieldFromInstruction32(Insn, 5, 1)) 3269 return MCDisassembler::Fail; // UNDEFINED 3270 index = fieldFromInstruction32(Insn, 6, 2); 3271 if (fieldFromInstruction32(Insn, 4, 1)) 3272 align = 2; 3273 break; 3274 case 2: 3275 if (fieldFromInstruction32(Insn, 6, 1)) 3276 return MCDisassembler::Fail; // UNDEFINED 3277 index = fieldFromInstruction32(Insn, 7, 1); 3278 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3279 align = 4; 3280 } 3281 3282 if (Rm != 0xF) { // Writeback 3283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3284 return MCDisassembler::Fail; 3285 } 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 Inst.addOperand(MCOperand::CreateImm(align)); 3289 if (Rm != 0xF) { 3290 if (Rm != 0xD) { 3291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 } else 3294 Inst.addOperand(MCOperand::CreateReg(0)); 3295 } 3296 3297 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 Inst.addOperand(MCOperand::CreateImm(index)); 3300 3301 return S; 3302 } 3303 3304 3305 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3306 uint64_t Address, const void *Decoder) { 3307 DecodeStatus S = MCDisassembler::Success; 3308 3309 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3310 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3311 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3312 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3313 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3314 3315 unsigned align = 0; 3316 unsigned index = 0; 3317 unsigned inc = 1; 3318 switch (size) { 3319 default: 3320 return MCDisassembler::Fail; 3321 case 0: 3322 index = fieldFromInstruction32(Insn, 5, 3); 3323 if (fieldFromInstruction32(Insn, 4, 1)) 3324 align = 2; 3325 break; 3326 case 1: 3327 index = fieldFromInstruction32(Insn, 6, 2); 3328 if (fieldFromInstruction32(Insn, 4, 1)) 3329 align = 4; 3330 if (fieldFromInstruction32(Insn, 5, 1)) 3331 inc = 2; 3332 break; 3333 case 2: 3334 if (fieldFromInstruction32(Insn, 5, 1)) 3335 return MCDisassembler::Fail; // UNDEFINED 3336 index = fieldFromInstruction32(Insn, 7, 1); 3337 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3338 align = 8; 3339 if (fieldFromInstruction32(Insn, 6, 1)) 3340 inc = 2; 3341 break; 3342 } 3343 3344 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3345 return MCDisassembler::Fail; 3346 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3347 return MCDisassembler::Fail; 3348 if (Rm != 0xF) { // Writeback 3349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 } 3352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3353 return MCDisassembler::Fail; 3354 Inst.addOperand(MCOperand::CreateImm(align)); 3355 if (Rm != 0xF) { 3356 if (Rm != 0xD) { 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 } else 3360 Inst.addOperand(MCOperand::CreateReg(0)); 3361 } 3362 3363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 Inst.addOperand(MCOperand::CreateImm(index)); 3368 3369 return S; 3370 } 3371 3372 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3373 uint64_t Address, const void *Decoder) { 3374 DecodeStatus S = MCDisassembler::Success; 3375 3376 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3377 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3378 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3379 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3380 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3381 3382 unsigned align = 0; 3383 unsigned index = 0; 3384 unsigned inc = 1; 3385 switch (size) { 3386 default: 3387 return MCDisassembler::Fail; 3388 case 0: 3389 index = fieldFromInstruction32(Insn, 5, 3); 3390 if (fieldFromInstruction32(Insn, 4, 1)) 3391 align = 2; 3392 break; 3393 case 1: 3394 index = fieldFromInstruction32(Insn, 6, 2); 3395 if (fieldFromInstruction32(Insn, 4, 1)) 3396 align = 4; 3397 if (fieldFromInstruction32(Insn, 5, 1)) 3398 inc = 2; 3399 break; 3400 case 2: 3401 if (fieldFromInstruction32(Insn, 5, 1)) 3402 return MCDisassembler::Fail; // UNDEFINED 3403 index = fieldFromInstruction32(Insn, 7, 1); 3404 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3405 align = 8; 3406 if (fieldFromInstruction32(Insn, 6, 1)) 3407 inc = 2; 3408 break; 3409 } 3410 3411 if (Rm != 0xF) { // Writeback 3412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 } 3415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 Inst.addOperand(MCOperand::CreateImm(align)); 3418 if (Rm != 0xF) { 3419 if (Rm != 0xD) { 3420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3421 return MCDisassembler::Fail; 3422 } else 3423 Inst.addOperand(MCOperand::CreateReg(0)); 3424 } 3425 3426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 Inst.addOperand(MCOperand::CreateImm(index)); 3431 3432 return S; 3433 } 3434 3435 3436 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3437 uint64_t Address, const void *Decoder) { 3438 DecodeStatus S = MCDisassembler::Success; 3439 3440 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3441 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3442 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3443 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3444 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3445 3446 unsigned align = 0; 3447 unsigned index = 0; 3448 unsigned inc = 1; 3449 switch (size) { 3450 default: 3451 return MCDisassembler::Fail; 3452 case 0: 3453 if (fieldFromInstruction32(Insn, 4, 1)) 3454 return MCDisassembler::Fail; // UNDEFINED 3455 index = fieldFromInstruction32(Insn, 5, 3); 3456 break; 3457 case 1: 3458 if (fieldFromInstruction32(Insn, 4, 1)) 3459 return MCDisassembler::Fail; // UNDEFINED 3460 index = fieldFromInstruction32(Insn, 6, 2); 3461 if (fieldFromInstruction32(Insn, 5, 1)) 3462 inc = 2; 3463 break; 3464 case 2: 3465 if (fieldFromInstruction32(Insn, 4, 2)) 3466 return MCDisassembler::Fail; // UNDEFINED 3467 index = fieldFromInstruction32(Insn, 7, 1); 3468 if (fieldFromInstruction32(Insn, 6, 1)) 3469 inc = 2; 3470 break; 3471 } 3472 3473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3474 return MCDisassembler::Fail; 3475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3478 return MCDisassembler::Fail; 3479 3480 if (Rm != 0xF) { // Writeback 3481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 } 3484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 Inst.addOperand(MCOperand::CreateImm(align)); 3487 if (Rm != 0xF) { 3488 if (Rm != 0xD) { 3489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 } else 3492 Inst.addOperand(MCOperand::CreateReg(0)); 3493 } 3494 3495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3498 return MCDisassembler::Fail; 3499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 Inst.addOperand(MCOperand::CreateImm(index)); 3502 3503 return S; 3504 } 3505 3506 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3507 uint64_t Address, const void *Decoder) { 3508 DecodeStatus S = MCDisassembler::Success; 3509 3510 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3511 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3512 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3513 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3514 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3515 3516 unsigned align = 0; 3517 unsigned index = 0; 3518 unsigned inc = 1; 3519 switch (size) { 3520 default: 3521 return MCDisassembler::Fail; 3522 case 0: 3523 if (fieldFromInstruction32(Insn, 4, 1)) 3524 return MCDisassembler::Fail; // UNDEFINED 3525 index = fieldFromInstruction32(Insn, 5, 3); 3526 break; 3527 case 1: 3528 if (fieldFromInstruction32(Insn, 4, 1)) 3529 return MCDisassembler::Fail; // UNDEFINED 3530 index = fieldFromInstruction32(Insn, 6, 2); 3531 if (fieldFromInstruction32(Insn, 5, 1)) 3532 inc = 2; 3533 break; 3534 case 2: 3535 if (fieldFromInstruction32(Insn, 4, 2)) 3536 return MCDisassembler::Fail; // UNDEFINED 3537 index = fieldFromInstruction32(Insn, 7, 1); 3538 if (fieldFromInstruction32(Insn, 6, 1)) 3539 inc = 2; 3540 break; 3541 } 3542 3543 if (Rm != 0xF) { // Writeback 3544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 } 3547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 Inst.addOperand(MCOperand::CreateImm(align)); 3550 if (Rm != 0xF) { 3551 if (Rm != 0xD) { 3552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3553 return MCDisassembler::Fail; 3554 } else 3555 Inst.addOperand(MCOperand::CreateReg(0)); 3556 } 3557 3558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 Inst.addOperand(MCOperand::CreateImm(index)); 3565 3566 return S; 3567 } 3568 3569 3570 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3571 uint64_t Address, const void *Decoder) { 3572 DecodeStatus S = MCDisassembler::Success; 3573 3574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3576 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3577 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3578 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3579 3580 unsigned align = 0; 3581 unsigned index = 0; 3582 unsigned inc = 1; 3583 switch (size) { 3584 default: 3585 return MCDisassembler::Fail; 3586 case 0: 3587 if (fieldFromInstruction32(Insn, 4, 1)) 3588 align = 4; 3589 index = fieldFromInstruction32(Insn, 5, 3); 3590 break; 3591 case 1: 3592 if (fieldFromInstruction32(Insn, 4, 1)) 3593 align = 8; 3594 index = fieldFromInstruction32(Insn, 6, 2); 3595 if (fieldFromInstruction32(Insn, 5, 1)) 3596 inc = 2; 3597 break; 3598 case 2: 3599 if (fieldFromInstruction32(Insn, 4, 2)) 3600 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3601 index = fieldFromInstruction32(Insn, 7, 1); 3602 if (fieldFromInstruction32(Insn, 6, 1)) 3603 inc = 2; 3604 break; 3605 } 3606 3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 3616 if (Rm != 0xF) { // Writeback 3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 } 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 Inst.addOperand(MCOperand::CreateImm(align)); 3623 if (Rm != 0xF) { 3624 if (Rm != 0xD) { 3625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 } else 3628 Inst.addOperand(MCOperand::CreateReg(0)); 3629 } 3630 3631 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 Inst.addOperand(MCOperand::CreateImm(index)); 3640 3641 return S; 3642 } 3643 3644 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3645 uint64_t Address, const void *Decoder) { 3646 DecodeStatus S = MCDisassembler::Success; 3647 3648 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3649 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3650 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3651 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3652 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3653 3654 unsigned align = 0; 3655 unsigned index = 0; 3656 unsigned inc = 1; 3657 switch (size) { 3658 default: 3659 return MCDisassembler::Fail; 3660 case 0: 3661 if (fieldFromInstruction32(Insn, 4, 1)) 3662 align = 4; 3663 index = fieldFromInstruction32(Insn, 5, 3); 3664 break; 3665 case 1: 3666 if (fieldFromInstruction32(Insn, 4, 1)) 3667 align = 8; 3668 index = fieldFromInstruction32(Insn, 6, 2); 3669 if (fieldFromInstruction32(Insn, 5, 1)) 3670 inc = 2; 3671 break; 3672 case 2: 3673 if (fieldFromInstruction32(Insn, 4, 2)) 3674 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3675 index = fieldFromInstruction32(Insn, 7, 1); 3676 if (fieldFromInstruction32(Insn, 6, 1)) 3677 inc = 2; 3678 break; 3679 } 3680 3681 if (Rm != 0xF) { // Writeback 3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3683 return MCDisassembler::Fail; 3684 } 3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 Inst.addOperand(MCOperand::CreateImm(align)); 3688 if (Rm != 0xF) { 3689 if (Rm != 0xD) { 3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 } else 3693 Inst.addOperand(MCOperand::CreateReg(0)); 3694 } 3695 3696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 Inst.addOperand(MCOperand::CreateImm(index)); 3705 3706 return S; 3707 } 3708 3709 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3710 uint64_t Address, const void *Decoder) { 3711 DecodeStatus S = MCDisassembler::Success; 3712 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3713 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3714 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3715 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3716 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3717 3718 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3719 S = MCDisassembler::SoftFail; 3720 3721 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 3732 return S; 3733 } 3734 3735 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3736 uint64_t Address, const void *Decoder) { 3737 DecodeStatus S = MCDisassembler::Success; 3738 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3739 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3740 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3741 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3742 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3743 3744 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3745 S = MCDisassembler::SoftFail; 3746 3747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3750 return MCDisassembler::Fail; 3751 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3752 return MCDisassembler::Fail; 3753 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3756 return MCDisassembler::Fail; 3757 3758 return S; 3759 } 3760 3761 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3762 uint64_t Address, const void *Decoder) { 3763 DecodeStatus S = MCDisassembler::Success; 3764 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3765 // The InstPrinter needs to have the low bit of the predicate in 3766 // the mask operand to be able to print it properly. 3767 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3768 3769 if (pred == 0xF) { 3770 pred = 0xE; 3771 S = MCDisassembler::SoftFail; 3772 } 3773 3774 if ((mask & 0xF) == 0) { 3775 // Preserve the high bit of the mask, which is the low bit of 3776 // the predicate. 3777 mask &= 0x10; 3778 mask |= 0x8; 3779 S = MCDisassembler::SoftFail; 3780 } 3781 3782 Inst.addOperand(MCOperand::CreateImm(pred)); 3783 Inst.addOperand(MCOperand::CreateImm(mask)); 3784 return S; 3785 } 3786 3787 static DecodeStatus 3788 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3789 uint64_t Address, const void *Decoder) { 3790 DecodeStatus S = MCDisassembler::Success; 3791 3792 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3793 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3795 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3796 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3797 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3798 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3799 bool writeback = (W == 1) | (P == 0); 3800 3801 addr |= (U << 8) | (Rn << 9); 3802 3803 if (writeback && (Rn == Rt || Rn == Rt2)) 3804 Check(S, MCDisassembler::SoftFail); 3805 if (Rt == Rt2) 3806 Check(S, MCDisassembler::SoftFail); 3807 3808 // Rt 3809 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 // Rt2 3812 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3813 return MCDisassembler::Fail; 3814 // Writeback operand 3815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3816 return MCDisassembler::Fail; 3817 // addr 3818 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 3821 return S; 3822 } 3823 3824 static DecodeStatus 3825 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3826 uint64_t Address, const void *Decoder) { 3827 DecodeStatus S = MCDisassembler::Success; 3828 3829 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3830 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3831 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3832 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3833 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3834 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3835 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3836 bool writeback = (W == 1) | (P == 0); 3837 3838 addr |= (U << 8) | (Rn << 9); 3839 3840 if (writeback && (Rn == Rt || Rn == Rt2)) 3841 Check(S, MCDisassembler::SoftFail); 3842 3843 // Writeback operand 3844 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3845 return MCDisassembler::Fail; 3846 // Rt 3847 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3848 return MCDisassembler::Fail; 3849 // Rt2 3850 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3851 return MCDisassembler::Fail; 3852 // addr 3853 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3854 return MCDisassembler::Fail; 3855 3856 return S; 3857 } 3858 3859 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 3860 uint64_t Address, const void *Decoder) { 3861 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 3862 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 3863 if (sign1 != sign2) return MCDisassembler::Fail; 3864 3865 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 3866 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 3867 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 3868 Val |= sign1 << 12; 3869 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 3870 3871 return MCDisassembler::Success; 3872 } 3873 3874