1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream) const; 51 52 /// getEDInfo - See MCDisassembler. 53 EDInstInfo *getEDInfo() const; 54 private: 55 }; 56 57 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 58 class ThumbDisassembler : public MCDisassembler { 59 public: 60 /// Constructor - Initializes the disassembler. 61 /// 62 ThumbDisassembler(const MCSubtargetInfo &STI) : 63 MCDisassembler(STI) { 64 } 65 66 ~ThumbDisassembler() { 67 } 68 69 /// getInstruction - See MCDisassembler. 70 DecodeStatus getInstruction(MCInst &instr, 71 uint64_t &size, 72 const MemoryObject ®ion, 73 uint64_t address, 74 raw_ostream &vStream) const; 75 76 /// getEDInfo - See MCDisassembler. 77 EDInstInfo *getEDInfo() const; 78 private: 79 mutable std::vector<unsigned> ITBlock; 80 DecodeStatus AddThumbPredicate(MCInst&) const; 81 void UpdateThumbVFPPredicate(MCInst&) const; 82 }; 83 } 84 85 static bool Check(DecodeStatus &Out, DecodeStatus In) { 86 switch (In) { 87 case MCDisassembler::Success: 88 // Out stays the same. 89 return true; 90 case MCDisassembler::SoftFail: 91 Out = In; 92 return true; 93 case MCDisassembler::Fail: 94 Out = In; 95 return false; 96 } 97 return false; 98 } 99 100 101 // Forward declare these because the autogenerated code will reference them. 102 // Definitions are further down. 103 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 125 uint64_t Address, const void *Decoder); 126 127 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 140 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 157 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 158 unsigned Insn, 159 uint64_t Adddress, 160 const void *Decoder); 161 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 248 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 301 #include "ARMGenDisassemblerTables.inc" 302 #include "ARMGenInstrInfo.inc" 303 #include "ARMGenEDInfo.inc" 304 305 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 306 return new ARMDisassembler(STI); 307 } 308 309 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 310 return new ThumbDisassembler(STI); 311 } 312 313 EDInstInfo *ARMDisassembler::getEDInfo() const { 314 return instInfoARM; 315 } 316 317 EDInstInfo *ThumbDisassembler::getEDInfo() const { 318 return instInfoARM; 319 } 320 321 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 322 const MemoryObject &Region, 323 uint64_t Address, 324 raw_ostream &os) const { 325 uint8_t bytes[4]; 326 327 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 328 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 329 330 // We want to read exactly 4 bytes of data. 331 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 332 Size = 0; 333 return MCDisassembler::Fail; 334 } 335 336 // Encoded as a small-endian 32-bit word in the stream. 337 uint32_t insn = (bytes[3] << 24) | 338 (bytes[2] << 16) | 339 (bytes[1] << 8) | 340 (bytes[0] << 0); 341 342 // Calling the auto-generated decoder function. 343 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 344 if (result != MCDisassembler::Fail) { 345 Size = 4; 346 return result; 347 } 348 349 // VFP and NEON instructions, similarly, are shared between ARM 350 // and Thumb modes. 351 MI.clear(); 352 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 353 if (result != MCDisassembler::Fail) { 354 Size = 4; 355 return result; 356 } 357 358 MI.clear(); 359 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 360 if (result != MCDisassembler::Fail) { 361 Size = 4; 362 // Add a fake predicate operand, because we share these instruction 363 // definitions with Thumb2 where these instructions are predicable. 364 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 365 return MCDisassembler::Fail; 366 return result; 367 } 368 369 MI.clear(); 370 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 371 if (result != MCDisassembler::Fail) { 372 Size = 4; 373 // Add a fake predicate operand, because we share these instruction 374 // definitions with Thumb2 where these instructions are predicable. 375 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 376 return MCDisassembler::Fail; 377 return result; 378 } 379 380 MI.clear(); 381 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 4; 384 // Add a fake predicate operand, because we share these instruction 385 // definitions with Thumb2 where these instructions are predicable. 386 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 387 return MCDisassembler::Fail; 388 return result; 389 } 390 391 MI.clear(); 392 393 Size = 0; 394 return MCDisassembler::Fail; 395 } 396 397 namespace llvm { 398 extern MCInstrDesc ARMInsts[]; 399 } 400 401 // Thumb1 instructions don't have explicit S bits. Rather, they 402 // implicitly set CPSR. Since it's not represented in the encoding, the 403 // auto-generated decoder won't inject the CPSR operand. We need to fix 404 // that as a post-pass. 405 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 406 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 407 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 408 MCInst::iterator I = MI.begin(); 409 for (unsigned i = 0; i < NumOps; ++i, ++I) { 410 if (I == MI.end()) break; 411 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 412 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 413 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 414 return; 415 } 416 } 417 418 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 419 } 420 421 // Most Thumb instructions don't have explicit predicates in the 422 // encoding, but rather get their predicates from IT context. We need 423 // to fix up the predicate operands using this context information as a 424 // post-pass. 425 MCDisassembler::DecodeStatus 426 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 427 // A few instructions actually have predicates encoded in them. Don't 428 // try to overwrite it if we're seeing one of those. 429 switch (MI.getOpcode()) { 430 case ARM::tBcc: 431 case ARM::t2Bcc: 432 case ARM::tCBZ: 433 case ARM::tCBNZ: 434 // Some instructions (mostly conditional branches) are not 435 // allowed in IT blocks. 436 if (!ITBlock.empty()) 437 return SoftFail; 438 return Success; 439 break; 440 default: 441 break; 442 } 443 444 // If we're in an IT block, base the predicate on that. Otherwise, 445 // assume a predicate of AL. 446 unsigned CC; 447 if (!ITBlock.empty()) { 448 CC = ITBlock.back(); 449 if (CC == 0xF) 450 CC = ARMCC::AL; 451 ITBlock.pop_back(); 452 } else 453 CC = ARMCC::AL; 454 455 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 456 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 457 MCInst::iterator I = MI.begin(); 458 for (unsigned i = 0; i < NumOps; ++i, ++I) { 459 if (I == MI.end()) break; 460 if (OpInfo[i].isPredicate()) { 461 I = MI.insert(I, MCOperand::CreateImm(CC)); 462 ++I; 463 if (CC == ARMCC::AL) 464 MI.insert(I, MCOperand::CreateReg(0)); 465 else 466 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 467 return Success; 468 } 469 } 470 471 I = MI.insert(I, MCOperand::CreateImm(CC)); 472 ++I; 473 if (CC == ARMCC::AL) 474 MI.insert(I, MCOperand::CreateReg(0)); 475 else 476 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 477 478 return Success; 479 } 480 481 // Thumb VFP instructions are a special case. Because we share their 482 // encodings between ARM and Thumb modes, and they are predicable in ARM 483 // mode, the auto-generated decoder will give them an (incorrect) 484 // predicate operand. We need to rewrite these operands based on the IT 485 // context as a post-pass. 486 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 487 unsigned CC; 488 if (!ITBlock.empty()) { 489 CC = ITBlock.back(); 490 ITBlock.pop_back(); 491 } else 492 CC = ARMCC::AL; 493 494 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 495 MCInst::iterator I = MI.begin(); 496 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 497 for (unsigned i = 0; i < NumOps; ++i, ++I) { 498 if (OpInfo[i].isPredicate() ) { 499 I->setImm(CC); 500 ++I; 501 if (CC == ARMCC::AL) 502 I->setReg(0); 503 else 504 I->setReg(ARM::CPSR); 505 return; 506 } 507 } 508 } 509 510 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 511 const MemoryObject &Region, 512 uint64_t Address, 513 raw_ostream &os) const { 514 uint8_t bytes[4]; 515 516 assert((STI.getFeatureBits() & ARM::ModeThumb) && 517 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 518 519 // We want to read exactly 2 bytes of data. 520 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 521 Size = 0; 522 return MCDisassembler::Fail; 523 } 524 525 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 526 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 527 if (result != MCDisassembler::Fail) { 528 Size = 2; 529 Check(result, AddThumbPredicate(MI)); 530 return result; 531 } 532 533 MI.clear(); 534 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 535 if (result) { 536 Size = 2; 537 bool InITBlock = !ITBlock.empty(); 538 Check(result, AddThumbPredicate(MI)); 539 AddThumb1SBit(MI, InITBlock); 540 return result; 541 } 542 543 MI.clear(); 544 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 545 if (result != MCDisassembler::Fail) { 546 Size = 2; 547 Check(result, AddThumbPredicate(MI)); 548 549 // If we find an IT instruction, we need to parse its condition 550 // code and mask operands so that we can apply them correctly 551 // to the subsequent instructions. 552 if (MI.getOpcode() == ARM::t2IT) { 553 // (3 - the number of trailing zeros) is the number of then / else. 554 unsigned firstcond = MI.getOperand(0).getImm(); 555 unsigned Mask = MI.getOperand(1).getImm(); 556 unsigned CondBit0 = Mask >> 4 & 1; 557 unsigned NumTZ = CountTrailingZeros_32(Mask); 558 assert(NumTZ <= 3 && "Invalid IT mask!"); 559 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 560 bool T = ((Mask >> Pos) & 1) == CondBit0; 561 if (T) 562 ITBlock.insert(ITBlock.begin(), firstcond); 563 else 564 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 565 } 566 567 ITBlock.push_back(firstcond); 568 } 569 570 return result; 571 } 572 573 // We want to read exactly 4 bytes of data. 574 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 575 Size = 0; 576 return MCDisassembler::Fail; 577 } 578 579 uint32_t insn32 = (bytes[3] << 8) | 580 (bytes[2] << 0) | 581 (bytes[1] << 24) | 582 (bytes[0] << 16); 583 MI.clear(); 584 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 585 if (result != MCDisassembler::Fail) { 586 Size = 4; 587 bool InITBlock = ITBlock.size(); 588 Check(result, AddThumbPredicate(MI)); 589 AddThumb1SBit(MI, InITBlock); 590 return result; 591 } 592 593 MI.clear(); 594 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 595 if (result != MCDisassembler::Fail) { 596 Size = 4; 597 Check(result, AddThumbPredicate(MI)); 598 return result; 599 } 600 601 MI.clear(); 602 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 603 if (result != MCDisassembler::Fail) { 604 Size = 4; 605 UpdateThumbVFPPredicate(MI); 606 return result; 607 } 608 609 MI.clear(); 610 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 611 if (result != MCDisassembler::Fail) { 612 Size = 4; 613 Check(result, AddThumbPredicate(MI)); 614 return result; 615 } 616 617 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 618 MI.clear(); 619 uint32_t NEONLdStInsn = insn32; 620 NEONLdStInsn &= 0xF0FFFFFF; 621 NEONLdStInsn |= 0x04000000; 622 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 623 if (result != MCDisassembler::Fail) { 624 Size = 4; 625 Check(result, AddThumbPredicate(MI)); 626 return result; 627 } 628 } 629 630 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 631 MI.clear(); 632 uint32_t NEONDataInsn = insn32; 633 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 634 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 635 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 636 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 637 if (result != MCDisassembler::Fail) { 638 Size = 4; 639 Check(result, AddThumbPredicate(MI)); 640 return result; 641 } 642 } 643 644 Size = 0; 645 return MCDisassembler::Fail; 646 } 647 648 649 extern "C" void LLVMInitializeARMDisassembler() { 650 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 651 createARMDisassembler); 652 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 653 createThumbDisassembler); 654 } 655 656 static const unsigned GPRDecoderTable[] = { 657 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 658 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 659 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 660 ARM::R12, ARM::SP, ARM::LR, ARM::PC 661 }; 662 663 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 664 uint64_t Address, const void *Decoder) { 665 if (RegNo > 15) 666 return MCDisassembler::Fail; 667 668 unsigned Register = GPRDecoderTable[RegNo]; 669 Inst.addOperand(MCOperand::CreateReg(Register)); 670 return MCDisassembler::Success; 671 } 672 673 static DecodeStatus 674 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 675 uint64_t Address, const void *Decoder) { 676 if (RegNo == 15) return MCDisassembler::Fail; 677 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 678 } 679 680 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 681 uint64_t Address, const void *Decoder) { 682 if (RegNo > 7) 683 return MCDisassembler::Fail; 684 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 685 } 686 687 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 688 uint64_t Address, const void *Decoder) { 689 unsigned Register = 0; 690 switch (RegNo) { 691 case 0: 692 Register = ARM::R0; 693 break; 694 case 1: 695 Register = ARM::R1; 696 break; 697 case 2: 698 Register = ARM::R2; 699 break; 700 case 3: 701 Register = ARM::R3; 702 break; 703 case 9: 704 Register = ARM::R9; 705 break; 706 case 12: 707 Register = ARM::R12; 708 break; 709 default: 710 return MCDisassembler::Fail; 711 } 712 713 Inst.addOperand(MCOperand::CreateReg(Register)); 714 return MCDisassembler::Success; 715 } 716 717 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 718 uint64_t Address, const void *Decoder) { 719 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 720 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 721 } 722 723 static const unsigned SPRDecoderTable[] = { 724 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 725 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 726 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 727 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 728 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 729 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 730 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 731 ARM::S28, ARM::S29, ARM::S30, ARM::S31 732 }; 733 734 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 735 uint64_t Address, const void *Decoder) { 736 if (RegNo > 31) 737 return MCDisassembler::Fail; 738 739 unsigned Register = SPRDecoderTable[RegNo]; 740 Inst.addOperand(MCOperand::CreateReg(Register)); 741 return MCDisassembler::Success; 742 } 743 744 static const unsigned DPRDecoderTable[] = { 745 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 746 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 747 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 748 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 749 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 750 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 751 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 752 ARM::D28, ARM::D29, ARM::D30, ARM::D31 753 }; 754 755 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 756 uint64_t Address, const void *Decoder) { 757 if (RegNo > 31) 758 return MCDisassembler::Fail; 759 760 unsigned Register = DPRDecoderTable[RegNo]; 761 Inst.addOperand(MCOperand::CreateReg(Register)); 762 return MCDisassembler::Success; 763 } 764 765 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 766 uint64_t Address, const void *Decoder) { 767 if (RegNo > 7) 768 return MCDisassembler::Fail; 769 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 770 } 771 772 static DecodeStatus 773 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 774 uint64_t Address, const void *Decoder) { 775 if (RegNo > 15) 776 return MCDisassembler::Fail; 777 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 778 } 779 780 static const unsigned QPRDecoderTable[] = { 781 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 782 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 783 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 784 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 785 }; 786 787 788 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 789 uint64_t Address, const void *Decoder) { 790 if (RegNo > 31) 791 return MCDisassembler::Fail; 792 RegNo >>= 1; 793 794 unsigned Register = QPRDecoderTable[RegNo]; 795 Inst.addOperand(MCOperand::CreateReg(Register)); 796 return MCDisassembler::Success; 797 } 798 799 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 800 uint64_t Address, const void *Decoder) { 801 if (Val == 0xF) return MCDisassembler::Fail; 802 // AL predicate is not allowed on Thumb1 branches. 803 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 804 return MCDisassembler::Fail; 805 Inst.addOperand(MCOperand::CreateImm(Val)); 806 if (Val == ARMCC::AL) { 807 Inst.addOperand(MCOperand::CreateReg(0)); 808 } else 809 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 810 return MCDisassembler::Success; 811 } 812 813 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 814 uint64_t Address, const void *Decoder) { 815 if (Val) 816 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 817 else 818 Inst.addOperand(MCOperand::CreateReg(0)); 819 return MCDisassembler::Success; 820 } 821 822 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 823 uint64_t Address, const void *Decoder) { 824 uint32_t imm = Val & 0xFF; 825 uint32_t rot = (Val & 0xF00) >> 7; 826 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 827 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 828 return MCDisassembler::Success; 829 } 830 831 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 832 uint64_t Address, const void *Decoder) { 833 DecodeStatus S = MCDisassembler::Success; 834 835 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 836 unsigned type = fieldFromInstruction32(Val, 5, 2); 837 unsigned imm = fieldFromInstruction32(Val, 7, 5); 838 839 // Register-immediate 840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 841 return MCDisassembler::Fail; 842 843 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 844 switch (type) { 845 case 0: 846 Shift = ARM_AM::lsl; 847 break; 848 case 1: 849 Shift = ARM_AM::lsr; 850 break; 851 case 2: 852 Shift = ARM_AM::asr; 853 break; 854 case 3: 855 Shift = ARM_AM::ror; 856 break; 857 } 858 859 if (Shift == ARM_AM::ror && imm == 0) 860 Shift = ARM_AM::rrx; 861 862 unsigned Op = Shift | (imm << 3); 863 Inst.addOperand(MCOperand::CreateImm(Op)); 864 865 return S; 866 } 867 868 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 869 uint64_t Address, const void *Decoder) { 870 DecodeStatus S = MCDisassembler::Success; 871 872 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 873 unsigned type = fieldFromInstruction32(Val, 5, 2); 874 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 875 876 // Register-register 877 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 878 return MCDisassembler::Fail; 879 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 880 return MCDisassembler::Fail; 881 882 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 883 switch (type) { 884 case 0: 885 Shift = ARM_AM::lsl; 886 break; 887 case 1: 888 Shift = ARM_AM::lsr; 889 break; 890 case 2: 891 Shift = ARM_AM::asr; 892 break; 893 case 3: 894 Shift = ARM_AM::ror; 895 break; 896 } 897 898 Inst.addOperand(MCOperand::CreateImm(Shift)); 899 900 return S; 901 } 902 903 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 904 uint64_t Address, const void *Decoder) { 905 DecodeStatus S = MCDisassembler::Success; 906 907 // Empty register lists are not allowed. 908 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 909 for (unsigned i = 0; i < 16; ++i) { 910 if (Val & (1 << i)) { 911 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 912 return MCDisassembler::Fail; 913 } 914 } 915 916 return S; 917 } 918 919 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 920 uint64_t Address, const void *Decoder) { 921 DecodeStatus S = MCDisassembler::Success; 922 923 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 924 unsigned regs = Val & 0xFF; 925 926 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 927 return MCDisassembler::Fail; 928 for (unsigned i = 0; i < (regs - 1); ++i) { 929 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 930 return MCDisassembler::Fail; 931 } 932 933 return S; 934 } 935 936 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 937 uint64_t Address, const void *Decoder) { 938 DecodeStatus S = MCDisassembler::Success; 939 940 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 941 unsigned regs = (Val & 0xFF) / 2; 942 943 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 944 return MCDisassembler::Fail; 945 for (unsigned i = 0; i < (regs - 1); ++i) { 946 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 947 return MCDisassembler::Fail; 948 } 949 950 return S; 951 } 952 953 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 954 uint64_t Address, const void *Decoder) { 955 // This operand encodes a mask of contiguous zeros between a specified MSB 956 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 957 // the mask of all bits LSB-and-lower, and then xor them to create 958 // the mask of that's all ones on [msb, lsb]. Finally we not it to 959 // create the final mask. 960 unsigned msb = fieldFromInstruction32(Val, 5, 5); 961 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 962 uint32_t msb_mask = (1 << (msb+1)) - 1; 963 uint32_t lsb_mask = (1 << lsb) - 1; 964 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 965 return MCDisassembler::Success; 966 } 967 968 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 969 uint64_t Address, const void *Decoder) { 970 DecodeStatus S = MCDisassembler::Success; 971 972 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 973 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 974 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 975 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 976 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 977 unsigned U = fieldFromInstruction32(Insn, 23, 1); 978 979 switch (Inst.getOpcode()) { 980 case ARM::LDC_OFFSET: 981 case ARM::LDC_PRE: 982 case ARM::LDC_POST: 983 case ARM::LDC_OPTION: 984 case ARM::LDCL_OFFSET: 985 case ARM::LDCL_PRE: 986 case ARM::LDCL_POST: 987 case ARM::LDCL_OPTION: 988 case ARM::STC_OFFSET: 989 case ARM::STC_PRE: 990 case ARM::STC_POST: 991 case ARM::STC_OPTION: 992 case ARM::STCL_OFFSET: 993 case ARM::STCL_PRE: 994 case ARM::STCL_POST: 995 case ARM::STCL_OPTION: 996 case ARM::t2LDC_OFFSET: 997 case ARM::t2LDC_PRE: 998 case ARM::t2LDC_POST: 999 case ARM::t2LDC_OPTION: 1000 case ARM::t2LDCL_OFFSET: 1001 case ARM::t2LDCL_PRE: 1002 case ARM::t2LDCL_POST: 1003 case ARM::t2LDCL_OPTION: 1004 case ARM::t2STC_OFFSET: 1005 case ARM::t2STC_PRE: 1006 case ARM::t2STC_POST: 1007 case ARM::t2STC_OPTION: 1008 case ARM::t2STCL_OFFSET: 1009 case ARM::t2STCL_PRE: 1010 case ARM::t2STCL_POST: 1011 case ARM::t2STCL_OPTION: 1012 if (coproc == 0xA || coproc == 0xB) 1013 return MCDisassembler::Fail; 1014 break; 1015 default: 1016 break; 1017 } 1018 1019 Inst.addOperand(MCOperand::CreateImm(coproc)); 1020 Inst.addOperand(MCOperand::CreateImm(CRd)); 1021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1022 return MCDisassembler::Fail; 1023 switch (Inst.getOpcode()) { 1024 case ARM::LDC_OPTION: 1025 case ARM::LDCL_OPTION: 1026 case ARM::LDC2_OPTION: 1027 case ARM::LDC2L_OPTION: 1028 case ARM::STC_OPTION: 1029 case ARM::STCL_OPTION: 1030 case ARM::STC2_OPTION: 1031 case ARM::STC2L_OPTION: 1032 case ARM::LDCL_POST: 1033 case ARM::STCL_POST: 1034 case ARM::LDC2L_POST: 1035 case ARM::STC2L_POST: 1036 case ARM::t2LDC_OPTION: 1037 case ARM::t2LDCL_OPTION: 1038 case ARM::t2STC_OPTION: 1039 case ARM::t2STCL_OPTION: 1040 case ARM::t2LDCL_POST: 1041 case ARM::t2STCL_POST: 1042 break; 1043 default: 1044 Inst.addOperand(MCOperand::CreateReg(0)); 1045 break; 1046 } 1047 1048 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1049 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1050 1051 bool writeback = (P == 0) || (W == 1); 1052 unsigned idx_mode = 0; 1053 if (P && writeback) 1054 idx_mode = ARMII::IndexModePre; 1055 else if (!P && writeback) 1056 idx_mode = ARMII::IndexModePost; 1057 1058 switch (Inst.getOpcode()) { 1059 case ARM::LDCL_POST: 1060 case ARM::STCL_POST: 1061 case ARM::t2LDCL_POST: 1062 case ARM::t2STCL_POST: 1063 case ARM::LDC2L_POST: 1064 case ARM::STC2L_POST: 1065 imm |= U << 8; 1066 case ARM::LDC_OPTION: 1067 case ARM::LDCL_OPTION: 1068 case ARM::LDC2_OPTION: 1069 case ARM::LDC2L_OPTION: 1070 case ARM::STC_OPTION: 1071 case ARM::STCL_OPTION: 1072 case ARM::STC2_OPTION: 1073 case ARM::STC2L_OPTION: 1074 case ARM::t2LDC_OPTION: 1075 case ARM::t2LDCL_OPTION: 1076 case ARM::t2STC_OPTION: 1077 case ARM::t2STCL_OPTION: 1078 Inst.addOperand(MCOperand::CreateImm(imm)); 1079 break; 1080 default: 1081 if (U) 1082 Inst.addOperand(MCOperand::CreateImm( 1083 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1084 else 1085 Inst.addOperand(MCOperand::CreateImm( 1086 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1087 break; 1088 } 1089 1090 switch (Inst.getOpcode()) { 1091 case ARM::LDC_OFFSET: 1092 case ARM::LDC_PRE: 1093 case ARM::LDC_POST: 1094 case ARM::LDC_OPTION: 1095 case ARM::LDCL_OFFSET: 1096 case ARM::LDCL_PRE: 1097 case ARM::LDCL_POST: 1098 case ARM::LDCL_OPTION: 1099 case ARM::STC_OFFSET: 1100 case ARM::STC_PRE: 1101 case ARM::STC_POST: 1102 case ARM::STC_OPTION: 1103 case ARM::STCL_OFFSET: 1104 case ARM::STCL_PRE: 1105 case ARM::STCL_POST: 1106 case ARM::STCL_OPTION: 1107 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1108 return MCDisassembler::Fail; 1109 break; 1110 default: 1111 break; 1112 } 1113 1114 return S; 1115 } 1116 1117 static DecodeStatus 1118 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1119 uint64_t Address, const void *Decoder) { 1120 DecodeStatus S = MCDisassembler::Success; 1121 1122 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1123 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1124 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1125 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1126 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1127 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1128 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1129 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1130 1131 // On stores, the writeback operand precedes Rt. 1132 switch (Inst.getOpcode()) { 1133 case ARM::STR_POST_IMM: 1134 case ARM::STR_POST_REG: 1135 case ARM::STRB_POST_IMM: 1136 case ARM::STRB_POST_REG: 1137 case ARM::STRT_POST_REG: 1138 case ARM::STRT_POST_IMM: 1139 case ARM::STRBT_POST_REG: 1140 case ARM::STRBT_POST_IMM: 1141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1142 return MCDisassembler::Fail; 1143 break; 1144 default: 1145 break; 1146 } 1147 1148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1149 return MCDisassembler::Fail; 1150 1151 // On loads, the writeback operand comes after Rt. 1152 switch (Inst.getOpcode()) { 1153 case ARM::LDR_POST_IMM: 1154 case ARM::LDR_POST_REG: 1155 case ARM::LDRB_POST_IMM: 1156 case ARM::LDRB_POST_REG: 1157 case ARM::LDRBT_POST_REG: 1158 case ARM::LDRBT_POST_IMM: 1159 case ARM::LDRT_POST_REG: 1160 case ARM::LDRT_POST_IMM: 1161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1162 return MCDisassembler::Fail; 1163 break; 1164 default: 1165 break; 1166 } 1167 1168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1169 return MCDisassembler::Fail; 1170 1171 ARM_AM::AddrOpc Op = ARM_AM::add; 1172 if (!fieldFromInstruction32(Insn, 23, 1)) 1173 Op = ARM_AM::sub; 1174 1175 bool writeback = (P == 0) || (W == 1); 1176 unsigned idx_mode = 0; 1177 if (P && writeback) 1178 idx_mode = ARMII::IndexModePre; 1179 else if (!P && writeback) 1180 idx_mode = ARMII::IndexModePost; 1181 1182 if (writeback && (Rn == 15 || Rn == Rt)) 1183 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1184 1185 if (reg) { 1186 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1187 return MCDisassembler::Fail; 1188 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1189 switch( fieldFromInstruction32(Insn, 5, 2)) { 1190 case 0: 1191 Opc = ARM_AM::lsl; 1192 break; 1193 case 1: 1194 Opc = ARM_AM::lsr; 1195 break; 1196 case 2: 1197 Opc = ARM_AM::asr; 1198 break; 1199 case 3: 1200 Opc = ARM_AM::ror; 1201 break; 1202 default: 1203 return MCDisassembler::Fail; 1204 } 1205 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1206 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1207 1208 Inst.addOperand(MCOperand::CreateImm(imm)); 1209 } else { 1210 Inst.addOperand(MCOperand::CreateReg(0)); 1211 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1212 Inst.addOperand(MCOperand::CreateImm(tmp)); 1213 } 1214 1215 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1216 return MCDisassembler::Fail; 1217 1218 return S; 1219 } 1220 1221 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1222 uint64_t Address, const void *Decoder) { 1223 DecodeStatus S = MCDisassembler::Success; 1224 1225 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1226 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1227 unsigned type = fieldFromInstruction32(Val, 5, 2); 1228 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1229 unsigned U = fieldFromInstruction32(Val, 12, 1); 1230 1231 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1232 switch (type) { 1233 case 0: 1234 ShOp = ARM_AM::lsl; 1235 break; 1236 case 1: 1237 ShOp = ARM_AM::lsr; 1238 break; 1239 case 2: 1240 ShOp = ARM_AM::asr; 1241 break; 1242 case 3: 1243 ShOp = ARM_AM::ror; 1244 break; 1245 } 1246 1247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1248 return MCDisassembler::Fail; 1249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 unsigned shift; 1252 if (U) 1253 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1254 else 1255 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1256 Inst.addOperand(MCOperand::CreateImm(shift)); 1257 1258 return S; 1259 } 1260 1261 static DecodeStatus 1262 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1263 uint64_t Address, const void *Decoder) { 1264 DecodeStatus S = MCDisassembler::Success; 1265 1266 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1267 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1268 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1269 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1270 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1271 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1272 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1273 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1274 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1275 1276 bool writeback = (W == 1) | (P == 0); 1277 1278 // For {LD,ST}RD, Rt must be even, else undefined. 1279 switch (Inst.getOpcode()) { 1280 case ARM::STRD: 1281 case ARM::STRD_PRE: 1282 case ARM::STRD_POST: 1283 case ARM::LDRD: 1284 case ARM::LDRD_PRE: 1285 case ARM::LDRD_POST: 1286 if (Rt & 0x1) return MCDisassembler::Fail; 1287 break; 1288 default: 1289 break; 1290 } 1291 1292 if (writeback) { // Writeback 1293 if (P) 1294 U |= ARMII::IndexModePre << 9; 1295 else 1296 U |= ARMII::IndexModePost << 9; 1297 1298 // On stores, the writeback operand precedes Rt. 1299 switch (Inst.getOpcode()) { 1300 case ARM::STRD: 1301 case ARM::STRD_PRE: 1302 case ARM::STRD_POST: 1303 case ARM::STRH: 1304 case ARM::STRH_PRE: 1305 case ARM::STRH_POST: 1306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1307 return MCDisassembler::Fail; 1308 break; 1309 default: 1310 break; 1311 } 1312 } 1313 1314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1315 return MCDisassembler::Fail; 1316 switch (Inst.getOpcode()) { 1317 case ARM::STRD: 1318 case ARM::STRD_PRE: 1319 case ARM::STRD_POST: 1320 case ARM::LDRD: 1321 case ARM::LDRD_PRE: 1322 case ARM::LDRD_POST: 1323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1324 return MCDisassembler::Fail; 1325 break; 1326 default: 1327 break; 1328 } 1329 1330 if (writeback) { 1331 // On loads, the writeback operand comes after Rt. 1332 switch (Inst.getOpcode()) { 1333 case ARM::LDRD: 1334 case ARM::LDRD_PRE: 1335 case ARM::LDRD_POST: 1336 case ARM::LDRH: 1337 case ARM::LDRH_PRE: 1338 case ARM::LDRH_POST: 1339 case ARM::LDRSH: 1340 case ARM::LDRSH_PRE: 1341 case ARM::LDRSH_POST: 1342 case ARM::LDRSB: 1343 case ARM::LDRSB_PRE: 1344 case ARM::LDRSB_POST: 1345 case ARM::LDRHTr: 1346 case ARM::LDRSBTr: 1347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1348 return MCDisassembler::Fail; 1349 break; 1350 default: 1351 break; 1352 } 1353 } 1354 1355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1356 return MCDisassembler::Fail; 1357 1358 if (type) { 1359 Inst.addOperand(MCOperand::CreateReg(0)); 1360 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1361 } else { 1362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1363 return MCDisassembler::Fail; 1364 Inst.addOperand(MCOperand::CreateImm(U)); 1365 } 1366 1367 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1368 return MCDisassembler::Fail; 1369 1370 return S; 1371 } 1372 1373 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1374 uint64_t Address, const void *Decoder) { 1375 DecodeStatus S = MCDisassembler::Success; 1376 1377 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1378 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1379 1380 switch (mode) { 1381 case 0: 1382 mode = ARM_AM::da; 1383 break; 1384 case 1: 1385 mode = ARM_AM::ia; 1386 break; 1387 case 2: 1388 mode = ARM_AM::db; 1389 break; 1390 case 3: 1391 mode = ARM_AM::ib; 1392 break; 1393 } 1394 1395 Inst.addOperand(MCOperand::CreateImm(mode)); 1396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1397 return MCDisassembler::Fail; 1398 1399 return S; 1400 } 1401 1402 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1403 unsigned Insn, 1404 uint64_t Address, const void *Decoder) { 1405 DecodeStatus S = MCDisassembler::Success; 1406 1407 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1408 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1409 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1410 1411 if (pred == 0xF) { 1412 switch (Inst.getOpcode()) { 1413 case ARM::LDMDA: 1414 Inst.setOpcode(ARM::RFEDA); 1415 break; 1416 case ARM::LDMDA_UPD: 1417 Inst.setOpcode(ARM::RFEDA_UPD); 1418 break; 1419 case ARM::LDMDB: 1420 Inst.setOpcode(ARM::RFEDB); 1421 break; 1422 case ARM::LDMDB_UPD: 1423 Inst.setOpcode(ARM::RFEDB_UPD); 1424 break; 1425 case ARM::LDMIA: 1426 Inst.setOpcode(ARM::RFEIA); 1427 break; 1428 case ARM::LDMIA_UPD: 1429 Inst.setOpcode(ARM::RFEIA_UPD); 1430 break; 1431 case ARM::LDMIB: 1432 Inst.setOpcode(ARM::RFEIB); 1433 break; 1434 case ARM::LDMIB_UPD: 1435 Inst.setOpcode(ARM::RFEIB_UPD); 1436 break; 1437 case ARM::STMDA: 1438 Inst.setOpcode(ARM::SRSDA); 1439 break; 1440 case ARM::STMDA_UPD: 1441 Inst.setOpcode(ARM::SRSDA_UPD); 1442 break; 1443 case ARM::STMDB: 1444 Inst.setOpcode(ARM::SRSDB); 1445 break; 1446 case ARM::STMDB_UPD: 1447 Inst.setOpcode(ARM::SRSDB_UPD); 1448 break; 1449 case ARM::STMIA: 1450 Inst.setOpcode(ARM::SRSIA); 1451 break; 1452 case ARM::STMIA_UPD: 1453 Inst.setOpcode(ARM::SRSIA_UPD); 1454 break; 1455 case ARM::STMIB: 1456 Inst.setOpcode(ARM::SRSIB); 1457 break; 1458 case ARM::STMIB_UPD: 1459 Inst.setOpcode(ARM::SRSIB_UPD); 1460 break; 1461 default: 1462 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1463 } 1464 1465 // For stores (which become SRS's, the only operand is the mode. 1466 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1467 Inst.addOperand( 1468 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1469 return S; 1470 } 1471 1472 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1473 } 1474 1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1476 return MCDisassembler::Fail; 1477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1478 return MCDisassembler::Fail; // Tied 1479 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1480 return MCDisassembler::Fail; 1481 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 1484 return S; 1485 } 1486 1487 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1488 uint64_t Address, const void *Decoder) { 1489 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1490 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1491 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1492 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1493 1494 DecodeStatus S = MCDisassembler::Success; 1495 1496 // imod == '01' --> UNPREDICTABLE 1497 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1498 // return failure here. The '01' imod value is unprintable, so there's 1499 // nothing useful we could do even if we returned UNPREDICTABLE. 1500 1501 if (imod == 1) return MCDisassembler::Fail; 1502 1503 if (imod && M) { 1504 Inst.setOpcode(ARM::CPS3p); 1505 Inst.addOperand(MCOperand::CreateImm(imod)); 1506 Inst.addOperand(MCOperand::CreateImm(iflags)); 1507 Inst.addOperand(MCOperand::CreateImm(mode)); 1508 } else if (imod && !M) { 1509 Inst.setOpcode(ARM::CPS2p); 1510 Inst.addOperand(MCOperand::CreateImm(imod)); 1511 Inst.addOperand(MCOperand::CreateImm(iflags)); 1512 if (mode) S = MCDisassembler::SoftFail; 1513 } else if (!imod && M) { 1514 Inst.setOpcode(ARM::CPS1p); 1515 Inst.addOperand(MCOperand::CreateImm(mode)); 1516 if (iflags) S = MCDisassembler::SoftFail; 1517 } else { 1518 // imod == '00' && M == '0' --> UNPREDICTABLE 1519 Inst.setOpcode(ARM::CPS1p); 1520 Inst.addOperand(MCOperand::CreateImm(mode)); 1521 S = MCDisassembler::SoftFail; 1522 } 1523 1524 return S; 1525 } 1526 1527 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1528 uint64_t Address, const void *Decoder) { 1529 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1530 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1531 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1532 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1533 1534 DecodeStatus S = MCDisassembler::Success; 1535 1536 // imod == '01' --> UNPREDICTABLE 1537 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1538 // return failure here. The '01' imod value is unprintable, so there's 1539 // nothing useful we could do even if we returned UNPREDICTABLE. 1540 1541 if (imod == 1) return MCDisassembler::Fail; 1542 1543 if (imod && M) { 1544 Inst.setOpcode(ARM::t2CPS3p); 1545 Inst.addOperand(MCOperand::CreateImm(imod)); 1546 Inst.addOperand(MCOperand::CreateImm(iflags)); 1547 Inst.addOperand(MCOperand::CreateImm(mode)); 1548 } else if (imod && !M) { 1549 Inst.setOpcode(ARM::t2CPS2p); 1550 Inst.addOperand(MCOperand::CreateImm(imod)); 1551 Inst.addOperand(MCOperand::CreateImm(iflags)); 1552 if (mode) S = MCDisassembler::SoftFail; 1553 } else if (!imod && M) { 1554 Inst.setOpcode(ARM::t2CPS1p); 1555 Inst.addOperand(MCOperand::CreateImm(mode)); 1556 if (iflags) S = MCDisassembler::SoftFail; 1557 } else { 1558 // imod == '00' && M == '0' --> UNPREDICTABLE 1559 Inst.setOpcode(ARM::t2CPS1p); 1560 Inst.addOperand(MCOperand::CreateImm(mode)); 1561 S = MCDisassembler::SoftFail; 1562 } 1563 1564 return S; 1565 } 1566 1567 1568 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1569 uint64_t Address, const void *Decoder) { 1570 DecodeStatus S = MCDisassembler::Success; 1571 1572 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1573 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1574 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1575 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1576 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1577 1578 if (pred == 0xF) 1579 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1580 1581 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1584 return MCDisassembler::Fail; 1585 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1586 return MCDisassembler::Fail; 1587 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1588 return MCDisassembler::Fail; 1589 1590 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1591 return MCDisassembler::Fail; 1592 1593 return S; 1594 } 1595 1596 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1597 uint64_t Address, const void *Decoder) { 1598 DecodeStatus S = MCDisassembler::Success; 1599 1600 unsigned add = fieldFromInstruction32(Val, 12, 1); 1601 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1602 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1603 1604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1605 return MCDisassembler::Fail; 1606 1607 if (!add) imm *= -1; 1608 if (imm == 0 && !add) imm = INT32_MIN; 1609 Inst.addOperand(MCOperand::CreateImm(imm)); 1610 1611 return S; 1612 } 1613 1614 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1615 uint64_t Address, const void *Decoder) { 1616 DecodeStatus S = MCDisassembler::Success; 1617 1618 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1619 unsigned U = fieldFromInstruction32(Val, 8, 1); 1620 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1621 1622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1623 return MCDisassembler::Fail; 1624 1625 if (U) 1626 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1627 else 1628 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1629 1630 return S; 1631 } 1632 1633 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1634 uint64_t Address, const void *Decoder) { 1635 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1636 } 1637 1638 static DecodeStatus 1639 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1640 uint64_t Address, const void *Decoder) { 1641 DecodeStatus S = MCDisassembler::Success; 1642 1643 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1644 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1645 1646 if (pred == 0xF) { 1647 Inst.setOpcode(ARM::BLXi); 1648 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1649 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1650 return S; 1651 } 1652 1653 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1654 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1655 return MCDisassembler::Fail; 1656 1657 return S; 1658 } 1659 1660 1661 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1662 uint64_t Address, const void *Decoder) { 1663 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1664 return MCDisassembler::Success; 1665 } 1666 1667 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1668 uint64_t Address, const void *Decoder) { 1669 DecodeStatus S = MCDisassembler::Success; 1670 1671 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1672 unsigned align = fieldFromInstruction32(Val, 4, 2); 1673 1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1675 return MCDisassembler::Fail; 1676 if (!align) 1677 Inst.addOperand(MCOperand::CreateImm(0)); 1678 else 1679 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1680 1681 return S; 1682 } 1683 1684 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1685 uint64_t Address, const void *Decoder) { 1686 DecodeStatus S = MCDisassembler::Success; 1687 1688 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1689 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1690 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1692 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1693 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1694 1695 // First output register 1696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1697 return MCDisassembler::Fail; 1698 1699 // Second output register 1700 switch (Inst.getOpcode()) { 1701 case ARM::VLD1q8: 1702 case ARM::VLD1q16: 1703 case ARM::VLD1q32: 1704 case ARM::VLD1q64: 1705 case ARM::VLD1q8_UPD: 1706 case ARM::VLD1q16_UPD: 1707 case ARM::VLD1q32_UPD: 1708 case ARM::VLD1q64_UPD: 1709 case ARM::VLD1d8T: 1710 case ARM::VLD1d16T: 1711 case ARM::VLD1d32T: 1712 case ARM::VLD1d64T: 1713 case ARM::VLD1d8T_UPD: 1714 case ARM::VLD1d16T_UPD: 1715 case ARM::VLD1d32T_UPD: 1716 case ARM::VLD1d64T_UPD: 1717 case ARM::VLD1d8Q: 1718 case ARM::VLD1d16Q: 1719 case ARM::VLD1d32Q: 1720 case ARM::VLD1d64Q: 1721 case ARM::VLD1d8Q_UPD: 1722 case ARM::VLD1d16Q_UPD: 1723 case ARM::VLD1d32Q_UPD: 1724 case ARM::VLD1d64Q_UPD: 1725 case ARM::VLD2d8: 1726 case ARM::VLD2d16: 1727 case ARM::VLD2d32: 1728 case ARM::VLD2d8_UPD: 1729 case ARM::VLD2d16_UPD: 1730 case ARM::VLD2d32_UPD: 1731 case ARM::VLD2q8: 1732 case ARM::VLD2q16: 1733 case ARM::VLD2q32: 1734 case ARM::VLD2q8_UPD: 1735 case ARM::VLD2q16_UPD: 1736 case ARM::VLD2q32_UPD: 1737 case ARM::VLD3d8: 1738 case ARM::VLD3d16: 1739 case ARM::VLD3d32: 1740 case ARM::VLD3d8_UPD: 1741 case ARM::VLD3d16_UPD: 1742 case ARM::VLD3d32_UPD: 1743 case ARM::VLD4d8: 1744 case ARM::VLD4d16: 1745 case ARM::VLD4d32: 1746 case ARM::VLD4d8_UPD: 1747 case ARM::VLD4d16_UPD: 1748 case ARM::VLD4d32_UPD: 1749 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1750 return MCDisassembler::Fail; 1751 break; 1752 case ARM::VLD2b8: 1753 case ARM::VLD2b16: 1754 case ARM::VLD2b32: 1755 case ARM::VLD2b8_UPD: 1756 case ARM::VLD2b16_UPD: 1757 case ARM::VLD2b32_UPD: 1758 case ARM::VLD3q8: 1759 case ARM::VLD3q16: 1760 case ARM::VLD3q32: 1761 case ARM::VLD3q8_UPD: 1762 case ARM::VLD3q16_UPD: 1763 case ARM::VLD3q32_UPD: 1764 case ARM::VLD4q8: 1765 case ARM::VLD4q16: 1766 case ARM::VLD4q32: 1767 case ARM::VLD4q8_UPD: 1768 case ARM::VLD4q16_UPD: 1769 case ARM::VLD4q32_UPD: 1770 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1771 return MCDisassembler::Fail; 1772 default: 1773 break; 1774 } 1775 1776 // Third output register 1777 switch(Inst.getOpcode()) { 1778 case ARM::VLD1d8T: 1779 case ARM::VLD1d16T: 1780 case ARM::VLD1d32T: 1781 case ARM::VLD1d64T: 1782 case ARM::VLD1d8T_UPD: 1783 case ARM::VLD1d16T_UPD: 1784 case ARM::VLD1d32T_UPD: 1785 case ARM::VLD1d64T_UPD: 1786 case ARM::VLD1d8Q: 1787 case ARM::VLD1d16Q: 1788 case ARM::VLD1d32Q: 1789 case ARM::VLD1d64Q: 1790 case ARM::VLD1d8Q_UPD: 1791 case ARM::VLD1d16Q_UPD: 1792 case ARM::VLD1d32Q_UPD: 1793 case ARM::VLD1d64Q_UPD: 1794 case ARM::VLD2q8: 1795 case ARM::VLD2q16: 1796 case ARM::VLD2q32: 1797 case ARM::VLD2q8_UPD: 1798 case ARM::VLD2q16_UPD: 1799 case ARM::VLD2q32_UPD: 1800 case ARM::VLD3d8: 1801 case ARM::VLD3d16: 1802 case ARM::VLD3d32: 1803 case ARM::VLD3d8_UPD: 1804 case ARM::VLD3d16_UPD: 1805 case ARM::VLD3d32_UPD: 1806 case ARM::VLD4d8: 1807 case ARM::VLD4d16: 1808 case ARM::VLD4d32: 1809 case ARM::VLD4d8_UPD: 1810 case ARM::VLD4d16_UPD: 1811 case ARM::VLD4d32_UPD: 1812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1813 return MCDisassembler::Fail; 1814 break; 1815 case ARM::VLD3q8: 1816 case ARM::VLD3q16: 1817 case ARM::VLD3q32: 1818 case ARM::VLD3q8_UPD: 1819 case ARM::VLD3q16_UPD: 1820 case ARM::VLD3q32_UPD: 1821 case ARM::VLD4q8: 1822 case ARM::VLD4q16: 1823 case ARM::VLD4q32: 1824 case ARM::VLD4q8_UPD: 1825 case ARM::VLD4q16_UPD: 1826 case ARM::VLD4q32_UPD: 1827 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1828 return MCDisassembler::Fail; 1829 break; 1830 default: 1831 break; 1832 } 1833 1834 // Fourth output register 1835 switch (Inst.getOpcode()) { 1836 case ARM::VLD1d8Q: 1837 case ARM::VLD1d16Q: 1838 case ARM::VLD1d32Q: 1839 case ARM::VLD1d64Q: 1840 case ARM::VLD1d8Q_UPD: 1841 case ARM::VLD1d16Q_UPD: 1842 case ARM::VLD1d32Q_UPD: 1843 case ARM::VLD1d64Q_UPD: 1844 case ARM::VLD2q8: 1845 case ARM::VLD2q16: 1846 case ARM::VLD2q32: 1847 case ARM::VLD2q8_UPD: 1848 case ARM::VLD2q16_UPD: 1849 case ARM::VLD2q32_UPD: 1850 case ARM::VLD4d8: 1851 case ARM::VLD4d16: 1852 case ARM::VLD4d32: 1853 case ARM::VLD4d8_UPD: 1854 case ARM::VLD4d16_UPD: 1855 case ARM::VLD4d32_UPD: 1856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1857 return MCDisassembler::Fail; 1858 break; 1859 case ARM::VLD4q8: 1860 case ARM::VLD4q16: 1861 case ARM::VLD4q32: 1862 case ARM::VLD4q8_UPD: 1863 case ARM::VLD4q16_UPD: 1864 case ARM::VLD4q32_UPD: 1865 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1866 return MCDisassembler::Fail; 1867 break; 1868 default: 1869 break; 1870 } 1871 1872 // Writeback operand 1873 switch (Inst.getOpcode()) { 1874 case ARM::VLD1d8_UPD: 1875 case ARM::VLD1d16_UPD: 1876 case ARM::VLD1d32_UPD: 1877 case ARM::VLD1d64_UPD: 1878 case ARM::VLD1q8_UPD: 1879 case ARM::VLD1q16_UPD: 1880 case ARM::VLD1q32_UPD: 1881 case ARM::VLD1q64_UPD: 1882 case ARM::VLD1d8T_UPD: 1883 case ARM::VLD1d16T_UPD: 1884 case ARM::VLD1d32T_UPD: 1885 case ARM::VLD1d64T_UPD: 1886 case ARM::VLD1d8Q_UPD: 1887 case ARM::VLD1d16Q_UPD: 1888 case ARM::VLD1d32Q_UPD: 1889 case ARM::VLD1d64Q_UPD: 1890 case ARM::VLD2d8_UPD: 1891 case ARM::VLD2d16_UPD: 1892 case ARM::VLD2d32_UPD: 1893 case ARM::VLD2q8_UPD: 1894 case ARM::VLD2q16_UPD: 1895 case ARM::VLD2q32_UPD: 1896 case ARM::VLD2b8_UPD: 1897 case ARM::VLD2b16_UPD: 1898 case ARM::VLD2b32_UPD: 1899 case ARM::VLD3d8_UPD: 1900 case ARM::VLD3d16_UPD: 1901 case ARM::VLD3d32_UPD: 1902 case ARM::VLD3q8_UPD: 1903 case ARM::VLD3q16_UPD: 1904 case ARM::VLD3q32_UPD: 1905 case ARM::VLD4d8_UPD: 1906 case ARM::VLD4d16_UPD: 1907 case ARM::VLD4d32_UPD: 1908 case ARM::VLD4q8_UPD: 1909 case ARM::VLD4q16_UPD: 1910 case ARM::VLD4q32_UPD: 1911 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 break; 1914 default: 1915 break; 1916 } 1917 1918 // AddrMode6 Base (register+alignment) 1919 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1920 return MCDisassembler::Fail; 1921 1922 // AddrMode6 Offset (register) 1923 if (Rm == 0xD) 1924 Inst.addOperand(MCOperand::CreateReg(0)); 1925 else if (Rm != 0xF) { 1926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1927 return MCDisassembler::Fail; 1928 } 1929 1930 return S; 1931 } 1932 1933 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1934 uint64_t Address, const void *Decoder) { 1935 DecodeStatus S = MCDisassembler::Success; 1936 1937 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1938 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1939 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1940 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1941 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1942 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1943 1944 // Writeback Operand 1945 switch (Inst.getOpcode()) { 1946 case ARM::VST1d8_UPD: 1947 case ARM::VST1d16_UPD: 1948 case ARM::VST1d32_UPD: 1949 case ARM::VST1d64_UPD: 1950 case ARM::VST1q8_UPD: 1951 case ARM::VST1q16_UPD: 1952 case ARM::VST1q32_UPD: 1953 case ARM::VST1q64_UPD: 1954 case ARM::VST1d8T_UPD: 1955 case ARM::VST1d16T_UPD: 1956 case ARM::VST1d32T_UPD: 1957 case ARM::VST1d64T_UPD: 1958 case ARM::VST1d8Q_UPD: 1959 case ARM::VST1d16Q_UPD: 1960 case ARM::VST1d32Q_UPD: 1961 case ARM::VST1d64Q_UPD: 1962 case ARM::VST2d8_UPD: 1963 case ARM::VST2d16_UPD: 1964 case ARM::VST2d32_UPD: 1965 case ARM::VST2q8_UPD: 1966 case ARM::VST2q16_UPD: 1967 case ARM::VST2q32_UPD: 1968 case ARM::VST2b8_UPD: 1969 case ARM::VST2b16_UPD: 1970 case ARM::VST2b32_UPD: 1971 case ARM::VST3d8_UPD: 1972 case ARM::VST3d16_UPD: 1973 case ARM::VST3d32_UPD: 1974 case ARM::VST3q8_UPD: 1975 case ARM::VST3q16_UPD: 1976 case ARM::VST3q32_UPD: 1977 case ARM::VST4d8_UPD: 1978 case ARM::VST4d16_UPD: 1979 case ARM::VST4d32_UPD: 1980 case ARM::VST4q8_UPD: 1981 case ARM::VST4q16_UPD: 1982 case ARM::VST4q32_UPD: 1983 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1984 return MCDisassembler::Fail; 1985 break; 1986 default: 1987 break; 1988 } 1989 1990 // AddrMode6 Base (register+alignment) 1991 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1992 return MCDisassembler::Fail; 1993 1994 // AddrMode6 Offset (register) 1995 if (Rm == 0xD) 1996 Inst.addOperand(MCOperand::CreateReg(0)); 1997 else if (Rm != 0xF) { 1998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1999 return MCDisassembler::Fail; 2000 } 2001 2002 // First input register 2003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2004 return MCDisassembler::Fail; 2005 2006 // Second input register 2007 switch (Inst.getOpcode()) { 2008 case ARM::VST1q8: 2009 case ARM::VST1q16: 2010 case ARM::VST1q32: 2011 case ARM::VST1q64: 2012 case ARM::VST1q8_UPD: 2013 case ARM::VST1q16_UPD: 2014 case ARM::VST1q32_UPD: 2015 case ARM::VST1q64_UPD: 2016 case ARM::VST1d8T: 2017 case ARM::VST1d16T: 2018 case ARM::VST1d32T: 2019 case ARM::VST1d64T: 2020 case ARM::VST1d8T_UPD: 2021 case ARM::VST1d16T_UPD: 2022 case ARM::VST1d32T_UPD: 2023 case ARM::VST1d64T_UPD: 2024 case ARM::VST1d8Q: 2025 case ARM::VST1d16Q: 2026 case ARM::VST1d32Q: 2027 case ARM::VST1d64Q: 2028 case ARM::VST1d8Q_UPD: 2029 case ARM::VST1d16Q_UPD: 2030 case ARM::VST1d32Q_UPD: 2031 case ARM::VST1d64Q_UPD: 2032 case ARM::VST2d8: 2033 case ARM::VST2d16: 2034 case ARM::VST2d32: 2035 case ARM::VST2d8_UPD: 2036 case ARM::VST2d16_UPD: 2037 case ARM::VST2d32_UPD: 2038 case ARM::VST2q8: 2039 case ARM::VST2q16: 2040 case ARM::VST2q32: 2041 case ARM::VST2q8_UPD: 2042 case ARM::VST2q16_UPD: 2043 case ARM::VST2q32_UPD: 2044 case ARM::VST3d8: 2045 case ARM::VST3d16: 2046 case ARM::VST3d32: 2047 case ARM::VST3d8_UPD: 2048 case ARM::VST3d16_UPD: 2049 case ARM::VST3d32_UPD: 2050 case ARM::VST4d8: 2051 case ARM::VST4d16: 2052 case ARM::VST4d32: 2053 case ARM::VST4d8_UPD: 2054 case ARM::VST4d16_UPD: 2055 case ARM::VST4d32_UPD: 2056 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2057 return MCDisassembler::Fail; 2058 break; 2059 case ARM::VST2b8: 2060 case ARM::VST2b16: 2061 case ARM::VST2b32: 2062 case ARM::VST2b8_UPD: 2063 case ARM::VST2b16_UPD: 2064 case ARM::VST2b32_UPD: 2065 case ARM::VST3q8: 2066 case ARM::VST3q16: 2067 case ARM::VST3q32: 2068 case ARM::VST3q8_UPD: 2069 case ARM::VST3q16_UPD: 2070 case ARM::VST3q32_UPD: 2071 case ARM::VST4q8: 2072 case ARM::VST4q16: 2073 case ARM::VST4q32: 2074 case ARM::VST4q8_UPD: 2075 case ARM::VST4q16_UPD: 2076 case ARM::VST4q32_UPD: 2077 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2078 return MCDisassembler::Fail; 2079 break; 2080 default: 2081 break; 2082 } 2083 2084 // Third input register 2085 switch (Inst.getOpcode()) { 2086 case ARM::VST1d8T: 2087 case ARM::VST1d16T: 2088 case ARM::VST1d32T: 2089 case ARM::VST1d64T: 2090 case ARM::VST1d8T_UPD: 2091 case ARM::VST1d16T_UPD: 2092 case ARM::VST1d32T_UPD: 2093 case ARM::VST1d64T_UPD: 2094 case ARM::VST1d8Q: 2095 case ARM::VST1d16Q: 2096 case ARM::VST1d32Q: 2097 case ARM::VST1d64Q: 2098 case ARM::VST1d8Q_UPD: 2099 case ARM::VST1d16Q_UPD: 2100 case ARM::VST1d32Q_UPD: 2101 case ARM::VST1d64Q_UPD: 2102 case ARM::VST2q8: 2103 case ARM::VST2q16: 2104 case ARM::VST2q32: 2105 case ARM::VST2q8_UPD: 2106 case ARM::VST2q16_UPD: 2107 case ARM::VST2q32_UPD: 2108 case ARM::VST3d8: 2109 case ARM::VST3d16: 2110 case ARM::VST3d32: 2111 case ARM::VST3d8_UPD: 2112 case ARM::VST3d16_UPD: 2113 case ARM::VST3d32_UPD: 2114 case ARM::VST4d8: 2115 case ARM::VST4d16: 2116 case ARM::VST4d32: 2117 case ARM::VST4d8_UPD: 2118 case ARM::VST4d16_UPD: 2119 case ARM::VST4d32_UPD: 2120 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 break; 2123 case ARM::VST3q8: 2124 case ARM::VST3q16: 2125 case ARM::VST3q32: 2126 case ARM::VST3q8_UPD: 2127 case ARM::VST3q16_UPD: 2128 case ARM::VST3q32_UPD: 2129 case ARM::VST4q8: 2130 case ARM::VST4q16: 2131 case ARM::VST4q32: 2132 case ARM::VST4q8_UPD: 2133 case ARM::VST4q16_UPD: 2134 case ARM::VST4q32_UPD: 2135 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 break; 2138 default: 2139 break; 2140 } 2141 2142 // Fourth input register 2143 switch (Inst.getOpcode()) { 2144 case ARM::VST1d8Q: 2145 case ARM::VST1d16Q: 2146 case ARM::VST1d32Q: 2147 case ARM::VST1d64Q: 2148 case ARM::VST1d8Q_UPD: 2149 case ARM::VST1d16Q_UPD: 2150 case ARM::VST1d32Q_UPD: 2151 case ARM::VST1d64Q_UPD: 2152 case ARM::VST2q8: 2153 case ARM::VST2q16: 2154 case ARM::VST2q32: 2155 case ARM::VST2q8_UPD: 2156 case ARM::VST2q16_UPD: 2157 case ARM::VST2q32_UPD: 2158 case ARM::VST4d8: 2159 case ARM::VST4d16: 2160 case ARM::VST4d32: 2161 case ARM::VST4d8_UPD: 2162 case ARM::VST4d16_UPD: 2163 case ARM::VST4d32_UPD: 2164 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 break; 2167 case ARM::VST4q8: 2168 case ARM::VST4q16: 2169 case ARM::VST4q32: 2170 case ARM::VST4q8_UPD: 2171 case ARM::VST4q16_UPD: 2172 case ARM::VST4q32_UPD: 2173 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 break; 2176 default: 2177 break; 2178 } 2179 2180 return S; 2181 } 2182 2183 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2184 uint64_t Address, const void *Decoder) { 2185 DecodeStatus S = MCDisassembler::Success; 2186 2187 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2188 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2190 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2191 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2192 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2193 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2194 2195 align *= (1 << size); 2196 2197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 if (regs == 2) { 2200 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2201 return MCDisassembler::Fail; 2202 } 2203 if (Rm != 0xF) { 2204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 } 2207 2208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2209 return MCDisassembler::Fail; 2210 Inst.addOperand(MCOperand::CreateImm(align)); 2211 2212 if (Rm == 0xD) 2213 Inst.addOperand(MCOperand::CreateReg(0)); 2214 else if (Rm != 0xF) { 2215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2216 return MCDisassembler::Fail; 2217 } 2218 2219 return S; 2220 } 2221 2222 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2223 uint64_t Address, const void *Decoder) { 2224 DecodeStatus S = MCDisassembler::Success; 2225 2226 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2227 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2228 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2229 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2230 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2231 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2232 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2233 align *= 2*size; 2234 2235 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2236 return MCDisassembler::Fail; 2237 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2238 return MCDisassembler::Fail; 2239 if (Rm != 0xF) { 2240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2241 return MCDisassembler::Fail; 2242 } 2243 2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 Inst.addOperand(MCOperand::CreateImm(align)); 2247 2248 if (Rm == 0xD) 2249 Inst.addOperand(MCOperand::CreateReg(0)); 2250 else if (Rm != 0xF) { 2251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2252 return MCDisassembler::Fail; 2253 } 2254 2255 return S; 2256 } 2257 2258 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2259 uint64_t Address, const void *Decoder) { 2260 DecodeStatus S = MCDisassembler::Success; 2261 2262 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2263 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2264 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2265 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2266 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2267 2268 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2269 return MCDisassembler::Fail; 2270 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2273 return MCDisassembler::Fail; 2274 if (Rm != 0xF) { 2275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2276 return MCDisassembler::Fail; 2277 } 2278 2279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2280 return MCDisassembler::Fail; 2281 Inst.addOperand(MCOperand::CreateImm(0)); 2282 2283 if (Rm == 0xD) 2284 Inst.addOperand(MCOperand::CreateReg(0)); 2285 else if (Rm != 0xF) { 2286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2287 return MCDisassembler::Fail; 2288 } 2289 2290 return S; 2291 } 2292 2293 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2294 uint64_t Address, const void *Decoder) { 2295 DecodeStatus S = MCDisassembler::Success; 2296 2297 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2298 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2299 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2300 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2301 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2302 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2303 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2304 2305 if (size == 0x3) { 2306 size = 4; 2307 align = 16; 2308 } else { 2309 if (size == 2) { 2310 size = 1 << size; 2311 align *= 8; 2312 } else { 2313 size = 1 << size; 2314 align *= 4*size; 2315 } 2316 } 2317 2318 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2319 return MCDisassembler::Fail; 2320 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2323 return MCDisassembler::Fail; 2324 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2325 return MCDisassembler::Fail; 2326 if (Rm != 0xF) { 2327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2328 return MCDisassembler::Fail; 2329 } 2330 2331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2332 return MCDisassembler::Fail; 2333 Inst.addOperand(MCOperand::CreateImm(align)); 2334 2335 if (Rm == 0xD) 2336 Inst.addOperand(MCOperand::CreateReg(0)); 2337 else if (Rm != 0xF) { 2338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2339 return MCDisassembler::Fail; 2340 } 2341 2342 return S; 2343 } 2344 2345 static DecodeStatus 2346 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2347 uint64_t Address, const void *Decoder) { 2348 DecodeStatus S = MCDisassembler::Success; 2349 2350 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2351 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2352 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2353 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2354 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2355 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2356 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2357 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2358 2359 if (Q) { 2360 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2361 return MCDisassembler::Fail; 2362 } else { 2363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2364 return MCDisassembler::Fail; 2365 } 2366 2367 Inst.addOperand(MCOperand::CreateImm(imm)); 2368 2369 switch (Inst.getOpcode()) { 2370 case ARM::VORRiv4i16: 2371 case ARM::VORRiv2i32: 2372 case ARM::VBICiv4i16: 2373 case ARM::VBICiv2i32: 2374 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2375 return MCDisassembler::Fail; 2376 break; 2377 case ARM::VORRiv8i16: 2378 case ARM::VORRiv4i32: 2379 case ARM::VBICiv8i16: 2380 case ARM::VBICiv4i32: 2381 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2382 return MCDisassembler::Fail; 2383 break; 2384 default: 2385 break; 2386 } 2387 2388 return S; 2389 } 2390 2391 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2392 uint64_t Address, const void *Decoder) { 2393 DecodeStatus S = MCDisassembler::Success; 2394 2395 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2396 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2397 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2398 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2399 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2400 2401 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2404 return MCDisassembler::Fail; 2405 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2406 2407 return S; 2408 } 2409 2410 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2411 uint64_t Address, const void *Decoder) { 2412 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2413 return MCDisassembler::Success; 2414 } 2415 2416 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2417 uint64_t Address, const void *Decoder) { 2418 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2419 return MCDisassembler::Success; 2420 } 2421 2422 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2423 uint64_t Address, const void *Decoder) { 2424 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2425 return MCDisassembler::Success; 2426 } 2427 2428 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2429 uint64_t Address, const void *Decoder) { 2430 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2431 return MCDisassembler::Success; 2432 } 2433 2434 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2435 uint64_t Address, const void *Decoder) { 2436 DecodeStatus S = MCDisassembler::Success; 2437 2438 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2439 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2440 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2441 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2442 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2443 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2444 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2445 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2446 2447 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2448 return MCDisassembler::Fail; 2449 if (op) { 2450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2451 return MCDisassembler::Fail; // Writeback 2452 } 2453 2454 for (unsigned i = 0; i < length; ++i) { 2455 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2456 return MCDisassembler::Fail; 2457 } 2458 2459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 2462 return S; 2463 } 2464 2465 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2466 uint64_t Address, const void *Decoder) { 2467 // The immediate needs to be a fully instantiated float. However, the 2468 // auto-generated decoder is only able to fill in some of the bits 2469 // necessary. For instance, the 'b' bit is replicated multiple times, 2470 // and is even present in inverted form in one bit. We do a little 2471 // binary parsing here to fill in those missing bits, and then 2472 // reinterpret it all as a float. 2473 union { 2474 uint32_t integer; 2475 float fp; 2476 } fp_conv; 2477 2478 fp_conv.integer = Val; 2479 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2480 fp_conv.integer |= b << 26; 2481 fp_conv.integer |= b << 27; 2482 fp_conv.integer |= b << 28; 2483 fp_conv.integer |= b << 29; 2484 fp_conv.integer |= (~b & 0x1) << 30; 2485 2486 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2487 return MCDisassembler::Success; 2488 } 2489 2490 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2491 uint64_t Address, const void *Decoder) { 2492 DecodeStatus S = MCDisassembler::Success; 2493 2494 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2495 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2496 2497 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2498 return MCDisassembler::Fail; 2499 2500 switch(Inst.getOpcode()) { 2501 default: 2502 return MCDisassembler::Fail; 2503 case ARM::tADR: 2504 break; // tADR does not explicitly represent the PC as an operand. 2505 case ARM::tADDrSPi: 2506 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2507 break; 2508 } 2509 2510 Inst.addOperand(MCOperand::CreateImm(imm)); 2511 return S; 2512 } 2513 2514 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2515 uint64_t Address, const void *Decoder) { 2516 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2517 return MCDisassembler::Success; 2518 } 2519 2520 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2521 uint64_t Address, const void *Decoder) { 2522 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2523 return MCDisassembler::Success; 2524 } 2525 2526 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2527 uint64_t Address, const void *Decoder) { 2528 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2529 return MCDisassembler::Success; 2530 } 2531 2532 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2533 uint64_t Address, const void *Decoder) { 2534 DecodeStatus S = MCDisassembler::Success; 2535 2536 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2537 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2538 2539 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2540 return MCDisassembler::Fail; 2541 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2542 return MCDisassembler::Fail; 2543 2544 return S; 2545 } 2546 2547 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2548 uint64_t Address, const void *Decoder) { 2549 DecodeStatus S = MCDisassembler::Success; 2550 2551 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2552 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2553 2554 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2555 return MCDisassembler::Fail; 2556 Inst.addOperand(MCOperand::CreateImm(imm)); 2557 2558 return S; 2559 } 2560 2561 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2562 uint64_t Address, const void *Decoder) { 2563 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2564 2565 return MCDisassembler::Success; 2566 } 2567 2568 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2569 uint64_t Address, const void *Decoder) { 2570 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2571 Inst.addOperand(MCOperand::CreateImm(Val)); 2572 2573 return MCDisassembler::Success; 2574 } 2575 2576 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2577 uint64_t Address, const void *Decoder) { 2578 DecodeStatus S = MCDisassembler::Success; 2579 2580 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2581 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2582 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2583 2584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2585 return MCDisassembler::Fail; 2586 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2587 return MCDisassembler::Fail; 2588 Inst.addOperand(MCOperand::CreateImm(imm)); 2589 2590 return S; 2591 } 2592 2593 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2594 uint64_t Address, const void *Decoder) { 2595 DecodeStatus S = MCDisassembler::Success; 2596 2597 switch (Inst.getOpcode()) { 2598 case ARM::t2PLDs: 2599 case ARM::t2PLDWs: 2600 case ARM::t2PLIs: 2601 break; 2602 default: { 2603 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 } 2607 } 2608 2609 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2610 if (Rn == 0xF) { 2611 switch (Inst.getOpcode()) { 2612 case ARM::t2LDRBs: 2613 Inst.setOpcode(ARM::t2LDRBpci); 2614 break; 2615 case ARM::t2LDRHs: 2616 Inst.setOpcode(ARM::t2LDRHpci); 2617 break; 2618 case ARM::t2LDRSHs: 2619 Inst.setOpcode(ARM::t2LDRSHpci); 2620 break; 2621 case ARM::t2LDRSBs: 2622 Inst.setOpcode(ARM::t2LDRSBpci); 2623 break; 2624 case ARM::t2PLDs: 2625 Inst.setOpcode(ARM::t2PLDi12); 2626 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2627 break; 2628 default: 2629 return MCDisassembler::Fail; 2630 } 2631 2632 int imm = fieldFromInstruction32(Insn, 0, 12); 2633 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2634 Inst.addOperand(MCOperand::CreateImm(imm)); 2635 2636 return S; 2637 } 2638 2639 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2640 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2641 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2642 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2643 return MCDisassembler::Fail; 2644 2645 return S; 2646 } 2647 2648 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2649 uint64_t Address, const void *Decoder) { 2650 int imm = Val & 0xFF; 2651 if (!(Val & 0x100)) imm *= -1; 2652 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2653 2654 return MCDisassembler::Success; 2655 } 2656 2657 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2658 uint64_t Address, const void *Decoder) { 2659 DecodeStatus S = MCDisassembler::Success; 2660 2661 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2662 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2663 2664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2665 return MCDisassembler::Fail; 2666 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2667 return MCDisassembler::Fail; 2668 2669 return S; 2670 } 2671 2672 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2673 uint64_t Address, const void *Decoder) { 2674 int imm = Val & 0xFF; 2675 if (!(Val & 0x100)) imm *= -1; 2676 Inst.addOperand(MCOperand::CreateImm(imm)); 2677 2678 return MCDisassembler::Success; 2679 } 2680 2681 2682 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2683 uint64_t Address, const void *Decoder) { 2684 DecodeStatus S = MCDisassembler::Success; 2685 2686 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2687 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2688 2689 // Some instructions always use an additive offset. 2690 switch (Inst.getOpcode()) { 2691 case ARM::t2LDRT: 2692 case ARM::t2LDRBT: 2693 case ARM::t2LDRHT: 2694 case ARM::t2LDRSBT: 2695 case ARM::t2LDRSHT: 2696 imm |= 0x100; 2697 break; 2698 default: 2699 break; 2700 } 2701 2702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2703 return MCDisassembler::Fail; 2704 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 2707 return S; 2708 } 2709 2710 2711 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2712 uint64_t Address, const void *Decoder) { 2713 DecodeStatus S = MCDisassembler::Success; 2714 2715 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2716 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2717 2718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 Inst.addOperand(MCOperand::CreateImm(imm)); 2721 2722 return S; 2723 } 2724 2725 2726 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2727 uint64_t Address, const void *Decoder) { 2728 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2729 2730 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2731 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2732 Inst.addOperand(MCOperand::CreateImm(imm)); 2733 2734 return MCDisassembler::Success; 2735 } 2736 2737 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2738 uint64_t Address, const void *Decoder) { 2739 DecodeStatus S = MCDisassembler::Success; 2740 2741 if (Inst.getOpcode() == ARM::tADDrSP) { 2742 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2743 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2744 2745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2746 return MCDisassembler::Fail; 2747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2750 } else if (Inst.getOpcode() == ARM::tADDspr) { 2751 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2752 2753 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2754 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 } 2758 2759 return S; 2760 } 2761 2762 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2763 uint64_t Address, const void *Decoder) { 2764 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2765 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2766 2767 Inst.addOperand(MCOperand::CreateImm(imod)); 2768 Inst.addOperand(MCOperand::CreateImm(flags)); 2769 2770 return MCDisassembler::Success; 2771 } 2772 2773 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2774 uint64_t Address, const void *Decoder) { 2775 DecodeStatus S = MCDisassembler::Success; 2776 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2777 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2778 2779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 Inst.addOperand(MCOperand::CreateImm(add)); 2782 2783 return S; 2784 } 2785 2786 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2787 uint64_t Address, const void *Decoder) { 2788 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2789 return MCDisassembler::Success; 2790 } 2791 2792 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2793 uint64_t Address, const void *Decoder) { 2794 if (Val == 0xA || Val == 0xB) 2795 return MCDisassembler::Fail; 2796 2797 Inst.addOperand(MCOperand::CreateImm(Val)); 2798 return MCDisassembler::Success; 2799 } 2800 2801 static DecodeStatus 2802 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2803 uint64_t Address, const void *Decoder) { 2804 DecodeStatus S = MCDisassembler::Success; 2805 2806 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2807 if (pred == 0xE || pred == 0xF) { 2808 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2809 switch (opc) { 2810 default: 2811 return MCDisassembler::Fail; 2812 case 0xf3bf8f4: 2813 Inst.setOpcode(ARM::t2DSB); 2814 break; 2815 case 0xf3bf8f5: 2816 Inst.setOpcode(ARM::t2DMB); 2817 break; 2818 case 0xf3bf8f6: 2819 Inst.setOpcode(ARM::t2ISB); 2820 break; 2821 } 2822 2823 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2824 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2825 } 2826 2827 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2828 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2829 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2830 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2831 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2832 2833 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 2838 return S; 2839 } 2840 2841 // Decode a shifted immediate operand. These basically consist 2842 // of an 8-bit value, and a 4-bit directive that specifies either 2843 // a splat operation or a rotation. 2844 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2845 uint64_t Address, const void *Decoder) { 2846 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2847 if (ctrl == 0) { 2848 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2849 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2850 switch (byte) { 2851 case 0: 2852 Inst.addOperand(MCOperand::CreateImm(imm)); 2853 break; 2854 case 1: 2855 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2856 break; 2857 case 2: 2858 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2859 break; 2860 case 3: 2861 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2862 (imm << 8) | imm)); 2863 break; 2864 } 2865 } else { 2866 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2867 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2868 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2869 Inst.addOperand(MCOperand::CreateImm(imm)); 2870 } 2871 2872 return MCDisassembler::Success; 2873 } 2874 2875 static DecodeStatus 2876 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2877 uint64_t Address, const void *Decoder){ 2878 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2879 return MCDisassembler::Success; 2880 } 2881 2882 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2883 uint64_t Address, const void *Decoder){ 2884 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2885 return MCDisassembler::Success; 2886 } 2887 2888 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2889 uint64_t Address, const void *Decoder) { 2890 switch (Val) { 2891 default: 2892 return MCDisassembler::Fail; 2893 case 0xF: // SY 2894 case 0xE: // ST 2895 case 0xB: // ISH 2896 case 0xA: // ISHST 2897 case 0x7: // NSH 2898 case 0x6: // NSHST 2899 case 0x3: // OSH 2900 case 0x2: // OSHST 2901 break; 2902 } 2903 2904 Inst.addOperand(MCOperand::CreateImm(Val)); 2905 return MCDisassembler::Success; 2906 } 2907 2908 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2909 uint64_t Address, const void *Decoder) { 2910 if (!Val) return MCDisassembler::Fail; 2911 Inst.addOperand(MCOperand::CreateImm(Val)); 2912 return MCDisassembler::Success; 2913 } 2914 2915 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2916 uint64_t Address, const void *Decoder) { 2917 DecodeStatus S = MCDisassembler::Success; 2918 2919 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2920 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2921 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2922 2923 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2924 2925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 2934 return S; 2935 } 2936 2937 2938 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2939 uint64_t Address, const void *Decoder){ 2940 DecodeStatus S = MCDisassembler::Success; 2941 2942 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2943 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2944 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2945 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2946 2947 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 2950 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2951 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 2952 2953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2954 return MCDisassembler::Fail; 2955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2956 return MCDisassembler::Fail; 2957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2958 return MCDisassembler::Fail; 2959 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 2962 return S; 2963 } 2964 2965 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 2966 uint64_t Address, const void *Decoder) { 2967 DecodeStatus S = MCDisassembler::Success; 2968 2969 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2970 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2971 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2972 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2973 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2974 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2975 2976 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2977 2978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2979 return MCDisassembler::Fail; 2980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2985 return MCDisassembler::Fail; 2986 2987 return S; 2988 } 2989 2990 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 2991 uint64_t Address, const void *Decoder) { 2992 DecodeStatus S = MCDisassembler::Success; 2993 2994 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2995 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2996 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2997 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2998 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2999 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3001 3002 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3003 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3004 3005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 3014 return S; 3015 } 3016 3017 3018 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3019 uint64_t Address, const void *Decoder) { 3020 DecodeStatus S = MCDisassembler::Success; 3021 3022 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3023 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3024 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3025 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3026 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3027 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3028 3029 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3030 3031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3032 return MCDisassembler::Fail; 3033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3038 return MCDisassembler::Fail; 3039 3040 return S; 3041 } 3042 3043 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3044 uint64_t Address, const void *Decoder) { 3045 DecodeStatus S = MCDisassembler::Success; 3046 3047 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3048 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3049 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3050 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3051 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3052 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3053 3054 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3055 3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3057 return MCDisassembler::Fail; 3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3061 return MCDisassembler::Fail; 3062 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 3065 return S; 3066 } 3067 3068 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3069 uint64_t Address, const void *Decoder) { 3070 DecodeStatus S = MCDisassembler::Success; 3071 3072 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3073 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3074 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3075 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3076 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3077 3078 unsigned align = 0; 3079 unsigned index = 0; 3080 switch (size) { 3081 default: 3082 return MCDisassembler::Fail; 3083 case 0: 3084 if (fieldFromInstruction32(Insn, 4, 1)) 3085 return MCDisassembler::Fail; // UNDEFINED 3086 index = fieldFromInstruction32(Insn, 5, 3); 3087 break; 3088 case 1: 3089 if (fieldFromInstruction32(Insn, 5, 1)) 3090 return MCDisassembler::Fail; // UNDEFINED 3091 index = fieldFromInstruction32(Insn, 6, 2); 3092 if (fieldFromInstruction32(Insn, 4, 1)) 3093 align = 2; 3094 break; 3095 case 2: 3096 if (fieldFromInstruction32(Insn, 6, 1)) 3097 return MCDisassembler::Fail; // UNDEFINED 3098 index = fieldFromInstruction32(Insn, 7, 1); 3099 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3100 align = 4; 3101 } 3102 3103 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3104 return MCDisassembler::Fail; 3105 if (Rm != 0xF) { // Writeback 3106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3107 return MCDisassembler::Fail; 3108 } 3109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3110 return MCDisassembler::Fail; 3111 Inst.addOperand(MCOperand::CreateImm(align)); 3112 if (Rm != 0xF) { 3113 if (Rm != 0xD) { 3114 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3115 return MCDisassembler::Fail; 3116 } else 3117 Inst.addOperand(MCOperand::CreateReg(0)); 3118 } 3119 3120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3121 return MCDisassembler::Fail; 3122 Inst.addOperand(MCOperand::CreateImm(index)); 3123 3124 return S; 3125 } 3126 3127 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3128 uint64_t Address, const void *Decoder) { 3129 DecodeStatus S = MCDisassembler::Success; 3130 3131 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3132 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3133 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3134 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3135 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3136 3137 unsigned align = 0; 3138 unsigned index = 0; 3139 switch (size) { 3140 default: 3141 return MCDisassembler::Fail; 3142 case 0: 3143 if (fieldFromInstruction32(Insn, 4, 1)) 3144 return MCDisassembler::Fail; // UNDEFINED 3145 index = fieldFromInstruction32(Insn, 5, 3); 3146 break; 3147 case 1: 3148 if (fieldFromInstruction32(Insn, 5, 1)) 3149 return MCDisassembler::Fail; // UNDEFINED 3150 index = fieldFromInstruction32(Insn, 6, 2); 3151 if (fieldFromInstruction32(Insn, 4, 1)) 3152 align = 2; 3153 break; 3154 case 2: 3155 if (fieldFromInstruction32(Insn, 6, 1)) 3156 return MCDisassembler::Fail; // UNDEFINED 3157 index = fieldFromInstruction32(Insn, 7, 1); 3158 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3159 align = 4; 3160 } 3161 3162 if (Rm != 0xF) { // Writeback 3163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3164 return MCDisassembler::Fail; 3165 } 3166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3167 return MCDisassembler::Fail; 3168 Inst.addOperand(MCOperand::CreateImm(align)); 3169 if (Rm != 0xF) { 3170 if (Rm != 0xD) { 3171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3172 return MCDisassembler::Fail; 3173 } else 3174 Inst.addOperand(MCOperand::CreateReg(0)); 3175 } 3176 3177 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3178 return MCDisassembler::Fail; 3179 Inst.addOperand(MCOperand::CreateImm(index)); 3180 3181 return S; 3182 } 3183 3184 3185 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3186 uint64_t Address, const void *Decoder) { 3187 DecodeStatus S = MCDisassembler::Success; 3188 3189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3190 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3191 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3192 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3193 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3194 3195 unsigned align = 0; 3196 unsigned index = 0; 3197 unsigned inc = 1; 3198 switch (size) { 3199 default: 3200 return MCDisassembler::Fail; 3201 case 0: 3202 index = fieldFromInstruction32(Insn, 5, 3); 3203 if (fieldFromInstruction32(Insn, 4, 1)) 3204 align = 2; 3205 break; 3206 case 1: 3207 index = fieldFromInstruction32(Insn, 6, 2); 3208 if (fieldFromInstruction32(Insn, 4, 1)) 3209 align = 4; 3210 if (fieldFromInstruction32(Insn, 5, 1)) 3211 inc = 2; 3212 break; 3213 case 2: 3214 if (fieldFromInstruction32(Insn, 5, 1)) 3215 return MCDisassembler::Fail; // UNDEFINED 3216 index = fieldFromInstruction32(Insn, 7, 1); 3217 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3218 align = 8; 3219 if (fieldFromInstruction32(Insn, 6, 1)) 3220 inc = 2; 3221 break; 3222 } 3223 3224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3225 return MCDisassembler::Fail; 3226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 if (Rm != 0xF) { // Writeback 3229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 } 3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3233 return MCDisassembler::Fail; 3234 Inst.addOperand(MCOperand::CreateImm(align)); 3235 if (Rm != 0xF) { 3236 if (Rm != 0xD) { 3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3238 return MCDisassembler::Fail; 3239 } else 3240 Inst.addOperand(MCOperand::CreateReg(0)); 3241 } 3242 3243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 Inst.addOperand(MCOperand::CreateImm(index)); 3248 3249 return S; 3250 } 3251 3252 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3253 uint64_t Address, const void *Decoder) { 3254 DecodeStatus S = MCDisassembler::Success; 3255 3256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3257 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3258 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3259 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3260 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3261 3262 unsigned align = 0; 3263 unsigned index = 0; 3264 unsigned inc = 1; 3265 switch (size) { 3266 default: 3267 return MCDisassembler::Fail; 3268 case 0: 3269 index = fieldFromInstruction32(Insn, 5, 3); 3270 if (fieldFromInstruction32(Insn, 4, 1)) 3271 align = 2; 3272 break; 3273 case 1: 3274 index = fieldFromInstruction32(Insn, 6, 2); 3275 if (fieldFromInstruction32(Insn, 4, 1)) 3276 align = 4; 3277 if (fieldFromInstruction32(Insn, 5, 1)) 3278 inc = 2; 3279 break; 3280 case 2: 3281 if (fieldFromInstruction32(Insn, 5, 1)) 3282 return MCDisassembler::Fail; // UNDEFINED 3283 index = fieldFromInstruction32(Insn, 7, 1); 3284 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3285 align = 8; 3286 if (fieldFromInstruction32(Insn, 6, 1)) 3287 inc = 2; 3288 break; 3289 } 3290 3291 if (Rm != 0xF) { // Writeback 3292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3293 return MCDisassembler::Fail; 3294 } 3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3296 return MCDisassembler::Fail; 3297 Inst.addOperand(MCOperand::CreateImm(align)); 3298 if (Rm != 0xF) { 3299 if (Rm != 0xD) { 3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3301 return MCDisassembler::Fail; 3302 } else 3303 Inst.addOperand(MCOperand::CreateReg(0)); 3304 } 3305 3306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 Inst.addOperand(MCOperand::CreateImm(index)); 3311 3312 return S; 3313 } 3314 3315 3316 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3317 uint64_t Address, const void *Decoder) { 3318 DecodeStatus S = MCDisassembler::Success; 3319 3320 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3321 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3322 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3323 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3324 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3325 3326 unsigned align = 0; 3327 unsigned index = 0; 3328 unsigned inc = 1; 3329 switch (size) { 3330 default: 3331 return MCDisassembler::Fail; 3332 case 0: 3333 if (fieldFromInstruction32(Insn, 4, 1)) 3334 return MCDisassembler::Fail; // UNDEFINED 3335 index = fieldFromInstruction32(Insn, 5, 3); 3336 break; 3337 case 1: 3338 if (fieldFromInstruction32(Insn, 4, 1)) 3339 return MCDisassembler::Fail; // UNDEFINED 3340 index = fieldFromInstruction32(Insn, 6, 2); 3341 if (fieldFromInstruction32(Insn, 5, 1)) 3342 inc = 2; 3343 break; 3344 case 2: 3345 if (fieldFromInstruction32(Insn, 4, 2)) 3346 return MCDisassembler::Fail; // UNDEFINED 3347 index = fieldFromInstruction32(Insn, 7, 1); 3348 if (fieldFromInstruction32(Insn, 6, 1)) 3349 inc = 2; 3350 break; 3351 } 3352 3353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3354 return MCDisassembler::Fail; 3355 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 3360 if (Rm != 0xF) { // Writeback 3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 } 3364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3365 return MCDisassembler::Fail; 3366 Inst.addOperand(MCOperand::CreateImm(align)); 3367 if (Rm != 0xF) { 3368 if (Rm != 0xD) { 3369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 } else 3372 Inst.addOperand(MCOperand::CreateReg(0)); 3373 } 3374 3375 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3376 return MCDisassembler::Fail; 3377 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3378 return MCDisassembler::Fail; 3379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 Inst.addOperand(MCOperand::CreateImm(index)); 3382 3383 return S; 3384 } 3385 3386 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3387 uint64_t Address, const void *Decoder) { 3388 DecodeStatus S = MCDisassembler::Success; 3389 3390 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3391 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3392 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3393 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3394 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3395 3396 unsigned align = 0; 3397 unsigned index = 0; 3398 unsigned inc = 1; 3399 switch (size) { 3400 default: 3401 return MCDisassembler::Fail; 3402 case 0: 3403 if (fieldFromInstruction32(Insn, 4, 1)) 3404 return MCDisassembler::Fail; // UNDEFINED 3405 index = fieldFromInstruction32(Insn, 5, 3); 3406 break; 3407 case 1: 3408 if (fieldFromInstruction32(Insn, 4, 1)) 3409 return MCDisassembler::Fail; // UNDEFINED 3410 index = fieldFromInstruction32(Insn, 6, 2); 3411 if (fieldFromInstruction32(Insn, 5, 1)) 3412 inc = 2; 3413 break; 3414 case 2: 3415 if (fieldFromInstruction32(Insn, 4, 2)) 3416 return MCDisassembler::Fail; // UNDEFINED 3417 index = fieldFromInstruction32(Insn, 7, 1); 3418 if (fieldFromInstruction32(Insn, 6, 1)) 3419 inc = 2; 3420 break; 3421 } 3422 3423 if (Rm != 0xF) { // Writeback 3424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3425 return MCDisassembler::Fail; 3426 } 3427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3428 return MCDisassembler::Fail; 3429 Inst.addOperand(MCOperand::CreateImm(align)); 3430 if (Rm != 0xF) { 3431 if (Rm != 0xD) { 3432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3433 return MCDisassembler::Fail; 3434 } else 3435 Inst.addOperand(MCOperand::CreateReg(0)); 3436 } 3437 3438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3439 return MCDisassembler::Fail; 3440 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3441 return MCDisassembler::Fail; 3442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 Inst.addOperand(MCOperand::CreateImm(index)); 3445 3446 return S; 3447 } 3448 3449 3450 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3451 uint64_t Address, const void *Decoder) { 3452 DecodeStatus S = MCDisassembler::Success; 3453 3454 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3455 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3456 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3457 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3458 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3459 3460 unsigned align = 0; 3461 unsigned index = 0; 3462 unsigned inc = 1; 3463 switch (size) { 3464 default: 3465 return MCDisassembler::Fail; 3466 case 0: 3467 if (fieldFromInstruction32(Insn, 4, 1)) 3468 align = 4; 3469 index = fieldFromInstruction32(Insn, 5, 3); 3470 break; 3471 case 1: 3472 if (fieldFromInstruction32(Insn, 4, 1)) 3473 align = 8; 3474 index = fieldFromInstruction32(Insn, 6, 2); 3475 if (fieldFromInstruction32(Insn, 5, 1)) 3476 inc = 2; 3477 break; 3478 case 2: 3479 if (fieldFromInstruction32(Insn, 4, 2)) 3480 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3481 index = fieldFromInstruction32(Insn, 7, 1); 3482 if (fieldFromInstruction32(Insn, 6, 1)) 3483 inc = 2; 3484 break; 3485 } 3486 3487 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 3496 if (Rm != 0xF) { // Writeback 3497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3498 return MCDisassembler::Fail; 3499 } 3500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3501 return MCDisassembler::Fail; 3502 Inst.addOperand(MCOperand::CreateImm(align)); 3503 if (Rm != 0xF) { 3504 if (Rm != 0xD) { 3505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 } else 3508 Inst.addOperand(MCOperand::CreateReg(0)); 3509 } 3510 3511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3516 return MCDisassembler::Fail; 3517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 Inst.addOperand(MCOperand::CreateImm(index)); 3520 3521 return S; 3522 } 3523 3524 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3525 uint64_t Address, const void *Decoder) { 3526 DecodeStatus S = MCDisassembler::Success; 3527 3528 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3529 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3530 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3531 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3532 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3533 3534 unsigned align = 0; 3535 unsigned index = 0; 3536 unsigned inc = 1; 3537 switch (size) { 3538 default: 3539 return MCDisassembler::Fail; 3540 case 0: 3541 if (fieldFromInstruction32(Insn, 4, 1)) 3542 align = 4; 3543 index = fieldFromInstruction32(Insn, 5, 3); 3544 break; 3545 case 1: 3546 if (fieldFromInstruction32(Insn, 4, 1)) 3547 align = 8; 3548 index = fieldFromInstruction32(Insn, 6, 2); 3549 if (fieldFromInstruction32(Insn, 5, 1)) 3550 inc = 2; 3551 break; 3552 case 2: 3553 if (fieldFromInstruction32(Insn, 4, 2)) 3554 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3555 index = fieldFromInstruction32(Insn, 7, 1); 3556 if (fieldFromInstruction32(Insn, 6, 1)) 3557 inc = 2; 3558 break; 3559 } 3560 3561 if (Rm != 0xF) { // Writeback 3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 } 3565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 Inst.addOperand(MCOperand::CreateImm(align)); 3568 if (Rm != 0xF) { 3569 if (Rm != 0xD) { 3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 } else 3573 Inst.addOperand(MCOperand::CreateReg(0)); 3574 } 3575 3576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3581 return MCDisassembler::Fail; 3582 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 Inst.addOperand(MCOperand::CreateImm(index)); 3585 3586 return S; 3587 } 3588 3589 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3590 uint64_t Address, const void *Decoder) { 3591 DecodeStatus S = MCDisassembler::Success; 3592 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3593 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3594 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3595 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3596 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3597 3598 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3599 S = MCDisassembler::SoftFail; 3600 3601 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 3612 return S; 3613 } 3614 3615 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3616 uint64_t Address, const void *Decoder) { 3617 DecodeStatus S = MCDisassembler::Success; 3618 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3619 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3620 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3621 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3622 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3623 3624 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3625 S = MCDisassembler::SoftFail; 3626 3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3628 return MCDisassembler::Fail; 3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 3638 return S; 3639 } 3640 3641 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3642 uint64_t Address, const void *Decoder) { 3643 DecodeStatus S = MCDisassembler::Success; 3644 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3645 // The InstPrinter needs to have the low bit of the predicate in 3646 // the mask operand to be able to print it properly. 3647 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3648 3649 if (pred == 0xF) { 3650 pred = 0xE; 3651 S = MCDisassembler::SoftFail; 3652 } 3653 3654 if ((mask & 0xF) == 0) { 3655 // Preserve the high bit of the mask, which is the low bit of 3656 // the predicate. 3657 mask &= 0x10; 3658 mask |= 0x8; 3659 S = MCDisassembler::SoftFail; 3660 } 3661 3662 Inst.addOperand(MCOperand::CreateImm(pred)); 3663 Inst.addOperand(MCOperand::CreateImm(mask)); 3664 return S; 3665 } 3666 3667 static DecodeStatus 3668 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3669 uint64_t Address, const void *Decoder) { 3670 DecodeStatus S = MCDisassembler::Success; 3671 3672 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3673 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3674 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3675 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3676 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3677 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3678 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3679 bool writeback = (W == 1) | (P == 0); 3680 3681 addr |= (U << 8) | (Rn << 9); 3682 3683 if (writeback && (Rn == Rt || Rn == Rt2)) 3684 Check(S, MCDisassembler::SoftFail); 3685 if (Rt == Rt2) 3686 Check(S, MCDisassembler::SoftFail); 3687 3688 // Rt 3689 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 // Rt2 3692 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 // Writeback operand 3695 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 // addr 3698 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 3701 return S; 3702 } 3703 3704 static DecodeStatus 3705 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3706 uint64_t Address, const void *Decoder) { 3707 DecodeStatus S = MCDisassembler::Success; 3708 3709 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3710 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3711 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3712 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3713 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3714 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3715 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3716 bool writeback = (W == 1) | (P == 0); 3717 3718 addr |= (U << 8) | (Rn << 9); 3719 3720 if (writeback && (Rn == Rt || Rn == Rt2)) 3721 Check(S, MCDisassembler::SoftFail); 3722 3723 // Writeback operand 3724 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3725 return MCDisassembler::Fail; 3726 // Rt 3727 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 // Rt2 3730 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 // addr 3733 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3734 return MCDisassembler::Fail; 3735 3736 return S; 3737 } 3738