1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream) const; 51 52 /// getEDInfo - See MCDisassembler. 53 EDInstInfo *getEDInfo() const; 54 private: 55 }; 56 57 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 58 class ThumbDisassembler : public MCDisassembler { 59 public: 60 /// Constructor - Initializes the disassembler. 61 /// 62 ThumbDisassembler(const MCSubtargetInfo &STI) : 63 MCDisassembler(STI) { 64 } 65 66 ~ThumbDisassembler() { 67 } 68 69 /// getInstruction - See MCDisassembler. 70 DecodeStatus getInstruction(MCInst &instr, 71 uint64_t &size, 72 const MemoryObject ®ion, 73 uint64_t address, 74 raw_ostream &vStream) const; 75 76 /// getEDInfo - See MCDisassembler. 77 EDInstInfo *getEDInfo() const; 78 private: 79 mutable std::vector<unsigned> ITBlock; 80 DecodeStatus AddThumbPredicate(MCInst&) const; 81 void UpdateThumbVFPPredicate(MCInst&) const; 82 }; 83 } 84 85 static bool Check(DecodeStatus &Out, DecodeStatus In) { 86 switch (In) { 87 case MCDisassembler::Success: 88 // Out stays the same. 89 return true; 90 case MCDisassembler::SoftFail: 91 Out = In; 92 return true; 93 case MCDisassembler::Fail: 94 Out = In; 95 return false; 96 } 97 return false; 98 } 99 100 101 // Forward declare these because the autogenerated code will reference them. 102 // Definitions are further down. 103 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 125 uint64_t Address, const void *Decoder); 126 127 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 140 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 157 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 158 unsigned Insn, 159 uint64_t Adddress, 160 const void *Decoder); 161 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 248 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 307 308 #include "ARMGenDisassemblerTables.inc" 309 #include "ARMGenInstrInfo.inc" 310 #include "ARMGenEDInfo.inc" 311 312 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 313 return new ARMDisassembler(STI); 314 } 315 316 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 317 return new ThumbDisassembler(STI); 318 } 319 320 EDInstInfo *ARMDisassembler::getEDInfo() const { 321 return instInfoARM; 322 } 323 324 EDInstInfo *ThumbDisassembler::getEDInfo() const { 325 return instInfoARM; 326 } 327 328 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 329 const MemoryObject &Region, 330 uint64_t Address, 331 raw_ostream &os) const { 332 uint8_t bytes[4]; 333 334 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 335 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 336 337 // We want to read exactly 4 bytes of data. 338 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 339 Size = 0; 340 return MCDisassembler::Fail; 341 } 342 343 // Encoded as a small-endian 32-bit word in the stream. 344 uint32_t insn = (bytes[3] << 24) | 345 (bytes[2] << 16) | 346 (bytes[1] << 8) | 347 (bytes[0] << 0); 348 349 // Calling the auto-generated decoder function. 350 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 351 if (result != MCDisassembler::Fail) { 352 Size = 4; 353 return result; 354 } 355 356 // VFP and NEON instructions, similarly, are shared between ARM 357 // and Thumb modes. 358 MI.clear(); 359 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 360 if (result != MCDisassembler::Fail) { 361 Size = 4; 362 return result; 363 } 364 365 MI.clear(); 366 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 367 if (result != MCDisassembler::Fail) { 368 Size = 4; 369 // Add a fake predicate operand, because we share these instruction 370 // definitions with Thumb2 where these instructions are predicable. 371 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 372 return MCDisassembler::Fail; 373 return result; 374 } 375 376 MI.clear(); 377 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 378 if (result != MCDisassembler::Fail) { 379 Size = 4; 380 // Add a fake predicate operand, because we share these instruction 381 // definitions with Thumb2 where these instructions are predicable. 382 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 383 return MCDisassembler::Fail; 384 return result; 385 } 386 387 MI.clear(); 388 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 389 if (result != MCDisassembler::Fail) { 390 Size = 4; 391 // Add a fake predicate operand, because we share these instruction 392 // definitions with Thumb2 where these instructions are predicable. 393 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 394 return MCDisassembler::Fail; 395 return result; 396 } 397 398 MI.clear(); 399 400 Size = 0; 401 return MCDisassembler::Fail; 402 } 403 404 namespace llvm { 405 extern MCInstrDesc ARMInsts[]; 406 } 407 408 // Thumb1 instructions don't have explicit S bits. Rather, they 409 // implicitly set CPSR. Since it's not represented in the encoding, the 410 // auto-generated decoder won't inject the CPSR operand. We need to fix 411 // that as a post-pass. 412 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 413 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 414 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 415 MCInst::iterator I = MI.begin(); 416 for (unsigned i = 0; i < NumOps; ++i, ++I) { 417 if (I == MI.end()) break; 418 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 419 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 420 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 421 return; 422 } 423 } 424 425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 426 } 427 428 // Most Thumb instructions don't have explicit predicates in the 429 // encoding, but rather get their predicates from IT context. We need 430 // to fix up the predicate operands using this context information as a 431 // post-pass. 432 MCDisassembler::DecodeStatus 433 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 434 MCDisassembler::DecodeStatus S = Success; 435 436 // A few instructions actually have predicates encoded in them. Don't 437 // try to overwrite it if we're seeing one of those. 438 switch (MI.getOpcode()) { 439 case ARM::tBcc: 440 case ARM::t2Bcc: 441 case ARM::tCBZ: 442 case ARM::tCBNZ: 443 // Some instructions (mostly conditional branches) are not 444 // allowed in IT blocks. 445 if (!ITBlock.empty()) 446 S = SoftFail; 447 else 448 return Success; 449 break; 450 case ARM::tB: 451 case ARM::t2B: 452 // Some instructions (mostly unconditional branches) can 453 // only appears at the end of, or outside of, an IT. 454 if (ITBlock.size() > 1) 455 S = SoftFail; 456 break; 457 default: 458 break; 459 } 460 461 // If we're in an IT block, base the predicate on that. Otherwise, 462 // assume a predicate of AL. 463 unsigned CC; 464 if (!ITBlock.empty()) { 465 CC = ITBlock.back(); 466 if (CC == 0xF) 467 CC = ARMCC::AL; 468 ITBlock.pop_back(); 469 } else 470 CC = ARMCC::AL; 471 472 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 473 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 474 MCInst::iterator I = MI.begin(); 475 for (unsigned i = 0; i < NumOps; ++i, ++I) { 476 if (I == MI.end()) break; 477 if (OpInfo[i].isPredicate()) { 478 I = MI.insert(I, MCOperand::CreateImm(CC)); 479 ++I; 480 if (CC == ARMCC::AL) 481 MI.insert(I, MCOperand::CreateReg(0)); 482 else 483 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 484 return S; 485 } 486 } 487 488 I = MI.insert(I, MCOperand::CreateImm(CC)); 489 ++I; 490 if (CC == ARMCC::AL) 491 MI.insert(I, MCOperand::CreateReg(0)); 492 else 493 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 494 495 return S; 496 } 497 498 // Thumb VFP instructions are a special case. Because we share their 499 // encodings between ARM and Thumb modes, and they are predicable in ARM 500 // mode, the auto-generated decoder will give them an (incorrect) 501 // predicate operand. We need to rewrite these operands based on the IT 502 // context as a post-pass. 503 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 504 unsigned CC; 505 if (!ITBlock.empty()) { 506 CC = ITBlock.back(); 507 ITBlock.pop_back(); 508 } else 509 CC = ARMCC::AL; 510 511 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 512 MCInst::iterator I = MI.begin(); 513 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 514 for (unsigned i = 0; i < NumOps; ++i, ++I) { 515 if (OpInfo[i].isPredicate() ) { 516 I->setImm(CC); 517 ++I; 518 if (CC == ARMCC::AL) 519 I->setReg(0); 520 else 521 I->setReg(ARM::CPSR); 522 return; 523 } 524 } 525 } 526 527 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 528 const MemoryObject &Region, 529 uint64_t Address, 530 raw_ostream &os) const { 531 uint8_t bytes[4]; 532 533 assert((STI.getFeatureBits() & ARM::ModeThumb) && 534 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 535 536 // We want to read exactly 2 bytes of data. 537 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 538 Size = 0; 539 return MCDisassembler::Fail; 540 } 541 542 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 543 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 544 if (result != MCDisassembler::Fail) { 545 Size = 2; 546 Check(result, AddThumbPredicate(MI)); 547 return result; 548 } 549 550 MI.clear(); 551 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 552 if (result) { 553 Size = 2; 554 bool InITBlock = !ITBlock.empty(); 555 Check(result, AddThumbPredicate(MI)); 556 AddThumb1SBit(MI, InITBlock); 557 return result; 558 } 559 560 MI.clear(); 561 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 562 if (result != MCDisassembler::Fail) { 563 Size = 2; 564 Check(result, AddThumbPredicate(MI)); 565 566 // If we find an IT instruction, we need to parse its condition 567 // code and mask operands so that we can apply them correctly 568 // to the subsequent instructions. 569 if (MI.getOpcode() == ARM::t2IT) { 570 // (3 - the number of trailing zeros) is the number of then / else. 571 unsigned firstcond = MI.getOperand(0).getImm(); 572 unsigned Mask = MI.getOperand(1).getImm(); 573 unsigned CondBit0 = Mask >> 4 & 1; 574 unsigned NumTZ = CountTrailingZeros_32(Mask); 575 assert(NumTZ <= 3 && "Invalid IT mask!"); 576 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 577 bool T = ((Mask >> Pos) & 1) == CondBit0; 578 if (T) 579 ITBlock.insert(ITBlock.begin(), firstcond); 580 else 581 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 582 } 583 584 ITBlock.push_back(firstcond); 585 } 586 587 return result; 588 } 589 590 // We want to read exactly 4 bytes of data. 591 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 592 Size = 0; 593 return MCDisassembler::Fail; 594 } 595 596 uint32_t insn32 = (bytes[3] << 8) | 597 (bytes[2] << 0) | 598 (bytes[1] << 24) | 599 (bytes[0] << 16); 600 MI.clear(); 601 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 602 if (result != MCDisassembler::Fail) { 603 Size = 4; 604 bool InITBlock = ITBlock.size(); 605 Check(result, AddThumbPredicate(MI)); 606 AddThumb1SBit(MI, InITBlock); 607 return result; 608 } 609 610 MI.clear(); 611 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 612 if (result != MCDisassembler::Fail) { 613 Size = 4; 614 Check(result, AddThumbPredicate(MI)); 615 return result; 616 } 617 618 MI.clear(); 619 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 620 if (result != MCDisassembler::Fail) { 621 Size = 4; 622 UpdateThumbVFPPredicate(MI); 623 return result; 624 } 625 626 MI.clear(); 627 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 628 if (result != MCDisassembler::Fail) { 629 Size = 4; 630 Check(result, AddThumbPredicate(MI)); 631 return result; 632 } 633 634 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 635 MI.clear(); 636 uint32_t NEONLdStInsn = insn32; 637 NEONLdStInsn &= 0xF0FFFFFF; 638 NEONLdStInsn |= 0x04000000; 639 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 640 if (result != MCDisassembler::Fail) { 641 Size = 4; 642 Check(result, AddThumbPredicate(MI)); 643 return result; 644 } 645 } 646 647 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 648 MI.clear(); 649 uint32_t NEONDataInsn = insn32; 650 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 651 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 652 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 653 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 654 if (result != MCDisassembler::Fail) { 655 Size = 4; 656 Check(result, AddThumbPredicate(MI)); 657 return result; 658 } 659 } 660 661 Size = 0; 662 return MCDisassembler::Fail; 663 } 664 665 666 extern "C" void LLVMInitializeARMDisassembler() { 667 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 668 createARMDisassembler); 669 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 670 createThumbDisassembler); 671 } 672 673 static const unsigned GPRDecoderTable[] = { 674 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 675 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 676 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 677 ARM::R12, ARM::SP, ARM::LR, ARM::PC 678 }; 679 680 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 681 uint64_t Address, const void *Decoder) { 682 if (RegNo > 15) 683 return MCDisassembler::Fail; 684 685 unsigned Register = GPRDecoderTable[RegNo]; 686 Inst.addOperand(MCOperand::CreateReg(Register)); 687 return MCDisassembler::Success; 688 } 689 690 static DecodeStatus 691 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 692 uint64_t Address, const void *Decoder) { 693 if (RegNo == 15) return MCDisassembler::Fail; 694 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 695 } 696 697 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 698 uint64_t Address, const void *Decoder) { 699 if (RegNo > 7) 700 return MCDisassembler::Fail; 701 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 702 } 703 704 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 705 uint64_t Address, const void *Decoder) { 706 unsigned Register = 0; 707 switch (RegNo) { 708 case 0: 709 Register = ARM::R0; 710 break; 711 case 1: 712 Register = ARM::R1; 713 break; 714 case 2: 715 Register = ARM::R2; 716 break; 717 case 3: 718 Register = ARM::R3; 719 break; 720 case 9: 721 Register = ARM::R9; 722 break; 723 case 12: 724 Register = ARM::R12; 725 break; 726 default: 727 return MCDisassembler::Fail; 728 } 729 730 Inst.addOperand(MCOperand::CreateReg(Register)); 731 return MCDisassembler::Success; 732 } 733 734 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 735 uint64_t Address, const void *Decoder) { 736 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 737 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 738 } 739 740 static const unsigned SPRDecoderTable[] = { 741 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 742 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 743 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 744 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 745 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 746 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 747 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 748 ARM::S28, ARM::S29, ARM::S30, ARM::S31 749 }; 750 751 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 752 uint64_t Address, const void *Decoder) { 753 if (RegNo > 31) 754 return MCDisassembler::Fail; 755 756 unsigned Register = SPRDecoderTable[RegNo]; 757 Inst.addOperand(MCOperand::CreateReg(Register)); 758 return MCDisassembler::Success; 759 } 760 761 static const unsigned DPRDecoderTable[] = { 762 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 763 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 764 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 765 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 766 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 767 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 768 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 769 ARM::D28, ARM::D29, ARM::D30, ARM::D31 770 }; 771 772 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 773 uint64_t Address, const void *Decoder) { 774 if (RegNo > 31) 775 return MCDisassembler::Fail; 776 777 unsigned Register = DPRDecoderTable[RegNo]; 778 Inst.addOperand(MCOperand::CreateReg(Register)); 779 return MCDisassembler::Success; 780 } 781 782 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 783 uint64_t Address, const void *Decoder) { 784 if (RegNo > 7) 785 return MCDisassembler::Fail; 786 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 787 } 788 789 static DecodeStatus 790 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 791 uint64_t Address, const void *Decoder) { 792 if (RegNo > 15) 793 return MCDisassembler::Fail; 794 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 795 } 796 797 static const unsigned QPRDecoderTable[] = { 798 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 799 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 800 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 801 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 802 }; 803 804 805 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 806 uint64_t Address, const void *Decoder) { 807 if (RegNo > 31) 808 return MCDisassembler::Fail; 809 RegNo >>= 1; 810 811 unsigned Register = QPRDecoderTable[RegNo]; 812 Inst.addOperand(MCOperand::CreateReg(Register)); 813 return MCDisassembler::Success; 814 } 815 816 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 817 uint64_t Address, const void *Decoder) { 818 if (Val == 0xF) return MCDisassembler::Fail; 819 // AL predicate is not allowed on Thumb1 branches. 820 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 821 return MCDisassembler::Fail; 822 Inst.addOperand(MCOperand::CreateImm(Val)); 823 if (Val == ARMCC::AL) { 824 Inst.addOperand(MCOperand::CreateReg(0)); 825 } else 826 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 827 return MCDisassembler::Success; 828 } 829 830 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 831 uint64_t Address, const void *Decoder) { 832 if (Val) 833 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 834 else 835 Inst.addOperand(MCOperand::CreateReg(0)); 836 return MCDisassembler::Success; 837 } 838 839 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 840 uint64_t Address, const void *Decoder) { 841 uint32_t imm = Val & 0xFF; 842 uint32_t rot = (Val & 0xF00) >> 7; 843 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 844 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 845 return MCDisassembler::Success; 846 } 847 848 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 849 uint64_t Address, const void *Decoder) { 850 DecodeStatus S = MCDisassembler::Success; 851 852 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 853 unsigned type = fieldFromInstruction32(Val, 5, 2); 854 unsigned imm = fieldFromInstruction32(Val, 7, 5); 855 856 // Register-immediate 857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 858 return MCDisassembler::Fail; 859 860 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 861 switch (type) { 862 case 0: 863 Shift = ARM_AM::lsl; 864 break; 865 case 1: 866 Shift = ARM_AM::lsr; 867 break; 868 case 2: 869 Shift = ARM_AM::asr; 870 break; 871 case 3: 872 Shift = ARM_AM::ror; 873 break; 874 } 875 876 if (Shift == ARM_AM::ror && imm == 0) 877 Shift = ARM_AM::rrx; 878 879 unsigned Op = Shift | (imm << 3); 880 Inst.addOperand(MCOperand::CreateImm(Op)); 881 882 return S; 883 } 884 885 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 886 uint64_t Address, const void *Decoder) { 887 DecodeStatus S = MCDisassembler::Success; 888 889 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 890 unsigned type = fieldFromInstruction32(Val, 5, 2); 891 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 892 893 // Register-register 894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 895 return MCDisassembler::Fail; 896 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 897 return MCDisassembler::Fail; 898 899 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 900 switch (type) { 901 case 0: 902 Shift = ARM_AM::lsl; 903 break; 904 case 1: 905 Shift = ARM_AM::lsr; 906 break; 907 case 2: 908 Shift = ARM_AM::asr; 909 break; 910 case 3: 911 Shift = ARM_AM::ror; 912 break; 913 } 914 915 Inst.addOperand(MCOperand::CreateImm(Shift)); 916 917 return S; 918 } 919 920 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 921 uint64_t Address, const void *Decoder) { 922 DecodeStatus S = MCDisassembler::Success; 923 924 bool writebackLoad = false; 925 unsigned writebackReg = 0; 926 switch (Inst.getOpcode()) { 927 default: 928 break; 929 case ARM::LDMIA_UPD: 930 case ARM::LDMDB_UPD: 931 case ARM::LDMIB_UPD: 932 case ARM::LDMDA_UPD: 933 case ARM::t2LDMIA_UPD: 934 case ARM::t2LDMDB_UPD: 935 writebackLoad = true; 936 writebackReg = Inst.getOperand(0).getReg(); 937 break; 938 } 939 940 // Empty register lists are not allowed. 941 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 942 for (unsigned i = 0; i < 16; ++i) { 943 if (Val & (1 << i)) { 944 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 945 return MCDisassembler::Fail; 946 // Writeback not allowed if Rn is in the target list. 947 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 948 Check(S, MCDisassembler::SoftFail); 949 } 950 } 951 952 return S; 953 } 954 955 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 956 uint64_t Address, const void *Decoder) { 957 DecodeStatus S = MCDisassembler::Success; 958 959 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 960 unsigned regs = Val & 0xFF; 961 962 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 963 return MCDisassembler::Fail; 964 for (unsigned i = 0; i < (regs - 1); ++i) { 965 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 966 return MCDisassembler::Fail; 967 } 968 969 return S; 970 } 971 972 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 973 uint64_t Address, const void *Decoder) { 974 DecodeStatus S = MCDisassembler::Success; 975 976 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 977 unsigned regs = (Val & 0xFF) / 2; 978 979 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 980 return MCDisassembler::Fail; 981 for (unsigned i = 0; i < (regs - 1); ++i) { 982 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 983 return MCDisassembler::Fail; 984 } 985 986 return S; 987 } 988 989 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 990 uint64_t Address, const void *Decoder) { 991 // This operand encodes a mask of contiguous zeros between a specified MSB 992 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 993 // the mask of all bits LSB-and-lower, and then xor them to create 994 // the mask of that's all ones on [msb, lsb]. Finally we not it to 995 // create the final mask. 996 unsigned msb = fieldFromInstruction32(Val, 5, 5); 997 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 998 uint32_t msb_mask = (1 << (msb+1)) - 1; 999 uint32_t lsb_mask = (1 << lsb) - 1; 1000 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1001 return MCDisassembler::Success; 1002 } 1003 1004 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1005 uint64_t Address, const void *Decoder) { 1006 DecodeStatus S = MCDisassembler::Success; 1007 1008 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1009 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1010 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1011 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1012 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1013 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1014 1015 switch (Inst.getOpcode()) { 1016 case ARM::LDC_OFFSET: 1017 case ARM::LDC_PRE: 1018 case ARM::LDC_POST: 1019 case ARM::LDC_OPTION: 1020 case ARM::LDCL_OFFSET: 1021 case ARM::LDCL_PRE: 1022 case ARM::LDCL_POST: 1023 case ARM::LDCL_OPTION: 1024 case ARM::STC_OFFSET: 1025 case ARM::STC_PRE: 1026 case ARM::STC_POST: 1027 case ARM::STC_OPTION: 1028 case ARM::STCL_OFFSET: 1029 case ARM::STCL_PRE: 1030 case ARM::STCL_POST: 1031 case ARM::STCL_OPTION: 1032 case ARM::t2LDC_OFFSET: 1033 case ARM::t2LDC_PRE: 1034 case ARM::t2LDC_POST: 1035 case ARM::t2LDC_OPTION: 1036 case ARM::t2LDCL_OFFSET: 1037 case ARM::t2LDCL_PRE: 1038 case ARM::t2LDCL_POST: 1039 case ARM::t2LDCL_OPTION: 1040 case ARM::t2STC_OFFSET: 1041 case ARM::t2STC_PRE: 1042 case ARM::t2STC_POST: 1043 case ARM::t2STC_OPTION: 1044 case ARM::t2STCL_OFFSET: 1045 case ARM::t2STCL_PRE: 1046 case ARM::t2STCL_POST: 1047 case ARM::t2STCL_OPTION: 1048 if (coproc == 0xA || coproc == 0xB) 1049 return MCDisassembler::Fail; 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 Inst.addOperand(MCOperand::CreateImm(coproc)); 1056 Inst.addOperand(MCOperand::CreateImm(CRd)); 1057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1058 return MCDisassembler::Fail; 1059 switch (Inst.getOpcode()) { 1060 case ARM::LDC_OPTION: 1061 case ARM::LDCL_OPTION: 1062 case ARM::LDC2_OPTION: 1063 case ARM::LDC2L_OPTION: 1064 case ARM::STC_OPTION: 1065 case ARM::STCL_OPTION: 1066 case ARM::STC2_OPTION: 1067 case ARM::STC2L_OPTION: 1068 case ARM::LDCL_POST: 1069 case ARM::STCL_POST: 1070 case ARM::LDC2L_POST: 1071 case ARM::STC2L_POST: 1072 case ARM::t2LDC_OPTION: 1073 case ARM::t2LDCL_OPTION: 1074 case ARM::t2STC_OPTION: 1075 case ARM::t2STCL_OPTION: 1076 case ARM::t2LDCL_POST: 1077 case ARM::t2STCL_POST: 1078 break; 1079 default: 1080 Inst.addOperand(MCOperand::CreateReg(0)); 1081 break; 1082 } 1083 1084 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1085 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1086 1087 bool writeback = (P == 0) || (W == 1); 1088 unsigned idx_mode = 0; 1089 if (P && writeback) 1090 idx_mode = ARMII::IndexModePre; 1091 else if (!P && writeback) 1092 idx_mode = ARMII::IndexModePost; 1093 1094 switch (Inst.getOpcode()) { 1095 case ARM::LDCL_POST: 1096 case ARM::STCL_POST: 1097 case ARM::t2LDCL_POST: 1098 case ARM::t2STCL_POST: 1099 case ARM::LDC2L_POST: 1100 case ARM::STC2L_POST: 1101 imm |= U << 8; 1102 case ARM::LDC_OPTION: 1103 case ARM::LDCL_OPTION: 1104 case ARM::LDC2_OPTION: 1105 case ARM::LDC2L_OPTION: 1106 case ARM::STC_OPTION: 1107 case ARM::STCL_OPTION: 1108 case ARM::STC2_OPTION: 1109 case ARM::STC2L_OPTION: 1110 case ARM::t2LDC_OPTION: 1111 case ARM::t2LDCL_OPTION: 1112 case ARM::t2STC_OPTION: 1113 case ARM::t2STCL_OPTION: 1114 Inst.addOperand(MCOperand::CreateImm(imm)); 1115 break; 1116 default: 1117 if (U) 1118 Inst.addOperand(MCOperand::CreateImm( 1119 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1120 else 1121 Inst.addOperand(MCOperand::CreateImm( 1122 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1123 break; 1124 } 1125 1126 switch (Inst.getOpcode()) { 1127 case ARM::LDC_OFFSET: 1128 case ARM::LDC_PRE: 1129 case ARM::LDC_POST: 1130 case ARM::LDC_OPTION: 1131 case ARM::LDCL_OFFSET: 1132 case ARM::LDCL_PRE: 1133 case ARM::LDCL_POST: 1134 case ARM::LDCL_OPTION: 1135 case ARM::STC_OFFSET: 1136 case ARM::STC_PRE: 1137 case ARM::STC_POST: 1138 case ARM::STC_OPTION: 1139 case ARM::STCL_OFFSET: 1140 case ARM::STCL_PRE: 1141 case ARM::STCL_POST: 1142 case ARM::STCL_OPTION: 1143 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1144 return MCDisassembler::Fail; 1145 break; 1146 default: 1147 break; 1148 } 1149 1150 return S; 1151 } 1152 1153 static DecodeStatus 1154 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1155 uint64_t Address, const void *Decoder) { 1156 DecodeStatus S = MCDisassembler::Success; 1157 1158 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1159 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1160 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1161 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1162 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1163 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1164 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1165 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1166 1167 // On stores, the writeback operand precedes Rt. 1168 switch (Inst.getOpcode()) { 1169 case ARM::STR_POST_IMM: 1170 case ARM::STR_POST_REG: 1171 case ARM::STRB_POST_IMM: 1172 case ARM::STRB_POST_REG: 1173 case ARM::STRT_POST_REG: 1174 case ARM::STRT_POST_IMM: 1175 case ARM::STRBT_POST_REG: 1176 case ARM::STRBT_POST_IMM: 1177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1178 return MCDisassembler::Fail; 1179 break; 1180 default: 1181 break; 1182 } 1183 1184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1185 return MCDisassembler::Fail; 1186 1187 // On loads, the writeback operand comes after Rt. 1188 switch (Inst.getOpcode()) { 1189 case ARM::LDR_POST_IMM: 1190 case ARM::LDR_POST_REG: 1191 case ARM::LDRB_POST_IMM: 1192 case ARM::LDRB_POST_REG: 1193 case ARM::LDRBT_POST_REG: 1194 case ARM::LDRBT_POST_IMM: 1195 case ARM::LDRT_POST_REG: 1196 case ARM::LDRT_POST_IMM: 1197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1198 return MCDisassembler::Fail; 1199 break; 1200 default: 1201 break; 1202 } 1203 1204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1205 return MCDisassembler::Fail; 1206 1207 ARM_AM::AddrOpc Op = ARM_AM::add; 1208 if (!fieldFromInstruction32(Insn, 23, 1)) 1209 Op = ARM_AM::sub; 1210 1211 bool writeback = (P == 0) || (W == 1); 1212 unsigned idx_mode = 0; 1213 if (P && writeback) 1214 idx_mode = ARMII::IndexModePre; 1215 else if (!P && writeback) 1216 idx_mode = ARMII::IndexModePost; 1217 1218 if (writeback && (Rn == 15 || Rn == Rt)) 1219 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1220 1221 if (reg) { 1222 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1223 return MCDisassembler::Fail; 1224 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1225 switch( fieldFromInstruction32(Insn, 5, 2)) { 1226 case 0: 1227 Opc = ARM_AM::lsl; 1228 break; 1229 case 1: 1230 Opc = ARM_AM::lsr; 1231 break; 1232 case 2: 1233 Opc = ARM_AM::asr; 1234 break; 1235 case 3: 1236 Opc = ARM_AM::ror; 1237 break; 1238 default: 1239 return MCDisassembler::Fail; 1240 } 1241 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1242 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1243 1244 Inst.addOperand(MCOperand::CreateImm(imm)); 1245 } else { 1246 Inst.addOperand(MCOperand::CreateReg(0)); 1247 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1248 Inst.addOperand(MCOperand::CreateImm(tmp)); 1249 } 1250 1251 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1252 return MCDisassembler::Fail; 1253 1254 return S; 1255 } 1256 1257 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1258 uint64_t Address, const void *Decoder) { 1259 DecodeStatus S = MCDisassembler::Success; 1260 1261 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1262 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1263 unsigned type = fieldFromInstruction32(Val, 5, 2); 1264 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1265 unsigned U = fieldFromInstruction32(Val, 12, 1); 1266 1267 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1268 switch (type) { 1269 case 0: 1270 ShOp = ARM_AM::lsl; 1271 break; 1272 case 1: 1273 ShOp = ARM_AM::lsr; 1274 break; 1275 case 2: 1276 ShOp = ARM_AM::asr; 1277 break; 1278 case 3: 1279 ShOp = ARM_AM::ror; 1280 break; 1281 } 1282 1283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1284 return MCDisassembler::Fail; 1285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1286 return MCDisassembler::Fail; 1287 unsigned shift; 1288 if (U) 1289 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1290 else 1291 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1292 Inst.addOperand(MCOperand::CreateImm(shift)); 1293 1294 return S; 1295 } 1296 1297 static DecodeStatus 1298 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1299 uint64_t Address, const void *Decoder) { 1300 DecodeStatus S = MCDisassembler::Success; 1301 1302 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1303 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1304 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1305 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1306 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1307 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1308 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1309 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1310 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1311 1312 bool writeback = (W == 1) | (P == 0); 1313 1314 // For {LD,ST}RD, Rt must be even, else undefined. 1315 switch (Inst.getOpcode()) { 1316 case ARM::STRD: 1317 case ARM::STRD_PRE: 1318 case ARM::STRD_POST: 1319 case ARM::LDRD: 1320 case ARM::LDRD_PRE: 1321 case ARM::LDRD_POST: 1322 if (Rt & 0x1) return MCDisassembler::Fail; 1323 break; 1324 default: 1325 break; 1326 } 1327 1328 if (writeback) { // Writeback 1329 if (P) 1330 U |= ARMII::IndexModePre << 9; 1331 else 1332 U |= ARMII::IndexModePost << 9; 1333 1334 // On stores, the writeback operand precedes Rt. 1335 switch (Inst.getOpcode()) { 1336 case ARM::STRD: 1337 case ARM::STRD_PRE: 1338 case ARM::STRD_POST: 1339 case ARM::STRH: 1340 case ARM::STRH_PRE: 1341 case ARM::STRH_POST: 1342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1343 return MCDisassembler::Fail; 1344 break; 1345 default: 1346 break; 1347 } 1348 } 1349 1350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1351 return MCDisassembler::Fail; 1352 switch (Inst.getOpcode()) { 1353 case ARM::STRD: 1354 case ARM::STRD_PRE: 1355 case ARM::STRD_POST: 1356 case ARM::LDRD: 1357 case ARM::LDRD_PRE: 1358 case ARM::LDRD_POST: 1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1360 return MCDisassembler::Fail; 1361 break; 1362 default: 1363 break; 1364 } 1365 1366 if (writeback) { 1367 // On loads, the writeback operand comes after Rt. 1368 switch (Inst.getOpcode()) { 1369 case ARM::LDRD: 1370 case ARM::LDRD_PRE: 1371 case ARM::LDRD_POST: 1372 case ARM::LDRH: 1373 case ARM::LDRH_PRE: 1374 case ARM::LDRH_POST: 1375 case ARM::LDRSH: 1376 case ARM::LDRSH_PRE: 1377 case ARM::LDRSH_POST: 1378 case ARM::LDRSB: 1379 case ARM::LDRSB_PRE: 1380 case ARM::LDRSB_POST: 1381 case ARM::LDRHTr: 1382 case ARM::LDRSBTr: 1383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1384 return MCDisassembler::Fail; 1385 break; 1386 default: 1387 break; 1388 } 1389 } 1390 1391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1392 return MCDisassembler::Fail; 1393 1394 if (type) { 1395 Inst.addOperand(MCOperand::CreateReg(0)); 1396 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1397 } else { 1398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1399 return MCDisassembler::Fail; 1400 Inst.addOperand(MCOperand::CreateImm(U)); 1401 } 1402 1403 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1404 return MCDisassembler::Fail; 1405 1406 return S; 1407 } 1408 1409 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1410 uint64_t Address, const void *Decoder) { 1411 DecodeStatus S = MCDisassembler::Success; 1412 1413 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1414 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1415 1416 switch (mode) { 1417 case 0: 1418 mode = ARM_AM::da; 1419 break; 1420 case 1: 1421 mode = ARM_AM::ia; 1422 break; 1423 case 2: 1424 mode = ARM_AM::db; 1425 break; 1426 case 3: 1427 mode = ARM_AM::ib; 1428 break; 1429 } 1430 1431 Inst.addOperand(MCOperand::CreateImm(mode)); 1432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1433 return MCDisassembler::Fail; 1434 1435 return S; 1436 } 1437 1438 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1439 unsigned Insn, 1440 uint64_t Address, const void *Decoder) { 1441 DecodeStatus S = MCDisassembler::Success; 1442 1443 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1444 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1445 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1446 1447 if (pred == 0xF) { 1448 switch (Inst.getOpcode()) { 1449 case ARM::LDMDA: 1450 Inst.setOpcode(ARM::RFEDA); 1451 break; 1452 case ARM::LDMDA_UPD: 1453 Inst.setOpcode(ARM::RFEDA_UPD); 1454 break; 1455 case ARM::LDMDB: 1456 Inst.setOpcode(ARM::RFEDB); 1457 break; 1458 case ARM::LDMDB_UPD: 1459 Inst.setOpcode(ARM::RFEDB_UPD); 1460 break; 1461 case ARM::LDMIA: 1462 Inst.setOpcode(ARM::RFEIA); 1463 break; 1464 case ARM::LDMIA_UPD: 1465 Inst.setOpcode(ARM::RFEIA_UPD); 1466 break; 1467 case ARM::LDMIB: 1468 Inst.setOpcode(ARM::RFEIB); 1469 break; 1470 case ARM::LDMIB_UPD: 1471 Inst.setOpcode(ARM::RFEIB_UPD); 1472 break; 1473 case ARM::STMDA: 1474 Inst.setOpcode(ARM::SRSDA); 1475 break; 1476 case ARM::STMDA_UPD: 1477 Inst.setOpcode(ARM::SRSDA_UPD); 1478 break; 1479 case ARM::STMDB: 1480 Inst.setOpcode(ARM::SRSDB); 1481 break; 1482 case ARM::STMDB_UPD: 1483 Inst.setOpcode(ARM::SRSDB_UPD); 1484 break; 1485 case ARM::STMIA: 1486 Inst.setOpcode(ARM::SRSIA); 1487 break; 1488 case ARM::STMIA_UPD: 1489 Inst.setOpcode(ARM::SRSIA_UPD); 1490 break; 1491 case ARM::STMIB: 1492 Inst.setOpcode(ARM::SRSIB); 1493 break; 1494 case ARM::STMIB_UPD: 1495 Inst.setOpcode(ARM::SRSIB_UPD); 1496 break; 1497 default: 1498 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1499 } 1500 1501 // For stores (which become SRS's, the only operand is the mode. 1502 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1503 Inst.addOperand( 1504 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1505 return S; 1506 } 1507 1508 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1509 } 1510 1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1512 return MCDisassembler::Fail; 1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1514 return MCDisassembler::Fail; // Tied 1515 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1516 return MCDisassembler::Fail; 1517 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1518 return MCDisassembler::Fail; 1519 1520 return S; 1521 } 1522 1523 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1524 uint64_t Address, const void *Decoder) { 1525 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1526 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1527 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1528 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1529 1530 DecodeStatus S = MCDisassembler::Success; 1531 1532 // imod == '01' --> UNPREDICTABLE 1533 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1534 // return failure here. The '01' imod value is unprintable, so there's 1535 // nothing useful we could do even if we returned UNPREDICTABLE. 1536 1537 if (imod == 1) return MCDisassembler::Fail; 1538 1539 if (imod && M) { 1540 Inst.setOpcode(ARM::CPS3p); 1541 Inst.addOperand(MCOperand::CreateImm(imod)); 1542 Inst.addOperand(MCOperand::CreateImm(iflags)); 1543 Inst.addOperand(MCOperand::CreateImm(mode)); 1544 } else if (imod && !M) { 1545 Inst.setOpcode(ARM::CPS2p); 1546 Inst.addOperand(MCOperand::CreateImm(imod)); 1547 Inst.addOperand(MCOperand::CreateImm(iflags)); 1548 if (mode) S = MCDisassembler::SoftFail; 1549 } else if (!imod && M) { 1550 Inst.setOpcode(ARM::CPS1p); 1551 Inst.addOperand(MCOperand::CreateImm(mode)); 1552 if (iflags) S = MCDisassembler::SoftFail; 1553 } else { 1554 // imod == '00' && M == '0' --> UNPREDICTABLE 1555 Inst.setOpcode(ARM::CPS1p); 1556 Inst.addOperand(MCOperand::CreateImm(mode)); 1557 S = MCDisassembler::SoftFail; 1558 } 1559 1560 return S; 1561 } 1562 1563 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1564 uint64_t Address, const void *Decoder) { 1565 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1566 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1567 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1568 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1569 1570 DecodeStatus S = MCDisassembler::Success; 1571 1572 // imod == '01' --> UNPREDICTABLE 1573 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1574 // return failure here. The '01' imod value is unprintable, so there's 1575 // nothing useful we could do even if we returned UNPREDICTABLE. 1576 1577 if (imod == 1) return MCDisassembler::Fail; 1578 1579 if (imod && M) { 1580 Inst.setOpcode(ARM::t2CPS3p); 1581 Inst.addOperand(MCOperand::CreateImm(imod)); 1582 Inst.addOperand(MCOperand::CreateImm(iflags)); 1583 Inst.addOperand(MCOperand::CreateImm(mode)); 1584 } else if (imod && !M) { 1585 Inst.setOpcode(ARM::t2CPS2p); 1586 Inst.addOperand(MCOperand::CreateImm(imod)); 1587 Inst.addOperand(MCOperand::CreateImm(iflags)); 1588 if (mode) S = MCDisassembler::SoftFail; 1589 } else if (!imod && M) { 1590 Inst.setOpcode(ARM::t2CPS1p); 1591 Inst.addOperand(MCOperand::CreateImm(mode)); 1592 if (iflags) S = MCDisassembler::SoftFail; 1593 } else { 1594 // imod == '00' && M == '0' --> UNPREDICTABLE 1595 Inst.setOpcode(ARM::t2CPS1p); 1596 Inst.addOperand(MCOperand::CreateImm(mode)); 1597 S = MCDisassembler::SoftFail; 1598 } 1599 1600 return S; 1601 } 1602 1603 1604 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1605 uint64_t Address, const void *Decoder) { 1606 DecodeStatus S = MCDisassembler::Success; 1607 1608 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1609 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1610 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1611 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1612 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1613 1614 if (pred == 0xF) 1615 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1616 1617 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1618 return MCDisassembler::Fail; 1619 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1620 return MCDisassembler::Fail; 1621 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1622 return MCDisassembler::Fail; 1623 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1624 return MCDisassembler::Fail; 1625 1626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1627 return MCDisassembler::Fail; 1628 1629 return S; 1630 } 1631 1632 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1633 uint64_t Address, const void *Decoder) { 1634 DecodeStatus S = MCDisassembler::Success; 1635 1636 unsigned add = fieldFromInstruction32(Val, 12, 1); 1637 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1638 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1639 1640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1641 return MCDisassembler::Fail; 1642 1643 if (!add) imm *= -1; 1644 if (imm == 0 && !add) imm = INT32_MIN; 1645 Inst.addOperand(MCOperand::CreateImm(imm)); 1646 1647 return S; 1648 } 1649 1650 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1651 uint64_t Address, const void *Decoder) { 1652 DecodeStatus S = MCDisassembler::Success; 1653 1654 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1655 unsigned U = fieldFromInstruction32(Val, 8, 1); 1656 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1657 1658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1659 return MCDisassembler::Fail; 1660 1661 if (U) 1662 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1663 else 1664 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1665 1666 return S; 1667 } 1668 1669 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1670 uint64_t Address, const void *Decoder) { 1671 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1672 } 1673 1674 static DecodeStatus 1675 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1676 uint64_t Address, const void *Decoder) { 1677 DecodeStatus S = MCDisassembler::Success; 1678 1679 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1680 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1681 1682 if (pred == 0xF) { 1683 Inst.setOpcode(ARM::BLXi); 1684 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1685 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1686 return S; 1687 } 1688 1689 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1690 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1691 return MCDisassembler::Fail; 1692 1693 return S; 1694 } 1695 1696 1697 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1698 uint64_t Address, const void *Decoder) { 1699 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1700 return MCDisassembler::Success; 1701 } 1702 1703 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1704 uint64_t Address, const void *Decoder) { 1705 DecodeStatus S = MCDisassembler::Success; 1706 1707 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1708 unsigned align = fieldFromInstruction32(Val, 4, 2); 1709 1710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1711 return MCDisassembler::Fail; 1712 if (!align) 1713 Inst.addOperand(MCOperand::CreateImm(0)); 1714 else 1715 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1716 1717 return S; 1718 } 1719 1720 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1721 uint64_t Address, const void *Decoder) { 1722 DecodeStatus S = MCDisassembler::Success; 1723 1724 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1725 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1726 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1727 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1728 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1729 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1730 1731 // First output register 1732 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1733 return MCDisassembler::Fail; 1734 1735 // Second output register 1736 switch (Inst.getOpcode()) { 1737 case ARM::VLD1q8: 1738 case ARM::VLD1q16: 1739 case ARM::VLD1q32: 1740 case ARM::VLD1q64: 1741 case ARM::VLD1q8_UPD: 1742 case ARM::VLD1q16_UPD: 1743 case ARM::VLD1q32_UPD: 1744 case ARM::VLD1q64_UPD: 1745 case ARM::VLD1d8T: 1746 case ARM::VLD1d16T: 1747 case ARM::VLD1d32T: 1748 case ARM::VLD1d64T: 1749 case ARM::VLD1d8T_UPD: 1750 case ARM::VLD1d16T_UPD: 1751 case ARM::VLD1d32T_UPD: 1752 case ARM::VLD1d64T_UPD: 1753 case ARM::VLD1d8Q: 1754 case ARM::VLD1d16Q: 1755 case ARM::VLD1d32Q: 1756 case ARM::VLD1d64Q: 1757 case ARM::VLD1d8Q_UPD: 1758 case ARM::VLD1d16Q_UPD: 1759 case ARM::VLD1d32Q_UPD: 1760 case ARM::VLD1d64Q_UPD: 1761 case ARM::VLD2d8: 1762 case ARM::VLD2d16: 1763 case ARM::VLD2d32: 1764 case ARM::VLD2d8_UPD: 1765 case ARM::VLD2d16_UPD: 1766 case ARM::VLD2d32_UPD: 1767 case ARM::VLD2q8: 1768 case ARM::VLD2q16: 1769 case ARM::VLD2q32: 1770 case ARM::VLD2q8_UPD: 1771 case ARM::VLD2q16_UPD: 1772 case ARM::VLD2q32_UPD: 1773 case ARM::VLD3d8: 1774 case ARM::VLD3d16: 1775 case ARM::VLD3d32: 1776 case ARM::VLD3d8_UPD: 1777 case ARM::VLD3d16_UPD: 1778 case ARM::VLD3d32_UPD: 1779 case ARM::VLD4d8: 1780 case ARM::VLD4d16: 1781 case ARM::VLD4d32: 1782 case ARM::VLD4d8_UPD: 1783 case ARM::VLD4d16_UPD: 1784 case ARM::VLD4d32_UPD: 1785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 break; 1788 case ARM::VLD2b8: 1789 case ARM::VLD2b16: 1790 case ARM::VLD2b32: 1791 case ARM::VLD2b8_UPD: 1792 case ARM::VLD2b16_UPD: 1793 case ARM::VLD2b32_UPD: 1794 case ARM::VLD3q8: 1795 case ARM::VLD3q16: 1796 case ARM::VLD3q32: 1797 case ARM::VLD3q8_UPD: 1798 case ARM::VLD3q16_UPD: 1799 case ARM::VLD3q32_UPD: 1800 case ARM::VLD4q8: 1801 case ARM::VLD4q16: 1802 case ARM::VLD4q32: 1803 case ARM::VLD4q8_UPD: 1804 case ARM::VLD4q16_UPD: 1805 case ARM::VLD4q32_UPD: 1806 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1807 return MCDisassembler::Fail; 1808 default: 1809 break; 1810 } 1811 1812 // Third output register 1813 switch(Inst.getOpcode()) { 1814 case ARM::VLD1d8T: 1815 case ARM::VLD1d16T: 1816 case ARM::VLD1d32T: 1817 case ARM::VLD1d64T: 1818 case ARM::VLD1d8T_UPD: 1819 case ARM::VLD1d16T_UPD: 1820 case ARM::VLD1d32T_UPD: 1821 case ARM::VLD1d64T_UPD: 1822 case ARM::VLD1d8Q: 1823 case ARM::VLD1d16Q: 1824 case ARM::VLD1d32Q: 1825 case ARM::VLD1d64Q: 1826 case ARM::VLD1d8Q_UPD: 1827 case ARM::VLD1d16Q_UPD: 1828 case ARM::VLD1d32Q_UPD: 1829 case ARM::VLD1d64Q_UPD: 1830 case ARM::VLD2q8: 1831 case ARM::VLD2q16: 1832 case ARM::VLD2q32: 1833 case ARM::VLD2q8_UPD: 1834 case ARM::VLD2q16_UPD: 1835 case ARM::VLD2q32_UPD: 1836 case ARM::VLD3d8: 1837 case ARM::VLD3d16: 1838 case ARM::VLD3d32: 1839 case ARM::VLD3d8_UPD: 1840 case ARM::VLD3d16_UPD: 1841 case ARM::VLD3d32_UPD: 1842 case ARM::VLD4d8: 1843 case ARM::VLD4d16: 1844 case ARM::VLD4d32: 1845 case ARM::VLD4d8_UPD: 1846 case ARM::VLD4d16_UPD: 1847 case ARM::VLD4d32_UPD: 1848 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1849 return MCDisassembler::Fail; 1850 break; 1851 case ARM::VLD3q8: 1852 case ARM::VLD3q16: 1853 case ARM::VLD3q32: 1854 case ARM::VLD3q8_UPD: 1855 case ARM::VLD3q16_UPD: 1856 case ARM::VLD3q32_UPD: 1857 case ARM::VLD4q8: 1858 case ARM::VLD4q16: 1859 case ARM::VLD4q32: 1860 case ARM::VLD4q8_UPD: 1861 case ARM::VLD4q16_UPD: 1862 case ARM::VLD4q32_UPD: 1863 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1864 return MCDisassembler::Fail; 1865 break; 1866 default: 1867 break; 1868 } 1869 1870 // Fourth output register 1871 switch (Inst.getOpcode()) { 1872 case ARM::VLD1d8Q: 1873 case ARM::VLD1d16Q: 1874 case ARM::VLD1d32Q: 1875 case ARM::VLD1d64Q: 1876 case ARM::VLD1d8Q_UPD: 1877 case ARM::VLD1d16Q_UPD: 1878 case ARM::VLD1d32Q_UPD: 1879 case ARM::VLD1d64Q_UPD: 1880 case ARM::VLD2q8: 1881 case ARM::VLD2q16: 1882 case ARM::VLD2q32: 1883 case ARM::VLD2q8_UPD: 1884 case ARM::VLD2q16_UPD: 1885 case ARM::VLD2q32_UPD: 1886 case ARM::VLD4d8: 1887 case ARM::VLD4d16: 1888 case ARM::VLD4d32: 1889 case ARM::VLD4d8_UPD: 1890 case ARM::VLD4d16_UPD: 1891 case ARM::VLD4d32_UPD: 1892 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1893 return MCDisassembler::Fail; 1894 break; 1895 case ARM::VLD4q8: 1896 case ARM::VLD4q16: 1897 case ARM::VLD4q32: 1898 case ARM::VLD4q8_UPD: 1899 case ARM::VLD4q16_UPD: 1900 case ARM::VLD4q32_UPD: 1901 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1902 return MCDisassembler::Fail; 1903 break; 1904 default: 1905 break; 1906 } 1907 1908 // Writeback operand 1909 switch (Inst.getOpcode()) { 1910 case ARM::VLD1d8_UPD: 1911 case ARM::VLD1d16_UPD: 1912 case ARM::VLD1d32_UPD: 1913 case ARM::VLD1d64_UPD: 1914 case ARM::VLD1q8_UPD: 1915 case ARM::VLD1q16_UPD: 1916 case ARM::VLD1q32_UPD: 1917 case ARM::VLD1q64_UPD: 1918 case ARM::VLD1d8T_UPD: 1919 case ARM::VLD1d16T_UPD: 1920 case ARM::VLD1d32T_UPD: 1921 case ARM::VLD1d64T_UPD: 1922 case ARM::VLD1d8Q_UPD: 1923 case ARM::VLD1d16Q_UPD: 1924 case ARM::VLD1d32Q_UPD: 1925 case ARM::VLD1d64Q_UPD: 1926 case ARM::VLD2d8_UPD: 1927 case ARM::VLD2d16_UPD: 1928 case ARM::VLD2d32_UPD: 1929 case ARM::VLD2q8_UPD: 1930 case ARM::VLD2q16_UPD: 1931 case ARM::VLD2q32_UPD: 1932 case ARM::VLD2b8_UPD: 1933 case ARM::VLD2b16_UPD: 1934 case ARM::VLD2b32_UPD: 1935 case ARM::VLD3d8_UPD: 1936 case ARM::VLD3d16_UPD: 1937 case ARM::VLD3d32_UPD: 1938 case ARM::VLD3q8_UPD: 1939 case ARM::VLD3q16_UPD: 1940 case ARM::VLD3q32_UPD: 1941 case ARM::VLD4d8_UPD: 1942 case ARM::VLD4d16_UPD: 1943 case ARM::VLD4d32_UPD: 1944 case ARM::VLD4q8_UPD: 1945 case ARM::VLD4q16_UPD: 1946 case ARM::VLD4q32_UPD: 1947 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1948 return MCDisassembler::Fail; 1949 break; 1950 default: 1951 break; 1952 } 1953 1954 // AddrMode6 Base (register+alignment) 1955 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1956 return MCDisassembler::Fail; 1957 1958 // AddrMode6 Offset (register) 1959 if (Rm == 0xD) 1960 Inst.addOperand(MCOperand::CreateReg(0)); 1961 else if (Rm != 0xF) { 1962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1963 return MCDisassembler::Fail; 1964 } 1965 1966 return S; 1967 } 1968 1969 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1970 uint64_t Address, const void *Decoder) { 1971 DecodeStatus S = MCDisassembler::Success; 1972 1973 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1974 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1975 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1976 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1977 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1978 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1979 1980 // Writeback Operand 1981 switch (Inst.getOpcode()) { 1982 case ARM::VST1d8_UPD: 1983 case ARM::VST1d16_UPD: 1984 case ARM::VST1d32_UPD: 1985 case ARM::VST1d64_UPD: 1986 case ARM::VST1q8_UPD: 1987 case ARM::VST1q16_UPD: 1988 case ARM::VST1q32_UPD: 1989 case ARM::VST1q64_UPD: 1990 case ARM::VST1d8T_UPD: 1991 case ARM::VST1d16T_UPD: 1992 case ARM::VST1d32T_UPD: 1993 case ARM::VST1d64T_UPD: 1994 case ARM::VST1d8Q_UPD: 1995 case ARM::VST1d16Q_UPD: 1996 case ARM::VST1d32Q_UPD: 1997 case ARM::VST1d64Q_UPD: 1998 case ARM::VST2d8_UPD: 1999 case ARM::VST2d16_UPD: 2000 case ARM::VST2d32_UPD: 2001 case ARM::VST2q8_UPD: 2002 case ARM::VST2q16_UPD: 2003 case ARM::VST2q32_UPD: 2004 case ARM::VST2b8_UPD: 2005 case ARM::VST2b16_UPD: 2006 case ARM::VST2b32_UPD: 2007 case ARM::VST3d8_UPD: 2008 case ARM::VST3d16_UPD: 2009 case ARM::VST3d32_UPD: 2010 case ARM::VST3q8_UPD: 2011 case ARM::VST3q16_UPD: 2012 case ARM::VST3q32_UPD: 2013 case ARM::VST4d8_UPD: 2014 case ARM::VST4d16_UPD: 2015 case ARM::VST4d32_UPD: 2016 case ARM::VST4q8_UPD: 2017 case ARM::VST4q16_UPD: 2018 case ARM::VST4q32_UPD: 2019 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2020 return MCDisassembler::Fail; 2021 break; 2022 default: 2023 break; 2024 } 2025 2026 // AddrMode6 Base (register+alignment) 2027 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2028 return MCDisassembler::Fail; 2029 2030 // AddrMode6 Offset (register) 2031 if (Rm == 0xD) 2032 Inst.addOperand(MCOperand::CreateReg(0)); 2033 else if (Rm != 0xF) { 2034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2035 return MCDisassembler::Fail; 2036 } 2037 2038 // First input register 2039 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2040 return MCDisassembler::Fail; 2041 2042 // Second input register 2043 switch (Inst.getOpcode()) { 2044 case ARM::VST1q8: 2045 case ARM::VST1q16: 2046 case ARM::VST1q32: 2047 case ARM::VST1q64: 2048 case ARM::VST1q8_UPD: 2049 case ARM::VST1q16_UPD: 2050 case ARM::VST1q32_UPD: 2051 case ARM::VST1q64_UPD: 2052 case ARM::VST1d8T: 2053 case ARM::VST1d16T: 2054 case ARM::VST1d32T: 2055 case ARM::VST1d64T: 2056 case ARM::VST1d8T_UPD: 2057 case ARM::VST1d16T_UPD: 2058 case ARM::VST1d32T_UPD: 2059 case ARM::VST1d64T_UPD: 2060 case ARM::VST1d8Q: 2061 case ARM::VST1d16Q: 2062 case ARM::VST1d32Q: 2063 case ARM::VST1d64Q: 2064 case ARM::VST1d8Q_UPD: 2065 case ARM::VST1d16Q_UPD: 2066 case ARM::VST1d32Q_UPD: 2067 case ARM::VST1d64Q_UPD: 2068 case ARM::VST2d8: 2069 case ARM::VST2d16: 2070 case ARM::VST2d32: 2071 case ARM::VST2d8_UPD: 2072 case ARM::VST2d16_UPD: 2073 case ARM::VST2d32_UPD: 2074 case ARM::VST2q8: 2075 case ARM::VST2q16: 2076 case ARM::VST2q32: 2077 case ARM::VST2q8_UPD: 2078 case ARM::VST2q16_UPD: 2079 case ARM::VST2q32_UPD: 2080 case ARM::VST3d8: 2081 case ARM::VST3d16: 2082 case ARM::VST3d32: 2083 case ARM::VST3d8_UPD: 2084 case ARM::VST3d16_UPD: 2085 case ARM::VST3d32_UPD: 2086 case ARM::VST4d8: 2087 case ARM::VST4d16: 2088 case ARM::VST4d32: 2089 case ARM::VST4d8_UPD: 2090 case ARM::VST4d16_UPD: 2091 case ARM::VST4d32_UPD: 2092 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2093 return MCDisassembler::Fail; 2094 break; 2095 case ARM::VST2b8: 2096 case ARM::VST2b16: 2097 case ARM::VST2b32: 2098 case ARM::VST2b8_UPD: 2099 case ARM::VST2b16_UPD: 2100 case ARM::VST2b32_UPD: 2101 case ARM::VST3q8: 2102 case ARM::VST3q16: 2103 case ARM::VST3q32: 2104 case ARM::VST3q8_UPD: 2105 case ARM::VST3q16_UPD: 2106 case ARM::VST3q32_UPD: 2107 case ARM::VST4q8: 2108 case ARM::VST4q16: 2109 case ARM::VST4q32: 2110 case ARM::VST4q8_UPD: 2111 case ARM::VST4q16_UPD: 2112 case ARM::VST4q32_UPD: 2113 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2114 return MCDisassembler::Fail; 2115 break; 2116 default: 2117 break; 2118 } 2119 2120 // Third input register 2121 switch (Inst.getOpcode()) { 2122 case ARM::VST1d8T: 2123 case ARM::VST1d16T: 2124 case ARM::VST1d32T: 2125 case ARM::VST1d64T: 2126 case ARM::VST1d8T_UPD: 2127 case ARM::VST1d16T_UPD: 2128 case ARM::VST1d32T_UPD: 2129 case ARM::VST1d64T_UPD: 2130 case ARM::VST1d8Q: 2131 case ARM::VST1d16Q: 2132 case ARM::VST1d32Q: 2133 case ARM::VST1d64Q: 2134 case ARM::VST1d8Q_UPD: 2135 case ARM::VST1d16Q_UPD: 2136 case ARM::VST1d32Q_UPD: 2137 case ARM::VST1d64Q_UPD: 2138 case ARM::VST2q8: 2139 case ARM::VST2q16: 2140 case ARM::VST2q32: 2141 case ARM::VST2q8_UPD: 2142 case ARM::VST2q16_UPD: 2143 case ARM::VST2q32_UPD: 2144 case ARM::VST3d8: 2145 case ARM::VST3d16: 2146 case ARM::VST3d32: 2147 case ARM::VST3d8_UPD: 2148 case ARM::VST3d16_UPD: 2149 case ARM::VST3d32_UPD: 2150 case ARM::VST4d8: 2151 case ARM::VST4d16: 2152 case ARM::VST4d32: 2153 case ARM::VST4d8_UPD: 2154 case ARM::VST4d16_UPD: 2155 case ARM::VST4d32_UPD: 2156 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2157 return MCDisassembler::Fail; 2158 break; 2159 case ARM::VST3q8: 2160 case ARM::VST3q16: 2161 case ARM::VST3q32: 2162 case ARM::VST3q8_UPD: 2163 case ARM::VST3q16_UPD: 2164 case ARM::VST3q32_UPD: 2165 case ARM::VST4q8: 2166 case ARM::VST4q16: 2167 case ARM::VST4q32: 2168 case ARM::VST4q8_UPD: 2169 case ARM::VST4q16_UPD: 2170 case ARM::VST4q32_UPD: 2171 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 break; 2174 default: 2175 break; 2176 } 2177 2178 // Fourth input register 2179 switch (Inst.getOpcode()) { 2180 case ARM::VST1d8Q: 2181 case ARM::VST1d16Q: 2182 case ARM::VST1d32Q: 2183 case ARM::VST1d64Q: 2184 case ARM::VST1d8Q_UPD: 2185 case ARM::VST1d16Q_UPD: 2186 case ARM::VST1d32Q_UPD: 2187 case ARM::VST1d64Q_UPD: 2188 case ARM::VST2q8: 2189 case ARM::VST2q16: 2190 case ARM::VST2q32: 2191 case ARM::VST2q8_UPD: 2192 case ARM::VST2q16_UPD: 2193 case ARM::VST2q32_UPD: 2194 case ARM::VST4d8: 2195 case ARM::VST4d16: 2196 case ARM::VST4d32: 2197 case ARM::VST4d8_UPD: 2198 case ARM::VST4d16_UPD: 2199 case ARM::VST4d32_UPD: 2200 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2201 return MCDisassembler::Fail; 2202 break; 2203 case ARM::VST4q8: 2204 case ARM::VST4q16: 2205 case ARM::VST4q32: 2206 case ARM::VST4q8_UPD: 2207 case ARM::VST4q16_UPD: 2208 case ARM::VST4q32_UPD: 2209 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2210 return MCDisassembler::Fail; 2211 break; 2212 default: 2213 break; 2214 } 2215 2216 return S; 2217 } 2218 2219 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2220 uint64_t Address, const void *Decoder) { 2221 DecodeStatus S = MCDisassembler::Success; 2222 2223 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2224 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2226 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2227 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2228 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2229 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2230 2231 align *= (1 << size); 2232 2233 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2234 return MCDisassembler::Fail; 2235 if (regs == 2) { 2236 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 } 2239 if (Rm != 0xF) { 2240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2241 return MCDisassembler::Fail; 2242 } 2243 2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 Inst.addOperand(MCOperand::CreateImm(align)); 2247 2248 if (Rm == 0xD) 2249 Inst.addOperand(MCOperand::CreateReg(0)); 2250 else if (Rm != 0xF) { 2251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2252 return MCDisassembler::Fail; 2253 } 2254 2255 return S; 2256 } 2257 2258 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2259 uint64_t Address, const void *Decoder) { 2260 DecodeStatus S = MCDisassembler::Success; 2261 2262 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2263 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2264 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2265 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2266 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2267 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2268 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2269 align *= 2*size; 2270 2271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2274 return MCDisassembler::Fail; 2275 if (Rm != 0xF) { 2276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2277 return MCDisassembler::Fail; 2278 } 2279 2280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2281 return MCDisassembler::Fail; 2282 Inst.addOperand(MCOperand::CreateImm(align)); 2283 2284 if (Rm == 0xD) 2285 Inst.addOperand(MCOperand::CreateReg(0)); 2286 else if (Rm != 0xF) { 2287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2288 return MCDisassembler::Fail; 2289 } 2290 2291 return S; 2292 } 2293 2294 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2295 uint64_t Address, const void *Decoder) { 2296 DecodeStatus S = MCDisassembler::Success; 2297 2298 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2299 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2300 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2301 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2302 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2303 2304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2305 return MCDisassembler::Fail; 2306 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2307 return MCDisassembler::Fail; 2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2309 return MCDisassembler::Fail; 2310 if (Rm != 0xF) { 2311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2312 return MCDisassembler::Fail; 2313 } 2314 2315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2316 return MCDisassembler::Fail; 2317 Inst.addOperand(MCOperand::CreateImm(0)); 2318 2319 if (Rm == 0xD) 2320 Inst.addOperand(MCOperand::CreateReg(0)); 2321 else if (Rm != 0xF) { 2322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2323 return MCDisassembler::Fail; 2324 } 2325 2326 return S; 2327 } 2328 2329 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2330 uint64_t Address, const void *Decoder) { 2331 DecodeStatus S = MCDisassembler::Success; 2332 2333 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2334 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2335 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2336 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2337 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2338 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2339 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2340 2341 if (size == 0x3) { 2342 size = 4; 2343 align = 16; 2344 } else { 2345 if (size == 2) { 2346 size = 1 << size; 2347 align *= 8; 2348 } else { 2349 size = 1 << size; 2350 align *= 4*size; 2351 } 2352 } 2353 2354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2355 return MCDisassembler::Fail; 2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2357 return MCDisassembler::Fail; 2358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2359 return MCDisassembler::Fail; 2360 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2361 return MCDisassembler::Fail; 2362 if (Rm != 0xF) { 2363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2364 return MCDisassembler::Fail; 2365 } 2366 2367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2368 return MCDisassembler::Fail; 2369 Inst.addOperand(MCOperand::CreateImm(align)); 2370 2371 if (Rm == 0xD) 2372 Inst.addOperand(MCOperand::CreateReg(0)); 2373 else if (Rm != 0xF) { 2374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2375 return MCDisassembler::Fail; 2376 } 2377 2378 return S; 2379 } 2380 2381 static DecodeStatus 2382 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2383 uint64_t Address, const void *Decoder) { 2384 DecodeStatus S = MCDisassembler::Success; 2385 2386 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2387 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2388 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2389 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2390 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2391 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2392 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2393 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2394 2395 if (Q) { 2396 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2397 return MCDisassembler::Fail; 2398 } else { 2399 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2400 return MCDisassembler::Fail; 2401 } 2402 2403 Inst.addOperand(MCOperand::CreateImm(imm)); 2404 2405 switch (Inst.getOpcode()) { 2406 case ARM::VORRiv4i16: 2407 case ARM::VORRiv2i32: 2408 case ARM::VBICiv4i16: 2409 case ARM::VBICiv2i32: 2410 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2411 return MCDisassembler::Fail; 2412 break; 2413 case ARM::VORRiv8i16: 2414 case ARM::VORRiv4i32: 2415 case ARM::VBICiv8i16: 2416 case ARM::VBICiv4i32: 2417 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2418 return MCDisassembler::Fail; 2419 break; 2420 default: 2421 break; 2422 } 2423 2424 return S; 2425 } 2426 2427 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2428 uint64_t Address, const void *Decoder) { 2429 DecodeStatus S = MCDisassembler::Success; 2430 2431 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2432 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2433 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2434 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2435 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2436 2437 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2442 2443 return S; 2444 } 2445 2446 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2447 uint64_t Address, const void *Decoder) { 2448 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2449 return MCDisassembler::Success; 2450 } 2451 2452 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2453 uint64_t Address, const void *Decoder) { 2454 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2455 return MCDisassembler::Success; 2456 } 2457 2458 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2459 uint64_t Address, const void *Decoder) { 2460 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2461 return MCDisassembler::Success; 2462 } 2463 2464 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2465 uint64_t Address, const void *Decoder) { 2466 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2467 return MCDisassembler::Success; 2468 } 2469 2470 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2471 uint64_t Address, const void *Decoder) { 2472 DecodeStatus S = MCDisassembler::Success; 2473 2474 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2475 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2476 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2477 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2478 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2479 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2480 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2481 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2482 2483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2484 return MCDisassembler::Fail; 2485 if (op) { 2486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2487 return MCDisassembler::Fail; // Writeback 2488 } 2489 2490 for (unsigned i = 0; i < length; ++i) { 2491 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 } 2494 2495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2496 return MCDisassembler::Fail; 2497 2498 return S; 2499 } 2500 2501 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2502 uint64_t Address, const void *Decoder) { 2503 // The immediate needs to be a fully instantiated float. However, the 2504 // auto-generated decoder is only able to fill in some of the bits 2505 // necessary. For instance, the 'b' bit is replicated multiple times, 2506 // and is even present in inverted form in one bit. We do a little 2507 // binary parsing here to fill in those missing bits, and then 2508 // reinterpret it all as a float. 2509 union { 2510 uint32_t integer; 2511 float fp; 2512 } fp_conv; 2513 2514 fp_conv.integer = Val; 2515 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2516 fp_conv.integer |= b << 26; 2517 fp_conv.integer |= b << 27; 2518 fp_conv.integer |= b << 28; 2519 fp_conv.integer |= b << 29; 2520 fp_conv.integer |= (~b & 0x1) << 30; 2521 2522 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2523 return MCDisassembler::Success; 2524 } 2525 2526 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2527 uint64_t Address, const void *Decoder) { 2528 DecodeStatus S = MCDisassembler::Success; 2529 2530 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2531 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2532 2533 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 2536 switch(Inst.getOpcode()) { 2537 default: 2538 return MCDisassembler::Fail; 2539 case ARM::tADR: 2540 break; // tADR does not explicitly represent the PC as an operand. 2541 case ARM::tADDrSPi: 2542 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2543 break; 2544 } 2545 2546 Inst.addOperand(MCOperand::CreateImm(imm)); 2547 return S; 2548 } 2549 2550 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2551 uint64_t Address, const void *Decoder) { 2552 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2553 return MCDisassembler::Success; 2554 } 2555 2556 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2557 uint64_t Address, const void *Decoder) { 2558 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2559 return MCDisassembler::Success; 2560 } 2561 2562 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2563 uint64_t Address, const void *Decoder) { 2564 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2565 return MCDisassembler::Success; 2566 } 2567 2568 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2569 uint64_t Address, const void *Decoder) { 2570 DecodeStatus S = MCDisassembler::Success; 2571 2572 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2573 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2574 2575 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2578 return MCDisassembler::Fail; 2579 2580 return S; 2581 } 2582 2583 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2584 uint64_t Address, const void *Decoder) { 2585 DecodeStatus S = MCDisassembler::Success; 2586 2587 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2588 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2589 2590 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2591 return MCDisassembler::Fail; 2592 Inst.addOperand(MCOperand::CreateImm(imm)); 2593 2594 return S; 2595 } 2596 2597 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2598 uint64_t Address, const void *Decoder) { 2599 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2600 2601 return MCDisassembler::Success; 2602 } 2603 2604 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2605 uint64_t Address, const void *Decoder) { 2606 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2607 Inst.addOperand(MCOperand::CreateImm(Val)); 2608 2609 return MCDisassembler::Success; 2610 } 2611 2612 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2613 uint64_t Address, const void *Decoder) { 2614 DecodeStatus S = MCDisassembler::Success; 2615 2616 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2617 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2618 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2619 2620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2621 return MCDisassembler::Fail; 2622 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2623 return MCDisassembler::Fail; 2624 Inst.addOperand(MCOperand::CreateImm(imm)); 2625 2626 return S; 2627 } 2628 2629 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2630 uint64_t Address, const void *Decoder) { 2631 DecodeStatus S = MCDisassembler::Success; 2632 2633 switch (Inst.getOpcode()) { 2634 case ARM::t2PLDs: 2635 case ARM::t2PLDWs: 2636 case ARM::t2PLIs: 2637 break; 2638 default: { 2639 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2641 return MCDisassembler::Fail; 2642 } 2643 } 2644 2645 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2646 if (Rn == 0xF) { 2647 switch (Inst.getOpcode()) { 2648 case ARM::t2LDRBs: 2649 Inst.setOpcode(ARM::t2LDRBpci); 2650 break; 2651 case ARM::t2LDRHs: 2652 Inst.setOpcode(ARM::t2LDRHpci); 2653 break; 2654 case ARM::t2LDRSHs: 2655 Inst.setOpcode(ARM::t2LDRSHpci); 2656 break; 2657 case ARM::t2LDRSBs: 2658 Inst.setOpcode(ARM::t2LDRSBpci); 2659 break; 2660 case ARM::t2PLDs: 2661 Inst.setOpcode(ARM::t2PLDi12); 2662 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2663 break; 2664 default: 2665 return MCDisassembler::Fail; 2666 } 2667 2668 int imm = fieldFromInstruction32(Insn, 0, 12); 2669 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2670 Inst.addOperand(MCOperand::CreateImm(imm)); 2671 2672 return S; 2673 } 2674 2675 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2676 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2677 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2678 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 2681 return S; 2682 } 2683 2684 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2685 uint64_t Address, const void *Decoder) { 2686 int imm = Val & 0xFF; 2687 if (!(Val & 0x100)) imm *= -1; 2688 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2689 2690 return MCDisassembler::Success; 2691 } 2692 2693 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2694 uint64_t Address, const void *Decoder) { 2695 DecodeStatus S = MCDisassembler::Success; 2696 2697 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2698 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2699 2700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2703 return MCDisassembler::Fail; 2704 2705 return S; 2706 } 2707 2708 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2709 uint64_t Address, const void *Decoder) { 2710 DecodeStatus S = MCDisassembler::Success; 2711 2712 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2713 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2714 2715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 2718 Inst.addOperand(MCOperand::CreateImm(imm)); 2719 2720 return S; 2721 } 2722 2723 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2724 uint64_t Address, const void *Decoder) { 2725 int imm = Val & 0xFF; 2726 if (!(Val & 0x100)) imm *= -1; 2727 Inst.addOperand(MCOperand::CreateImm(imm)); 2728 2729 return MCDisassembler::Success; 2730 } 2731 2732 2733 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2734 uint64_t Address, const void *Decoder) { 2735 DecodeStatus S = MCDisassembler::Success; 2736 2737 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2738 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2739 2740 // Some instructions always use an additive offset. 2741 switch (Inst.getOpcode()) { 2742 case ARM::t2LDRT: 2743 case ARM::t2LDRBT: 2744 case ARM::t2LDRHT: 2745 case ARM::t2LDRSBT: 2746 case ARM::t2LDRSHT: 2747 imm |= 0x100; 2748 break; 2749 default: 2750 break; 2751 } 2752 2753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 2758 return S; 2759 } 2760 2761 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2762 uint64_t Address, const void *Decoder) { 2763 DecodeStatus S = MCDisassembler::Success; 2764 2765 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2766 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2767 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2768 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2769 addr |= Rn << 9; 2770 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2771 2772 if (!load) { 2773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 } 2776 2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 2780 if (load) { 2781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 } 2784 2785 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 2788 return S; 2789 } 2790 2791 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2792 uint64_t Address, const void *Decoder) { 2793 DecodeStatus S = MCDisassembler::Success; 2794 2795 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2796 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2797 2798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 Inst.addOperand(MCOperand::CreateImm(imm)); 2801 2802 return S; 2803 } 2804 2805 2806 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2807 uint64_t Address, const void *Decoder) { 2808 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2809 2810 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2811 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2812 Inst.addOperand(MCOperand::CreateImm(imm)); 2813 2814 return MCDisassembler::Success; 2815 } 2816 2817 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2818 uint64_t Address, const void *Decoder) { 2819 DecodeStatus S = MCDisassembler::Success; 2820 2821 if (Inst.getOpcode() == ARM::tADDrSP) { 2822 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2823 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2824 2825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2828 return MCDisassembler::Fail; 2829 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2830 } else if (Inst.getOpcode() == ARM::tADDspr) { 2831 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2832 2833 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2834 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 } 2838 2839 return S; 2840 } 2841 2842 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2843 uint64_t Address, const void *Decoder) { 2844 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2845 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2846 2847 Inst.addOperand(MCOperand::CreateImm(imod)); 2848 Inst.addOperand(MCOperand::CreateImm(flags)); 2849 2850 return MCDisassembler::Success; 2851 } 2852 2853 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2854 uint64_t Address, const void *Decoder) { 2855 DecodeStatus S = MCDisassembler::Success; 2856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2857 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2858 2859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 Inst.addOperand(MCOperand::CreateImm(add)); 2862 2863 return S; 2864 } 2865 2866 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2867 uint64_t Address, const void *Decoder) { 2868 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2869 return MCDisassembler::Success; 2870 } 2871 2872 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2873 uint64_t Address, const void *Decoder) { 2874 if (Val == 0xA || Val == 0xB) 2875 return MCDisassembler::Fail; 2876 2877 Inst.addOperand(MCOperand::CreateImm(Val)); 2878 return MCDisassembler::Success; 2879 } 2880 2881 static DecodeStatus 2882 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2883 uint64_t Address, const void *Decoder) { 2884 DecodeStatus S = MCDisassembler::Success; 2885 2886 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2887 if (pred == 0xE || pred == 0xF) { 2888 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2889 switch (opc) { 2890 default: 2891 return MCDisassembler::Fail; 2892 case 0xf3bf8f4: 2893 Inst.setOpcode(ARM::t2DSB); 2894 break; 2895 case 0xf3bf8f5: 2896 Inst.setOpcode(ARM::t2DMB); 2897 break; 2898 case 0xf3bf8f6: 2899 Inst.setOpcode(ARM::t2ISB); 2900 break; 2901 } 2902 2903 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2904 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2905 } 2906 2907 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2908 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2909 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2910 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2911 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2912 2913 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2914 return MCDisassembler::Fail; 2915 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2916 return MCDisassembler::Fail; 2917 2918 return S; 2919 } 2920 2921 // Decode a shifted immediate operand. These basically consist 2922 // of an 8-bit value, and a 4-bit directive that specifies either 2923 // a splat operation or a rotation. 2924 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2925 uint64_t Address, const void *Decoder) { 2926 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2927 if (ctrl == 0) { 2928 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2929 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2930 switch (byte) { 2931 case 0: 2932 Inst.addOperand(MCOperand::CreateImm(imm)); 2933 break; 2934 case 1: 2935 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2936 break; 2937 case 2: 2938 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2939 break; 2940 case 3: 2941 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2942 (imm << 8) | imm)); 2943 break; 2944 } 2945 } else { 2946 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2947 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2948 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2949 Inst.addOperand(MCOperand::CreateImm(imm)); 2950 } 2951 2952 return MCDisassembler::Success; 2953 } 2954 2955 static DecodeStatus 2956 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2957 uint64_t Address, const void *Decoder){ 2958 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2959 return MCDisassembler::Success; 2960 } 2961 2962 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2963 uint64_t Address, const void *Decoder){ 2964 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2965 return MCDisassembler::Success; 2966 } 2967 2968 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2969 uint64_t Address, const void *Decoder) { 2970 switch (Val) { 2971 default: 2972 return MCDisassembler::Fail; 2973 case 0xF: // SY 2974 case 0xE: // ST 2975 case 0xB: // ISH 2976 case 0xA: // ISHST 2977 case 0x7: // NSH 2978 case 0x6: // NSHST 2979 case 0x3: // OSH 2980 case 0x2: // OSHST 2981 break; 2982 } 2983 2984 Inst.addOperand(MCOperand::CreateImm(Val)); 2985 return MCDisassembler::Success; 2986 } 2987 2988 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2989 uint64_t Address, const void *Decoder) { 2990 if (!Val) return MCDisassembler::Fail; 2991 Inst.addOperand(MCOperand::CreateImm(Val)); 2992 return MCDisassembler::Success; 2993 } 2994 2995 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2996 uint64_t Address, const void *Decoder) { 2997 DecodeStatus S = MCDisassembler::Success; 2998 2999 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3000 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3001 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3002 3003 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3004 3005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 3014 return S; 3015 } 3016 3017 3018 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3019 uint64_t Address, const void *Decoder){ 3020 DecodeStatus S = MCDisassembler::Success; 3021 3022 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3023 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3024 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3025 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3026 3027 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3028 return MCDisassembler::Fail; 3029 3030 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3031 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3032 3033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3038 return MCDisassembler::Fail; 3039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 3042 return S; 3043 } 3044 3045 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3046 uint64_t Address, const void *Decoder) { 3047 DecodeStatus S = MCDisassembler::Success; 3048 3049 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3050 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3051 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3052 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3053 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3054 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3055 3056 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3057 3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3061 return MCDisassembler::Fail; 3062 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 3067 return S; 3068 } 3069 3070 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3071 uint64_t Address, const void *Decoder) { 3072 DecodeStatus S = MCDisassembler::Success; 3073 3074 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3075 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3076 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3077 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3078 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3079 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3080 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3081 3082 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3083 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3084 3085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3086 return MCDisassembler::Fail; 3087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 3094 return S; 3095 } 3096 3097 3098 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3099 uint64_t Address, const void *Decoder) { 3100 DecodeStatus S = MCDisassembler::Success; 3101 3102 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3103 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3104 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3105 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3106 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3107 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3108 3109 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3110 3111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3112 return MCDisassembler::Fail; 3113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3114 return MCDisassembler::Fail; 3115 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3116 return MCDisassembler::Fail; 3117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 3120 return S; 3121 } 3122 3123 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3124 uint64_t Address, const void *Decoder) { 3125 DecodeStatus S = MCDisassembler::Success; 3126 3127 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3128 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3129 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3130 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3131 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3132 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3133 3134 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3135 3136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3141 return MCDisassembler::Fail; 3142 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3143 return MCDisassembler::Fail; 3144 3145 return S; 3146 } 3147 3148 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3149 uint64_t Address, const void *Decoder) { 3150 DecodeStatus S = MCDisassembler::Success; 3151 3152 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3153 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3154 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3155 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3156 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3157 3158 unsigned align = 0; 3159 unsigned index = 0; 3160 switch (size) { 3161 default: 3162 return MCDisassembler::Fail; 3163 case 0: 3164 if (fieldFromInstruction32(Insn, 4, 1)) 3165 return MCDisassembler::Fail; // UNDEFINED 3166 index = fieldFromInstruction32(Insn, 5, 3); 3167 break; 3168 case 1: 3169 if (fieldFromInstruction32(Insn, 5, 1)) 3170 return MCDisassembler::Fail; // UNDEFINED 3171 index = fieldFromInstruction32(Insn, 6, 2); 3172 if (fieldFromInstruction32(Insn, 4, 1)) 3173 align = 2; 3174 break; 3175 case 2: 3176 if (fieldFromInstruction32(Insn, 6, 1)) 3177 return MCDisassembler::Fail; // UNDEFINED 3178 index = fieldFromInstruction32(Insn, 7, 1); 3179 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3180 align = 4; 3181 } 3182 3183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3184 return MCDisassembler::Fail; 3185 if (Rm != 0xF) { // Writeback 3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 } 3189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 Inst.addOperand(MCOperand::CreateImm(align)); 3192 if (Rm != 0xF) { 3193 if (Rm != 0xD) { 3194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3195 return MCDisassembler::Fail; 3196 } else 3197 Inst.addOperand(MCOperand::CreateReg(0)); 3198 } 3199 3200 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3201 return MCDisassembler::Fail; 3202 Inst.addOperand(MCOperand::CreateImm(index)); 3203 3204 return S; 3205 } 3206 3207 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3208 uint64_t Address, const void *Decoder) { 3209 DecodeStatus S = MCDisassembler::Success; 3210 3211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3212 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3213 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3214 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3215 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3216 3217 unsigned align = 0; 3218 unsigned index = 0; 3219 switch (size) { 3220 default: 3221 return MCDisassembler::Fail; 3222 case 0: 3223 if (fieldFromInstruction32(Insn, 4, 1)) 3224 return MCDisassembler::Fail; // UNDEFINED 3225 index = fieldFromInstruction32(Insn, 5, 3); 3226 break; 3227 case 1: 3228 if (fieldFromInstruction32(Insn, 5, 1)) 3229 return MCDisassembler::Fail; // UNDEFINED 3230 index = fieldFromInstruction32(Insn, 6, 2); 3231 if (fieldFromInstruction32(Insn, 4, 1)) 3232 align = 2; 3233 break; 3234 case 2: 3235 if (fieldFromInstruction32(Insn, 6, 1)) 3236 return MCDisassembler::Fail; // UNDEFINED 3237 index = fieldFromInstruction32(Insn, 7, 1); 3238 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3239 align = 4; 3240 } 3241 3242 if (Rm != 0xF) { // Writeback 3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 } 3246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 Inst.addOperand(MCOperand::CreateImm(align)); 3249 if (Rm != 0xF) { 3250 if (Rm != 0xD) { 3251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3252 return MCDisassembler::Fail; 3253 } else 3254 Inst.addOperand(MCOperand::CreateReg(0)); 3255 } 3256 3257 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 Inst.addOperand(MCOperand::CreateImm(index)); 3260 3261 return S; 3262 } 3263 3264 3265 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3266 uint64_t Address, const void *Decoder) { 3267 DecodeStatus S = MCDisassembler::Success; 3268 3269 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3271 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3272 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3273 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3274 3275 unsigned align = 0; 3276 unsigned index = 0; 3277 unsigned inc = 1; 3278 switch (size) { 3279 default: 3280 return MCDisassembler::Fail; 3281 case 0: 3282 index = fieldFromInstruction32(Insn, 5, 3); 3283 if (fieldFromInstruction32(Insn, 4, 1)) 3284 align = 2; 3285 break; 3286 case 1: 3287 index = fieldFromInstruction32(Insn, 6, 2); 3288 if (fieldFromInstruction32(Insn, 4, 1)) 3289 align = 4; 3290 if (fieldFromInstruction32(Insn, 5, 1)) 3291 inc = 2; 3292 break; 3293 case 2: 3294 if (fieldFromInstruction32(Insn, 5, 1)) 3295 return MCDisassembler::Fail; // UNDEFINED 3296 index = fieldFromInstruction32(Insn, 7, 1); 3297 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3298 align = 8; 3299 if (fieldFromInstruction32(Insn, 6, 1)) 3300 inc = 2; 3301 break; 3302 } 3303 3304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (Rm != 0xF) { // Writeback 3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 } 3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 Inst.addOperand(MCOperand::CreateImm(align)); 3315 if (Rm != 0xF) { 3316 if (Rm != 0xD) { 3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 } else 3320 Inst.addOperand(MCOperand::CreateReg(0)); 3321 } 3322 3323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 Inst.addOperand(MCOperand::CreateImm(index)); 3328 3329 return S; 3330 } 3331 3332 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3333 uint64_t Address, const void *Decoder) { 3334 DecodeStatus S = MCDisassembler::Success; 3335 3336 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3337 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3338 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3339 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3340 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3341 3342 unsigned align = 0; 3343 unsigned index = 0; 3344 unsigned inc = 1; 3345 switch (size) { 3346 default: 3347 return MCDisassembler::Fail; 3348 case 0: 3349 index = fieldFromInstruction32(Insn, 5, 3); 3350 if (fieldFromInstruction32(Insn, 4, 1)) 3351 align = 2; 3352 break; 3353 case 1: 3354 index = fieldFromInstruction32(Insn, 6, 2); 3355 if (fieldFromInstruction32(Insn, 4, 1)) 3356 align = 4; 3357 if (fieldFromInstruction32(Insn, 5, 1)) 3358 inc = 2; 3359 break; 3360 case 2: 3361 if (fieldFromInstruction32(Insn, 5, 1)) 3362 return MCDisassembler::Fail; // UNDEFINED 3363 index = fieldFromInstruction32(Insn, 7, 1); 3364 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3365 align = 8; 3366 if (fieldFromInstruction32(Insn, 6, 1)) 3367 inc = 2; 3368 break; 3369 } 3370 3371 if (Rm != 0xF) { // Writeback 3372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 } 3375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3376 return MCDisassembler::Fail; 3377 Inst.addOperand(MCOperand::CreateImm(align)); 3378 if (Rm != 0xF) { 3379 if (Rm != 0xD) { 3380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3381 return MCDisassembler::Fail; 3382 } else 3383 Inst.addOperand(MCOperand::CreateReg(0)); 3384 } 3385 3386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3389 return MCDisassembler::Fail; 3390 Inst.addOperand(MCOperand::CreateImm(index)); 3391 3392 return S; 3393 } 3394 3395 3396 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3397 uint64_t Address, const void *Decoder) { 3398 DecodeStatus S = MCDisassembler::Success; 3399 3400 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3401 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3402 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3403 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3404 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3405 3406 unsigned align = 0; 3407 unsigned index = 0; 3408 unsigned inc = 1; 3409 switch (size) { 3410 default: 3411 return MCDisassembler::Fail; 3412 case 0: 3413 if (fieldFromInstruction32(Insn, 4, 1)) 3414 return MCDisassembler::Fail; // UNDEFINED 3415 index = fieldFromInstruction32(Insn, 5, 3); 3416 break; 3417 case 1: 3418 if (fieldFromInstruction32(Insn, 4, 1)) 3419 return MCDisassembler::Fail; // UNDEFINED 3420 index = fieldFromInstruction32(Insn, 6, 2); 3421 if (fieldFromInstruction32(Insn, 5, 1)) 3422 inc = 2; 3423 break; 3424 case 2: 3425 if (fieldFromInstruction32(Insn, 4, 2)) 3426 return MCDisassembler::Fail; // UNDEFINED 3427 index = fieldFromInstruction32(Insn, 7, 1); 3428 if (fieldFromInstruction32(Insn, 6, 1)) 3429 inc = 2; 3430 break; 3431 } 3432 3433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 3440 if (Rm != 0xF) { // Writeback 3441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 } 3444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3445 return MCDisassembler::Fail; 3446 Inst.addOperand(MCOperand::CreateImm(align)); 3447 if (Rm != 0xF) { 3448 if (Rm != 0xD) { 3449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3450 return MCDisassembler::Fail; 3451 } else 3452 Inst.addOperand(MCOperand::CreateReg(0)); 3453 } 3454 3455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 Inst.addOperand(MCOperand::CreateImm(index)); 3462 3463 return S; 3464 } 3465 3466 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3467 uint64_t Address, const void *Decoder) { 3468 DecodeStatus S = MCDisassembler::Success; 3469 3470 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3471 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3472 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3473 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3474 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3475 3476 unsigned align = 0; 3477 unsigned index = 0; 3478 unsigned inc = 1; 3479 switch (size) { 3480 default: 3481 return MCDisassembler::Fail; 3482 case 0: 3483 if (fieldFromInstruction32(Insn, 4, 1)) 3484 return MCDisassembler::Fail; // UNDEFINED 3485 index = fieldFromInstruction32(Insn, 5, 3); 3486 break; 3487 case 1: 3488 if (fieldFromInstruction32(Insn, 4, 1)) 3489 return MCDisassembler::Fail; // UNDEFINED 3490 index = fieldFromInstruction32(Insn, 6, 2); 3491 if (fieldFromInstruction32(Insn, 5, 1)) 3492 inc = 2; 3493 break; 3494 case 2: 3495 if (fieldFromInstruction32(Insn, 4, 2)) 3496 return MCDisassembler::Fail; // UNDEFINED 3497 index = fieldFromInstruction32(Insn, 7, 1); 3498 if (fieldFromInstruction32(Insn, 6, 1)) 3499 inc = 2; 3500 break; 3501 } 3502 3503 if (Rm != 0xF) { // Writeback 3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3505 return MCDisassembler::Fail; 3506 } 3507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 Inst.addOperand(MCOperand::CreateImm(align)); 3510 if (Rm != 0xF) { 3511 if (Rm != 0xD) { 3512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 } else 3515 Inst.addOperand(MCOperand::CreateReg(0)); 3516 } 3517 3518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3519 return MCDisassembler::Fail; 3520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 Inst.addOperand(MCOperand::CreateImm(index)); 3525 3526 return S; 3527 } 3528 3529 3530 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3531 uint64_t Address, const void *Decoder) { 3532 DecodeStatus S = MCDisassembler::Success; 3533 3534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3536 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3537 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3538 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3539 3540 unsigned align = 0; 3541 unsigned index = 0; 3542 unsigned inc = 1; 3543 switch (size) { 3544 default: 3545 return MCDisassembler::Fail; 3546 case 0: 3547 if (fieldFromInstruction32(Insn, 4, 1)) 3548 align = 4; 3549 index = fieldFromInstruction32(Insn, 5, 3); 3550 break; 3551 case 1: 3552 if (fieldFromInstruction32(Insn, 4, 1)) 3553 align = 8; 3554 index = fieldFromInstruction32(Insn, 6, 2); 3555 if (fieldFromInstruction32(Insn, 5, 1)) 3556 inc = 2; 3557 break; 3558 case 2: 3559 if (fieldFromInstruction32(Insn, 4, 2)) 3560 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3561 index = fieldFromInstruction32(Insn, 7, 1); 3562 if (fieldFromInstruction32(Insn, 6, 1)) 3563 inc = 2; 3564 break; 3565 } 3566 3567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 3576 if (Rm != 0xF) { // Writeback 3577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 } 3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3581 return MCDisassembler::Fail; 3582 Inst.addOperand(MCOperand::CreateImm(align)); 3583 if (Rm != 0xF) { 3584 if (Rm != 0xD) { 3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 } else 3588 Inst.addOperand(MCOperand::CreateReg(0)); 3589 } 3590 3591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 Inst.addOperand(MCOperand::CreateImm(index)); 3600 3601 return S; 3602 } 3603 3604 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3605 uint64_t Address, const void *Decoder) { 3606 DecodeStatus S = MCDisassembler::Success; 3607 3608 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3609 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3610 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3611 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3612 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3613 3614 unsigned align = 0; 3615 unsigned index = 0; 3616 unsigned inc = 1; 3617 switch (size) { 3618 default: 3619 return MCDisassembler::Fail; 3620 case 0: 3621 if (fieldFromInstruction32(Insn, 4, 1)) 3622 align = 4; 3623 index = fieldFromInstruction32(Insn, 5, 3); 3624 break; 3625 case 1: 3626 if (fieldFromInstruction32(Insn, 4, 1)) 3627 align = 8; 3628 index = fieldFromInstruction32(Insn, 6, 2); 3629 if (fieldFromInstruction32(Insn, 5, 1)) 3630 inc = 2; 3631 break; 3632 case 2: 3633 if (fieldFromInstruction32(Insn, 4, 2)) 3634 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3635 index = fieldFromInstruction32(Insn, 7, 1); 3636 if (fieldFromInstruction32(Insn, 6, 1)) 3637 inc = 2; 3638 break; 3639 } 3640 3641 if (Rm != 0xF) { // Writeback 3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 } 3645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 Inst.addOperand(MCOperand::CreateImm(align)); 3648 if (Rm != 0xF) { 3649 if (Rm != 0xD) { 3650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 } else 3653 Inst.addOperand(MCOperand::CreateReg(0)); 3654 } 3655 3656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3661 return MCDisassembler::Fail; 3662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3663 return MCDisassembler::Fail; 3664 Inst.addOperand(MCOperand::CreateImm(index)); 3665 3666 return S; 3667 } 3668 3669 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3670 uint64_t Address, const void *Decoder) { 3671 DecodeStatus S = MCDisassembler::Success; 3672 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3673 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3674 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3675 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3676 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3677 3678 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3679 S = MCDisassembler::SoftFail; 3680 3681 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3682 return MCDisassembler::Fail; 3683 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3684 return MCDisassembler::Fail; 3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3688 return MCDisassembler::Fail; 3689 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 3692 return S; 3693 } 3694 3695 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3696 uint64_t Address, const void *Decoder) { 3697 DecodeStatus S = MCDisassembler::Success; 3698 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3699 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3700 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3701 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3702 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3703 3704 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3705 S = MCDisassembler::SoftFail; 3706 3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3708 return MCDisassembler::Fail; 3709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3710 return MCDisassembler::Fail; 3711 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3712 return MCDisassembler::Fail; 3713 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3714 return MCDisassembler::Fail; 3715 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3716 return MCDisassembler::Fail; 3717 3718 return S; 3719 } 3720 3721 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3722 uint64_t Address, const void *Decoder) { 3723 DecodeStatus S = MCDisassembler::Success; 3724 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3725 // The InstPrinter needs to have the low bit of the predicate in 3726 // the mask operand to be able to print it properly. 3727 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3728 3729 if (pred == 0xF) { 3730 pred = 0xE; 3731 S = MCDisassembler::SoftFail; 3732 } 3733 3734 if ((mask & 0xF) == 0) { 3735 // Preserve the high bit of the mask, which is the low bit of 3736 // the predicate. 3737 mask &= 0x10; 3738 mask |= 0x8; 3739 S = MCDisassembler::SoftFail; 3740 } 3741 3742 Inst.addOperand(MCOperand::CreateImm(pred)); 3743 Inst.addOperand(MCOperand::CreateImm(mask)); 3744 return S; 3745 } 3746 3747 static DecodeStatus 3748 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3749 uint64_t Address, const void *Decoder) { 3750 DecodeStatus S = MCDisassembler::Success; 3751 3752 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3753 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3754 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3755 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3756 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3757 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3758 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3759 bool writeback = (W == 1) | (P == 0); 3760 3761 addr |= (U << 8) | (Rn << 9); 3762 3763 if (writeback && (Rn == Rt || Rn == Rt2)) 3764 Check(S, MCDisassembler::SoftFail); 3765 if (Rt == Rt2) 3766 Check(S, MCDisassembler::SoftFail); 3767 3768 // Rt 3769 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3770 return MCDisassembler::Fail; 3771 // Rt2 3772 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 // Writeback operand 3775 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 // addr 3778 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3779 return MCDisassembler::Fail; 3780 3781 return S; 3782 } 3783 3784 static DecodeStatus 3785 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3786 uint64_t Address, const void *Decoder) { 3787 DecodeStatus S = MCDisassembler::Success; 3788 3789 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3790 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3791 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3792 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3793 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3794 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3795 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3796 bool writeback = (W == 1) | (P == 0); 3797 3798 addr |= (U << 8) | (Rn << 9); 3799 3800 if (writeback && (Rn == Rt || Rn == Rt2)) 3801 Check(S, MCDisassembler::SoftFail); 3802 3803 // Writeback operand 3804 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3805 return MCDisassembler::Fail; 3806 // Rt 3807 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3808 return MCDisassembler::Fail; 3809 // Rt2 3810 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 // addr 3813 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 3816 return S; 3817 } 3818 3819 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 3820 uint64_t Address, const void *Decoder) { 3821 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 3822 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 3823 if (sign1 != sign2) return MCDisassembler::Fail; 3824 3825 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 3826 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 3827 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 3828 Val |= sign1 << 12; 3829 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 3830 3831 return MCDisassembler::Success; 3832 } 3833 3834