1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 EDInstInfo *getEDInfo() const; 55 private: 56 }; 57 58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59 class ThumbDisassembler : public MCDisassembler { 60 public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 EDInstInfo *getEDInfo() const; 80 private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84 }; 85 } 86 87 static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 return false; 100 } 101 102 103 // Forward declare these because the autogenerated code will reference them. 104 // Definitions are further down. 105 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128 129 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 142 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 147 unsigned Insn, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 159 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 160 unsigned Insn, 161 uint64_t Adddress, 162 const void *Decoder); 163 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 250 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 311 312 #include "ARMGenDisassemblerTables.inc" 313 #include "ARMGenInstrInfo.inc" 314 #include "ARMGenEDInfo.inc" 315 316 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 317 return new ARMDisassembler(STI); 318 } 319 320 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 321 return new ThumbDisassembler(STI); 322 } 323 324 EDInstInfo *ARMDisassembler::getEDInfo() const { 325 return instInfoARM; 326 } 327 328 EDInstInfo *ThumbDisassembler::getEDInfo() const { 329 return instInfoARM; 330 } 331 332 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 333 const MemoryObject &Region, 334 uint64_t Address, 335 raw_ostream &os, 336 raw_ostream &cs) const { 337 uint8_t bytes[4]; 338 339 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 340 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 341 342 // We want to read exactly 4 bytes of data. 343 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 344 Size = 0; 345 return MCDisassembler::Fail; 346 } 347 348 // Encoded as a small-endian 32-bit word in the stream. 349 uint32_t insn = (bytes[3] << 24) | 350 (bytes[2] << 16) | 351 (bytes[1] << 8) | 352 (bytes[0] << 0); 353 354 // Calling the auto-generated decoder function. 355 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 356 if (result != MCDisassembler::Fail) { 357 Size = 4; 358 return result; 359 } 360 361 // VFP and NEON instructions, similarly, are shared between ARM 362 // and Thumb modes. 363 MI.clear(); 364 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 365 if (result != MCDisassembler::Fail) { 366 Size = 4; 367 return result; 368 } 369 370 MI.clear(); 371 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 372 if (result != MCDisassembler::Fail) { 373 Size = 4; 374 // Add a fake predicate operand, because we share these instruction 375 // definitions with Thumb2 where these instructions are predicable. 376 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 377 return MCDisassembler::Fail; 378 return result; 379 } 380 381 MI.clear(); 382 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 // Add a fake predicate operand, because we share these instruction 386 // definitions with Thumb2 where these instructions are predicable. 387 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 388 return MCDisassembler::Fail; 389 return result; 390 } 391 392 MI.clear(); 393 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 394 if (result != MCDisassembler::Fail) { 395 Size = 4; 396 // Add a fake predicate operand, because we share these instruction 397 // definitions with Thumb2 where these instructions are predicable. 398 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 399 return MCDisassembler::Fail; 400 return result; 401 } 402 403 MI.clear(); 404 405 Size = 0; 406 return MCDisassembler::Fail; 407 } 408 409 namespace llvm { 410 extern MCInstrDesc ARMInsts[]; 411 } 412 413 // Thumb1 instructions don't have explicit S bits. Rather, they 414 // implicitly set CPSR. Since it's not represented in the encoding, the 415 // auto-generated decoder won't inject the CPSR operand. We need to fix 416 // that as a post-pass. 417 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 418 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 419 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 420 MCInst::iterator I = MI.begin(); 421 for (unsigned i = 0; i < NumOps; ++i, ++I) { 422 if (I == MI.end()) break; 423 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 424 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 426 return; 427 } 428 } 429 430 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 431 } 432 433 // Most Thumb instructions don't have explicit predicates in the 434 // encoding, but rather get their predicates from IT context. We need 435 // to fix up the predicate operands using this context information as a 436 // post-pass. 437 MCDisassembler::DecodeStatus 438 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 439 MCDisassembler::DecodeStatus S = Success; 440 441 // A few instructions actually have predicates encoded in them. Don't 442 // try to overwrite it if we're seeing one of those. 443 switch (MI.getOpcode()) { 444 case ARM::tBcc: 445 case ARM::t2Bcc: 446 case ARM::tCBZ: 447 case ARM::tCBNZ: 448 case ARM::tCPS: 449 case ARM::t2CPS3p: 450 case ARM::t2CPS2p: 451 case ARM::t2CPS1p: 452 case ARM::tMOVSr: 453 // Some instructions (mostly conditional branches) are not 454 // allowed in IT blocks. 455 if (!ITBlock.empty()) 456 S = SoftFail; 457 else 458 return Success; 459 break; 460 case ARM::tB: 461 case ARM::t2B: 462 case ARM::t2TBB: 463 case ARM::t2TBH: 464 // Some instructions (mostly unconditional branches) can 465 // only appears at the end of, or outside of, an IT. 466 if (ITBlock.size() > 1) 467 S = SoftFail; 468 break; 469 default: 470 break; 471 } 472 473 // If we're in an IT block, base the predicate on that. Otherwise, 474 // assume a predicate of AL. 475 unsigned CC; 476 if (!ITBlock.empty()) { 477 CC = ITBlock.back(); 478 if (CC == 0xF) 479 CC = ARMCC::AL; 480 ITBlock.pop_back(); 481 } else 482 CC = ARMCC::AL; 483 484 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 485 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 486 MCInst::iterator I = MI.begin(); 487 for (unsigned i = 0; i < NumOps; ++i, ++I) { 488 if (I == MI.end()) break; 489 if (OpInfo[i].isPredicate()) { 490 I = MI.insert(I, MCOperand::CreateImm(CC)); 491 ++I; 492 if (CC == ARMCC::AL) 493 MI.insert(I, MCOperand::CreateReg(0)); 494 else 495 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 496 return S; 497 } 498 } 499 500 I = MI.insert(I, MCOperand::CreateImm(CC)); 501 ++I; 502 if (CC == ARMCC::AL) 503 MI.insert(I, MCOperand::CreateReg(0)); 504 else 505 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 506 507 return S; 508 } 509 510 // Thumb VFP instructions are a special case. Because we share their 511 // encodings between ARM and Thumb modes, and they are predicable in ARM 512 // mode, the auto-generated decoder will give them an (incorrect) 513 // predicate operand. We need to rewrite these operands based on the IT 514 // context as a post-pass. 515 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 516 unsigned CC; 517 if (!ITBlock.empty()) { 518 CC = ITBlock.back(); 519 ITBlock.pop_back(); 520 } else 521 CC = ARMCC::AL; 522 523 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 524 MCInst::iterator I = MI.begin(); 525 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 526 for (unsigned i = 0; i < NumOps; ++i, ++I) { 527 if (OpInfo[i].isPredicate() ) { 528 I->setImm(CC); 529 ++I; 530 if (CC == ARMCC::AL) 531 I->setReg(0); 532 else 533 I->setReg(ARM::CPSR); 534 return; 535 } 536 } 537 } 538 539 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 540 const MemoryObject &Region, 541 uint64_t Address, 542 raw_ostream &os, 543 raw_ostream &cs) const { 544 uint8_t bytes[4]; 545 546 assert((STI.getFeatureBits() & ARM::ModeThumb) && 547 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 548 549 // We want to read exactly 2 bytes of data. 550 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 551 Size = 0; 552 return MCDisassembler::Fail; 553 } 554 555 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 556 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 557 if (result != MCDisassembler::Fail) { 558 Size = 2; 559 Check(result, AddThumbPredicate(MI)); 560 return result; 561 } 562 563 MI.clear(); 564 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 565 if (result) { 566 Size = 2; 567 bool InITBlock = !ITBlock.empty(); 568 Check(result, AddThumbPredicate(MI)); 569 AddThumb1SBit(MI, InITBlock); 570 return result; 571 } 572 573 MI.clear(); 574 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 575 if (result != MCDisassembler::Fail) { 576 Size = 2; 577 Check(result, AddThumbPredicate(MI)); 578 579 // If we find an IT instruction, we need to parse its condition 580 // code and mask operands so that we can apply them correctly 581 // to the subsequent instructions. 582 if (MI.getOpcode() == ARM::t2IT) { 583 // Nested IT blocks are UNPREDICTABLE. 584 if (!ITBlock.empty()) 585 return MCDisassembler::SoftFail; 586 587 // (3 - the number of trailing zeros) is the number of then / else. 588 unsigned firstcond = MI.getOperand(0).getImm(); 589 unsigned Mask = MI.getOperand(1).getImm(); 590 unsigned CondBit0 = Mask >> 4 & 1; 591 unsigned NumTZ = CountTrailingZeros_32(Mask); 592 assert(NumTZ <= 3 && "Invalid IT mask!"); 593 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 594 bool T = ((Mask >> Pos) & 1) == CondBit0; 595 if (T) 596 ITBlock.insert(ITBlock.begin(), firstcond); 597 else 598 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 599 } 600 601 ITBlock.push_back(firstcond); 602 } 603 604 return result; 605 } 606 607 // We want to read exactly 4 bytes of data. 608 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 609 Size = 0; 610 return MCDisassembler::Fail; 611 } 612 613 uint32_t insn32 = (bytes[3] << 8) | 614 (bytes[2] << 0) | 615 (bytes[1] << 24) | 616 (bytes[0] << 16); 617 MI.clear(); 618 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 619 if (result != MCDisassembler::Fail) { 620 Size = 4; 621 bool InITBlock = ITBlock.size(); 622 Check(result, AddThumbPredicate(MI)); 623 AddThumb1SBit(MI, InITBlock); 624 return result; 625 } 626 627 MI.clear(); 628 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 629 if (result != MCDisassembler::Fail) { 630 Size = 4; 631 Check(result, AddThumbPredicate(MI)); 632 return result; 633 } 634 635 MI.clear(); 636 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 637 if (result != MCDisassembler::Fail) { 638 Size = 4; 639 UpdateThumbVFPPredicate(MI); 640 return result; 641 } 642 643 MI.clear(); 644 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 645 if (result != MCDisassembler::Fail) { 646 Size = 4; 647 Check(result, AddThumbPredicate(MI)); 648 return result; 649 } 650 651 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 652 MI.clear(); 653 uint32_t NEONLdStInsn = insn32; 654 NEONLdStInsn &= 0xF0FFFFFF; 655 NEONLdStInsn |= 0x04000000; 656 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 657 if (result != MCDisassembler::Fail) { 658 Size = 4; 659 Check(result, AddThumbPredicate(MI)); 660 return result; 661 } 662 } 663 664 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 665 MI.clear(); 666 uint32_t NEONDataInsn = insn32; 667 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 668 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 669 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 670 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 671 if (result != MCDisassembler::Fail) { 672 Size = 4; 673 Check(result, AddThumbPredicate(MI)); 674 return result; 675 } 676 } 677 678 Size = 0; 679 return MCDisassembler::Fail; 680 } 681 682 683 extern "C" void LLVMInitializeARMDisassembler() { 684 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 685 createARMDisassembler); 686 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 687 createThumbDisassembler); 688 } 689 690 static const unsigned GPRDecoderTable[] = { 691 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 692 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 693 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 694 ARM::R12, ARM::SP, ARM::LR, ARM::PC 695 }; 696 697 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 698 uint64_t Address, const void *Decoder) { 699 if (RegNo > 15) 700 return MCDisassembler::Fail; 701 702 unsigned Register = GPRDecoderTable[RegNo]; 703 Inst.addOperand(MCOperand::CreateReg(Register)); 704 return MCDisassembler::Success; 705 } 706 707 static DecodeStatus 708 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 709 uint64_t Address, const void *Decoder) { 710 if (RegNo == 15) return MCDisassembler::Fail; 711 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 712 } 713 714 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 715 uint64_t Address, const void *Decoder) { 716 if (RegNo > 7) 717 return MCDisassembler::Fail; 718 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 719 } 720 721 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 722 uint64_t Address, const void *Decoder) { 723 unsigned Register = 0; 724 switch (RegNo) { 725 case 0: 726 Register = ARM::R0; 727 break; 728 case 1: 729 Register = ARM::R1; 730 break; 731 case 2: 732 Register = ARM::R2; 733 break; 734 case 3: 735 Register = ARM::R3; 736 break; 737 case 9: 738 Register = ARM::R9; 739 break; 740 case 12: 741 Register = ARM::R12; 742 break; 743 default: 744 return MCDisassembler::Fail; 745 } 746 747 Inst.addOperand(MCOperand::CreateReg(Register)); 748 return MCDisassembler::Success; 749 } 750 751 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 752 uint64_t Address, const void *Decoder) { 753 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 754 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 755 } 756 757 static const unsigned SPRDecoderTable[] = { 758 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 759 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 760 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 761 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 762 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 763 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 764 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 765 ARM::S28, ARM::S29, ARM::S30, ARM::S31 766 }; 767 768 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 769 uint64_t Address, const void *Decoder) { 770 if (RegNo > 31) 771 return MCDisassembler::Fail; 772 773 unsigned Register = SPRDecoderTable[RegNo]; 774 Inst.addOperand(MCOperand::CreateReg(Register)); 775 return MCDisassembler::Success; 776 } 777 778 static const unsigned DPRDecoderTable[] = { 779 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 780 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 781 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 782 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 783 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 784 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 785 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 786 ARM::D28, ARM::D29, ARM::D30, ARM::D31 787 }; 788 789 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 790 uint64_t Address, const void *Decoder) { 791 if (RegNo > 31) 792 return MCDisassembler::Fail; 793 794 unsigned Register = DPRDecoderTable[RegNo]; 795 Inst.addOperand(MCOperand::CreateReg(Register)); 796 return MCDisassembler::Success; 797 } 798 799 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 800 uint64_t Address, const void *Decoder) { 801 if (RegNo > 7) 802 return MCDisassembler::Fail; 803 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 804 } 805 806 static DecodeStatus 807 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 808 uint64_t Address, const void *Decoder) { 809 if (RegNo > 15) 810 return MCDisassembler::Fail; 811 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 812 } 813 814 static const unsigned QPRDecoderTable[] = { 815 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 816 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 817 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 818 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 819 }; 820 821 822 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 823 uint64_t Address, const void *Decoder) { 824 if (RegNo > 31) 825 return MCDisassembler::Fail; 826 RegNo >>= 1; 827 828 unsigned Register = QPRDecoderTable[RegNo]; 829 Inst.addOperand(MCOperand::CreateReg(Register)); 830 return MCDisassembler::Success; 831 } 832 833 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 834 uint64_t Address, const void *Decoder) { 835 if (Val == 0xF) return MCDisassembler::Fail; 836 // AL predicate is not allowed on Thumb1 branches. 837 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 838 return MCDisassembler::Fail; 839 Inst.addOperand(MCOperand::CreateImm(Val)); 840 if (Val == ARMCC::AL) { 841 Inst.addOperand(MCOperand::CreateReg(0)); 842 } else 843 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 844 return MCDisassembler::Success; 845 } 846 847 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 848 uint64_t Address, const void *Decoder) { 849 if (Val) 850 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 851 else 852 Inst.addOperand(MCOperand::CreateReg(0)); 853 return MCDisassembler::Success; 854 } 855 856 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 857 uint64_t Address, const void *Decoder) { 858 uint32_t imm = Val & 0xFF; 859 uint32_t rot = (Val & 0xF00) >> 7; 860 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 861 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 862 return MCDisassembler::Success; 863 } 864 865 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 866 uint64_t Address, const void *Decoder) { 867 DecodeStatus S = MCDisassembler::Success; 868 869 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 870 unsigned type = fieldFromInstruction32(Val, 5, 2); 871 unsigned imm = fieldFromInstruction32(Val, 7, 5); 872 873 // Register-immediate 874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 875 return MCDisassembler::Fail; 876 877 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 878 switch (type) { 879 case 0: 880 Shift = ARM_AM::lsl; 881 break; 882 case 1: 883 Shift = ARM_AM::lsr; 884 break; 885 case 2: 886 Shift = ARM_AM::asr; 887 break; 888 case 3: 889 Shift = ARM_AM::ror; 890 break; 891 } 892 893 if (Shift == ARM_AM::ror && imm == 0) 894 Shift = ARM_AM::rrx; 895 896 unsigned Op = Shift | (imm << 3); 897 Inst.addOperand(MCOperand::CreateImm(Op)); 898 899 return S; 900 } 901 902 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 903 uint64_t Address, const void *Decoder) { 904 DecodeStatus S = MCDisassembler::Success; 905 906 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 907 unsigned type = fieldFromInstruction32(Val, 5, 2); 908 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 909 910 // Register-register 911 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 912 return MCDisassembler::Fail; 913 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 914 return MCDisassembler::Fail; 915 916 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 917 switch (type) { 918 case 0: 919 Shift = ARM_AM::lsl; 920 break; 921 case 1: 922 Shift = ARM_AM::lsr; 923 break; 924 case 2: 925 Shift = ARM_AM::asr; 926 break; 927 case 3: 928 Shift = ARM_AM::ror; 929 break; 930 } 931 932 Inst.addOperand(MCOperand::CreateImm(Shift)); 933 934 return S; 935 } 936 937 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 938 uint64_t Address, const void *Decoder) { 939 DecodeStatus S = MCDisassembler::Success; 940 941 bool writebackLoad = false; 942 unsigned writebackReg = 0; 943 switch (Inst.getOpcode()) { 944 default: 945 break; 946 case ARM::LDMIA_UPD: 947 case ARM::LDMDB_UPD: 948 case ARM::LDMIB_UPD: 949 case ARM::LDMDA_UPD: 950 case ARM::t2LDMIA_UPD: 951 case ARM::t2LDMDB_UPD: 952 writebackLoad = true; 953 writebackReg = Inst.getOperand(0).getReg(); 954 break; 955 } 956 957 // Empty register lists are not allowed. 958 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 959 for (unsigned i = 0; i < 16; ++i) { 960 if (Val & (1 << i)) { 961 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 962 return MCDisassembler::Fail; 963 // Writeback not allowed if Rn is in the target list. 964 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 965 Check(S, MCDisassembler::SoftFail); 966 } 967 } 968 969 return S; 970 } 971 972 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 973 uint64_t Address, const void *Decoder) { 974 DecodeStatus S = MCDisassembler::Success; 975 976 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 977 unsigned regs = Val & 0xFF; 978 979 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 980 return MCDisassembler::Fail; 981 for (unsigned i = 0; i < (regs - 1); ++i) { 982 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 983 return MCDisassembler::Fail; 984 } 985 986 return S; 987 } 988 989 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 990 uint64_t Address, const void *Decoder) { 991 DecodeStatus S = MCDisassembler::Success; 992 993 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 994 unsigned regs = (Val & 0xFF) / 2; 995 996 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 997 return MCDisassembler::Fail; 998 for (unsigned i = 0; i < (regs - 1); ++i) { 999 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1000 return MCDisassembler::Fail; 1001 } 1002 1003 return S; 1004 } 1005 1006 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1007 uint64_t Address, const void *Decoder) { 1008 // This operand encodes a mask of contiguous zeros between a specified MSB 1009 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1010 // the mask of all bits LSB-and-lower, and then xor them to create 1011 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1012 // create the final mask. 1013 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1014 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1015 1016 DecodeStatus S = MCDisassembler::Success; 1017 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1018 1019 uint32_t msb_mask = 0xFFFFFFFF; 1020 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1021 uint32_t lsb_mask = (1U << lsb) - 1; 1022 1023 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1024 return S; 1025 } 1026 1027 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1028 uint64_t Address, const void *Decoder) { 1029 DecodeStatus S = MCDisassembler::Success; 1030 1031 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1032 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1033 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1034 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1035 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1036 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1037 1038 switch (Inst.getOpcode()) { 1039 case ARM::LDC_OFFSET: 1040 case ARM::LDC_PRE: 1041 case ARM::LDC_POST: 1042 case ARM::LDC_OPTION: 1043 case ARM::LDCL_OFFSET: 1044 case ARM::LDCL_PRE: 1045 case ARM::LDCL_POST: 1046 case ARM::LDCL_OPTION: 1047 case ARM::STC_OFFSET: 1048 case ARM::STC_PRE: 1049 case ARM::STC_POST: 1050 case ARM::STC_OPTION: 1051 case ARM::STCL_OFFSET: 1052 case ARM::STCL_PRE: 1053 case ARM::STCL_POST: 1054 case ARM::STCL_OPTION: 1055 case ARM::t2LDC_OFFSET: 1056 case ARM::t2LDC_PRE: 1057 case ARM::t2LDC_POST: 1058 case ARM::t2LDC_OPTION: 1059 case ARM::t2LDCL_OFFSET: 1060 case ARM::t2LDCL_PRE: 1061 case ARM::t2LDCL_POST: 1062 case ARM::t2LDCL_OPTION: 1063 case ARM::t2STC_OFFSET: 1064 case ARM::t2STC_PRE: 1065 case ARM::t2STC_POST: 1066 case ARM::t2STC_OPTION: 1067 case ARM::t2STCL_OFFSET: 1068 case ARM::t2STCL_PRE: 1069 case ARM::t2STCL_POST: 1070 case ARM::t2STCL_OPTION: 1071 if (coproc == 0xA || coproc == 0xB) 1072 return MCDisassembler::Fail; 1073 break; 1074 default: 1075 break; 1076 } 1077 1078 Inst.addOperand(MCOperand::CreateImm(coproc)); 1079 Inst.addOperand(MCOperand::CreateImm(CRd)); 1080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1081 return MCDisassembler::Fail; 1082 switch (Inst.getOpcode()) { 1083 case ARM::LDC_OPTION: 1084 case ARM::LDCL_OPTION: 1085 case ARM::LDC2_OPTION: 1086 case ARM::LDC2L_OPTION: 1087 case ARM::STC_OPTION: 1088 case ARM::STCL_OPTION: 1089 case ARM::STC2_OPTION: 1090 case ARM::STC2L_OPTION: 1091 case ARM::LDCL_POST: 1092 case ARM::STCL_POST: 1093 case ARM::LDC2L_POST: 1094 case ARM::STC2L_POST: 1095 case ARM::t2LDC_OPTION: 1096 case ARM::t2LDCL_OPTION: 1097 case ARM::t2STC_OPTION: 1098 case ARM::t2STCL_OPTION: 1099 case ARM::t2LDCL_POST: 1100 case ARM::t2STCL_POST: 1101 break; 1102 default: 1103 Inst.addOperand(MCOperand::CreateReg(0)); 1104 break; 1105 } 1106 1107 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1108 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1109 1110 bool writeback = (P == 0) || (W == 1); 1111 unsigned idx_mode = 0; 1112 if (P && writeback) 1113 idx_mode = ARMII::IndexModePre; 1114 else if (!P && writeback) 1115 idx_mode = ARMII::IndexModePost; 1116 1117 switch (Inst.getOpcode()) { 1118 case ARM::LDCL_POST: 1119 case ARM::STCL_POST: 1120 case ARM::t2LDCL_POST: 1121 case ARM::t2STCL_POST: 1122 case ARM::LDC2L_POST: 1123 case ARM::STC2L_POST: 1124 imm |= U << 8; 1125 case ARM::LDC_OPTION: 1126 case ARM::LDCL_OPTION: 1127 case ARM::LDC2_OPTION: 1128 case ARM::LDC2L_OPTION: 1129 case ARM::STC_OPTION: 1130 case ARM::STCL_OPTION: 1131 case ARM::STC2_OPTION: 1132 case ARM::STC2L_OPTION: 1133 case ARM::t2LDC_OPTION: 1134 case ARM::t2LDCL_OPTION: 1135 case ARM::t2STC_OPTION: 1136 case ARM::t2STCL_OPTION: 1137 Inst.addOperand(MCOperand::CreateImm(imm)); 1138 break; 1139 default: 1140 if (U) 1141 Inst.addOperand(MCOperand::CreateImm( 1142 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1143 else 1144 Inst.addOperand(MCOperand::CreateImm( 1145 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1146 break; 1147 } 1148 1149 switch (Inst.getOpcode()) { 1150 case ARM::LDC_OFFSET: 1151 case ARM::LDC_PRE: 1152 case ARM::LDC_POST: 1153 case ARM::LDC_OPTION: 1154 case ARM::LDCL_OFFSET: 1155 case ARM::LDCL_PRE: 1156 case ARM::LDCL_POST: 1157 case ARM::LDCL_OPTION: 1158 case ARM::STC_OFFSET: 1159 case ARM::STC_PRE: 1160 case ARM::STC_POST: 1161 case ARM::STC_OPTION: 1162 case ARM::STCL_OFFSET: 1163 case ARM::STCL_PRE: 1164 case ARM::STCL_POST: 1165 case ARM::STCL_OPTION: 1166 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1167 return MCDisassembler::Fail; 1168 break; 1169 default: 1170 break; 1171 } 1172 1173 return S; 1174 } 1175 1176 static DecodeStatus 1177 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1178 uint64_t Address, const void *Decoder) { 1179 DecodeStatus S = MCDisassembler::Success; 1180 1181 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1182 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1183 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1184 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1185 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1186 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1187 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1188 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1189 1190 // On stores, the writeback operand precedes Rt. 1191 switch (Inst.getOpcode()) { 1192 case ARM::STR_POST_IMM: 1193 case ARM::STR_POST_REG: 1194 case ARM::STRB_POST_IMM: 1195 case ARM::STRB_POST_REG: 1196 case ARM::STRT_POST_REG: 1197 case ARM::STRT_POST_IMM: 1198 case ARM::STRBT_POST_REG: 1199 case ARM::STRBT_POST_IMM: 1200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1201 return MCDisassembler::Fail; 1202 break; 1203 default: 1204 break; 1205 } 1206 1207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1208 return MCDisassembler::Fail; 1209 1210 // On loads, the writeback operand comes after Rt. 1211 switch (Inst.getOpcode()) { 1212 case ARM::LDR_POST_IMM: 1213 case ARM::LDR_POST_REG: 1214 case ARM::LDRB_POST_IMM: 1215 case ARM::LDRB_POST_REG: 1216 case ARM::LDRBT_POST_REG: 1217 case ARM::LDRBT_POST_IMM: 1218 case ARM::LDRT_POST_REG: 1219 case ARM::LDRT_POST_IMM: 1220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1221 return MCDisassembler::Fail; 1222 break; 1223 default: 1224 break; 1225 } 1226 1227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1228 return MCDisassembler::Fail; 1229 1230 ARM_AM::AddrOpc Op = ARM_AM::add; 1231 if (!fieldFromInstruction32(Insn, 23, 1)) 1232 Op = ARM_AM::sub; 1233 1234 bool writeback = (P == 0) || (W == 1); 1235 unsigned idx_mode = 0; 1236 if (P && writeback) 1237 idx_mode = ARMII::IndexModePre; 1238 else if (!P && writeback) 1239 idx_mode = ARMII::IndexModePost; 1240 1241 if (writeback && (Rn == 15 || Rn == Rt)) 1242 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1243 1244 if (reg) { 1245 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1246 return MCDisassembler::Fail; 1247 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1248 switch( fieldFromInstruction32(Insn, 5, 2)) { 1249 case 0: 1250 Opc = ARM_AM::lsl; 1251 break; 1252 case 1: 1253 Opc = ARM_AM::lsr; 1254 break; 1255 case 2: 1256 Opc = ARM_AM::asr; 1257 break; 1258 case 3: 1259 Opc = ARM_AM::ror; 1260 break; 1261 default: 1262 return MCDisassembler::Fail; 1263 } 1264 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1265 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1266 1267 Inst.addOperand(MCOperand::CreateImm(imm)); 1268 } else { 1269 Inst.addOperand(MCOperand::CreateReg(0)); 1270 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1271 Inst.addOperand(MCOperand::CreateImm(tmp)); 1272 } 1273 1274 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1275 return MCDisassembler::Fail; 1276 1277 return S; 1278 } 1279 1280 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1281 uint64_t Address, const void *Decoder) { 1282 DecodeStatus S = MCDisassembler::Success; 1283 1284 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1285 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1286 unsigned type = fieldFromInstruction32(Val, 5, 2); 1287 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1288 unsigned U = fieldFromInstruction32(Val, 12, 1); 1289 1290 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1291 switch (type) { 1292 case 0: 1293 ShOp = ARM_AM::lsl; 1294 break; 1295 case 1: 1296 ShOp = ARM_AM::lsr; 1297 break; 1298 case 2: 1299 ShOp = ARM_AM::asr; 1300 break; 1301 case 3: 1302 ShOp = ARM_AM::ror; 1303 break; 1304 } 1305 1306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1307 return MCDisassembler::Fail; 1308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1309 return MCDisassembler::Fail; 1310 unsigned shift; 1311 if (U) 1312 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1313 else 1314 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1315 Inst.addOperand(MCOperand::CreateImm(shift)); 1316 1317 return S; 1318 } 1319 1320 static DecodeStatus 1321 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1322 uint64_t Address, const void *Decoder) { 1323 DecodeStatus S = MCDisassembler::Success; 1324 1325 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1326 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1327 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1328 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1329 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1330 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1331 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1332 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1333 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1334 1335 bool writeback = (W == 1) | (P == 0); 1336 1337 // For {LD,ST}RD, Rt must be even, else undefined. 1338 switch (Inst.getOpcode()) { 1339 case ARM::STRD: 1340 case ARM::STRD_PRE: 1341 case ARM::STRD_POST: 1342 case ARM::LDRD: 1343 case ARM::LDRD_PRE: 1344 case ARM::LDRD_POST: 1345 if (Rt & 0x1) return MCDisassembler::Fail; 1346 break; 1347 default: 1348 break; 1349 } 1350 1351 if (writeback) { // Writeback 1352 if (P) 1353 U |= ARMII::IndexModePre << 9; 1354 else 1355 U |= ARMII::IndexModePost << 9; 1356 1357 // On stores, the writeback operand precedes Rt. 1358 switch (Inst.getOpcode()) { 1359 case ARM::STRD: 1360 case ARM::STRD_PRE: 1361 case ARM::STRD_POST: 1362 case ARM::STRH: 1363 case ARM::STRH_PRE: 1364 case ARM::STRH_POST: 1365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 } 1372 1373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1374 return MCDisassembler::Fail; 1375 switch (Inst.getOpcode()) { 1376 case ARM::STRD: 1377 case ARM::STRD_PRE: 1378 case ARM::STRD_POST: 1379 case ARM::LDRD: 1380 case ARM::LDRD_PRE: 1381 case ARM::LDRD_POST: 1382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1383 return MCDisassembler::Fail; 1384 break; 1385 default: 1386 break; 1387 } 1388 1389 if (writeback) { 1390 // On loads, the writeback operand comes after Rt. 1391 switch (Inst.getOpcode()) { 1392 case ARM::LDRD: 1393 case ARM::LDRD_PRE: 1394 case ARM::LDRD_POST: 1395 case ARM::LDRH: 1396 case ARM::LDRH_PRE: 1397 case ARM::LDRH_POST: 1398 case ARM::LDRSH: 1399 case ARM::LDRSH_PRE: 1400 case ARM::LDRSH_POST: 1401 case ARM::LDRSB: 1402 case ARM::LDRSB_PRE: 1403 case ARM::LDRSB_POST: 1404 case ARM::LDRHTr: 1405 case ARM::LDRSBTr: 1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 break; 1409 default: 1410 break; 1411 } 1412 } 1413 1414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1415 return MCDisassembler::Fail; 1416 1417 if (type) { 1418 Inst.addOperand(MCOperand::CreateReg(0)); 1419 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1420 } else { 1421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1422 return MCDisassembler::Fail; 1423 Inst.addOperand(MCOperand::CreateImm(U)); 1424 } 1425 1426 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1427 return MCDisassembler::Fail; 1428 1429 return S; 1430 } 1431 1432 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1433 uint64_t Address, const void *Decoder) { 1434 DecodeStatus S = MCDisassembler::Success; 1435 1436 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1437 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1438 1439 switch (mode) { 1440 case 0: 1441 mode = ARM_AM::da; 1442 break; 1443 case 1: 1444 mode = ARM_AM::ia; 1445 break; 1446 case 2: 1447 mode = ARM_AM::db; 1448 break; 1449 case 3: 1450 mode = ARM_AM::ib; 1451 break; 1452 } 1453 1454 Inst.addOperand(MCOperand::CreateImm(mode)); 1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1456 return MCDisassembler::Fail; 1457 1458 return S; 1459 } 1460 1461 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1462 unsigned Insn, 1463 uint64_t Address, const void *Decoder) { 1464 DecodeStatus S = MCDisassembler::Success; 1465 1466 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1467 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1468 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1469 1470 if (pred == 0xF) { 1471 switch (Inst.getOpcode()) { 1472 case ARM::LDMDA: 1473 Inst.setOpcode(ARM::RFEDA); 1474 break; 1475 case ARM::LDMDA_UPD: 1476 Inst.setOpcode(ARM::RFEDA_UPD); 1477 break; 1478 case ARM::LDMDB: 1479 Inst.setOpcode(ARM::RFEDB); 1480 break; 1481 case ARM::LDMDB_UPD: 1482 Inst.setOpcode(ARM::RFEDB_UPD); 1483 break; 1484 case ARM::LDMIA: 1485 Inst.setOpcode(ARM::RFEIA); 1486 break; 1487 case ARM::LDMIA_UPD: 1488 Inst.setOpcode(ARM::RFEIA_UPD); 1489 break; 1490 case ARM::LDMIB: 1491 Inst.setOpcode(ARM::RFEIB); 1492 break; 1493 case ARM::LDMIB_UPD: 1494 Inst.setOpcode(ARM::RFEIB_UPD); 1495 break; 1496 case ARM::STMDA: 1497 Inst.setOpcode(ARM::SRSDA); 1498 break; 1499 case ARM::STMDA_UPD: 1500 Inst.setOpcode(ARM::SRSDA_UPD); 1501 break; 1502 case ARM::STMDB: 1503 Inst.setOpcode(ARM::SRSDB); 1504 break; 1505 case ARM::STMDB_UPD: 1506 Inst.setOpcode(ARM::SRSDB_UPD); 1507 break; 1508 case ARM::STMIA: 1509 Inst.setOpcode(ARM::SRSIA); 1510 break; 1511 case ARM::STMIA_UPD: 1512 Inst.setOpcode(ARM::SRSIA_UPD); 1513 break; 1514 case ARM::STMIB: 1515 Inst.setOpcode(ARM::SRSIB); 1516 break; 1517 case ARM::STMIB_UPD: 1518 Inst.setOpcode(ARM::SRSIB_UPD); 1519 break; 1520 default: 1521 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1522 } 1523 1524 // For stores (which become SRS's, the only operand is the mode. 1525 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1526 Inst.addOperand( 1527 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1528 return S; 1529 } 1530 1531 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1532 } 1533 1534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1535 return MCDisassembler::Fail; 1536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1537 return MCDisassembler::Fail; // Tied 1538 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1539 return MCDisassembler::Fail; 1540 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1541 return MCDisassembler::Fail; 1542 1543 return S; 1544 } 1545 1546 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1547 uint64_t Address, const void *Decoder) { 1548 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1549 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1550 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1551 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1552 1553 DecodeStatus S = MCDisassembler::Success; 1554 1555 // imod == '01' --> UNPREDICTABLE 1556 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1557 // return failure here. The '01' imod value is unprintable, so there's 1558 // nothing useful we could do even if we returned UNPREDICTABLE. 1559 1560 if (imod == 1) return MCDisassembler::Fail; 1561 1562 if (imod && M) { 1563 Inst.setOpcode(ARM::CPS3p); 1564 Inst.addOperand(MCOperand::CreateImm(imod)); 1565 Inst.addOperand(MCOperand::CreateImm(iflags)); 1566 Inst.addOperand(MCOperand::CreateImm(mode)); 1567 } else if (imod && !M) { 1568 Inst.setOpcode(ARM::CPS2p); 1569 Inst.addOperand(MCOperand::CreateImm(imod)); 1570 Inst.addOperand(MCOperand::CreateImm(iflags)); 1571 if (mode) S = MCDisassembler::SoftFail; 1572 } else if (!imod && M) { 1573 Inst.setOpcode(ARM::CPS1p); 1574 Inst.addOperand(MCOperand::CreateImm(mode)); 1575 if (iflags) S = MCDisassembler::SoftFail; 1576 } else { 1577 // imod == '00' && M == '0' --> UNPREDICTABLE 1578 Inst.setOpcode(ARM::CPS1p); 1579 Inst.addOperand(MCOperand::CreateImm(mode)); 1580 S = MCDisassembler::SoftFail; 1581 } 1582 1583 return S; 1584 } 1585 1586 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1587 uint64_t Address, const void *Decoder) { 1588 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1589 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1590 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1591 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1592 1593 DecodeStatus S = MCDisassembler::Success; 1594 1595 // imod == '01' --> UNPREDICTABLE 1596 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1597 // return failure here. The '01' imod value is unprintable, so there's 1598 // nothing useful we could do even if we returned UNPREDICTABLE. 1599 1600 if (imod == 1) return MCDisassembler::Fail; 1601 1602 if (imod && M) { 1603 Inst.setOpcode(ARM::t2CPS3p); 1604 Inst.addOperand(MCOperand::CreateImm(imod)); 1605 Inst.addOperand(MCOperand::CreateImm(iflags)); 1606 Inst.addOperand(MCOperand::CreateImm(mode)); 1607 } else if (imod && !M) { 1608 Inst.setOpcode(ARM::t2CPS2p); 1609 Inst.addOperand(MCOperand::CreateImm(imod)); 1610 Inst.addOperand(MCOperand::CreateImm(iflags)); 1611 if (mode) S = MCDisassembler::SoftFail; 1612 } else if (!imod && M) { 1613 Inst.setOpcode(ARM::t2CPS1p); 1614 Inst.addOperand(MCOperand::CreateImm(mode)); 1615 if (iflags) S = MCDisassembler::SoftFail; 1616 } else { 1617 // imod == '00' && M == '0' --> UNPREDICTABLE 1618 Inst.setOpcode(ARM::t2CPS1p); 1619 Inst.addOperand(MCOperand::CreateImm(mode)); 1620 S = MCDisassembler::SoftFail; 1621 } 1622 1623 return S; 1624 } 1625 1626 1627 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1628 uint64_t Address, const void *Decoder) { 1629 DecodeStatus S = MCDisassembler::Success; 1630 1631 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1632 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1633 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1634 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1635 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1636 1637 if (pred == 0xF) 1638 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1639 1640 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1641 return MCDisassembler::Fail; 1642 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1643 return MCDisassembler::Fail; 1644 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1645 return MCDisassembler::Fail; 1646 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1647 return MCDisassembler::Fail; 1648 1649 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1650 return MCDisassembler::Fail; 1651 1652 return S; 1653 } 1654 1655 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1656 uint64_t Address, const void *Decoder) { 1657 DecodeStatus S = MCDisassembler::Success; 1658 1659 unsigned add = fieldFromInstruction32(Val, 12, 1); 1660 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1661 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1662 1663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1664 return MCDisassembler::Fail; 1665 1666 if (!add) imm *= -1; 1667 if (imm == 0 && !add) imm = INT32_MIN; 1668 Inst.addOperand(MCOperand::CreateImm(imm)); 1669 1670 return S; 1671 } 1672 1673 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1674 uint64_t Address, const void *Decoder) { 1675 DecodeStatus S = MCDisassembler::Success; 1676 1677 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1678 unsigned U = fieldFromInstruction32(Val, 8, 1); 1679 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1680 1681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1682 return MCDisassembler::Fail; 1683 1684 if (U) 1685 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1686 else 1687 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1688 1689 return S; 1690 } 1691 1692 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1693 uint64_t Address, const void *Decoder) { 1694 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1695 } 1696 1697 static DecodeStatus 1698 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1699 uint64_t Address, const void *Decoder) { 1700 DecodeStatus S = MCDisassembler::Success; 1701 1702 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1703 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1704 1705 if (pred == 0xF) { 1706 Inst.setOpcode(ARM::BLXi); 1707 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1708 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1709 return S; 1710 } 1711 1712 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1713 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1714 return MCDisassembler::Fail; 1715 1716 return S; 1717 } 1718 1719 1720 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1721 uint64_t Address, const void *Decoder) { 1722 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1723 return MCDisassembler::Success; 1724 } 1725 1726 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1727 uint64_t Address, const void *Decoder) { 1728 DecodeStatus S = MCDisassembler::Success; 1729 1730 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1731 unsigned align = fieldFromInstruction32(Val, 4, 2); 1732 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 if (!align) 1736 Inst.addOperand(MCOperand::CreateImm(0)); 1737 else 1738 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1739 1740 return S; 1741 } 1742 1743 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1744 uint64_t Address, const void *Decoder) { 1745 DecodeStatus S = MCDisassembler::Success; 1746 1747 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1748 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1749 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1750 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1751 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1752 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1753 1754 // First output register 1755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1756 return MCDisassembler::Fail; 1757 1758 // Second output register 1759 switch (Inst.getOpcode()) { 1760 case ARM::VLD1q8: 1761 case ARM::VLD1q16: 1762 case ARM::VLD1q32: 1763 case ARM::VLD1q64: 1764 case ARM::VLD1q8_UPD: 1765 case ARM::VLD1q16_UPD: 1766 case ARM::VLD1q32_UPD: 1767 case ARM::VLD1q64_UPD: 1768 case ARM::VLD1d8T: 1769 case ARM::VLD1d16T: 1770 case ARM::VLD1d32T: 1771 case ARM::VLD1d64T: 1772 case ARM::VLD1d8T_UPD: 1773 case ARM::VLD1d16T_UPD: 1774 case ARM::VLD1d32T_UPD: 1775 case ARM::VLD1d64T_UPD: 1776 case ARM::VLD1d8Q: 1777 case ARM::VLD1d16Q: 1778 case ARM::VLD1d32Q: 1779 case ARM::VLD1d64Q: 1780 case ARM::VLD1d8Q_UPD: 1781 case ARM::VLD1d16Q_UPD: 1782 case ARM::VLD1d32Q_UPD: 1783 case ARM::VLD1d64Q_UPD: 1784 case ARM::VLD2d8: 1785 case ARM::VLD2d16: 1786 case ARM::VLD2d32: 1787 case ARM::VLD2d8_UPD: 1788 case ARM::VLD2d16_UPD: 1789 case ARM::VLD2d32_UPD: 1790 case ARM::VLD2q8: 1791 case ARM::VLD2q16: 1792 case ARM::VLD2q32: 1793 case ARM::VLD2q8_UPD: 1794 case ARM::VLD2q16_UPD: 1795 case ARM::VLD2q32_UPD: 1796 case ARM::VLD3d8: 1797 case ARM::VLD3d16: 1798 case ARM::VLD3d32: 1799 case ARM::VLD3d8_UPD: 1800 case ARM::VLD3d16_UPD: 1801 case ARM::VLD3d32_UPD: 1802 case ARM::VLD4d8: 1803 case ARM::VLD4d16: 1804 case ARM::VLD4d32: 1805 case ARM::VLD4d8_UPD: 1806 case ARM::VLD4d16_UPD: 1807 case ARM::VLD4d32_UPD: 1808 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1809 return MCDisassembler::Fail; 1810 break; 1811 case ARM::VLD2b8: 1812 case ARM::VLD2b16: 1813 case ARM::VLD2b32: 1814 case ARM::VLD2b8_UPD: 1815 case ARM::VLD2b16_UPD: 1816 case ARM::VLD2b32_UPD: 1817 case ARM::VLD3q8: 1818 case ARM::VLD3q16: 1819 case ARM::VLD3q32: 1820 case ARM::VLD3q8_UPD: 1821 case ARM::VLD3q16_UPD: 1822 case ARM::VLD3q32_UPD: 1823 case ARM::VLD4q8: 1824 case ARM::VLD4q16: 1825 case ARM::VLD4q32: 1826 case ARM::VLD4q8_UPD: 1827 case ARM::VLD4q16_UPD: 1828 case ARM::VLD4q32_UPD: 1829 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1830 return MCDisassembler::Fail; 1831 default: 1832 break; 1833 } 1834 1835 // Third output register 1836 switch(Inst.getOpcode()) { 1837 case ARM::VLD1d8T: 1838 case ARM::VLD1d16T: 1839 case ARM::VLD1d32T: 1840 case ARM::VLD1d64T: 1841 case ARM::VLD1d8T_UPD: 1842 case ARM::VLD1d16T_UPD: 1843 case ARM::VLD1d32T_UPD: 1844 case ARM::VLD1d64T_UPD: 1845 case ARM::VLD1d8Q: 1846 case ARM::VLD1d16Q: 1847 case ARM::VLD1d32Q: 1848 case ARM::VLD1d64Q: 1849 case ARM::VLD1d8Q_UPD: 1850 case ARM::VLD1d16Q_UPD: 1851 case ARM::VLD1d32Q_UPD: 1852 case ARM::VLD1d64Q_UPD: 1853 case ARM::VLD2q8: 1854 case ARM::VLD2q16: 1855 case ARM::VLD2q32: 1856 case ARM::VLD2q8_UPD: 1857 case ARM::VLD2q16_UPD: 1858 case ARM::VLD2q32_UPD: 1859 case ARM::VLD3d8: 1860 case ARM::VLD3d16: 1861 case ARM::VLD3d32: 1862 case ARM::VLD3d8_UPD: 1863 case ARM::VLD3d16_UPD: 1864 case ARM::VLD3d32_UPD: 1865 case ARM::VLD4d8: 1866 case ARM::VLD4d16: 1867 case ARM::VLD4d32: 1868 case ARM::VLD4d8_UPD: 1869 case ARM::VLD4d16_UPD: 1870 case ARM::VLD4d32_UPD: 1871 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1872 return MCDisassembler::Fail; 1873 break; 1874 case ARM::VLD3q8: 1875 case ARM::VLD3q16: 1876 case ARM::VLD3q32: 1877 case ARM::VLD3q8_UPD: 1878 case ARM::VLD3q16_UPD: 1879 case ARM::VLD3q32_UPD: 1880 case ARM::VLD4q8: 1881 case ARM::VLD4q16: 1882 case ARM::VLD4q32: 1883 case ARM::VLD4q8_UPD: 1884 case ARM::VLD4q16_UPD: 1885 case ARM::VLD4q32_UPD: 1886 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1887 return MCDisassembler::Fail; 1888 break; 1889 default: 1890 break; 1891 } 1892 1893 // Fourth output register 1894 switch (Inst.getOpcode()) { 1895 case ARM::VLD1d8Q: 1896 case ARM::VLD1d16Q: 1897 case ARM::VLD1d32Q: 1898 case ARM::VLD1d64Q: 1899 case ARM::VLD1d8Q_UPD: 1900 case ARM::VLD1d16Q_UPD: 1901 case ARM::VLD1d32Q_UPD: 1902 case ARM::VLD1d64Q_UPD: 1903 case ARM::VLD2q8: 1904 case ARM::VLD2q16: 1905 case ARM::VLD2q32: 1906 case ARM::VLD2q8_UPD: 1907 case ARM::VLD2q16_UPD: 1908 case ARM::VLD2q32_UPD: 1909 case ARM::VLD4d8: 1910 case ARM::VLD4d16: 1911 case ARM::VLD4d32: 1912 case ARM::VLD4d8_UPD: 1913 case ARM::VLD4d16_UPD: 1914 case ARM::VLD4d32_UPD: 1915 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1916 return MCDisassembler::Fail; 1917 break; 1918 case ARM::VLD4q8: 1919 case ARM::VLD4q16: 1920 case ARM::VLD4q32: 1921 case ARM::VLD4q8_UPD: 1922 case ARM::VLD4q16_UPD: 1923 case ARM::VLD4q32_UPD: 1924 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1925 return MCDisassembler::Fail; 1926 break; 1927 default: 1928 break; 1929 } 1930 1931 // Writeback operand 1932 switch (Inst.getOpcode()) { 1933 case ARM::VLD1d8_UPD: 1934 case ARM::VLD1d16_UPD: 1935 case ARM::VLD1d32_UPD: 1936 case ARM::VLD1d64_UPD: 1937 case ARM::VLD1q8_UPD: 1938 case ARM::VLD1q16_UPD: 1939 case ARM::VLD1q32_UPD: 1940 case ARM::VLD1q64_UPD: 1941 case ARM::VLD1d8T_UPD: 1942 case ARM::VLD1d16T_UPD: 1943 case ARM::VLD1d32T_UPD: 1944 case ARM::VLD1d64T_UPD: 1945 case ARM::VLD1d8Q_UPD: 1946 case ARM::VLD1d16Q_UPD: 1947 case ARM::VLD1d32Q_UPD: 1948 case ARM::VLD1d64Q_UPD: 1949 case ARM::VLD2d8_UPD: 1950 case ARM::VLD2d16_UPD: 1951 case ARM::VLD2d32_UPD: 1952 case ARM::VLD2q8_UPD: 1953 case ARM::VLD2q16_UPD: 1954 case ARM::VLD2q32_UPD: 1955 case ARM::VLD2b8_UPD: 1956 case ARM::VLD2b16_UPD: 1957 case ARM::VLD2b32_UPD: 1958 case ARM::VLD3d8_UPD: 1959 case ARM::VLD3d16_UPD: 1960 case ARM::VLD3d32_UPD: 1961 case ARM::VLD3q8_UPD: 1962 case ARM::VLD3q16_UPD: 1963 case ARM::VLD3q32_UPD: 1964 case ARM::VLD4d8_UPD: 1965 case ARM::VLD4d16_UPD: 1966 case ARM::VLD4d32_UPD: 1967 case ARM::VLD4q8_UPD: 1968 case ARM::VLD4q16_UPD: 1969 case ARM::VLD4q32_UPD: 1970 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1971 return MCDisassembler::Fail; 1972 break; 1973 default: 1974 break; 1975 } 1976 1977 // AddrMode6 Base (register+alignment) 1978 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 1981 // AddrMode6 Offset (register) 1982 if (Rm == 0xD) 1983 Inst.addOperand(MCOperand::CreateReg(0)); 1984 else if (Rm != 0xF) { 1985 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1986 return MCDisassembler::Fail; 1987 } 1988 1989 return S; 1990 } 1991 1992 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1993 uint64_t Address, const void *Decoder) { 1994 DecodeStatus S = MCDisassembler::Success; 1995 1996 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1997 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1998 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1999 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2000 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2001 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2002 2003 // Writeback Operand 2004 switch (Inst.getOpcode()) { 2005 case ARM::VST1d8_UPD: 2006 case ARM::VST1d16_UPD: 2007 case ARM::VST1d32_UPD: 2008 case ARM::VST1d64_UPD: 2009 case ARM::VST1q8_UPD: 2010 case ARM::VST1q16_UPD: 2011 case ARM::VST1q32_UPD: 2012 case ARM::VST1q64_UPD: 2013 case ARM::VST1d8T_UPD: 2014 case ARM::VST1d16T_UPD: 2015 case ARM::VST1d32T_UPD: 2016 case ARM::VST1d64T_UPD: 2017 case ARM::VST1d8Q_UPD: 2018 case ARM::VST1d16Q_UPD: 2019 case ARM::VST1d32Q_UPD: 2020 case ARM::VST1d64Q_UPD: 2021 case ARM::VST2d8_UPD: 2022 case ARM::VST2d16_UPD: 2023 case ARM::VST2d32_UPD: 2024 case ARM::VST2q8_UPD: 2025 case ARM::VST2q16_UPD: 2026 case ARM::VST2q32_UPD: 2027 case ARM::VST2b8_UPD: 2028 case ARM::VST2b16_UPD: 2029 case ARM::VST2b32_UPD: 2030 case ARM::VST3d8_UPD: 2031 case ARM::VST3d16_UPD: 2032 case ARM::VST3d32_UPD: 2033 case ARM::VST3q8_UPD: 2034 case ARM::VST3q16_UPD: 2035 case ARM::VST3q32_UPD: 2036 case ARM::VST4d8_UPD: 2037 case ARM::VST4d16_UPD: 2038 case ARM::VST4d32_UPD: 2039 case ARM::VST4q8_UPD: 2040 case ARM::VST4q16_UPD: 2041 case ARM::VST4q32_UPD: 2042 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2043 return MCDisassembler::Fail; 2044 break; 2045 default: 2046 break; 2047 } 2048 2049 // AddrMode6 Base (register+alignment) 2050 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2051 return MCDisassembler::Fail; 2052 2053 // AddrMode6 Offset (register) 2054 if (Rm == 0xD) 2055 Inst.addOperand(MCOperand::CreateReg(0)); 2056 else if (Rm != 0xF) { 2057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2058 return MCDisassembler::Fail; 2059 } 2060 2061 // First input register 2062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2063 return MCDisassembler::Fail; 2064 2065 // Second input register 2066 switch (Inst.getOpcode()) { 2067 case ARM::VST1q8: 2068 case ARM::VST1q16: 2069 case ARM::VST1q32: 2070 case ARM::VST1q64: 2071 case ARM::VST1q8_UPD: 2072 case ARM::VST1q16_UPD: 2073 case ARM::VST1q32_UPD: 2074 case ARM::VST1q64_UPD: 2075 case ARM::VST1d8T: 2076 case ARM::VST1d16T: 2077 case ARM::VST1d32T: 2078 case ARM::VST1d64T: 2079 case ARM::VST1d8T_UPD: 2080 case ARM::VST1d16T_UPD: 2081 case ARM::VST1d32T_UPD: 2082 case ARM::VST1d64T_UPD: 2083 case ARM::VST1d8Q: 2084 case ARM::VST1d16Q: 2085 case ARM::VST1d32Q: 2086 case ARM::VST1d64Q: 2087 case ARM::VST1d8Q_UPD: 2088 case ARM::VST1d16Q_UPD: 2089 case ARM::VST1d32Q_UPD: 2090 case ARM::VST1d64Q_UPD: 2091 case ARM::VST2d8: 2092 case ARM::VST2d16: 2093 case ARM::VST2d32: 2094 case ARM::VST2d8_UPD: 2095 case ARM::VST2d16_UPD: 2096 case ARM::VST2d32_UPD: 2097 case ARM::VST2q8: 2098 case ARM::VST2q16: 2099 case ARM::VST2q32: 2100 case ARM::VST2q8_UPD: 2101 case ARM::VST2q16_UPD: 2102 case ARM::VST2q32_UPD: 2103 case ARM::VST3d8: 2104 case ARM::VST3d16: 2105 case ARM::VST3d32: 2106 case ARM::VST3d8_UPD: 2107 case ARM::VST3d16_UPD: 2108 case ARM::VST3d32_UPD: 2109 case ARM::VST4d8: 2110 case ARM::VST4d16: 2111 case ARM::VST4d32: 2112 case ARM::VST4d8_UPD: 2113 case ARM::VST4d16_UPD: 2114 case ARM::VST4d32_UPD: 2115 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2116 return MCDisassembler::Fail; 2117 break; 2118 case ARM::VST2b8: 2119 case ARM::VST2b16: 2120 case ARM::VST2b32: 2121 case ARM::VST2b8_UPD: 2122 case ARM::VST2b16_UPD: 2123 case ARM::VST2b32_UPD: 2124 case ARM::VST3q8: 2125 case ARM::VST3q16: 2126 case ARM::VST3q32: 2127 case ARM::VST3q8_UPD: 2128 case ARM::VST3q16_UPD: 2129 case ARM::VST3q32_UPD: 2130 case ARM::VST4q8: 2131 case ARM::VST4q16: 2132 case ARM::VST4q32: 2133 case ARM::VST4q8_UPD: 2134 case ARM::VST4q16_UPD: 2135 case ARM::VST4q32_UPD: 2136 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 break; 2139 default: 2140 break; 2141 } 2142 2143 // Third input register 2144 switch (Inst.getOpcode()) { 2145 case ARM::VST1d8T: 2146 case ARM::VST1d16T: 2147 case ARM::VST1d32T: 2148 case ARM::VST1d64T: 2149 case ARM::VST1d8T_UPD: 2150 case ARM::VST1d16T_UPD: 2151 case ARM::VST1d32T_UPD: 2152 case ARM::VST1d64T_UPD: 2153 case ARM::VST1d8Q: 2154 case ARM::VST1d16Q: 2155 case ARM::VST1d32Q: 2156 case ARM::VST1d64Q: 2157 case ARM::VST1d8Q_UPD: 2158 case ARM::VST1d16Q_UPD: 2159 case ARM::VST1d32Q_UPD: 2160 case ARM::VST1d64Q_UPD: 2161 case ARM::VST2q8: 2162 case ARM::VST2q16: 2163 case ARM::VST2q32: 2164 case ARM::VST2q8_UPD: 2165 case ARM::VST2q16_UPD: 2166 case ARM::VST2q32_UPD: 2167 case ARM::VST3d8: 2168 case ARM::VST3d16: 2169 case ARM::VST3d32: 2170 case ARM::VST3d8_UPD: 2171 case ARM::VST3d16_UPD: 2172 case ARM::VST3d32_UPD: 2173 case ARM::VST4d8: 2174 case ARM::VST4d16: 2175 case ARM::VST4d32: 2176 case ARM::VST4d8_UPD: 2177 case ARM::VST4d16_UPD: 2178 case ARM::VST4d32_UPD: 2179 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2180 return MCDisassembler::Fail; 2181 break; 2182 case ARM::VST3q8: 2183 case ARM::VST3q16: 2184 case ARM::VST3q32: 2185 case ARM::VST3q8_UPD: 2186 case ARM::VST3q16_UPD: 2187 case ARM::VST3q32_UPD: 2188 case ARM::VST4q8: 2189 case ARM::VST4q16: 2190 case ARM::VST4q32: 2191 case ARM::VST4q8_UPD: 2192 case ARM::VST4q16_UPD: 2193 case ARM::VST4q32_UPD: 2194 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2195 return MCDisassembler::Fail; 2196 break; 2197 default: 2198 break; 2199 } 2200 2201 // Fourth input register 2202 switch (Inst.getOpcode()) { 2203 case ARM::VST1d8Q: 2204 case ARM::VST1d16Q: 2205 case ARM::VST1d32Q: 2206 case ARM::VST1d64Q: 2207 case ARM::VST1d8Q_UPD: 2208 case ARM::VST1d16Q_UPD: 2209 case ARM::VST1d32Q_UPD: 2210 case ARM::VST1d64Q_UPD: 2211 case ARM::VST2q8: 2212 case ARM::VST2q16: 2213 case ARM::VST2q32: 2214 case ARM::VST2q8_UPD: 2215 case ARM::VST2q16_UPD: 2216 case ARM::VST2q32_UPD: 2217 case ARM::VST4d8: 2218 case ARM::VST4d16: 2219 case ARM::VST4d32: 2220 case ARM::VST4d8_UPD: 2221 case ARM::VST4d16_UPD: 2222 case ARM::VST4d32_UPD: 2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2224 return MCDisassembler::Fail; 2225 break; 2226 case ARM::VST4q8: 2227 case ARM::VST4q16: 2228 case ARM::VST4q32: 2229 case ARM::VST4q8_UPD: 2230 case ARM::VST4q16_UPD: 2231 case ARM::VST4q32_UPD: 2232 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2233 return MCDisassembler::Fail; 2234 break; 2235 default: 2236 break; 2237 } 2238 2239 return S; 2240 } 2241 2242 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2243 uint64_t Address, const void *Decoder) { 2244 DecodeStatus S = MCDisassembler::Success; 2245 2246 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2247 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2248 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2249 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2250 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2251 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2252 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2253 2254 align *= (1 << size); 2255 2256 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2257 return MCDisassembler::Fail; 2258 if (regs == 2) { 2259 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2260 return MCDisassembler::Fail; 2261 } 2262 if (Rm != 0xF) { 2263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2264 return MCDisassembler::Fail; 2265 } 2266 2267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2268 return MCDisassembler::Fail; 2269 Inst.addOperand(MCOperand::CreateImm(align)); 2270 2271 if (Rm == 0xD) 2272 Inst.addOperand(MCOperand::CreateReg(0)); 2273 else if (Rm != 0xF) { 2274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2275 return MCDisassembler::Fail; 2276 } 2277 2278 return S; 2279 } 2280 2281 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2282 uint64_t Address, const void *Decoder) { 2283 DecodeStatus S = MCDisassembler::Success; 2284 2285 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2286 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2287 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2288 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2289 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2290 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2291 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2292 align *= 2*size; 2293 2294 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2295 return MCDisassembler::Fail; 2296 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2297 return MCDisassembler::Fail; 2298 if (Rm != 0xF) { 2299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2300 return MCDisassembler::Fail; 2301 } 2302 2303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2304 return MCDisassembler::Fail; 2305 Inst.addOperand(MCOperand::CreateImm(align)); 2306 2307 if (Rm == 0xD) 2308 Inst.addOperand(MCOperand::CreateReg(0)); 2309 else if (Rm != 0xF) { 2310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2311 return MCDisassembler::Fail; 2312 } 2313 2314 return S; 2315 } 2316 2317 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2318 uint64_t Address, const void *Decoder) { 2319 DecodeStatus S = MCDisassembler::Success; 2320 2321 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2322 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2323 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2324 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2325 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2326 2327 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2328 return MCDisassembler::Fail; 2329 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2330 return MCDisassembler::Fail; 2331 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2332 return MCDisassembler::Fail; 2333 if (Rm != 0xF) { 2334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2335 return MCDisassembler::Fail; 2336 } 2337 2338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2339 return MCDisassembler::Fail; 2340 Inst.addOperand(MCOperand::CreateImm(0)); 2341 2342 if (Rm == 0xD) 2343 Inst.addOperand(MCOperand::CreateReg(0)); 2344 else if (Rm != 0xF) { 2345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2346 return MCDisassembler::Fail; 2347 } 2348 2349 return S; 2350 } 2351 2352 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2353 uint64_t Address, const void *Decoder) { 2354 DecodeStatus S = MCDisassembler::Success; 2355 2356 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2357 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2358 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2359 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2360 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2361 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2362 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2363 2364 if (size == 0x3) { 2365 size = 4; 2366 align = 16; 2367 } else { 2368 if (size == 2) { 2369 size = 1 << size; 2370 align *= 8; 2371 } else { 2372 size = 1 << size; 2373 align *= 4*size; 2374 } 2375 } 2376 2377 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2380 return MCDisassembler::Fail; 2381 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2382 return MCDisassembler::Fail; 2383 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 if (Rm != 0xF) { 2386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2387 return MCDisassembler::Fail; 2388 } 2389 2390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2391 return MCDisassembler::Fail; 2392 Inst.addOperand(MCOperand::CreateImm(align)); 2393 2394 if (Rm == 0xD) 2395 Inst.addOperand(MCOperand::CreateReg(0)); 2396 else if (Rm != 0xF) { 2397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2398 return MCDisassembler::Fail; 2399 } 2400 2401 return S; 2402 } 2403 2404 static DecodeStatus 2405 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2406 uint64_t Address, const void *Decoder) { 2407 DecodeStatus S = MCDisassembler::Success; 2408 2409 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2410 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2411 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2412 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2413 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2414 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2415 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2416 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2417 2418 if (Q) { 2419 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2420 return MCDisassembler::Fail; 2421 } else { 2422 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2423 return MCDisassembler::Fail; 2424 } 2425 2426 Inst.addOperand(MCOperand::CreateImm(imm)); 2427 2428 switch (Inst.getOpcode()) { 2429 case ARM::VORRiv4i16: 2430 case ARM::VORRiv2i32: 2431 case ARM::VBICiv4i16: 2432 case ARM::VBICiv2i32: 2433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2434 return MCDisassembler::Fail; 2435 break; 2436 case ARM::VORRiv8i16: 2437 case ARM::VORRiv4i32: 2438 case ARM::VBICiv8i16: 2439 case ARM::VBICiv4i32: 2440 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 break; 2443 default: 2444 break; 2445 } 2446 2447 return S; 2448 } 2449 2450 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2451 uint64_t Address, const void *Decoder) { 2452 DecodeStatus S = MCDisassembler::Success; 2453 2454 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2455 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2456 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2457 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2458 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2459 2460 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2463 return MCDisassembler::Fail; 2464 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2465 2466 return S; 2467 } 2468 2469 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2470 uint64_t Address, const void *Decoder) { 2471 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2472 return MCDisassembler::Success; 2473 } 2474 2475 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2476 uint64_t Address, const void *Decoder) { 2477 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2478 return MCDisassembler::Success; 2479 } 2480 2481 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2482 uint64_t Address, const void *Decoder) { 2483 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2484 return MCDisassembler::Success; 2485 } 2486 2487 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2488 uint64_t Address, const void *Decoder) { 2489 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2490 return MCDisassembler::Success; 2491 } 2492 2493 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2494 uint64_t Address, const void *Decoder) { 2495 DecodeStatus S = MCDisassembler::Success; 2496 2497 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2498 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2499 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2500 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2501 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2502 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2503 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2504 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2505 2506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2507 return MCDisassembler::Fail; 2508 if (op) { 2509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2510 return MCDisassembler::Fail; // Writeback 2511 } 2512 2513 for (unsigned i = 0; i < length; ++i) { 2514 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2515 return MCDisassembler::Fail; 2516 } 2517 2518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2519 return MCDisassembler::Fail; 2520 2521 return S; 2522 } 2523 2524 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2525 uint64_t Address, const void *Decoder) { 2526 // The immediate needs to be a fully instantiated float. However, the 2527 // auto-generated decoder is only able to fill in some of the bits 2528 // necessary. For instance, the 'b' bit is replicated multiple times, 2529 // and is even present in inverted form in one bit. We do a little 2530 // binary parsing here to fill in those missing bits, and then 2531 // reinterpret it all as a float. 2532 union { 2533 uint32_t integer; 2534 float fp; 2535 } fp_conv; 2536 2537 fp_conv.integer = Val; 2538 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2539 fp_conv.integer |= b << 26; 2540 fp_conv.integer |= b << 27; 2541 fp_conv.integer |= b << 28; 2542 fp_conv.integer |= b << 29; 2543 fp_conv.integer |= (~b & 0x1) << 30; 2544 2545 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2546 return MCDisassembler::Success; 2547 } 2548 2549 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2550 uint64_t Address, const void *Decoder) { 2551 DecodeStatus S = MCDisassembler::Success; 2552 2553 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2554 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2555 2556 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2557 return MCDisassembler::Fail; 2558 2559 switch(Inst.getOpcode()) { 2560 default: 2561 return MCDisassembler::Fail; 2562 case ARM::tADR: 2563 break; // tADR does not explicitly represent the PC as an operand. 2564 case ARM::tADDrSPi: 2565 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2566 break; 2567 } 2568 2569 Inst.addOperand(MCOperand::CreateImm(imm)); 2570 return S; 2571 } 2572 2573 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2574 uint64_t Address, const void *Decoder) { 2575 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2576 return MCDisassembler::Success; 2577 } 2578 2579 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2580 uint64_t Address, const void *Decoder) { 2581 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2582 return MCDisassembler::Success; 2583 } 2584 2585 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2586 uint64_t Address, const void *Decoder) { 2587 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2588 return MCDisassembler::Success; 2589 } 2590 2591 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2592 uint64_t Address, const void *Decoder) { 2593 DecodeStatus S = MCDisassembler::Success; 2594 2595 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2596 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2597 2598 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2599 return MCDisassembler::Fail; 2600 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2601 return MCDisassembler::Fail; 2602 2603 return S; 2604 } 2605 2606 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2607 uint64_t Address, const void *Decoder) { 2608 DecodeStatus S = MCDisassembler::Success; 2609 2610 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2611 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2612 2613 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2614 return MCDisassembler::Fail; 2615 Inst.addOperand(MCOperand::CreateImm(imm)); 2616 2617 return S; 2618 } 2619 2620 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2621 uint64_t Address, const void *Decoder) { 2622 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2623 2624 return MCDisassembler::Success; 2625 } 2626 2627 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2628 uint64_t Address, const void *Decoder) { 2629 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2630 Inst.addOperand(MCOperand::CreateImm(Val)); 2631 2632 return MCDisassembler::Success; 2633 } 2634 2635 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2636 uint64_t Address, const void *Decoder) { 2637 DecodeStatus S = MCDisassembler::Success; 2638 2639 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2640 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2641 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2642 2643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2644 return MCDisassembler::Fail; 2645 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2646 return MCDisassembler::Fail; 2647 Inst.addOperand(MCOperand::CreateImm(imm)); 2648 2649 return S; 2650 } 2651 2652 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2653 uint64_t Address, const void *Decoder) { 2654 DecodeStatus S = MCDisassembler::Success; 2655 2656 switch (Inst.getOpcode()) { 2657 case ARM::t2PLDs: 2658 case ARM::t2PLDWs: 2659 case ARM::t2PLIs: 2660 break; 2661 default: { 2662 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2664 return MCDisassembler::Fail; 2665 } 2666 } 2667 2668 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2669 if (Rn == 0xF) { 2670 switch (Inst.getOpcode()) { 2671 case ARM::t2LDRBs: 2672 Inst.setOpcode(ARM::t2LDRBpci); 2673 break; 2674 case ARM::t2LDRHs: 2675 Inst.setOpcode(ARM::t2LDRHpci); 2676 break; 2677 case ARM::t2LDRSHs: 2678 Inst.setOpcode(ARM::t2LDRSHpci); 2679 break; 2680 case ARM::t2LDRSBs: 2681 Inst.setOpcode(ARM::t2LDRSBpci); 2682 break; 2683 case ARM::t2PLDs: 2684 Inst.setOpcode(ARM::t2PLDi12); 2685 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2686 break; 2687 default: 2688 return MCDisassembler::Fail; 2689 } 2690 2691 int imm = fieldFromInstruction32(Insn, 0, 12); 2692 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2693 Inst.addOperand(MCOperand::CreateImm(imm)); 2694 2695 return S; 2696 } 2697 2698 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2699 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2700 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2701 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 2704 return S; 2705 } 2706 2707 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2708 uint64_t Address, const void *Decoder) { 2709 int imm = Val & 0xFF; 2710 if (!(Val & 0x100)) imm *= -1; 2711 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2712 2713 return MCDisassembler::Success; 2714 } 2715 2716 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2717 uint64_t Address, const void *Decoder) { 2718 DecodeStatus S = MCDisassembler::Success; 2719 2720 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2721 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2722 2723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2726 return MCDisassembler::Fail; 2727 2728 return S; 2729 } 2730 2731 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2732 uint64_t Address, const void *Decoder) { 2733 DecodeStatus S = MCDisassembler::Success; 2734 2735 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2736 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2737 2738 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2739 return MCDisassembler::Fail; 2740 2741 Inst.addOperand(MCOperand::CreateImm(imm)); 2742 2743 return S; 2744 } 2745 2746 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2747 uint64_t Address, const void *Decoder) { 2748 int imm = Val & 0xFF; 2749 if (Val == 0) 2750 imm = INT32_MIN; 2751 else if (!(Val & 0x100)) 2752 imm *= -1; 2753 Inst.addOperand(MCOperand::CreateImm(imm)); 2754 2755 return MCDisassembler::Success; 2756 } 2757 2758 2759 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2760 uint64_t Address, const void *Decoder) { 2761 DecodeStatus S = MCDisassembler::Success; 2762 2763 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2764 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2765 2766 // Some instructions always use an additive offset. 2767 switch (Inst.getOpcode()) { 2768 case ARM::t2LDRT: 2769 case ARM::t2LDRBT: 2770 case ARM::t2LDRHT: 2771 case ARM::t2LDRSBT: 2772 case ARM::t2LDRSHT: 2773 case ARM::t2STRT: 2774 case ARM::t2STRBT: 2775 case ARM::t2STRHT: 2776 imm |= 0x100; 2777 break; 2778 default: 2779 break; 2780 } 2781 2782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2783 return MCDisassembler::Fail; 2784 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2785 return MCDisassembler::Fail; 2786 2787 return S; 2788 } 2789 2790 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2791 uint64_t Address, const void *Decoder) { 2792 DecodeStatus S = MCDisassembler::Success; 2793 2794 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2795 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2796 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2797 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2798 addr |= Rn << 9; 2799 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2800 2801 if (!load) { 2802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2803 return MCDisassembler::Fail; 2804 } 2805 2806 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2807 return MCDisassembler::Fail; 2808 2809 if (load) { 2810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2811 return MCDisassembler::Fail; 2812 } 2813 2814 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2815 return MCDisassembler::Fail; 2816 2817 return S; 2818 } 2819 2820 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2821 uint64_t Address, const void *Decoder) { 2822 DecodeStatus S = MCDisassembler::Success; 2823 2824 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2825 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2826 2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2828 return MCDisassembler::Fail; 2829 Inst.addOperand(MCOperand::CreateImm(imm)); 2830 2831 return S; 2832 } 2833 2834 2835 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2836 uint64_t Address, const void *Decoder) { 2837 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2838 2839 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2840 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2841 Inst.addOperand(MCOperand::CreateImm(imm)); 2842 2843 return MCDisassembler::Success; 2844 } 2845 2846 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2847 uint64_t Address, const void *Decoder) { 2848 DecodeStatus S = MCDisassembler::Success; 2849 2850 if (Inst.getOpcode() == ARM::tADDrSP) { 2851 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2852 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2853 2854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2855 return MCDisassembler::Fail; 2856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2859 } else if (Inst.getOpcode() == ARM::tADDspr) { 2860 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2861 2862 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2863 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2865 return MCDisassembler::Fail; 2866 } 2867 2868 return S; 2869 } 2870 2871 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2872 uint64_t Address, const void *Decoder) { 2873 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2874 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2875 2876 Inst.addOperand(MCOperand::CreateImm(imod)); 2877 Inst.addOperand(MCOperand::CreateImm(flags)); 2878 2879 return MCDisassembler::Success; 2880 } 2881 2882 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2883 uint64_t Address, const void *Decoder) { 2884 DecodeStatus S = MCDisassembler::Success; 2885 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2886 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2887 2888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2889 return MCDisassembler::Fail; 2890 Inst.addOperand(MCOperand::CreateImm(add)); 2891 2892 return S; 2893 } 2894 2895 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2896 uint64_t Address, const void *Decoder) { 2897 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2898 return MCDisassembler::Success; 2899 } 2900 2901 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2902 uint64_t Address, const void *Decoder) { 2903 if (Val == 0xA || Val == 0xB) 2904 return MCDisassembler::Fail; 2905 2906 Inst.addOperand(MCOperand::CreateImm(Val)); 2907 return MCDisassembler::Success; 2908 } 2909 2910 static DecodeStatus 2911 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 2912 uint64_t Address, const void *Decoder) { 2913 DecodeStatus S = MCDisassembler::Success; 2914 2915 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2916 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2917 2918 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 2919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2922 return MCDisassembler::Fail; 2923 return S; 2924 } 2925 2926 static DecodeStatus 2927 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2928 uint64_t Address, const void *Decoder) { 2929 DecodeStatus S = MCDisassembler::Success; 2930 2931 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2932 if (pred == 0xE || pred == 0xF) { 2933 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2934 switch (opc) { 2935 default: 2936 return MCDisassembler::Fail; 2937 case 0xf3bf8f4: 2938 Inst.setOpcode(ARM::t2DSB); 2939 break; 2940 case 0xf3bf8f5: 2941 Inst.setOpcode(ARM::t2DMB); 2942 break; 2943 case 0xf3bf8f6: 2944 Inst.setOpcode(ARM::t2ISB); 2945 break; 2946 } 2947 2948 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2949 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2950 } 2951 2952 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2953 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2954 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2955 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2956 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2957 2958 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2959 return MCDisassembler::Fail; 2960 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 2963 return S; 2964 } 2965 2966 // Decode a shifted immediate operand. These basically consist 2967 // of an 8-bit value, and a 4-bit directive that specifies either 2968 // a splat operation or a rotation. 2969 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2970 uint64_t Address, const void *Decoder) { 2971 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2972 if (ctrl == 0) { 2973 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2974 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2975 switch (byte) { 2976 case 0: 2977 Inst.addOperand(MCOperand::CreateImm(imm)); 2978 break; 2979 case 1: 2980 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2981 break; 2982 case 2: 2983 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2984 break; 2985 case 3: 2986 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2987 (imm << 8) | imm)); 2988 break; 2989 } 2990 } else { 2991 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2992 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2993 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2994 Inst.addOperand(MCOperand::CreateImm(imm)); 2995 } 2996 2997 return MCDisassembler::Success; 2998 } 2999 3000 static DecodeStatus 3001 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3002 uint64_t Address, const void *Decoder){ 3003 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3004 return MCDisassembler::Success; 3005 } 3006 3007 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3008 uint64_t Address, const void *Decoder){ 3009 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3010 return MCDisassembler::Success; 3011 } 3012 3013 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3014 uint64_t Address, const void *Decoder) { 3015 switch (Val) { 3016 default: 3017 return MCDisassembler::Fail; 3018 case 0xF: // SY 3019 case 0xE: // ST 3020 case 0xB: // ISH 3021 case 0xA: // ISHST 3022 case 0x7: // NSH 3023 case 0x6: // NSHST 3024 case 0x3: // OSH 3025 case 0x2: // OSHST 3026 break; 3027 } 3028 3029 Inst.addOperand(MCOperand::CreateImm(Val)); 3030 return MCDisassembler::Success; 3031 } 3032 3033 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3034 uint64_t Address, const void *Decoder) { 3035 if (!Val) return MCDisassembler::Fail; 3036 Inst.addOperand(MCOperand::CreateImm(Val)); 3037 return MCDisassembler::Success; 3038 } 3039 3040 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3041 uint64_t Address, const void *Decoder) { 3042 DecodeStatus S = MCDisassembler::Success; 3043 3044 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3045 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3046 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3047 3048 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3049 3050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3053 return MCDisassembler::Fail; 3054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3055 return MCDisassembler::Fail; 3056 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3057 return MCDisassembler::Fail; 3058 3059 return S; 3060 } 3061 3062 3063 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3064 uint64_t Address, const void *Decoder){ 3065 DecodeStatus S = MCDisassembler::Success; 3066 3067 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3068 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3070 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3071 3072 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3073 return MCDisassembler::Fail; 3074 3075 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3076 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3077 3078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3079 return MCDisassembler::Fail; 3080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3081 return MCDisassembler::Fail; 3082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 3087 return S; 3088 } 3089 3090 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3091 uint64_t Address, const void *Decoder) { 3092 DecodeStatus S = MCDisassembler::Success; 3093 3094 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3095 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3096 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3097 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3098 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3099 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3100 3101 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3102 3103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3104 return MCDisassembler::Fail; 3105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3110 return MCDisassembler::Fail; 3111 3112 return S; 3113 } 3114 3115 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3116 uint64_t Address, const void *Decoder) { 3117 DecodeStatus S = MCDisassembler::Success; 3118 3119 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3120 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3121 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3122 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3123 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3124 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3125 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3126 3127 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3128 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3129 3130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3131 return MCDisassembler::Fail; 3132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3133 return MCDisassembler::Fail; 3134 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 3139 return S; 3140 } 3141 3142 3143 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3144 uint64_t Address, const void *Decoder) { 3145 DecodeStatus S = MCDisassembler::Success; 3146 3147 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3148 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3149 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3150 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3151 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3152 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3153 3154 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3155 3156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3157 return MCDisassembler::Fail; 3158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3159 return MCDisassembler::Fail; 3160 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3161 return MCDisassembler::Fail; 3162 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3163 return MCDisassembler::Fail; 3164 3165 return S; 3166 } 3167 3168 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3169 uint64_t Address, const void *Decoder) { 3170 DecodeStatus S = MCDisassembler::Success; 3171 3172 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3173 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3174 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3175 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3176 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3177 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3178 3179 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3180 3181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3184 return MCDisassembler::Fail; 3185 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3186 return MCDisassembler::Fail; 3187 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 3190 return S; 3191 } 3192 3193 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3194 uint64_t Address, const void *Decoder) { 3195 DecodeStatus S = MCDisassembler::Success; 3196 3197 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3198 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3199 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3200 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3201 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3202 3203 unsigned align = 0; 3204 unsigned index = 0; 3205 switch (size) { 3206 default: 3207 return MCDisassembler::Fail; 3208 case 0: 3209 if (fieldFromInstruction32(Insn, 4, 1)) 3210 return MCDisassembler::Fail; // UNDEFINED 3211 index = fieldFromInstruction32(Insn, 5, 3); 3212 break; 3213 case 1: 3214 if (fieldFromInstruction32(Insn, 5, 1)) 3215 return MCDisassembler::Fail; // UNDEFINED 3216 index = fieldFromInstruction32(Insn, 6, 2); 3217 if (fieldFromInstruction32(Insn, 4, 1)) 3218 align = 2; 3219 break; 3220 case 2: 3221 if (fieldFromInstruction32(Insn, 6, 1)) 3222 return MCDisassembler::Fail; // UNDEFINED 3223 index = fieldFromInstruction32(Insn, 7, 1); 3224 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3225 align = 4; 3226 } 3227 3228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 if (Rm != 0xF) { // Writeback 3231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3232 return MCDisassembler::Fail; 3233 } 3234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 Inst.addOperand(MCOperand::CreateImm(align)); 3237 if (Rm != 0xF) { 3238 if (Rm != 0xD) { 3239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3240 return MCDisassembler::Fail; 3241 } else 3242 Inst.addOperand(MCOperand::CreateReg(0)); 3243 } 3244 3245 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 Inst.addOperand(MCOperand::CreateImm(index)); 3248 3249 return S; 3250 } 3251 3252 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3253 uint64_t Address, const void *Decoder) { 3254 DecodeStatus S = MCDisassembler::Success; 3255 3256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3257 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3258 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3259 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3260 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3261 3262 unsigned align = 0; 3263 unsigned index = 0; 3264 switch (size) { 3265 default: 3266 return MCDisassembler::Fail; 3267 case 0: 3268 if (fieldFromInstruction32(Insn, 4, 1)) 3269 return MCDisassembler::Fail; // UNDEFINED 3270 index = fieldFromInstruction32(Insn, 5, 3); 3271 break; 3272 case 1: 3273 if (fieldFromInstruction32(Insn, 5, 1)) 3274 return MCDisassembler::Fail; // UNDEFINED 3275 index = fieldFromInstruction32(Insn, 6, 2); 3276 if (fieldFromInstruction32(Insn, 4, 1)) 3277 align = 2; 3278 break; 3279 case 2: 3280 if (fieldFromInstruction32(Insn, 6, 1)) 3281 return MCDisassembler::Fail; // UNDEFINED 3282 index = fieldFromInstruction32(Insn, 7, 1); 3283 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3284 align = 4; 3285 } 3286 3287 if (Rm != 0xF) { // Writeback 3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3289 return MCDisassembler::Fail; 3290 } 3291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 Inst.addOperand(MCOperand::CreateImm(align)); 3294 if (Rm != 0xF) { 3295 if (Rm != 0xD) { 3296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3297 return MCDisassembler::Fail; 3298 } else 3299 Inst.addOperand(MCOperand::CreateReg(0)); 3300 } 3301 3302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3303 return MCDisassembler::Fail; 3304 Inst.addOperand(MCOperand::CreateImm(index)); 3305 3306 return S; 3307 } 3308 3309 3310 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3311 uint64_t Address, const void *Decoder) { 3312 DecodeStatus S = MCDisassembler::Success; 3313 3314 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3315 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3316 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3317 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3318 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3319 3320 unsigned align = 0; 3321 unsigned index = 0; 3322 unsigned inc = 1; 3323 switch (size) { 3324 default: 3325 return MCDisassembler::Fail; 3326 case 0: 3327 index = fieldFromInstruction32(Insn, 5, 3); 3328 if (fieldFromInstruction32(Insn, 4, 1)) 3329 align = 2; 3330 break; 3331 case 1: 3332 index = fieldFromInstruction32(Insn, 6, 2); 3333 if (fieldFromInstruction32(Insn, 4, 1)) 3334 align = 4; 3335 if (fieldFromInstruction32(Insn, 5, 1)) 3336 inc = 2; 3337 break; 3338 case 2: 3339 if (fieldFromInstruction32(Insn, 5, 1)) 3340 return MCDisassembler::Fail; // UNDEFINED 3341 index = fieldFromInstruction32(Insn, 7, 1); 3342 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3343 align = 8; 3344 if (fieldFromInstruction32(Insn, 6, 1)) 3345 inc = 2; 3346 break; 3347 } 3348 3349 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 if (Rm != 0xF) { // Writeback 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 } 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 Inst.addOperand(MCOperand::CreateImm(align)); 3360 if (Rm != 0xF) { 3361 if (Rm != 0xD) { 3362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 } else 3365 Inst.addOperand(MCOperand::CreateReg(0)); 3366 } 3367 3368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3371 return MCDisassembler::Fail; 3372 Inst.addOperand(MCOperand::CreateImm(index)); 3373 3374 return S; 3375 } 3376 3377 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3378 uint64_t Address, const void *Decoder) { 3379 DecodeStatus S = MCDisassembler::Success; 3380 3381 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3382 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3383 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3384 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3385 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3386 3387 unsigned align = 0; 3388 unsigned index = 0; 3389 unsigned inc = 1; 3390 switch (size) { 3391 default: 3392 return MCDisassembler::Fail; 3393 case 0: 3394 index = fieldFromInstruction32(Insn, 5, 3); 3395 if (fieldFromInstruction32(Insn, 4, 1)) 3396 align = 2; 3397 break; 3398 case 1: 3399 index = fieldFromInstruction32(Insn, 6, 2); 3400 if (fieldFromInstruction32(Insn, 4, 1)) 3401 align = 4; 3402 if (fieldFromInstruction32(Insn, 5, 1)) 3403 inc = 2; 3404 break; 3405 case 2: 3406 if (fieldFromInstruction32(Insn, 5, 1)) 3407 return MCDisassembler::Fail; // UNDEFINED 3408 index = fieldFromInstruction32(Insn, 7, 1); 3409 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3410 align = 8; 3411 if (fieldFromInstruction32(Insn, 6, 1)) 3412 inc = 2; 3413 break; 3414 } 3415 3416 if (Rm != 0xF) { // Writeback 3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 } 3420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3421 return MCDisassembler::Fail; 3422 Inst.addOperand(MCOperand::CreateImm(align)); 3423 if (Rm != 0xF) { 3424 if (Rm != 0xD) { 3425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 } else 3428 Inst.addOperand(MCOperand::CreateReg(0)); 3429 } 3430 3431 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 Inst.addOperand(MCOperand::CreateImm(index)); 3436 3437 return S; 3438 } 3439 3440 3441 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3442 uint64_t Address, const void *Decoder) { 3443 DecodeStatus S = MCDisassembler::Success; 3444 3445 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3446 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3447 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3448 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3449 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3450 3451 unsigned align = 0; 3452 unsigned index = 0; 3453 unsigned inc = 1; 3454 switch (size) { 3455 default: 3456 return MCDisassembler::Fail; 3457 case 0: 3458 if (fieldFromInstruction32(Insn, 4, 1)) 3459 return MCDisassembler::Fail; // UNDEFINED 3460 index = fieldFromInstruction32(Insn, 5, 3); 3461 break; 3462 case 1: 3463 if (fieldFromInstruction32(Insn, 4, 1)) 3464 return MCDisassembler::Fail; // UNDEFINED 3465 index = fieldFromInstruction32(Insn, 6, 2); 3466 if (fieldFromInstruction32(Insn, 5, 1)) 3467 inc = 2; 3468 break; 3469 case 2: 3470 if (fieldFromInstruction32(Insn, 4, 2)) 3471 return MCDisassembler::Fail; // UNDEFINED 3472 index = fieldFromInstruction32(Insn, 7, 1); 3473 if (fieldFromInstruction32(Insn, 6, 1)) 3474 inc = 2; 3475 break; 3476 } 3477 3478 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3479 return MCDisassembler::Fail; 3480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3481 return MCDisassembler::Fail; 3482 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3483 return MCDisassembler::Fail; 3484 3485 if (Rm != 0xF) { // Writeback 3486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 } 3489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 Inst.addOperand(MCOperand::CreateImm(align)); 3492 if (Rm != 0xF) { 3493 if (Rm != 0xD) { 3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 } else 3497 Inst.addOperand(MCOperand::CreateReg(0)); 3498 } 3499 3500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3501 return MCDisassembler::Fail; 3502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3505 return MCDisassembler::Fail; 3506 Inst.addOperand(MCOperand::CreateImm(index)); 3507 3508 return S; 3509 } 3510 3511 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3512 uint64_t Address, const void *Decoder) { 3513 DecodeStatus S = MCDisassembler::Success; 3514 3515 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3517 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3518 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3519 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3520 3521 unsigned align = 0; 3522 unsigned index = 0; 3523 unsigned inc = 1; 3524 switch (size) { 3525 default: 3526 return MCDisassembler::Fail; 3527 case 0: 3528 if (fieldFromInstruction32(Insn, 4, 1)) 3529 return MCDisassembler::Fail; // UNDEFINED 3530 index = fieldFromInstruction32(Insn, 5, 3); 3531 break; 3532 case 1: 3533 if (fieldFromInstruction32(Insn, 4, 1)) 3534 return MCDisassembler::Fail; // UNDEFINED 3535 index = fieldFromInstruction32(Insn, 6, 2); 3536 if (fieldFromInstruction32(Insn, 5, 1)) 3537 inc = 2; 3538 break; 3539 case 2: 3540 if (fieldFromInstruction32(Insn, 4, 2)) 3541 return MCDisassembler::Fail; // UNDEFINED 3542 index = fieldFromInstruction32(Insn, 7, 1); 3543 if (fieldFromInstruction32(Insn, 6, 1)) 3544 inc = 2; 3545 break; 3546 } 3547 3548 if (Rm != 0xF) { // Writeback 3549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3550 return MCDisassembler::Fail; 3551 } 3552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3553 return MCDisassembler::Fail; 3554 Inst.addOperand(MCOperand::CreateImm(align)); 3555 if (Rm != 0xF) { 3556 if (Rm != 0xD) { 3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 } else 3560 Inst.addOperand(MCOperand::CreateReg(0)); 3561 } 3562 3563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3564 return MCDisassembler::Fail; 3565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 Inst.addOperand(MCOperand::CreateImm(index)); 3570 3571 return S; 3572 } 3573 3574 3575 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3576 uint64_t Address, const void *Decoder) { 3577 DecodeStatus S = MCDisassembler::Success; 3578 3579 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3580 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3581 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3582 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3583 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3584 3585 unsigned align = 0; 3586 unsigned index = 0; 3587 unsigned inc = 1; 3588 switch (size) { 3589 default: 3590 return MCDisassembler::Fail; 3591 case 0: 3592 if (fieldFromInstruction32(Insn, 4, 1)) 3593 align = 4; 3594 index = fieldFromInstruction32(Insn, 5, 3); 3595 break; 3596 case 1: 3597 if (fieldFromInstruction32(Insn, 4, 1)) 3598 align = 8; 3599 index = fieldFromInstruction32(Insn, 6, 2); 3600 if (fieldFromInstruction32(Insn, 5, 1)) 3601 inc = 2; 3602 break; 3603 case 2: 3604 if (fieldFromInstruction32(Insn, 4, 2)) 3605 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3606 index = fieldFromInstruction32(Insn, 7, 1); 3607 if (fieldFromInstruction32(Insn, 6, 1)) 3608 inc = 2; 3609 break; 3610 } 3611 3612 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3617 return MCDisassembler::Fail; 3618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 3621 if (Rm != 0xF) { // Writeback 3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 } 3625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 Inst.addOperand(MCOperand::CreateImm(align)); 3628 if (Rm != 0xF) { 3629 if (Rm != 0xD) { 3630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 } else 3633 Inst.addOperand(MCOperand::CreateReg(0)); 3634 } 3635 3636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 Inst.addOperand(MCOperand::CreateImm(index)); 3645 3646 return S; 3647 } 3648 3649 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3650 uint64_t Address, const void *Decoder) { 3651 DecodeStatus S = MCDisassembler::Success; 3652 3653 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3654 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3655 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3656 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3657 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3658 3659 unsigned align = 0; 3660 unsigned index = 0; 3661 unsigned inc = 1; 3662 switch (size) { 3663 default: 3664 return MCDisassembler::Fail; 3665 case 0: 3666 if (fieldFromInstruction32(Insn, 4, 1)) 3667 align = 4; 3668 index = fieldFromInstruction32(Insn, 5, 3); 3669 break; 3670 case 1: 3671 if (fieldFromInstruction32(Insn, 4, 1)) 3672 align = 8; 3673 index = fieldFromInstruction32(Insn, 6, 2); 3674 if (fieldFromInstruction32(Insn, 5, 1)) 3675 inc = 2; 3676 break; 3677 case 2: 3678 if (fieldFromInstruction32(Insn, 4, 2)) 3679 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3680 index = fieldFromInstruction32(Insn, 7, 1); 3681 if (fieldFromInstruction32(Insn, 6, 1)) 3682 inc = 2; 3683 break; 3684 } 3685 3686 if (Rm != 0xF) { // Writeback 3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3688 return MCDisassembler::Fail; 3689 } 3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 Inst.addOperand(MCOperand::CreateImm(align)); 3693 if (Rm != 0xF) { 3694 if (Rm != 0xD) { 3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 } else 3698 Inst.addOperand(MCOperand::CreateReg(0)); 3699 } 3700 3701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3702 return MCDisassembler::Fail; 3703 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3704 return MCDisassembler::Fail; 3705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3708 return MCDisassembler::Fail; 3709 Inst.addOperand(MCOperand::CreateImm(index)); 3710 3711 return S; 3712 } 3713 3714 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3715 uint64_t Address, const void *Decoder) { 3716 DecodeStatus S = MCDisassembler::Success; 3717 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3718 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3719 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3720 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3721 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3722 3723 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3724 S = MCDisassembler::SoftFail; 3725 3726 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 3737 return S; 3738 } 3739 3740 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3741 uint64_t Address, const void *Decoder) { 3742 DecodeStatus S = MCDisassembler::Success; 3743 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3744 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3745 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3746 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3747 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3748 3749 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3750 S = MCDisassembler::SoftFail; 3751 3752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3755 return MCDisassembler::Fail; 3756 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3757 return MCDisassembler::Fail; 3758 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3761 return MCDisassembler::Fail; 3762 3763 return S; 3764 } 3765 3766 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3767 uint64_t Address, const void *Decoder) { 3768 DecodeStatus S = MCDisassembler::Success; 3769 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3770 // The InstPrinter needs to have the low bit of the predicate in 3771 // the mask operand to be able to print it properly. 3772 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3773 3774 if (pred == 0xF) { 3775 pred = 0xE; 3776 S = MCDisassembler::SoftFail; 3777 } 3778 3779 if ((mask & 0xF) == 0) { 3780 // Preserve the high bit of the mask, which is the low bit of 3781 // the predicate. 3782 mask &= 0x10; 3783 mask |= 0x8; 3784 S = MCDisassembler::SoftFail; 3785 } 3786 3787 Inst.addOperand(MCOperand::CreateImm(pred)); 3788 Inst.addOperand(MCOperand::CreateImm(mask)); 3789 return S; 3790 } 3791 3792 static DecodeStatus 3793 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3794 uint64_t Address, const void *Decoder) { 3795 DecodeStatus S = MCDisassembler::Success; 3796 3797 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3798 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3799 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3800 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3801 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3802 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3803 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3804 bool writeback = (W == 1) | (P == 0); 3805 3806 addr |= (U << 8) | (Rn << 9); 3807 3808 if (writeback && (Rn == Rt || Rn == Rt2)) 3809 Check(S, MCDisassembler::SoftFail); 3810 if (Rt == Rt2) 3811 Check(S, MCDisassembler::SoftFail); 3812 3813 // Rt 3814 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3815 return MCDisassembler::Fail; 3816 // Rt2 3817 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 // Writeback operand 3820 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3821 return MCDisassembler::Fail; 3822 // addr 3823 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3824 return MCDisassembler::Fail; 3825 3826 return S; 3827 } 3828 3829 static DecodeStatus 3830 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3831 uint64_t Address, const void *Decoder) { 3832 DecodeStatus S = MCDisassembler::Success; 3833 3834 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3835 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3836 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3837 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3838 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3839 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3840 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3841 bool writeback = (W == 1) | (P == 0); 3842 3843 addr |= (U << 8) | (Rn << 9); 3844 3845 if (writeback && (Rn == Rt || Rn == Rt2)) 3846 Check(S, MCDisassembler::SoftFail); 3847 3848 // Writeback operand 3849 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3850 return MCDisassembler::Fail; 3851 // Rt 3852 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3853 return MCDisassembler::Fail; 3854 // Rt2 3855 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 // addr 3858 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 3861 return S; 3862 } 3863 3864 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 3865 uint64_t Address, const void *Decoder) { 3866 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 3867 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 3868 if (sign1 != sign2) return MCDisassembler::Fail; 3869 3870 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 3871 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 3872 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 3873 Val |= sign1 << 12; 3874 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 3875 3876 return MCDisassembler::Success; 3877 } 3878 3879