1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMRegisterInfo.h" 14 #include "ARMSubtarget.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream) const; 51 52 /// getEDInfo - See MCDisassembler. 53 EDInstInfo *getEDInfo() const; 54 private: 55 }; 56 57 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 58 class ThumbDisassembler : public MCDisassembler { 59 public: 60 /// Constructor - Initializes the disassembler. 61 /// 62 ThumbDisassembler(const MCSubtargetInfo &STI) : 63 MCDisassembler(STI) { 64 } 65 66 ~ThumbDisassembler() { 67 } 68 69 /// getInstruction - See MCDisassembler. 70 DecodeStatus getInstruction(MCInst &instr, 71 uint64_t &size, 72 const MemoryObject ®ion, 73 uint64_t address, 74 raw_ostream &vStream) const; 75 76 /// getEDInfo - See MCDisassembler. 77 EDInstInfo *getEDInfo() const; 78 private: 79 mutable std::vector<unsigned> ITBlock; 80 DecodeStatus AddThumbPredicate(MCInst&) const; 81 void UpdateThumbVFPPredicate(MCInst&) const; 82 }; 83 } 84 85 static bool Check(DecodeStatus &Out, DecodeStatus In) { 86 switch (In) { 87 case MCDisassembler::Success: 88 // Out stays the same. 89 return true; 90 case MCDisassembler::SoftFail: 91 Out = In; 92 return true; 93 case MCDisassembler::Fail: 94 Out = In; 95 return false; 96 } 97 return false; 98 } 99 100 101 // Forward declare these because the autogenerated code will reference them. 102 // Definitions are further down. 103 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 125 uint64_t Address, const void *Decoder); 126 127 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 140 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 157 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 158 unsigned Insn, 159 uint64_t Adddress, 160 const void *Decoder); 161 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 248 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 303 #include "ARMGenDisassemblerTables.inc" 304 #include "ARMGenInstrInfo.inc" 305 #include "ARMGenEDInfo.inc" 306 307 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 308 return new ARMDisassembler(STI); 309 } 310 311 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 312 return new ThumbDisassembler(STI); 313 } 314 315 EDInstInfo *ARMDisassembler::getEDInfo() const { 316 return instInfoARM; 317 } 318 319 EDInstInfo *ThumbDisassembler::getEDInfo() const { 320 return instInfoARM; 321 } 322 323 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 324 const MemoryObject &Region, 325 uint64_t Address, 326 raw_ostream &os) const { 327 uint8_t bytes[4]; 328 329 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 330 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 331 332 // We want to read exactly 4 bytes of data. 333 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 334 Size = 0; 335 return MCDisassembler::Fail; 336 } 337 338 // Encoded as a small-endian 32-bit word in the stream. 339 uint32_t insn = (bytes[3] << 24) | 340 (bytes[2] << 16) | 341 (bytes[1] << 8) | 342 (bytes[0] << 0); 343 344 // Calling the auto-generated decoder function. 345 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 346 if (result != MCDisassembler::Fail) { 347 Size = 4; 348 return result; 349 } 350 351 // VFP and NEON instructions, similarly, are shared between ARM 352 // and Thumb modes. 353 MI.clear(); 354 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 355 if (result != MCDisassembler::Fail) { 356 Size = 4; 357 return result; 358 } 359 360 MI.clear(); 361 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 362 if (result != MCDisassembler::Fail) { 363 Size = 4; 364 // Add a fake predicate operand, because we share these instruction 365 // definitions with Thumb2 where these instructions are predicable. 366 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 367 return MCDisassembler::Fail; 368 return result; 369 } 370 371 MI.clear(); 372 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 373 if (result != MCDisassembler::Fail) { 374 Size = 4; 375 // Add a fake predicate operand, because we share these instruction 376 // definitions with Thumb2 where these instructions are predicable. 377 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 378 return MCDisassembler::Fail; 379 return result; 380 } 381 382 MI.clear(); 383 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 384 if (result != MCDisassembler::Fail) { 385 Size = 4; 386 // Add a fake predicate operand, because we share these instruction 387 // definitions with Thumb2 where these instructions are predicable. 388 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 389 return MCDisassembler::Fail; 390 return result; 391 } 392 393 MI.clear(); 394 395 Size = 0; 396 return MCDisassembler::Fail; 397 } 398 399 namespace llvm { 400 extern MCInstrDesc ARMInsts[]; 401 } 402 403 // Thumb1 instructions don't have explicit S bits. Rather, they 404 // implicitly set CPSR. Since it's not represented in the encoding, the 405 // auto-generated decoder won't inject the CPSR operand. We need to fix 406 // that as a post-pass. 407 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 408 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 409 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 410 MCInst::iterator I = MI.begin(); 411 for (unsigned i = 0; i < NumOps; ++i, ++I) { 412 if (I == MI.end()) break; 413 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 414 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 415 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 416 return; 417 } 418 } 419 420 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 421 } 422 423 // Most Thumb instructions don't have explicit predicates in the 424 // encoding, but rather get their predicates from IT context. We need 425 // to fix up the predicate operands using this context information as a 426 // post-pass. 427 MCDisassembler::DecodeStatus 428 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 429 // A few instructions actually have predicates encoded in them. Don't 430 // try to overwrite it if we're seeing one of those. 431 switch (MI.getOpcode()) { 432 case ARM::tBcc: 433 case ARM::t2Bcc: 434 case ARM::tCBZ: 435 case ARM::tCBNZ: 436 // Some instructions (mostly conditional branches) are not 437 // allowed in IT blocks. 438 if (!ITBlock.empty()) 439 return SoftFail; 440 return Success; 441 break; 442 default: 443 break; 444 } 445 446 // If we're in an IT block, base the predicate on that. Otherwise, 447 // assume a predicate of AL. 448 unsigned CC; 449 if (!ITBlock.empty()) { 450 CC = ITBlock.back(); 451 if (CC == 0xF) 452 CC = ARMCC::AL; 453 ITBlock.pop_back(); 454 } else 455 CC = ARMCC::AL; 456 457 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 458 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 459 MCInst::iterator I = MI.begin(); 460 for (unsigned i = 0; i < NumOps; ++i, ++I) { 461 if (I == MI.end()) break; 462 if (OpInfo[i].isPredicate()) { 463 I = MI.insert(I, MCOperand::CreateImm(CC)); 464 ++I; 465 if (CC == ARMCC::AL) 466 MI.insert(I, MCOperand::CreateReg(0)); 467 else 468 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 469 return Success; 470 } 471 } 472 473 I = MI.insert(I, MCOperand::CreateImm(CC)); 474 ++I; 475 if (CC == ARMCC::AL) 476 MI.insert(I, MCOperand::CreateReg(0)); 477 else 478 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 479 480 return Success; 481 } 482 483 // Thumb VFP instructions are a special case. Because we share their 484 // encodings between ARM and Thumb modes, and they are predicable in ARM 485 // mode, the auto-generated decoder will give them an (incorrect) 486 // predicate operand. We need to rewrite these operands based on the IT 487 // context as a post-pass. 488 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 489 unsigned CC; 490 if (!ITBlock.empty()) { 491 CC = ITBlock.back(); 492 ITBlock.pop_back(); 493 } else 494 CC = ARMCC::AL; 495 496 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 497 MCInst::iterator I = MI.begin(); 498 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 499 for (unsigned i = 0; i < NumOps; ++i, ++I) { 500 if (OpInfo[i].isPredicate() ) { 501 I->setImm(CC); 502 ++I; 503 if (CC == ARMCC::AL) 504 I->setReg(0); 505 else 506 I->setReg(ARM::CPSR); 507 return; 508 } 509 } 510 } 511 512 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 513 const MemoryObject &Region, 514 uint64_t Address, 515 raw_ostream &os) const { 516 uint8_t bytes[4]; 517 518 assert((STI.getFeatureBits() & ARM::ModeThumb) && 519 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 520 521 // We want to read exactly 2 bytes of data. 522 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 523 Size = 0; 524 return MCDisassembler::Fail; 525 } 526 527 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 528 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 529 if (result != MCDisassembler::Fail) { 530 Size = 2; 531 Check(result, AddThumbPredicate(MI)); 532 return result; 533 } 534 535 MI.clear(); 536 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 537 if (result) { 538 Size = 2; 539 bool InITBlock = !ITBlock.empty(); 540 Check(result, AddThumbPredicate(MI)); 541 AddThumb1SBit(MI, InITBlock); 542 return result; 543 } 544 545 MI.clear(); 546 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 547 if (result != MCDisassembler::Fail) { 548 Size = 2; 549 Check(result, AddThumbPredicate(MI)); 550 551 // If we find an IT instruction, we need to parse its condition 552 // code and mask operands so that we can apply them correctly 553 // to the subsequent instructions. 554 if (MI.getOpcode() == ARM::t2IT) { 555 // (3 - the number of trailing zeros) is the number of then / else. 556 unsigned firstcond = MI.getOperand(0).getImm(); 557 unsigned Mask = MI.getOperand(1).getImm(); 558 unsigned CondBit0 = Mask >> 4 & 1; 559 unsigned NumTZ = CountTrailingZeros_32(Mask); 560 assert(NumTZ <= 3 && "Invalid IT mask!"); 561 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 562 bool T = ((Mask >> Pos) & 1) == CondBit0; 563 if (T) 564 ITBlock.insert(ITBlock.begin(), firstcond); 565 else 566 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 567 } 568 569 ITBlock.push_back(firstcond); 570 } 571 572 return result; 573 } 574 575 // We want to read exactly 4 bytes of data. 576 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 577 Size = 0; 578 return MCDisassembler::Fail; 579 } 580 581 uint32_t insn32 = (bytes[3] << 8) | 582 (bytes[2] << 0) | 583 (bytes[1] << 24) | 584 (bytes[0] << 16); 585 MI.clear(); 586 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 587 if (result != MCDisassembler::Fail) { 588 Size = 4; 589 bool InITBlock = ITBlock.size(); 590 Check(result, AddThumbPredicate(MI)); 591 AddThumb1SBit(MI, InITBlock); 592 return result; 593 } 594 595 MI.clear(); 596 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 597 if (result != MCDisassembler::Fail) { 598 Size = 4; 599 Check(result, AddThumbPredicate(MI)); 600 return result; 601 } 602 603 MI.clear(); 604 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 605 if (result != MCDisassembler::Fail) { 606 Size = 4; 607 UpdateThumbVFPPredicate(MI); 608 return result; 609 } 610 611 MI.clear(); 612 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 613 if (result != MCDisassembler::Fail) { 614 Size = 4; 615 Check(result, AddThumbPredicate(MI)); 616 return result; 617 } 618 619 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 620 MI.clear(); 621 uint32_t NEONLdStInsn = insn32; 622 NEONLdStInsn &= 0xF0FFFFFF; 623 NEONLdStInsn |= 0x04000000; 624 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 625 if (result != MCDisassembler::Fail) { 626 Size = 4; 627 Check(result, AddThumbPredicate(MI)); 628 return result; 629 } 630 } 631 632 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 633 MI.clear(); 634 uint32_t NEONDataInsn = insn32; 635 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 636 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 637 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 638 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 639 if (result != MCDisassembler::Fail) { 640 Size = 4; 641 Check(result, AddThumbPredicate(MI)); 642 return result; 643 } 644 } 645 646 Size = 0; 647 return MCDisassembler::Fail; 648 } 649 650 651 extern "C" void LLVMInitializeARMDisassembler() { 652 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 653 createARMDisassembler); 654 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 655 createThumbDisassembler); 656 } 657 658 static const unsigned GPRDecoderTable[] = { 659 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 660 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 661 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 662 ARM::R12, ARM::SP, ARM::LR, ARM::PC 663 }; 664 665 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 666 uint64_t Address, const void *Decoder) { 667 if (RegNo > 15) 668 return MCDisassembler::Fail; 669 670 unsigned Register = GPRDecoderTable[RegNo]; 671 Inst.addOperand(MCOperand::CreateReg(Register)); 672 return MCDisassembler::Success; 673 } 674 675 static DecodeStatus 676 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 677 uint64_t Address, const void *Decoder) { 678 if (RegNo == 15) return MCDisassembler::Fail; 679 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 680 } 681 682 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 683 uint64_t Address, const void *Decoder) { 684 if (RegNo > 7) 685 return MCDisassembler::Fail; 686 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 687 } 688 689 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 690 uint64_t Address, const void *Decoder) { 691 unsigned Register = 0; 692 switch (RegNo) { 693 case 0: 694 Register = ARM::R0; 695 break; 696 case 1: 697 Register = ARM::R1; 698 break; 699 case 2: 700 Register = ARM::R2; 701 break; 702 case 3: 703 Register = ARM::R3; 704 break; 705 case 9: 706 Register = ARM::R9; 707 break; 708 case 12: 709 Register = ARM::R12; 710 break; 711 default: 712 return MCDisassembler::Fail; 713 } 714 715 Inst.addOperand(MCOperand::CreateReg(Register)); 716 return MCDisassembler::Success; 717 } 718 719 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 720 uint64_t Address, const void *Decoder) { 721 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 722 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 723 } 724 725 static const unsigned SPRDecoderTable[] = { 726 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 727 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 728 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 729 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 730 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 731 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 732 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 733 ARM::S28, ARM::S29, ARM::S30, ARM::S31 734 }; 735 736 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 737 uint64_t Address, const void *Decoder) { 738 if (RegNo > 31) 739 return MCDisassembler::Fail; 740 741 unsigned Register = SPRDecoderTable[RegNo]; 742 Inst.addOperand(MCOperand::CreateReg(Register)); 743 return MCDisassembler::Success; 744 } 745 746 static const unsigned DPRDecoderTable[] = { 747 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 748 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 749 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 750 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 751 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 752 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 753 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 754 ARM::D28, ARM::D29, ARM::D30, ARM::D31 755 }; 756 757 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 758 uint64_t Address, const void *Decoder) { 759 if (RegNo > 31) 760 return MCDisassembler::Fail; 761 762 unsigned Register = DPRDecoderTable[RegNo]; 763 Inst.addOperand(MCOperand::CreateReg(Register)); 764 return MCDisassembler::Success; 765 } 766 767 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 768 uint64_t Address, const void *Decoder) { 769 if (RegNo > 7) 770 return MCDisassembler::Fail; 771 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 772 } 773 774 static DecodeStatus 775 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 776 uint64_t Address, const void *Decoder) { 777 if (RegNo > 15) 778 return MCDisassembler::Fail; 779 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 780 } 781 782 static const unsigned QPRDecoderTable[] = { 783 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 784 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 785 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 786 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 787 }; 788 789 790 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 791 uint64_t Address, const void *Decoder) { 792 if (RegNo > 31) 793 return MCDisassembler::Fail; 794 RegNo >>= 1; 795 796 unsigned Register = QPRDecoderTable[RegNo]; 797 Inst.addOperand(MCOperand::CreateReg(Register)); 798 return MCDisassembler::Success; 799 } 800 801 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 802 uint64_t Address, const void *Decoder) { 803 if (Val == 0xF) return MCDisassembler::Fail; 804 // AL predicate is not allowed on Thumb1 branches. 805 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 806 return MCDisassembler::Fail; 807 Inst.addOperand(MCOperand::CreateImm(Val)); 808 if (Val == ARMCC::AL) { 809 Inst.addOperand(MCOperand::CreateReg(0)); 810 } else 811 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 812 return MCDisassembler::Success; 813 } 814 815 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 816 uint64_t Address, const void *Decoder) { 817 if (Val) 818 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 819 else 820 Inst.addOperand(MCOperand::CreateReg(0)); 821 return MCDisassembler::Success; 822 } 823 824 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 825 uint64_t Address, const void *Decoder) { 826 uint32_t imm = Val & 0xFF; 827 uint32_t rot = (Val & 0xF00) >> 7; 828 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 829 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 830 return MCDisassembler::Success; 831 } 832 833 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 834 uint64_t Address, const void *Decoder) { 835 DecodeStatus S = MCDisassembler::Success; 836 837 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 838 unsigned type = fieldFromInstruction32(Val, 5, 2); 839 unsigned imm = fieldFromInstruction32(Val, 7, 5); 840 841 // Register-immediate 842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 843 return MCDisassembler::Fail; 844 845 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 846 switch (type) { 847 case 0: 848 Shift = ARM_AM::lsl; 849 break; 850 case 1: 851 Shift = ARM_AM::lsr; 852 break; 853 case 2: 854 Shift = ARM_AM::asr; 855 break; 856 case 3: 857 Shift = ARM_AM::ror; 858 break; 859 } 860 861 if (Shift == ARM_AM::ror && imm == 0) 862 Shift = ARM_AM::rrx; 863 864 unsigned Op = Shift | (imm << 3); 865 Inst.addOperand(MCOperand::CreateImm(Op)); 866 867 return S; 868 } 869 870 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 871 uint64_t Address, const void *Decoder) { 872 DecodeStatus S = MCDisassembler::Success; 873 874 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 875 unsigned type = fieldFromInstruction32(Val, 5, 2); 876 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 877 878 // Register-register 879 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 880 return MCDisassembler::Fail; 881 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 882 return MCDisassembler::Fail; 883 884 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 885 switch (type) { 886 case 0: 887 Shift = ARM_AM::lsl; 888 break; 889 case 1: 890 Shift = ARM_AM::lsr; 891 break; 892 case 2: 893 Shift = ARM_AM::asr; 894 break; 895 case 3: 896 Shift = ARM_AM::ror; 897 break; 898 } 899 900 Inst.addOperand(MCOperand::CreateImm(Shift)); 901 902 return S; 903 } 904 905 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 906 uint64_t Address, const void *Decoder) { 907 DecodeStatus S = MCDisassembler::Success; 908 909 // Empty register lists are not allowed. 910 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 911 for (unsigned i = 0; i < 16; ++i) { 912 if (Val & (1 << i)) { 913 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 914 return MCDisassembler::Fail; 915 } 916 } 917 918 return S; 919 } 920 921 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 922 uint64_t Address, const void *Decoder) { 923 DecodeStatus S = MCDisassembler::Success; 924 925 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 926 unsigned regs = Val & 0xFF; 927 928 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 929 return MCDisassembler::Fail; 930 for (unsigned i = 0; i < (regs - 1); ++i) { 931 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 932 return MCDisassembler::Fail; 933 } 934 935 return S; 936 } 937 938 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 939 uint64_t Address, const void *Decoder) { 940 DecodeStatus S = MCDisassembler::Success; 941 942 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 943 unsigned regs = (Val & 0xFF) / 2; 944 945 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 946 return MCDisassembler::Fail; 947 for (unsigned i = 0; i < (regs - 1); ++i) { 948 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 949 return MCDisassembler::Fail; 950 } 951 952 return S; 953 } 954 955 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 956 uint64_t Address, const void *Decoder) { 957 // This operand encodes a mask of contiguous zeros between a specified MSB 958 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 959 // the mask of all bits LSB-and-lower, and then xor them to create 960 // the mask of that's all ones on [msb, lsb]. Finally we not it to 961 // create the final mask. 962 unsigned msb = fieldFromInstruction32(Val, 5, 5); 963 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 964 uint32_t msb_mask = (1 << (msb+1)) - 1; 965 uint32_t lsb_mask = (1 << lsb) - 1; 966 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 967 return MCDisassembler::Success; 968 } 969 970 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 971 uint64_t Address, const void *Decoder) { 972 DecodeStatus S = MCDisassembler::Success; 973 974 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 975 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 976 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 977 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 978 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 979 unsigned U = fieldFromInstruction32(Insn, 23, 1); 980 981 switch (Inst.getOpcode()) { 982 case ARM::LDC_OFFSET: 983 case ARM::LDC_PRE: 984 case ARM::LDC_POST: 985 case ARM::LDC_OPTION: 986 case ARM::LDCL_OFFSET: 987 case ARM::LDCL_PRE: 988 case ARM::LDCL_POST: 989 case ARM::LDCL_OPTION: 990 case ARM::STC_OFFSET: 991 case ARM::STC_PRE: 992 case ARM::STC_POST: 993 case ARM::STC_OPTION: 994 case ARM::STCL_OFFSET: 995 case ARM::STCL_PRE: 996 case ARM::STCL_POST: 997 case ARM::STCL_OPTION: 998 case ARM::t2LDC_OFFSET: 999 case ARM::t2LDC_PRE: 1000 case ARM::t2LDC_POST: 1001 case ARM::t2LDC_OPTION: 1002 case ARM::t2LDCL_OFFSET: 1003 case ARM::t2LDCL_PRE: 1004 case ARM::t2LDCL_POST: 1005 case ARM::t2LDCL_OPTION: 1006 case ARM::t2STC_OFFSET: 1007 case ARM::t2STC_PRE: 1008 case ARM::t2STC_POST: 1009 case ARM::t2STC_OPTION: 1010 case ARM::t2STCL_OFFSET: 1011 case ARM::t2STCL_PRE: 1012 case ARM::t2STCL_POST: 1013 case ARM::t2STCL_OPTION: 1014 if (coproc == 0xA || coproc == 0xB) 1015 return MCDisassembler::Fail; 1016 break; 1017 default: 1018 break; 1019 } 1020 1021 Inst.addOperand(MCOperand::CreateImm(coproc)); 1022 Inst.addOperand(MCOperand::CreateImm(CRd)); 1023 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1024 return MCDisassembler::Fail; 1025 switch (Inst.getOpcode()) { 1026 case ARM::LDC_OPTION: 1027 case ARM::LDCL_OPTION: 1028 case ARM::LDC2_OPTION: 1029 case ARM::LDC2L_OPTION: 1030 case ARM::STC_OPTION: 1031 case ARM::STCL_OPTION: 1032 case ARM::STC2_OPTION: 1033 case ARM::STC2L_OPTION: 1034 case ARM::LDCL_POST: 1035 case ARM::STCL_POST: 1036 case ARM::LDC2L_POST: 1037 case ARM::STC2L_POST: 1038 case ARM::t2LDC_OPTION: 1039 case ARM::t2LDCL_OPTION: 1040 case ARM::t2STC_OPTION: 1041 case ARM::t2STCL_OPTION: 1042 case ARM::t2LDCL_POST: 1043 case ARM::t2STCL_POST: 1044 break; 1045 default: 1046 Inst.addOperand(MCOperand::CreateReg(0)); 1047 break; 1048 } 1049 1050 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1051 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1052 1053 bool writeback = (P == 0) || (W == 1); 1054 unsigned idx_mode = 0; 1055 if (P && writeback) 1056 idx_mode = ARMII::IndexModePre; 1057 else if (!P && writeback) 1058 idx_mode = ARMII::IndexModePost; 1059 1060 switch (Inst.getOpcode()) { 1061 case ARM::LDCL_POST: 1062 case ARM::STCL_POST: 1063 case ARM::t2LDCL_POST: 1064 case ARM::t2STCL_POST: 1065 case ARM::LDC2L_POST: 1066 case ARM::STC2L_POST: 1067 imm |= U << 8; 1068 case ARM::LDC_OPTION: 1069 case ARM::LDCL_OPTION: 1070 case ARM::LDC2_OPTION: 1071 case ARM::LDC2L_OPTION: 1072 case ARM::STC_OPTION: 1073 case ARM::STCL_OPTION: 1074 case ARM::STC2_OPTION: 1075 case ARM::STC2L_OPTION: 1076 case ARM::t2LDC_OPTION: 1077 case ARM::t2LDCL_OPTION: 1078 case ARM::t2STC_OPTION: 1079 case ARM::t2STCL_OPTION: 1080 Inst.addOperand(MCOperand::CreateImm(imm)); 1081 break; 1082 default: 1083 if (U) 1084 Inst.addOperand(MCOperand::CreateImm( 1085 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1086 else 1087 Inst.addOperand(MCOperand::CreateImm( 1088 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1089 break; 1090 } 1091 1092 switch (Inst.getOpcode()) { 1093 case ARM::LDC_OFFSET: 1094 case ARM::LDC_PRE: 1095 case ARM::LDC_POST: 1096 case ARM::LDC_OPTION: 1097 case ARM::LDCL_OFFSET: 1098 case ARM::LDCL_PRE: 1099 case ARM::LDCL_POST: 1100 case ARM::LDCL_OPTION: 1101 case ARM::STC_OFFSET: 1102 case ARM::STC_PRE: 1103 case ARM::STC_POST: 1104 case ARM::STC_OPTION: 1105 case ARM::STCL_OFFSET: 1106 case ARM::STCL_PRE: 1107 case ARM::STCL_POST: 1108 case ARM::STCL_OPTION: 1109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1110 return MCDisassembler::Fail; 1111 break; 1112 default: 1113 break; 1114 } 1115 1116 return S; 1117 } 1118 1119 static DecodeStatus 1120 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1121 uint64_t Address, const void *Decoder) { 1122 DecodeStatus S = MCDisassembler::Success; 1123 1124 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1125 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1126 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1127 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1128 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1129 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1130 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1131 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1132 1133 // On stores, the writeback operand precedes Rt. 1134 switch (Inst.getOpcode()) { 1135 case ARM::STR_POST_IMM: 1136 case ARM::STR_POST_REG: 1137 case ARM::STRB_POST_IMM: 1138 case ARM::STRB_POST_REG: 1139 case ARM::STRT_POST_REG: 1140 case ARM::STRT_POST_IMM: 1141 case ARM::STRBT_POST_REG: 1142 case ARM::STRBT_POST_IMM: 1143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1144 return MCDisassembler::Fail; 1145 break; 1146 default: 1147 break; 1148 } 1149 1150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1151 return MCDisassembler::Fail; 1152 1153 // On loads, the writeback operand comes after Rt. 1154 switch (Inst.getOpcode()) { 1155 case ARM::LDR_POST_IMM: 1156 case ARM::LDR_POST_REG: 1157 case ARM::LDRB_POST_IMM: 1158 case ARM::LDRB_POST_REG: 1159 case ARM::LDRBT_POST_REG: 1160 case ARM::LDRBT_POST_IMM: 1161 case ARM::LDRT_POST_REG: 1162 case ARM::LDRT_POST_IMM: 1163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1164 return MCDisassembler::Fail; 1165 break; 1166 default: 1167 break; 1168 } 1169 1170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1171 return MCDisassembler::Fail; 1172 1173 ARM_AM::AddrOpc Op = ARM_AM::add; 1174 if (!fieldFromInstruction32(Insn, 23, 1)) 1175 Op = ARM_AM::sub; 1176 1177 bool writeback = (P == 0) || (W == 1); 1178 unsigned idx_mode = 0; 1179 if (P && writeback) 1180 idx_mode = ARMII::IndexModePre; 1181 else if (!P && writeback) 1182 idx_mode = ARMII::IndexModePost; 1183 1184 if (writeback && (Rn == 15 || Rn == Rt)) 1185 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1186 1187 if (reg) { 1188 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1189 return MCDisassembler::Fail; 1190 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1191 switch( fieldFromInstruction32(Insn, 5, 2)) { 1192 case 0: 1193 Opc = ARM_AM::lsl; 1194 break; 1195 case 1: 1196 Opc = ARM_AM::lsr; 1197 break; 1198 case 2: 1199 Opc = ARM_AM::asr; 1200 break; 1201 case 3: 1202 Opc = ARM_AM::ror; 1203 break; 1204 default: 1205 return MCDisassembler::Fail; 1206 } 1207 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1208 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1209 1210 Inst.addOperand(MCOperand::CreateImm(imm)); 1211 } else { 1212 Inst.addOperand(MCOperand::CreateReg(0)); 1213 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1214 Inst.addOperand(MCOperand::CreateImm(tmp)); 1215 } 1216 1217 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1218 return MCDisassembler::Fail; 1219 1220 return S; 1221 } 1222 1223 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1228 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1229 unsigned type = fieldFromInstruction32(Val, 5, 2); 1230 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1231 unsigned U = fieldFromInstruction32(Val, 12, 1); 1232 1233 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1234 switch (type) { 1235 case 0: 1236 ShOp = ARM_AM::lsl; 1237 break; 1238 case 1: 1239 ShOp = ARM_AM::lsr; 1240 break; 1241 case 2: 1242 ShOp = ARM_AM::asr; 1243 break; 1244 case 3: 1245 ShOp = ARM_AM::ror; 1246 break; 1247 } 1248 1249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1252 return MCDisassembler::Fail; 1253 unsigned shift; 1254 if (U) 1255 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1256 else 1257 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1258 Inst.addOperand(MCOperand::CreateImm(shift)); 1259 1260 return S; 1261 } 1262 1263 static DecodeStatus 1264 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1265 uint64_t Address, const void *Decoder) { 1266 DecodeStatus S = MCDisassembler::Success; 1267 1268 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1269 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1271 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1272 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1273 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1274 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1275 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1276 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1277 1278 bool writeback = (W == 1) | (P == 0); 1279 1280 // For {LD,ST}RD, Rt must be even, else undefined. 1281 switch (Inst.getOpcode()) { 1282 case ARM::STRD: 1283 case ARM::STRD_PRE: 1284 case ARM::STRD_POST: 1285 case ARM::LDRD: 1286 case ARM::LDRD_PRE: 1287 case ARM::LDRD_POST: 1288 if (Rt & 0x1) return MCDisassembler::Fail; 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 if (writeback) { // Writeback 1295 if (P) 1296 U |= ARMII::IndexModePre << 9; 1297 else 1298 U |= ARMII::IndexModePost << 9; 1299 1300 // On stores, the writeback operand precedes Rt. 1301 switch (Inst.getOpcode()) { 1302 case ARM::STRD: 1303 case ARM::STRD_PRE: 1304 case ARM::STRD_POST: 1305 case ARM::STRH: 1306 case ARM::STRH_PRE: 1307 case ARM::STRH_POST: 1308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1309 return MCDisassembler::Fail; 1310 break; 1311 default: 1312 break; 1313 } 1314 } 1315 1316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1317 return MCDisassembler::Fail; 1318 switch (Inst.getOpcode()) { 1319 case ARM::STRD: 1320 case ARM::STRD_PRE: 1321 case ARM::STRD_POST: 1322 case ARM::LDRD: 1323 case ARM::LDRD_PRE: 1324 case ARM::LDRD_POST: 1325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1326 return MCDisassembler::Fail; 1327 break; 1328 default: 1329 break; 1330 } 1331 1332 if (writeback) { 1333 // On loads, the writeback operand comes after Rt. 1334 switch (Inst.getOpcode()) { 1335 case ARM::LDRD: 1336 case ARM::LDRD_PRE: 1337 case ARM::LDRD_POST: 1338 case ARM::LDRH: 1339 case ARM::LDRH_PRE: 1340 case ARM::LDRH_POST: 1341 case ARM::LDRSH: 1342 case ARM::LDRSH_PRE: 1343 case ARM::LDRSH_POST: 1344 case ARM::LDRSB: 1345 case ARM::LDRSB_PRE: 1346 case ARM::LDRSB_POST: 1347 case ARM::LDRHTr: 1348 case ARM::LDRSBTr: 1349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1350 return MCDisassembler::Fail; 1351 break; 1352 default: 1353 break; 1354 } 1355 } 1356 1357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1358 return MCDisassembler::Fail; 1359 1360 if (type) { 1361 Inst.addOperand(MCOperand::CreateReg(0)); 1362 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1363 } else { 1364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1365 return MCDisassembler::Fail; 1366 Inst.addOperand(MCOperand::CreateImm(U)); 1367 } 1368 1369 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1370 return MCDisassembler::Fail; 1371 1372 return S; 1373 } 1374 1375 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1376 uint64_t Address, const void *Decoder) { 1377 DecodeStatus S = MCDisassembler::Success; 1378 1379 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1380 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1381 1382 switch (mode) { 1383 case 0: 1384 mode = ARM_AM::da; 1385 break; 1386 case 1: 1387 mode = ARM_AM::ia; 1388 break; 1389 case 2: 1390 mode = ARM_AM::db; 1391 break; 1392 case 3: 1393 mode = ARM_AM::ib; 1394 break; 1395 } 1396 1397 Inst.addOperand(MCOperand::CreateImm(mode)); 1398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1399 return MCDisassembler::Fail; 1400 1401 return S; 1402 } 1403 1404 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1405 unsigned Insn, 1406 uint64_t Address, const void *Decoder) { 1407 DecodeStatus S = MCDisassembler::Success; 1408 1409 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1410 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1411 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1412 1413 if (pred == 0xF) { 1414 switch (Inst.getOpcode()) { 1415 case ARM::LDMDA: 1416 Inst.setOpcode(ARM::RFEDA); 1417 break; 1418 case ARM::LDMDA_UPD: 1419 Inst.setOpcode(ARM::RFEDA_UPD); 1420 break; 1421 case ARM::LDMDB: 1422 Inst.setOpcode(ARM::RFEDB); 1423 break; 1424 case ARM::LDMDB_UPD: 1425 Inst.setOpcode(ARM::RFEDB_UPD); 1426 break; 1427 case ARM::LDMIA: 1428 Inst.setOpcode(ARM::RFEIA); 1429 break; 1430 case ARM::LDMIA_UPD: 1431 Inst.setOpcode(ARM::RFEIA_UPD); 1432 break; 1433 case ARM::LDMIB: 1434 Inst.setOpcode(ARM::RFEIB); 1435 break; 1436 case ARM::LDMIB_UPD: 1437 Inst.setOpcode(ARM::RFEIB_UPD); 1438 break; 1439 case ARM::STMDA: 1440 Inst.setOpcode(ARM::SRSDA); 1441 break; 1442 case ARM::STMDA_UPD: 1443 Inst.setOpcode(ARM::SRSDA_UPD); 1444 break; 1445 case ARM::STMDB: 1446 Inst.setOpcode(ARM::SRSDB); 1447 break; 1448 case ARM::STMDB_UPD: 1449 Inst.setOpcode(ARM::SRSDB_UPD); 1450 break; 1451 case ARM::STMIA: 1452 Inst.setOpcode(ARM::SRSIA); 1453 break; 1454 case ARM::STMIA_UPD: 1455 Inst.setOpcode(ARM::SRSIA_UPD); 1456 break; 1457 case ARM::STMIB: 1458 Inst.setOpcode(ARM::SRSIB); 1459 break; 1460 case ARM::STMIB_UPD: 1461 Inst.setOpcode(ARM::SRSIB_UPD); 1462 break; 1463 default: 1464 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1465 } 1466 1467 // For stores (which become SRS's, the only operand is the mode. 1468 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1469 Inst.addOperand( 1470 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1471 return S; 1472 } 1473 1474 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1475 } 1476 1477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1478 return MCDisassembler::Fail; 1479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1480 return MCDisassembler::Fail; // Tied 1481 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1484 return MCDisassembler::Fail; 1485 1486 return S; 1487 } 1488 1489 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1490 uint64_t Address, const void *Decoder) { 1491 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1492 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1493 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1494 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1495 1496 DecodeStatus S = MCDisassembler::Success; 1497 1498 // imod == '01' --> UNPREDICTABLE 1499 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1500 // return failure here. The '01' imod value is unprintable, so there's 1501 // nothing useful we could do even if we returned UNPREDICTABLE. 1502 1503 if (imod == 1) return MCDisassembler::Fail; 1504 1505 if (imod && M) { 1506 Inst.setOpcode(ARM::CPS3p); 1507 Inst.addOperand(MCOperand::CreateImm(imod)); 1508 Inst.addOperand(MCOperand::CreateImm(iflags)); 1509 Inst.addOperand(MCOperand::CreateImm(mode)); 1510 } else if (imod && !M) { 1511 Inst.setOpcode(ARM::CPS2p); 1512 Inst.addOperand(MCOperand::CreateImm(imod)); 1513 Inst.addOperand(MCOperand::CreateImm(iflags)); 1514 if (mode) S = MCDisassembler::SoftFail; 1515 } else if (!imod && M) { 1516 Inst.setOpcode(ARM::CPS1p); 1517 Inst.addOperand(MCOperand::CreateImm(mode)); 1518 if (iflags) S = MCDisassembler::SoftFail; 1519 } else { 1520 // imod == '00' && M == '0' --> UNPREDICTABLE 1521 Inst.setOpcode(ARM::CPS1p); 1522 Inst.addOperand(MCOperand::CreateImm(mode)); 1523 S = MCDisassembler::SoftFail; 1524 } 1525 1526 return S; 1527 } 1528 1529 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1530 uint64_t Address, const void *Decoder) { 1531 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1532 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1533 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1534 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1535 1536 DecodeStatus S = MCDisassembler::Success; 1537 1538 // imod == '01' --> UNPREDICTABLE 1539 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1540 // return failure here. The '01' imod value is unprintable, so there's 1541 // nothing useful we could do even if we returned UNPREDICTABLE. 1542 1543 if (imod == 1) return MCDisassembler::Fail; 1544 1545 if (imod && M) { 1546 Inst.setOpcode(ARM::t2CPS3p); 1547 Inst.addOperand(MCOperand::CreateImm(imod)); 1548 Inst.addOperand(MCOperand::CreateImm(iflags)); 1549 Inst.addOperand(MCOperand::CreateImm(mode)); 1550 } else if (imod && !M) { 1551 Inst.setOpcode(ARM::t2CPS2p); 1552 Inst.addOperand(MCOperand::CreateImm(imod)); 1553 Inst.addOperand(MCOperand::CreateImm(iflags)); 1554 if (mode) S = MCDisassembler::SoftFail; 1555 } else if (!imod && M) { 1556 Inst.setOpcode(ARM::t2CPS1p); 1557 Inst.addOperand(MCOperand::CreateImm(mode)); 1558 if (iflags) S = MCDisassembler::SoftFail; 1559 } else { 1560 // imod == '00' && M == '0' --> UNPREDICTABLE 1561 Inst.setOpcode(ARM::t2CPS1p); 1562 Inst.addOperand(MCOperand::CreateImm(mode)); 1563 S = MCDisassembler::SoftFail; 1564 } 1565 1566 return S; 1567 } 1568 1569 1570 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1571 uint64_t Address, const void *Decoder) { 1572 DecodeStatus S = MCDisassembler::Success; 1573 1574 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1575 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1576 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1577 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1578 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1579 1580 if (pred == 0xF) 1581 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1582 1583 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1584 return MCDisassembler::Fail; 1585 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1586 return MCDisassembler::Fail; 1587 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1588 return MCDisassembler::Fail; 1589 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1590 return MCDisassembler::Fail; 1591 1592 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1593 return MCDisassembler::Fail; 1594 1595 return S; 1596 } 1597 1598 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1599 uint64_t Address, const void *Decoder) { 1600 DecodeStatus S = MCDisassembler::Success; 1601 1602 unsigned add = fieldFromInstruction32(Val, 12, 1); 1603 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1604 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1605 1606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1607 return MCDisassembler::Fail; 1608 1609 if (!add) imm *= -1; 1610 if (imm == 0 && !add) imm = INT32_MIN; 1611 Inst.addOperand(MCOperand::CreateImm(imm)); 1612 1613 return S; 1614 } 1615 1616 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1617 uint64_t Address, const void *Decoder) { 1618 DecodeStatus S = MCDisassembler::Success; 1619 1620 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1621 unsigned U = fieldFromInstruction32(Val, 8, 1); 1622 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1623 1624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1625 return MCDisassembler::Fail; 1626 1627 if (U) 1628 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1629 else 1630 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1631 1632 return S; 1633 } 1634 1635 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1636 uint64_t Address, const void *Decoder) { 1637 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1638 } 1639 1640 static DecodeStatus 1641 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1642 uint64_t Address, const void *Decoder) { 1643 DecodeStatus S = MCDisassembler::Success; 1644 1645 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1646 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1647 1648 if (pred == 0xF) { 1649 Inst.setOpcode(ARM::BLXi); 1650 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1651 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1652 return S; 1653 } 1654 1655 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1656 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1657 return MCDisassembler::Fail; 1658 1659 return S; 1660 } 1661 1662 1663 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1664 uint64_t Address, const void *Decoder) { 1665 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1666 return MCDisassembler::Success; 1667 } 1668 1669 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1670 uint64_t Address, const void *Decoder) { 1671 DecodeStatus S = MCDisassembler::Success; 1672 1673 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1674 unsigned align = fieldFromInstruction32(Val, 4, 2); 1675 1676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1677 return MCDisassembler::Fail; 1678 if (!align) 1679 Inst.addOperand(MCOperand::CreateImm(0)); 1680 else 1681 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1682 1683 return S; 1684 } 1685 1686 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1687 uint64_t Address, const void *Decoder) { 1688 DecodeStatus S = MCDisassembler::Success; 1689 1690 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1691 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1692 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1693 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1694 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1695 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1696 1697 // First output register 1698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1699 return MCDisassembler::Fail; 1700 1701 // Second output register 1702 switch (Inst.getOpcode()) { 1703 case ARM::VLD1q8: 1704 case ARM::VLD1q16: 1705 case ARM::VLD1q32: 1706 case ARM::VLD1q64: 1707 case ARM::VLD1q8_UPD: 1708 case ARM::VLD1q16_UPD: 1709 case ARM::VLD1q32_UPD: 1710 case ARM::VLD1q64_UPD: 1711 case ARM::VLD1d8T: 1712 case ARM::VLD1d16T: 1713 case ARM::VLD1d32T: 1714 case ARM::VLD1d64T: 1715 case ARM::VLD1d8T_UPD: 1716 case ARM::VLD1d16T_UPD: 1717 case ARM::VLD1d32T_UPD: 1718 case ARM::VLD1d64T_UPD: 1719 case ARM::VLD1d8Q: 1720 case ARM::VLD1d16Q: 1721 case ARM::VLD1d32Q: 1722 case ARM::VLD1d64Q: 1723 case ARM::VLD1d8Q_UPD: 1724 case ARM::VLD1d16Q_UPD: 1725 case ARM::VLD1d32Q_UPD: 1726 case ARM::VLD1d64Q_UPD: 1727 case ARM::VLD2d8: 1728 case ARM::VLD2d16: 1729 case ARM::VLD2d32: 1730 case ARM::VLD2d8_UPD: 1731 case ARM::VLD2d16_UPD: 1732 case ARM::VLD2d32_UPD: 1733 case ARM::VLD2q8: 1734 case ARM::VLD2q16: 1735 case ARM::VLD2q32: 1736 case ARM::VLD2q8_UPD: 1737 case ARM::VLD2q16_UPD: 1738 case ARM::VLD2q32_UPD: 1739 case ARM::VLD3d8: 1740 case ARM::VLD3d16: 1741 case ARM::VLD3d32: 1742 case ARM::VLD3d8_UPD: 1743 case ARM::VLD3d16_UPD: 1744 case ARM::VLD3d32_UPD: 1745 case ARM::VLD4d8: 1746 case ARM::VLD4d16: 1747 case ARM::VLD4d32: 1748 case ARM::VLD4d8_UPD: 1749 case ARM::VLD4d16_UPD: 1750 case ARM::VLD4d32_UPD: 1751 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1752 return MCDisassembler::Fail; 1753 break; 1754 case ARM::VLD2b8: 1755 case ARM::VLD2b16: 1756 case ARM::VLD2b32: 1757 case ARM::VLD2b8_UPD: 1758 case ARM::VLD2b16_UPD: 1759 case ARM::VLD2b32_UPD: 1760 case ARM::VLD3q8: 1761 case ARM::VLD3q16: 1762 case ARM::VLD3q32: 1763 case ARM::VLD3q8_UPD: 1764 case ARM::VLD3q16_UPD: 1765 case ARM::VLD3q32_UPD: 1766 case ARM::VLD4q8: 1767 case ARM::VLD4q16: 1768 case ARM::VLD4q32: 1769 case ARM::VLD4q8_UPD: 1770 case ARM::VLD4q16_UPD: 1771 case ARM::VLD4q32_UPD: 1772 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 default: 1775 break; 1776 } 1777 1778 // Third output register 1779 switch(Inst.getOpcode()) { 1780 case ARM::VLD1d8T: 1781 case ARM::VLD1d16T: 1782 case ARM::VLD1d32T: 1783 case ARM::VLD1d64T: 1784 case ARM::VLD1d8T_UPD: 1785 case ARM::VLD1d16T_UPD: 1786 case ARM::VLD1d32T_UPD: 1787 case ARM::VLD1d64T_UPD: 1788 case ARM::VLD1d8Q: 1789 case ARM::VLD1d16Q: 1790 case ARM::VLD1d32Q: 1791 case ARM::VLD1d64Q: 1792 case ARM::VLD1d8Q_UPD: 1793 case ARM::VLD1d16Q_UPD: 1794 case ARM::VLD1d32Q_UPD: 1795 case ARM::VLD1d64Q_UPD: 1796 case ARM::VLD2q8: 1797 case ARM::VLD2q16: 1798 case ARM::VLD2q32: 1799 case ARM::VLD2q8_UPD: 1800 case ARM::VLD2q16_UPD: 1801 case ARM::VLD2q32_UPD: 1802 case ARM::VLD3d8: 1803 case ARM::VLD3d16: 1804 case ARM::VLD3d32: 1805 case ARM::VLD3d8_UPD: 1806 case ARM::VLD3d16_UPD: 1807 case ARM::VLD3d32_UPD: 1808 case ARM::VLD4d8: 1809 case ARM::VLD4d16: 1810 case ARM::VLD4d32: 1811 case ARM::VLD4d8_UPD: 1812 case ARM::VLD4d16_UPD: 1813 case ARM::VLD4d32_UPD: 1814 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1815 return MCDisassembler::Fail; 1816 break; 1817 case ARM::VLD3q8: 1818 case ARM::VLD3q16: 1819 case ARM::VLD3q32: 1820 case ARM::VLD3q8_UPD: 1821 case ARM::VLD3q16_UPD: 1822 case ARM::VLD3q32_UPD: 1823 case ARM::VLD4q8: 1824 case ARM::VLD4q16: 1825 case ARM::VLD4q32: 1826 case ARM::VLD4q8_UPD: 1827 case ARM::VLD4q16_UPD: 1828 case ARM::VLD4q32_UPD: 1829 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1830 return MCDisassembler::Fail; 1831 break; 1832 default: 1833 break; 1834 } 1835 1836 // Fourth output register 1837 switch (Inst.getOpcode()) { 1838 case ARM::VLD1d8Q: 1839 case ARM::VLD1d16Q: 1840 case ARM::VLD1d32Q: 1841 case ARM::VLD1d64Q: 1842 case ARM::VLD1d8Q_UPD: 1843 case ARM::VLD1d16Q_UPD: 1844 case ARM::VLD1d32Q_UPD: 1845 case ARM::VLD1d64Q_UPD: 1846 case ARM::VLD2q8: 1847 case ARM::VLD2q16: 1848 case ARM::VLD2q32: 1849 case ARM::VLD2q8_UPD: 1850 case ARM::VLD2q16_UPD: 1851 case ARM::VLD2q32_UPD: 1852 case ARM::VLD4d8: 1853 case ARM::VLD4d16: 1854 case ARM::VLD4d32: 1855 case ARM::VLD4d8_UPD: 1856 case ARM::VLD4d16_UPD: 1857 case ARM::VLD4d32_UPD: 1858 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1859 return MCDisassembler::Fail; 1860 break; 1861 case ARM::VLD4q8: 1862 case ARM::VLD4q16: 1863 case ARM::VLD4q32: 1864 case ARM::VLD4q8_UPD: 1865 case ARM::VLD4q16_UPD: 1866 case ARM::VLD4q32_UPD: 1867 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1868 return MCDisassembler::Fail; 1869 break; 1870 default: 1871 break; 1872 } 1873 1874 // Writeback operand 1875 switch (Inst.getOpcode()) { 1876 case ARM::VLD1d8_UPD: 1877 case ARM::VLD1d16_UPD: 1878 case ARM::VLD1d32_UPD: 1879 case ARM::VLD1d64_UPD: 1880 case ARM::VLD1q8_UPD: 1881 case ARM::VLD1q16_UPD: 1882 case ARM::VLD1q32_UPD: 1883 case ARM::VLD1q64_UPD: 1884 case ARM::VLD1d8T_UPD: 1885 case ARM::VLD1d16T_UPD: 1886 case ARM::VLD1d32T_UPD: 1887 case ARM::VLD1d64T_UPD: 1888 case ARM::VLD1d8Q_UPD: 1889 case ARM::VLD1d16Q_UPD: 1890 case ARM::VLD1d32Q_UPD: 1891 case ARM::VLD1d64Q_UPD: 1892 case ARM::VLD2d8_UPD: 1893 case ARM::VLD2d16_UPD: 1894 case ARM::VLD2d32_UPD: 1895 case ARM::VLD2q8_UPD: 1896 case ARM::VLD2q16_UPD: 1897 case ARM::VLD2q32_UPD: 1898 case ARM::VLD2b8_UPD: 1899 case ARM::VLD2b16_UPD: 1900 case ARM::VLD2b32_UPD: 1901 case ARM::VLD3d8_UPD: 1902 case ARM::VLD3d16_UPD: 1903 case ARM::VLD3d32_UPD: 1904 case ARM::VLD3q8_UPD: 1905 case ARM::VLD3q16_UPD: 1906 case ARM::VLD3q32_UPD: 1907 case ARM::VLD4d8_UPD: 1908 case ARM::VLD4d16_UPD: 1909 case ARM::VLD4d32_UPD: 1910 case ARM::VLD4q8_UPD: 1911 case ARM::VLD4q16_UPD: 1912 case ARM::VLD4q32_UPD: 1913 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1914 return MCDisassembler::Fail; 1915 break; 1916 default: 1917 break; 1918 } 1919 1920 // AddrMode6 Base (register+alignment) 1921 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1922 return MCDisassembler::Fail; 1923 1924 // AddrMode6 Offset (register) 1925 if (Rm == 0xD) 1926 Inst.addOperand(MCOperand::CreateReg(0)); 1927 else if (Rm != 0xF) { 1928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1929 return MCDisassembler::Fail; 1930 } 1931 1932 return S; 1933 } 1934 1935 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1936 uint64_t Address, const void *Decoder) { 1937 DecodeStatus S = MCDisassembler::Success; 1938 1939 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1940 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1941 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1942 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1943 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1944 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1945 1946 // Writeback Operand 1947 switch (Inst.getOpcode()) { 1948 case ARM::VST1d8_UPD: 1949 case ARM::VST1d16_UPD: 1950 case ARM::VST1d32_UPD: 1951 case ARM::VST1d64_UPD: 1952 case ARM::VST1q8_UPD: 1953 case ARM::VST1q16_UPD: 1954 case ARM::VST1q32_UPD: 1955 case ARM::VST1q64_UPD: 1956 case ARM::VST1d8T_UPD: 1957 case ARM::VST1d16T_UPD: 1958 case ARM::VST1d32T_UPD: 1959 case ARM::VST1d64T_UPD: 1960 case ARM::VST1d8Q_UPD: 1961 case ARM::VST1d16Q_UPD: 1962 case ARM::VST1d32Q_UPD: 1963 case ARM::VST1d64Q_UPD: 1964 case ARM::VST2d8_UPD: 1965 case ARM::VST2d16_UPD: 1966 case ARM::VST2d32_UPD: 1967 case ARM::VST2q8_UPD: 1968 case ARM::VST2q16_UPD: 1969 case ARM::VST2q32_UPD: 1970 case ARM::VST2b8_UPD: 1971 case ARM::VST2b16_UPD: 1972 case ARM::VST2b32_UPD: 1973 case ARM::VST3d8_UPD: 1974 case ARM::VST3d16_UPD: 1975 case ARM::VST3d32_UPD: 1976 case ARM::VST3q8_UPD: 1977 case ARM::VST3q16_UPD: 1978 case ARM::VST3q32_UPD: 1979 case ARM::VST4d8_UPD: 1980 case ARM::VST4d16_UPD: 1981 case ARM::VST4d32_UPD: 1982 case ARM::VST4q8_UPD: 1983 case ARM::VST4q16_UPD: 1984 case ARM::VST4q32_UPD: 1985 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1986 return MCDisassembler::Fail; 1987 break; 1988 default: 1989 break; 1990 } 1991 1992 // AddrMode6 Base (register+alignment) 1993 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1994 return MCDisassembler::Fail; 1995 1996 // AddrMode6 Offset (register) 1997 if (Rm == 0xD) 1998 Inst.addOperand(MCOperand::CreateReg(0)); 1999 else if (Rm != 0xF) { 2000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2001 return MCDisassembler::Fail; 2002 } 2003 2004 // First input register 2005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2006 return MCDisassembler::Fail; 2007 2008 // Second input register 2009 switch (Inst.getOpcode()) { 2010 case ARM::VST1q8: 2011 case ARM::VST1q16: 2012 case ARM::VST1q32: 2013 case ARM::VST1q64: 2014 case ARM::VST1q8_UPD: 2015 case ARM::VST1q16_UPD: 2016 case ARM::VST1q32_UPD: 2017 case ARM::VST1q64_UPD: 2018 case ARM::VST1d8T: 2019 case ARM::VST1d16T: 2020 case ARM::VST1d32T: 2021 case ARM::VST1d64T: 2022 case ARM::VST1d8T_UPD: 2023 case ARM::VST1d16T_UPD: 2024 case ARM::VST1d32T_UPD: 2025 case ARM::VST1d64T_UPD: 2026 case ARM::VST1d8Q: 2027 case ARM::VST1d16Q: 2028 case ARM::VST1d32Q: 2029 case ARM::VST1d64Q: 2030 case ARM::VST1d8Q_UPD: 2031 case ARM::VST1d16Q_UPD: 2032 case ARM::VST1d32Q_UPD: 2033 case ARM::VST1d64Q_UPD: 2034 case ARM::VST2d8: 2035 case ARM::VST2d16: 2036 case ARM::VST2d32: 2037 case ARM::VST2d8_UPD: 2038 case ARM::VST2d16_UPD: 2039 case ARM::VST2d32_UPD: 2040 case ARM::VST2q8: 2041 case ARM::VST2q16: 2042 case ARM::VST2q32: 2043 case ARM::VST2q8_UPD: 2044 case ARM::VST2q16_UPD: 2045 case ARM::VST2q32_UPD: 2046 case ARM::VST3d8: 2047 case ARM::VST3d16: 2048 case ARM::VST3d32: 2049 case ARM::VST3d8_UPD: 2050 case ARM::VST3d16_UPD: 2051 case ARM::VST3d32_UPD: 2052 case ARM::VST4d8: 2053 case ARM::VST4d16: 2054 case ARM::VST4d32: 2055 case ARM::VST4d8_UPD: 2056 case ARM::VST4d16_UPD: 2057 case ARM::VST4d32_UPD: 2058 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 break; 2061 case ARM::VST2b8: 2062 case ARM::VST2b16: 2063 case ARM::VST2b32: 2064 case ARM::VST2b8_UPD: 2065 case ARM::VST2b16_UPD: 2066 case ARM::VST2b32_UPD: 2067 case ARM::VST3q8: 2068 case ARM::VST3q16: 2069 case ARM::VST3q32: 2070 case ARM::VST3q8_UPD: 2071 case ARM::VST3q16_UPD: 2072 case ARM::VST3q32_UPD: 2073 case ARM::VST4q8: 2074 case ARM::VST4q16: 2075 case ARM::VST4q32: 2076 case ARM::VST4q8_UPD: 2077 case ARM::VST4q16_UPD: 2078 case ARM::VST4q32_UPD: 2079 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 break; 2082 default: 2083 break; 2084 } 2085 2086 // Third input register 2087 switch (Inst.getOpcode()) { 2088 case ARM::VST1d8T: 2089 case ARM::VST1d16T: 2090 case ARM::VST1d32T: 2091 case ARM::VST1d64T: 2092 case ARM::VST1d8T_UPD: 2093 case ARM::VST1d16T_UPD: 2094 case ARM::VST1d32T_UPD: 2095 case ARM::VST1d64T_UPD: 2096 case ARM::VST1d8Q: 2097 case ARM::VST1d16Q: 2098 case ARM::VST1d32Q: 2099 case ARM::VST1d64Q: 2100 case ARM::VST1d8Q_UPD: 2101 case ARM::VST1d16Q_UPD: 2102 case ARM::VST1d32Q_UPD: 2103 case ARM::VST1d64Q_UPD: 2104 case ARM::VST2q8: 2105 case ARM::VST2q16: 2106 case ARM::VST2q32: 2107 case ARM::VST2q8_UPD: 2108 case ARM::VST2q16_UPD: 2109 case ARM::VST2q32_UPD: 2110 case ARM::VST3d8: 2111 case ARM::VST3d16: 2112 case ARM::VST3d32: 2113 case ARM::VST3d8_UPD: 2114 case ARM::VST3d16_UPD: 2115 case ARM::VST3d32_UPD: 2116 case ARM::VST4d8: 2117 case ARM::VST4d16: 2118 case ARM::VST4d32: 2119 case ARM::VST4d8_UPD: 2120 case ARM::VST4d16_UPD: 2121 case ARM::VST4d32_UPD: 2122 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2123 return MCDisassembler::Fail; 2124 break; 2125 case ARM::VST3q8: 2126 case ARM::VST3q16: 2127 case ARM::VST3q32: 2128 case ARM::VST3q8_UPD: 2129 case ARM::VST3q16_UPD: 2130 case ARM::VST3q32_UPD: 2131 case ARM::VST4q8: 2132 case ARM::VST4q16: 2133 case ARM::VST4q32: 2134 case ARM::VST4q8_UPD: 2135 case ARM::VST4q16_UPD: 2136 case ARM::VST4q32_UPD: 2137 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 break; 2140 default: 2141 break; 2142 } 2143 2144 // Fourth input register 2145 switch (Inst.getOpcode()) { 2146 case ARM::VST1d8Q: 2147 case ARM::VST1d16Q: 2148 case ARM::VST1d32Q: 2149 case ARM::VST1d64Q: 2150 case ARM::VST1d8Q_UPD: 2151 case ARM::VST1d16Q_UPD: 2152 case ARM::VST1d32Q_UPD: 2153 case ARM::VST1d64Q_UPD: 2154 case ARM::VST2q8: 2155 case ARM::VST2q16: 2156 case ARM::VST2q32: 2157 case ARM::VST2q8_UPD: 2158 case ARM::VST2q16_UPD: 2159 case ARM::VST2q32_UPD: 2160 case ARM::VST4d8: 2161 case ARM::VST4d16: 2162 case ARM::VST4d32: 2163 case ARM::VST4d8_UPD: 2164 case ARM::VST4d16_UPD: 2165 case ARM::VST4d32_UPD: 2166 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2167 return MCDisassembler::Fail; 2168 break; 2169 case ARM::VST4q8: 2170 case ARM::VST4q16: 2171 case ARM::VST4q32: 2172 case ARM::VST4q8_UPD: 2173 case ARM::VST4q16_UPD: 2174 case ARM::VST4q32_UPD: 2175 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2176 return MCDisassembler::Fail; 2177 break; 2178 default: 2179 break; 2180 } 2181 2182 return S; 2183 } 2184 2185 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2186 uint64_t Address, const void *Decoder) { 2187 DecodeStatus S = MCDisassembler::Success; 2188 2189 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2190 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2191 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2192 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2193 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2194 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2195 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2196 2197 align *= (1 << size); 2198 2199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 if (regs == 2) { 2202 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2203 return MCDisassembler::Fail; 2204 } 2205 if (Rm != 0xF) { 2206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 } 2209 2210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2211 return MCDisassembler::Fail; 2212 Inst.addOperand(MCOperand::CreateImm(align)); 2213 2214 if (Rm == 0xD) 2215 Inst.addOperand(MCOperand::CreateReg(0)); 2216 else if (Rm != 0xF) { 2217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 } 2220 2221 return S; 2222 } 2223 2224 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2225 uint64_t Address, const void *Decoder) { 2226 DecodeStatus S = MCDisassembler::Success; 2227 2228 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2229 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2230 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2231 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2232 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2233 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2234 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2235 align *= 2*size; 2236 2237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2238 return MCDisassembler::Fail; 2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 if (Rm != 0xF) { 2242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2243 return MCDisassembler::Fail; 2244 } 2245 2246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2247 return MCDisassembler::Fail; 2248 Inst.addOperand(MCOperand::CreateImm(align)); 2249 2250 if (Rm == 0xD) 2251 Inst.addOperand(MCOperand::CreateReg(0)); 2252 else if (Rm != 0xF) { 2253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2254 return MCDisassembler::Fail; 2255 } 2256 2257 return S; 2258 } 2259 2260 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2261 uint64_t Address, const void *Decoder) { 2262 DecodeStatus S = MCDisassembler::Success; 2263 2264 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2265 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2266 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2267 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2268 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2269 2270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2273 return MCDisassembler::Fail; 2274 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2275 return MCDisassembler::Fail; 2276 if (Rm != 0xF) { 2277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2278 return MCDisassembler::Fail; 2279 } 2280 2281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2282 return MCDisassembler::Fail; 2283 Inst.addOperand(MCOperand::CreateImm(0)); 2284 2285 if (Rm == 0xD) 2286 Inst.addOperand(MCOperand::CreateReg(0)); 2287 else if (Rm != 0xF) { 2288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2289 return MCDisassembler::Fail; 2290 } 2291 2292 return S; 2293 } 2294 2295 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2296 uint64_t Address, const void *Decoder) { 2297 DecodeStatus S = MCDisassembler::Success; 2298 2299 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2300 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2301 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2302 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2303 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2304 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2305 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2306 2307 if (size == 0x3) { 2308 size = 4; 2309 align = 16; 2310 } else { 2311 if (size == 2) { 2312 size = 1 << size; 2313 align *= 8; 2314 } else { 2315 size = 1 << size; 2316 align *= 4*size; 2317 } 2318 } 2319 2320 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2323 return MCDisassembler::Fail; 2324 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2325 return MCDisassembler::Fail; 2326 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2327 return MCDisassembler::Fail; 2328 if (Rm != 0xF) { 2329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2330 return MCDisassembler::Fail; 2331 } 2332 2333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2334 return MCDisassembler::Fail; 2335 Inst.addOperand(MCOperand::CreateImm(align)); 2336 2337 if (Rm == 0xD) 2338 Inst.addOperand(MCOperand::CreateReg(0)); 2339 else if (Rm != 0xF) { 2340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2341 return MCDisassembler::Fail; 2342 } 2343 2344 return S; 2345 } 2346 2347 static DecodeStatus 2348 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2349 uint64_t Address, const void *Decoder) { 2350 DecodeStatus S = MCDisassembler::Success; 2351 2352 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2353 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2354 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2355 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2356 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2357 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2358 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2359 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2360 2361 if (Q) { 2362 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2363 return MCDisassembler::Fail; 2364 } else { 2365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2366 return MCDisassembler::Fail; 2367 } 2368 2369 Inst.addOperand(MCOperand::CreateImm(imm)); 2370 2371 switch (Inst.getOpcode()) { 2372 case ARM::VORRiv4i16: 2373 case ARM::VORRiv2i32: 2374 case ARM::VBICiv4i16: 2375 case ARM::VBICiv2i32: 2376 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 break; 2379 case ARM::VORRiv8i16: 2380 case ARM::VORRiv4i32: 2381 case ARM::VBICiv8i16: 2382 case ARM::VBICiv4i32: 2383 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 break; 2386 default: 2387 break; 2388 } 2389 2390 return S; 2391 } 2392 2393 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2394 uint64_t Address, const void *Decoder) { 2395 DecodeStatus S = MCDisassembler::Success; 2396 2397 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2398 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2399 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2400 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2401 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2402 2403 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2404 return MCDisassembler::Fail; 2405 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2406 return MCDisassembler::Fail; 2407 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2408 2409 return S; 2410 } 2411 2412 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2413 uint64_t Address, const void *Decoder) { 2414 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2415 return MCDisassembler::Success; 2416 } 2417 2418 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2419 uint64_t Address, const void *Decoder) { 2420 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2421 return MCDisassembler::Success; 2422 } 2423 2424 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2425 uint64_t Address, const void *Decoder) { 2426 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2427 return MCDisassembler::Success; 2428 } 2429 2430 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2431 uint64_t Address, const void *Decoder) { 2432 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2433 return MCDisassembler::Success; 2434 } 2435 2436 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2437 uint64_t Address, const void *Decoder) { 2438 DecodeStatus S = MCDisassembler::Success; 2439 2440 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2441 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2442 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2443 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2444 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2445 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2446 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2447 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2448 2449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2450 return MCDisassembler::Fail; 2451 if (op) { 2452 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2453 return MCDisassembler::Fail; // Writeback 2454 } 2455 2456 for (unsigned i = 0; i < length; ++i) { 2457 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 } 2460 2461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2462 return MCDisassembler::Fail; 2463 2464 return S; 2465 } 2466 2467 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2468 uint64_t Address, const void *Decoder) { 2469 // The immediate needs to be a fully instantiated float. However, the 2470 // auto-generated decoder is only able to fill in some of the bits 2471 // necessary. For instance, the 'b' bit is replicated multiple times, 2472 // and is even present in inverted form in one bit. We do a little 2473 // binary parsing here to fill in those missing bits, and then 2474 // reinterpret it all as a float. 2475 union { 2476 uint32_t integer; 2477 float fp; 2478 } fp_conv; 2479 2480 fp_conv.integer = Val; 2481 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2482 fp_conv.integer |= b << 26; 2483 fp_conv.integer |= b << 27; 2484 fp_conv.integer |= b << 28; 2485 fp_conv.integer |= b << 29; 2486 fp_conv.integer |= (~b & 0x1) << 30; 2487 2488 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2489 return MCDisassembler::Success; 2490 } 2491 2492 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2493 uint64_t Address, const void *Decoder) { 2494 DecodeStatus S = MCDisassembler::Success; 2495 2496 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2497 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2498 2499 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2500 return MCDisassembler::Fail; 2501 2502 switch(Inst.getOpcode()) { 2503 default: 2504 return MCDisassembler::Fail; 2505 case ARM::tADR: 2506 break; // tADR does not explicitly represent the PC as an operand. 2507 case ARM::tADDrSPi: 2508 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2509 break; 2510 } 2511 2512 Inst.addOperand(MCOperand::CreateImm(imm)); 2513 return S; 2514 } 2515 2516 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2517 uint64_t Address, const void *Decoder) { 2518 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2519 return MCDisassembler::Success; 2520 } 2521 2522 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2523 uint64_t Address, const void *Decoder) { 2524 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2525 return MCDisassembler::Success; 2526 } 2527 2528 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2529 uint64_t Address, const void *Decoder) { 2530 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2531 return MCDisassembler::Success; 2532 } 2533 2534 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2535 uint64_t Address, const void *Decoder) { 2536 DecodeStatus S = MCDisassembler::Success; 2537 2538 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2539 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2540 2541 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2542 return MCDisassembler::Fail; 2543 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2544 return MCDisassembler::Fail; 2545 2546 return S; 2547 } 2548 2549 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2550 uint64_t Address, const void *Decoder) { 2551 DecodeStatus S = MCDisassembler::Success; 2552 2553 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2554 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2555 2556 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2557 return MCDisassembler::Fail; 2558 Inst.addOperand(MCOperand::CreateImm(imm)); 2559 2560 return S; 2561 } 2562 2563 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2564 uint64_t Address, const void *Decoder) { 2565 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2566 2567 return MCDisassembler::Success; 2568 } 2569 2570 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2571 uint64_t Address, const void *Decoder) { 2572 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2573 Inst.addOperand(MCOperand::CreateImm(Val)); 2574 2575 return MCDisassembler::Success; 2576 } 2577 2578 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2579 uint64_t Address, const void *Decoder) { 2580 DecodeStatus S = MCDisassembler::Success; 2581 2582 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2583 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2584 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2585 2586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2587 return MCDisassembler::Fail; 2588 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2589 return MCDisassembler::Fail; 2590 Inst.addOperand(MCOperand::CreateImm(imm)); 2591 2592 return S; 2593 } 2594 2595 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2596 uint64_t Address, const void *Decoder) { 2597 DecodeStatus S = MCDisassembler::Success; 2598 2599 switch (Inst.getOpcode()) { 2600 case ARM::t2PLDs: 2601 case ARM::t2PLDWs: 2602 case ARM::t2PLIs: 2603 break; 2604 default: { 2605 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2607 return MCDisassembler::Fail; 2608 } 2609 } 2610 2611 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2612 if (Rn == 0xF) { 2613 switch (Inst.getOpcode()) { 2614 case ARM::t2LDRBs: 2615 Inst.setOpcode(ARM::t2LDRBpci); 2616 break; 2617 case ARM::t2LDRHs: 2618 Inst.setOpcode(ARM::t2LDRHpci); 2619 break; 2620 case ARM::t2LDRSHs: 2621 Inst.setOpcode(ARM::t2LDRSHpci); 2622 break; 2623 case ARM::t2LDRSBs: 2624 Inst.setOpcode(ARM::t2LDRSBpci); 2625 break; 2626 case ARM::t2PLDs: 2627 Inst.setOpcode(ARM::t2PLDi12); 2628 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2629 break; 2630 default: 2631 return MCDisassembler::Fail; 2632 } 2633 2634 int imm = fieldFromInstruction32(Insn, 0, 12); 2635 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2636 Inst.addOperand(MCOperand::CreateImm(imm)); 2637 2638 return S; 2639 } 2640 2641 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2642 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2643 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2644 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2645 return MCDisassembler::Fail; 2646 2647 return S; 2648 } 2649 2650 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2651 uint64_t Address, const void *Decoder) { 2652 int imm = Val & 0xFF; 2653 if (!(Val & 0x100)) imm *= -1; 2654 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2655 2656 return MCDisassembler::Success; 2657 } 2658 2659 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2660 uint64_t Address, const void *Decoder) { 2661 DecodeStatus S = MCDisassembler::Success; 2662 2663 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2664 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2665 2666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2667 return MCDisassembler::Fail; 2668 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2669 return MCDisassembler::Fail; 2670 2671 return S; 2672 } 2673 2674 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2675 uint64_t Address, const void *Decoder) { 2676 DecodeStatus S = MCDisassembler::Success; 2677 2678 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2679 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2680 2681 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 2684 Inst.addOperand(MCOperand::CreateImm(imm)); 2685 2686 return S; 2687 } 2688 2689 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2690 uint64_t Address, const void *Decoder) { 2691 int imm = Val & 0xFF; 2692 if (!(Val & 0x100)) imm *= -1; 2693 Inst.addOperand(MCOperand::CreateImm(imm)); 2694 2695 return MCDisassembler::Success; 2696 } 2697 2698 2699 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2700 uint64_t Address, const void *Decoder) { 2701 DecodeStatus S = MCDisassembler::Success; 2702 2703 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2704 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2705 2706 // Some instructions always use an additive offset. 2707 switch (Inst.getOpcode()) { 2708 case ARM::t2LDRT: 2709 case ARM::t2LDRBT: 2710 case ARM::t2LDRHT: 2711 case ARM::t2LDRSBT: 2712 case ARM::t2LDRSHT: 2713 imm |= 0x100; 2714 break; 2715 default: 2716 break; 2717 } 2718 2719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 2724 return S; 2725 } 2726 2727 2728 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2729 uint64_t Address, const void *Decoder) { 2730 DecodeStatus S = MCDisassembler::Success; 2731 2732 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2733 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2734 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 Inst.addOperand(MCOperand::CreateImm(imm)); 2738 2739 return S; 2740 } 2741 2742 2743 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2744 uint64_t Address, const void *Decoder) { 2745 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2746 2747 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2748 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2749 Inst.addOperand(MCOperand::CreateImm(imm)); 2750 2751 return MCDisassembler::Success; 2752 } 2753 2754 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2755 uint64_t Address, const void *Decoder) { 2756 DecodeStatus S = MCDisassembler::Success; 2757 2758 if (Inst.getOpcode() == ARM::tADDrSP) { 2759 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2760 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2761 2762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2763 return MCDisassembler::Fail; 2764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2765 return MCDisassembler::Fail; 2766 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2767 } else if (Inst.getOpcode() == ARM::tADDspr) { 2768 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2769 2770 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2771 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2773 return MCDisassembler::Fail; 2774 } 2775 2776 return S; 2777 } 2778 2779 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2780 uint64_t Address, const void *Decoder) { 2781 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2782 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2783 2784 Inst.addOperand(MCOperand::CreateImm(imod)); 2785 Inst.addOperand(MCOperand::CreateImm(flags)); 2786 2787 return MCDisassembler::Success; 2788 } 2789 2790 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2791 uint64_t Address, const void *Decoder) { 2792 DecodeStatus S = MCDisassembler::Success; 2793 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2794 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2795 2796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2797 return MCDisassembler::Fail; 2798 Inst.addOperand(MCOperand::CreateImm(add)); 2799 2800 return S; 2801 } 2802 2803 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2804 uint64_t Address, const void *Decoder) { 2805 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2806 return MCDisassembler::Success; 2807 } 2808 2809 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2810 uint64_t Address, const void *Decoder) { 2811 if (Val == 0xA || Val == 0xB) 2812 return MCDisassembler::Fail; 2813 2814 Inst.addOperand(MCOperand::CreateImm(Val)); 2815 return MCDisassembler::Success; 2816 } 2817 2818 static DecodeStatus 2819 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2820 uint64_t Address, const void *Decoder) { 2821 DecodeStatus S = MCDisassembler::Success; 2822 2823 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2824 if (pred == 0xE || pred == 0xF) { 2825 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2826 switch (opc) { 2827 default: 2828 return MCDisassembler::Fail; 2829 case 0xf3bf8f4: 2830 Inst.setOpcode(ARM::t2DSB); 2831 break; 2832 case 0xf3bf8f5: 2833 Inst.setOpcode(ARM::t2DMB); 2834 break; 2835 case 0xf3bf8f6: 2836 Inst.setOpcode(ARM::t2ISB); 2837 break; 2838 } 2839 2840 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2841 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2842 } 2843 2844 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2845 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2846 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2847 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2848 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2849 2850 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2851 return MCDisassembler::Fail; 2852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2853 return MCDisassembler::Fail; 2854 2855 return S; 2856 } 2857 2858 // Decode a shifted immediate operand. These basically consist 2859 // of an 8-bit value, and a 4-bit directive that specifies either 2860 // a splat operation or a rotation. 2861 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2862 uint64_t Address, const void *Decoder) { 2863 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2864 if (ctrl == 0) { 2865 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2866 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2867 switch (byte) { 2868 case 0: 2869 Inst.addOperand(MCOperand::CreateImm(imm)); 2870 break; 2871 case 1: 2872 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2873 break; 2874 case 2: 2875 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2876 break; 2877 case 3: 2878 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2879 (imm << 8) | imm)); 2880 break; 2881 } 2882 } else { 2883 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2884 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2885 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2886 Inst.addOperand(MCOperand::CreateImm(imm)); 2887 } 2888 2889 return MCDisassembler::Success; 2890 } 2891 2892 static DecodeStatus 2893 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2894 uint64_t Address, const void *Decoder){ 2895 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2896 return MCDisassembler::Success; 2897 } 2898 2899 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2900 uint64_t Address, const void *Decoder){ 2901 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2902 return MCDisassembler::Success; 2903 } 2904 2905 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2906 uint64_t Address, const void *Decoder) { 2907 switch (Val) { 2908 default: 2909 return MCDisassembler::Fail; 2910 case 0xF: // SY 2911 case 0xE: // ST 2912 case 0xB: // ISH 2913 case 0xA: // ISHST 2914 case 0x7: // NSH 2915 case 0x6: // NSHST 2916 case 0x3: // OSH 2917 case 0x2: // OSHST 2918 break; 2919 } 2920 2921 Inst.addOperand(MCOperand::CreateImm(Val)); 2922 return MCDisassembler::Success; 2923 } 2924 2925 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2926 uint64_t Address, const void *Decoder) { 2927 if (!Val) return MCDisassembler::Fail; 2928 Inst.addOperand(MCOperand::CreateImm(Val)); 2929 return MCDisassembler::Success; 2930 } 2931 2932 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2933 uint64_t Address, const void *Decoder) { 2934 DecodeStatus S = MCDisassembler::Success; 2935 2936 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2937 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2938 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2939 2940 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2941 2942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2943 return MCDisassembler::Fail; 2944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2949 return MCDisassembler::Fail; 2950 2951 return S; 2952 } 2953 2954 2955 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2956 uint64_t Address, const void *Decoder){ 2957 DecodeStatus S = MCDisassembler::Success; 2958 2959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2960 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2961 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2962 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2963 2964 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2965 return MCDisassembler::Fail; 2966 2967 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2968 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 2969 2970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 2979 return S; 2980 } 2981 2982 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 2983 uint64_t Address, const void *Decoder) { 2984 DecodeStatus S = MCDisassembler::Success; 2985 2986 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2987 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2988 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2989 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2990 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2991 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2992 2993 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2994 2995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2996 return MCDisassembler::Fail; 2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 3004 return S; 3005 } 3006 3007 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3008 uint64_t Address, const void *Decoder) { 3009 DecodeStatus S = MCDisassembler::Success; 3010 3011 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3012 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3013 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3014 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3015 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3016 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3017 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3018 3019 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3020 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3021 3022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 3031 return S; 3032 } 3033 3034 3035 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3036 uint64_t Address, const void *Decoder) { 3037 DecodeStatus S = MCDisassembler::Success; 3038 3039 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3040 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3041 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3042 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3043 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3044 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3045 3046 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3047 3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3053 return MCDisassembler::Fail; 3054 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3055 return MCDisassembler::Fail; 3056 3057 return S; 3058 } 3059 3060 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3061 uint64_t Address, const void *Decoder) { 3062 DecodeStatus S = MCDisassembler::Success; 3063 3064 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3065 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3066 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3067 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3068 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3069 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3070 3071 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3072 3073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 3082 return S; 3083 } 3084 3085 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3086 uint64_t Address, const void *Decoder) { 3087 DecodeStatus S = MCDisassembler::Success; 3088 3089 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3090 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3091 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3092 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3093 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3094 3095 unsigned align = 0; 3096 unsigned index = 0; 3097 switch (size) { 3098 default: 3099 return MCDisassembler::Fail; 3100 case 0: 3101 if (fieldFromInstruction32(Insn, 4, 1)) 3102 return MCDisassembler::Fail; // UNDEFINED 3103 index = fieldFromInstruction32(Insn, 5, 3); 3104 break; 3105 case 1: 3106 if (fieldFromInstruction32(Insn, 5, 1)) 3107 return MCDisassembler::Fail; // UNDEFINED 3108 index = fieldFromInstruction32(Insn, 6, 2); 3109 if (fieldFromInstruction32(Insn, 4, 1)) 3110 align = 2; 3111 break; 3112 case 2: 3113 if (fieldFromInstruction32(Insn, 6, 1)) 3114 return MCDisassembler::Fail; // UNDEFINED 3115 index = fieldFromInstruction32(Insn, 7, 1); 3116 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3117 align = 4; 3118 } 3119 3120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3121 return MCDisassembler::Fail; 3122 if (Rm != 0xF) { // Writeback 3123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 } 3126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3127 return MCDisassembler::Fail; 3128 Inst.addOperand(MCOperand::CreateImm(align)); 3129 if (Rm != 0xF) { 3130 if (Rm != 0xD) { 3131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 } else 3134 Inst.addOperand(MCOperand::CreateReg(0)); 3135 } 3136 3137 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3138 return MCDisassembler::Fail; 3139 Inst.addOperand(MCOperand::CreateImm(index)); 3140 3141 return S; 3142 } 3143 3144 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3145 uint64_t Address, const void *Decoder) { 3146 DecodeStatus S = MCDisassembler::Success; 3147 3148 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3149 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3150 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3151 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3152 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3153 3154 unsigned align = 0; 3155 unsigned index = 0; 3156 switch (size) { 3157 default: 3158 return MCDisassembler::Fail; 3159 case 0: 3160 if (fieldFromInstruction32(Insn, 4, 1)) 3161 return MCDisassembler::Fail; // UNDEFINED 3162 index = fieldFromInstruction32(Insn, 5, 3); 3163 break; 3164 case 1: 3165 if (fieldFromInstruction32(Insn, 5, 1)) 3166 return MCDisassembler::Fail; // UNDEFINED 3167 index = fieldFromInstruction32(Insn, 6, 2); 3168 if (fieldFromInstruction32(Insn, 4, 1)) 3169 align = 2; 3170 break; 3171 case 2: 3172 if (fieldFromInstruction32(Insn, 6, 1)) 3173 return MCDisassembler::Fail; // UNDEFINED 3174 index = fieldFromInstruction32(Insn, 7, 1); 3175 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3176 align = 4; 3177 } 3178 3179 if (Rm != 0xF) { // Writeback 3180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3181 return MCDisassembler::Fail; 3182 } 3183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3184 return MCDisassembler::Fail; 3185 Inst.addOperand(MCOperand::CreateImm(align)); 3186 if (Rm != 0xF) { 3187 if (Rm != 0xD) { 3188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 } else 3191 Inst.addOperand(MCOperand::CreateReg(0)); 3192 } 3193 3194 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3195 return MCDisassembler::Fail; 3196 Inst.addOperand(MCOperand::CreateImm(index)); 3197 3198 return S; 3199 } 3200 3201 3202 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3203 uint64_t Address, const void *Decoder) { 3204 DecodeStatus S = MCDisassembler::Success; 3205 3206 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3207 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3209 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3210 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3211 3212 unsigned align = 0; 3213 unsigned index = 0; 3214 unsigned inc = 1; 3215 switch (size) { 3216 default: 3217 return MCDisassembler::Fail; 3218 case 0: 3219 index = fieldFromInstruction32(Insn, 5, 3); 3220 if (fieldFromInstruction32(Insn, 4, 1)) 3221 align = 2; 3222 break; 3223 case 1: 3224 index = fieldFromInstruction32(Insn, 6, 2); 3225 if (fieldFromInstruction32(Insn, 4, 1)) 3226 align = 4; 3227 if (fieldFromInstruction32(Insn, 5, 1)) 3228 inc = 2; 3229 break; 3230 case 2: 3231 if (fieldFromInstruction32(Insn, 5, 1)) 3232 return MCDisassembler::Fail; // UNDEFINED 3233 index = fieldFromInstruction32(Insn, 7, 1); 3234 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3235 align = 8; 3236 if (fieldFromInstruction32(Insn, 6, 1)) 3237 inc = 2; 3238 break; 3239 } 3240 3241 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3242 return MCDisassembler::Fail; 3243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 if (Rm != 0xF) { // Writeback 3246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 } 3249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3250 return MCDisassembler::Fail; 3251 Inst.addOperand(MCOperand::CreateImm(align)); 3252 if (Rm != 0xF) { 3253 if (Rm != 0xD) { 3254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 } else 3257 Inst.addOperand(MCOperand::CreateReg(0)); 3258 } 3259 3260 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3263 return MCDisassembler::Fail; 3264 Inst.addOperand(MCOperand::CreateImm(index)); 3265 3266 return S; 3267 } 3268 3269 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3270 uint64_t Address, const void *Decoder) { 3271 DecodeStatus S = MCDisassembler::Success; 3272 3273 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3274 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3275 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3276 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3277 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3278 3279 unsigned align = 0; 3280 unsigned index = 0; 3281 unsigned inc = 1; 3282 switch (size) { 3283 default: 3284 return MCDisassembler::Fail; 3285 case 0: 3286 index = fieldFromInstruction32(Insn, 5, 3); 3287 if (fieldFromInstruction32(Insn, 4, 1)) 3288 align = 2; 3289 break; 3290 case 1: 3291 index = fieldFromInstruction32(Insn, 6, 2); 3292 if (fieldFromInstruction32(Insn, 4, 1)) 3293 align = 4; 3294 if (fieldFromInstruction32(Insn, 5, 1)) 3295 inc = 2; 3296 break; 3297 case 2: 3298 if (fieldFromInstruction32(Insn, 5, 1)) 3299 return MCDisassembler::Fail; // UNDEFINED 3300 index = fieldFromInstruction32(Insn, 7, 1); 3301 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3302 align = 8; 3303 if (fieldFromInstruction32(Insn, 6, 1)) 3304 inc = 2; 3305 break; 3306 } 3307 3308 if (Rm != 0xF) { // Writeback 3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 } 3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 Inst.addOperand(MCOperand::CreateImm(align)); 3315 if (Rm != 0xF) { 3316 if (Rm != 0xD) { 3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 } else 3320 Inst.addOperand(MCOperand::CreateReg(0)); 3321 } 3322 3323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 Inst.addOperand(MCOperand::CreateImm(index)); 3328 3329 return S; 3330 } 3331 3332 3333 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3334 uint64_t Address, const void *Decoder) { 3335 DecodeStatus S = MCDisassembler::Success; 3336 3337 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3338 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3339 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3340 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3341 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3342 3343 unsigned align = 0; 3344 unsigned index = 0; 3345 unsigned inc = 1; 3346 switch (size) { 3347 default: 3348 return MCDisassembler::Fail; 3349 case 0: 3350 if (fieldFromInstruction32(Insn, 4, 1)) 3351 return MCDisassembler::Fail; // UNDEFINED 3352 index = fieldFromInstruction32(Insn, 5, 3); 3353 break; 3354 case 1: 3355 if (fieldFromInstruction32(Insn, 4, 1)) 3356 return MCDisassembler::Fail; // UNDEFINED 3357 index = fieldFromInstruction32(Insn, 6, 2); 3358 if (fieldFromInstruction32(Insn, 5, 1)) 3359 inc = 2; 3360 break; 3361 case 2: 3362 if (fieldFromInstruction32(Insn, 4, 2)) 3363 return MCDisassembler::Fail; // UNDEFINED 3364 index = fieldFromInstruction32(Insn, 7, 1); 3365 if (fieldFromInstruction32(Insn, 6, 1)) 3366 inc = 2; 3367 break; 3368 } 3369 3370 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3371 return MCDisassembler::Fail; 3372 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 3377 if (Rm != 0xF) { // Writeback 3378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 } 3381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3382 return MCDisassembler::Fail; 3383 Inst.addOperand(MCOperand::CreateImm(align)); 3384 if (Rm != 0xF) { 3385 if (Rm != 0xD) { 3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 } else 3389 Inst.addOperand(MCOperand::CreateReg(0)); 3390 } 3391 3392 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3393 return MCDisassembler::Fail; 3394 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3397 return MCDisassembler::Fail; 3398 Inst.addOperand(MCOperand::CreateImm(index)); 3399 3400 return S; 3401 } 3402 3403 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3404 uint64_t Address, const void *Decoder) { 3405 DecodeStatus S = MCDisassembler::Success; 3406 3407 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3408 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3409 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3410 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3411 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3412 3413 unsigned align = 0; 3414 unsigned index = 0; 3415 unsigned inc = 1; 3416 switch (size) { 3417 default: 3418 return MCDisassembler::Fail; 3419 case 0: 3420 if (fieldFromInstruction32(Insn, 4, 1)) 3421 return MCDisassembler::Fail; // UNDEFINED 3422 index = fieldFromInstruction32(Insn, 5, 3); 3423 break; 3424 case 1: 3425 if (fieldFromInstruction32(Insn, 4, 1)) 3426 return MCDisassembler::Fail; // UNDEFINED 3427 index = fieldFromInstruction32(Insn, 6, 2); 3428 if (fieldFromInstruction32(Insn, 5, 1)) 3429 inc = 2; 3430 break; 3431 case 2: 3432 if (fieldFromInstruction32(Insn, 4, 2)) 3433 return MCDisassembler::Fail; // UNDEFINED 3434 index = fieldFromInstruction32(Insn, 7, 1); 3435 if (fieldFromInstruction32(Insn, 6, 1)) 3436 inc = 2; 3437 break; 3438 } 3439 3440 if (Rm != 0xF) { // Writeback 3441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 } 3444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3445 return MCDisassembler::Fail; 3446 Inst.addOperand(MCOperand::CreateImm(align)); 3447 if (Rm != 0xF) { 3448 if (Rm != 0xD) { 3449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3450 return MCDisassembler::Fail; 3451 } else 3452 Inst.addOperand(MCOperand::CreateReg(0)); 3453 } 3454 3455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 Inst.addOperand(MCOperand::CreateImm(index)); 3462 3463 return S; 3464 } 3465 3466 3467 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3468 uint64_t Address, const void *Decoder) { 3469 DecodeStatus S = MCDisassembler::Success; 3470 3471 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3472 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3473 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3474 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3475 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3476 3477 unsigned align = 0; 3478 unsigned index = 0; 3479 unsigned inc = 1; 3480 switch (size) { 3481 default: 3482 return MCDisassembler::Fail; 3483 case 0: 3484 if (fieldFromInstruction32(Insn, 4, 1)) 3485 align = 4; 3486 index = fieldFromInstruction32(Insn, 5, 3); 3487 break; 3488 case 1: 3489 if (fieldFromInstruction32(Insn, 4, 1)) 3490 align = 8; 3491 index = fieldFromInstruction32(Insn, 6, 2); 3492 if (fieldFromInstruction32(Insn, 5, 1)) 3493 inc = 2; 3494 break; 3495 case 2: 3496 if (fieldFromInstruction32(Insn, 4, 2)) 3497 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3498 index = fieldFromInstruction32(Insn, 7, 1); 3499 if (fieldFromInstruction32(Insn, 6, 1)) 3500 inc = 2; 3501 break; 3502 } 3503 3504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3505 return MCDisassembler::Fail; 3506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3507 return MCDisassembler::Fail; 3508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3511 return MCDisassembler::Fail; 3512 3513 if (Rm != 0xF) { // Writeback 3514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 } 3517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 Inst.addOperand(MCOperand::CreateImm(align)); 3520 if (Rm != 0xF) { 3521 if (Rm != 0xD) { 3522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 } else 3525 Inst.addOperand(MCOperand::CreateReg(0)); 3526 } 3527 3528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3529 return MCDisassembler::Fail; 3530 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3533 return MCDisassembler::Fail; 3534 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 Inst.addOperand(MCOperand::CreateImm(index)); 3537 3538 return S; 3539 } 3540 3541 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3542 uint64_t Address, const void *Decoder) { 3543 DecodeStatus S = MCDisassembler::Success; 3544 3545 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3546 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3547 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3548 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3549 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3550 3551 unsigned align = 0; 3552 unsigned index = 0; 3553 unsigned inc = 1; 3554 switch (size) { 3555 default: 3556 return MCDisassembler::Fail; 3557 case 0: 3558 if (fieldFromInstruction32(Insn, 4, 1)) 3559 align = 4; 3560 index = fieldFromInstruction32(Insn, 5, 3); 3561 break; 3562 case 1: 3563 if (fieldFromInstruction32(Insn, 4, 1)) 3564 align = 8; 3565 index = fieldFromInstruction32(Insn, 6, 2); 3566 if (fieldFromInstruction32(Insn, 5, 1)) 3567 inc = 2; 3568 break; 3569 case 2: 3570 if (fieldFromInstruction32(Insn, 4, 2)) 3571 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3572 index = fieldFromInstruction32(Insn, 7, 1); 3573 if (fieldFromInstruction32(Insn, 6, 1)) 3574 inc = 2; 3575 break; 3576 } 3577 3578 if (Rm != 0xF) { // Writeback 3579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3580 return MCDisassembler::Fail; 3581 } 3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 Inst.addOperand(MCOperand::CreateImm(align)); 3585 if (Rm != 0xF) { 3586 if (Rm != 0xD) { 3587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3588 return MCDisassembler::Fail; 3589 } else 3590 Inst.addOperand(MCOperand::CreateReg(0)); 3591 } 3592 3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 Inst.addOperand(MCOperand::CreateImm(index)); 3602 3603 return S; 3604 } 3605 3606 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3607 uint64_t Address, const void *Decoder) { 3608 DecodeStatus S = MCDisassembler::Success; 3609 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3610 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3611 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3612 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3613 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3614 3615 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3616 S = MCDisassembler::SoftFail; 3617 3618 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3625 return MCDisassembler::Fail; 3626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 3629 return S; 3630 } 3631 3632 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3633 uint64_t Address, const void *Decoder) { 3634 DecodeStatus S = MCDisassembler::Success; 3635 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3636 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3637 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3638 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3639 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3640 3641 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3642 S = MCDisassembler::SoftFail; 3643 3644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3649 return MCDisassembler::Fail; 3650 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 3655 return S; 3656 } 3657 3658 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3659 uint64_t Address, const void *Decoder) { 3660 DecodeStatus S = MCDisassembler::Success; 3661 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3662 // The InstPrinter needs to have the low bit of the predicate in 3663 // the mask operand to be able to print it properly. 3664 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3665 3666 if (pred == 0xF) { 3667 pred = 0xE; 3668 S = MCDisassembler::SoftFail; 3669 } 3670 3671 if ((mask & 0xF) == 0) { 3672 // Preserve the high bit of the mask, which is the low bit of 3673 // the predicate. 3674 mask &= 0x10; 3675 mask |= 0x8; 3676 S = MCDisassembler::SoftFail; 3677 } 3678 3679 Inst.addOperand(MCOperand::CreateImm(pred)); 3680 Inst.addOperand(MCOperand::CreateImm(mask)); 3681 return S; 3682 } 3683 3684 static DecodeStatus 3685 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3686 uint64_t Address, const void *Decoder) { 3687 DecodeStatus S = MCDisassembler::Success; 3688 3689 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3690 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3692 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3693 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3694 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3695 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3696 bool writeback = (W == 1) | (P == 0); 3697 3698 addr |= (U << 8) | (Rn << 9); 3699 3700 if (writeback && (Rn == Rt || Rn == Rt2)) 3701 Check(S, MCDisassembler::SoftFail); 3702 if (Rt == Rt2) 3703 Check(S, MCDisassembler::SoftFail); 3704 3705 // Rt 3706 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3707 return MCDisassembler::Fail; 3708 // Rt2 3709 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3710 return MCDisassembler::Fail; 3711 // Writeback operand 3712 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 // addr 3715 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3716 return MCDisassembler::Fail; 3717 3718 return S; 3719 } 3720 3721 static DecodeStatus 3722 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3723 uint64_t Address, const void *Decoder) { 3724 DecodeStatus S = MCDisassembler::Success; 3725 3726 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3727 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3728 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3729 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3730 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3731 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3732 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3733 bool writeback = (W == 1) | (P == 0); 3734 3735 addr |= (U << 8) | (Rn << 9); 3736 3737 if (writeback && (Rn == Rt || Rn == Rt2)) 3738 Check(S, MCDisassembler::SoftFail); 3739 3740 // Writeback operand 3741 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3742 return MCDisassembler::Fail; 3743 // Rt 3744 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3745 return MCDisassembler::Fail; 3746 // Rt2 3747 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 // addr 3750 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 3753 return S; 3754 } 3755