Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)

llvm-svn: 159938

Correct decoder for T1 conditional B encoding

llvm-svn: 158055

ARMDisassembler.cpp: Fix utf8 char in comments.

llvm-svn: 157292

Tweak to the fix in r156212, as with the change in removing the shift the
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .

llvm-svn: 156213

Fix a bug in the ARM disassembler for wide branch conditional instructions
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046

llvm-svn: 156212

Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some case

Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!

llvm-svn: 156118

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Fixed disassembler for vstm/vldm ARM VFP instructions.

llvm-svn: 156077

ARM: Tweak tADDrSP definition for consistent operand order.

Make the operand order of the instruction match that of the asm syntax.

llvm-svn: 155747

Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.

llvm-svn: 155700

Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector

llvm-svn: 155439

Added support for disassembling unpredictable swp/swpb ARM instructions.

llvm-svn: 155004

Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

llvm-svn: 155001

Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .

Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .

llvm-svn: 154884

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Fix a few more places in the ARM disassembler so that branches get
symbolic operands added when using the C disassembler API.

llvm-svn: 154628

Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.

llvm-svn: 154544

Fix ARM disassembly of VLD instructions with writebacks.  And add test a case
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .

llvm-svn: 154459

ARMDisassembler: drop bogus dependency on ARMCodeGen

And indirectly, a dependency on most of the core LLVM optimization
libraries.

llvm-svn: 153957

Remove unnecessary llvm:: qualifications

llvm-svn: 153500

Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.

llvm-svn: 153252

Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM

llvm-svn: 153251

Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .

llvm-svn: 153218

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

llvm-svn: 153089

Use uint16_t to store registers and opcode in static tables in the target specific backends.

llvm-svn: 152537

Tidy up. Remove dead code that slipped into previous commit.

llvm-svn: 152184

ARM more NEON VLD/VST composite physical register refactoring.

Register pair, all lanes subscripting.

llvm-svn: 152157