1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "llvm/MC/EDInstInfo.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <vector> 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 // Handles the condition code status of instructions in IT blocks 35 class ITStatus 36 { 37 public: 38 // Returns the condition code for instruction in IT block 39 unsigned getITCC() { 40 unsigned CC = ARMCC::AL; 41 if (instrInITBlock()) 42 CC = ITStates.back(); 43 return CC; 44 } 45 46 // Advances the IT block state to the next T or E 47 void advanceITState() { 48 ITStates.pop_back(); 49 } 50 51 // Returns true if the current instruction is in an IT block 52 bool instrInITBlock() { 53 return !ITStates.empty(); 54 } 55 56 // Returns true if current instruction is the last instruction in an IT block 57 bool instrLastInITBlock() { 58 return ITStates.size() == 1; 59 } 60 61 // Called when decoding an IT instruction. Sets the IT state for the following 62 // instructions that for the IT block. Firstcond and Mask correspond to the 63 // fields in the IT instruction encoding. 64 void setITState(char Firstcond, char Mask) { 65 // (3 - the number of trailing zeros) is the number of then / else. 66 unsigned CondBit0 = Firstcond & 1; 67 unsigned NumTZ = CountTrailingZeros_32(Mask); 68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 69 assert(NumTZ <= 3 && "Invalid IT mask!"); 70 // push condition codes onto the stack the correct order for the pops 71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72 bool T = ((Mask >> Pos) & 1) == CondBit0; 73 if (T) 74 ITStates.push_back(CCBits); 75 else 76 ITStates.push_back(CCBits ^ 1); 77 } 78 ITStates.push_back(CCBits); 79 } 80 81 private: 82 std::vector<unsigned char> ITStates; 83 }; 84 } 85 86 namespace { 87 /// ARMDisassembler - ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 /// Constructor - Initializes the disassembler. 91 /// 92 ARMDisassembler(const MCSubtargetInfo &STI) : 93 MCDisassembler(STI) { 94 } 95 96 ~ARMDisassembler() { 97 } 98 99 /// getInstruction - See MCDisassembler. 100 DecodeStatus getInstruction(MCInst &instr, 101 uint64_t &size, 102 const MemoryObject ®ion, 103 uint64_t address, 104 raw_ostream &vStream, 105 raw_ostream &cStream) const; 106 107 /// getEDInfo - See MCDisassembler. 108 const EDInstInfo *getEDInfo() const; 109 private: 110 }; 111 112 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 113 class ThumbDisassembler : public MCDisassembler { 114 public: 115 /// Constructor - Initializes the disassembler. 116 /// 117 ThumbDisassembler(const MCSubtargetInfo &STI) : 118 MCDisassembler(STI) { 119 } 120 121 ~ThumbDisassembler() { 122 } 123 124 /// getInstruction - See MCDisassembler. 125 DecodeStatus getInstruction(MCInst &instr, 126 uint64_t &size, 127 const MemoryObject ®ion, 128 uint64_t address, 129 raw_ostream &vStream, 130 raw_ostream &cStream) const; 131 132 /// getEDInfo - See MCDisassembler. 133 const EDInstInfo *getEDInfo() const; 134 private: 135 mutable ITStatus ITBlock; 136 DecodeStatus AddThumbPredicate(MCInst&) const; 137 void UpdateThumbVFPPredicate(MCInst&) const; 138 }; 139 } 140 141 static bool Check(DecodeStatus &Out, DecodeStatus In) { 142 switch (In) { 143 case MCDisassembler::Success: 144 // Out stays the same. 145 return true; 146 case MCDisassembler::SoftFail: 147 Out = In; 148 return true; 149 case MCDisassembler::Fail: 150 Out = In; 151 return false; 152 } 153 llvm_unreachable("Invalid DecodeStatus!"); 154 } 155 156 157 // Forward declare these because the autogenerated code will reference them. 158 // Definitions are further down. 159 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 162 unsigned RegNo, uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 317 318 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 381 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 #include "ARMGenDisassemblerTables.inc" 386 #include "ARMGenInstrInfo.inc" 387 #include "ARMGenEDInfo.inc" 388 389 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 390 return new ARMDisassembler(STI); 391 } 392 393 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 394 return new ThumbDisassembler(STI); 395 } 396 397 const EDInstInfo *ARMDisassembler::getEDInfo() const { 398 return instInfoARM; 399 } 400 401 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 402 return instInfoARM; 403 } 404 405 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 const MemoryObject &Region, 407 uint64_t Address, 408 raw_ostream &os, 409 raw_ostream &cs) const { 410 CommentStream = &cs; 411 412 uint8_t bytes[4]; 413 414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 416 417 // We want to read exactly 4 bytes of data. 418 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 419 Size = 0; 420 return MCDisassembler::Fail; 421 } 422 423 // Encoded as a small-endian 32-bit word in the stream. 424 uint32_t insn = (bytes[3] << 24) | 425 (bytes[2] << 16) | 426 (bytes[1] << 8) | 427 (bytes[0] << 0); 428 429 // Calling the auto-generated decoder function. 430 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 431 if (result != MCDisassembler::Fail) { 432 Size = 4; 433 return result; 434 } 435 436 // VFP and NEON instructions, similarly, are shared between ARM 437 // and Thumb modes. 438 MI.clear(); 439 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 440 if (result != MCDisassembler::Fail) { 441 Size = 4; 442 return result; 443 } 444 445 MI.clear(); 446 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 447 if (result != MCDisassembler::Fail) { 448 Size = 4; 449 // Add a fake predicate operand, because we share these instruction 450 // definitions with Thumb2 where these instructions are predicable. 451 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 452 return MCDisassembler::Fail; 453 return result; 454 } 455 456 MI.clear(); 457 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 458 if (result != MCDisassembler::Fail) { 459 Size = 4; 460 // Add a fake predicate operand, because we share these instruction 461 // definitions with Thumb2 where these instructions are predicable. 462 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 463 return MCDisassembler::Fail; 464 return result; 465 } 466 467 MI.clear(); 468 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 469 if (result != MCDisassembler::Fail) { 470 Size = 4; 471 // Add a fake predicate operand, because we share these instruction 472 // definitions with Thumb2 where these instructions are predicable. 473 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 474 return MCDisassembler::Fail; 475 return result; 476 } 477 478 MI.clear(); 479 480 Size = 0; 481 return MCDisassembler::Fail; 482 } 483 484 namespace llvm { 485 extern const MCInstrDesc ARMInsts[]; 486 } 487 488 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 489 /// immediate Value in the MCInst. The immediate Value has had any PC 490 /// adjustment made by the caller. If the instruction is a branch instruction 491 /// then isBranch is true, else false. If the getOpInfo() function was set as 492 /// part of the setupForSymbolicDisassembly() call then that function is called 493 /// to get any symbolic information at the Address for this instruction. If 494 /// that returns non-zero then the symbolic information it returns is used to 495 /// create an MCExpr and that is added as an operand to the MCInst. If 496 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 497 /// Value is done and if a symbol is found an MCExpr is created with that, else 498 /// an MCExpr with Value is created. This function returns true if it adds an 499 /// operand to the MCInst and false otherwise. 500 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 501 bool isBranch, uint64_t InstSize, 502 MCInst &MI, const void *Decoder) { 503 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 504 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 505 struct LLVMOpInfo1 SymbolicOp; 506 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 507 SymbolicOp.Value = Value; 508 void *DisInfo = Dis->getDisInfoBlock(); 509 510 if (!getOpInfo || 511 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 512 // Clear SymbolicOp.Value from above and also all other fields. 513 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 514 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 515 if (!SymbolLookUp) 516 return false; 517 uint64_t ReferenceType; 518 if (isBranch) 519 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 520 else 521 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 522 const char *ReferenceName; 523 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 524 &ReferenceName); 525 if (Name) { 526 SymbolicOp.AddSymbol.Name = Name; 527 SymbolicOp.AddSymbol.Present = true; 528 } 529 // For branches always create an MCExpr so it gets printed as hex address. 530 else if (isBranch) { 531 SymbolicOp.Value = Value; 532 } 533 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 534 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 535 if (!Name && !isBranch) 536 return false; 537 } 538 539 MCContext *Ctx = Dis->getMCContext(); 540 const MCExpr *Add = NULL; 541 if (SymbolicOp.AddSymbol.Present) { 542 if (SymbolicOp.AddSymbol.Name) { 543 StringRef Name(SymbolicOp.AddSymbol.Name); 544 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 545 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 546 } else { 547 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 548 } 549 } 550 551 const MCExpr *Sub = NULL; 552 if (SymbolicOp.SubtractSymbol.Present) { 553 if (SymbolicOp.SubtractSymbol.Name) { 554 StringRef Name(SymbolicOp.SubtractSymbol.Name); 555 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 556 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 557 } else { 558 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 559 } 560 } 561 562 const MCExpr *Off = NULL; 563 if (SymbolicOp.Value != 0) 564 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 565 566 const MCExpr *Expr; 567 if (Sub) { 568 const MCExpr *LHS; 569 if (Add) 570 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 571 else 572 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 573 if (Off != 0) 574 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 575 else 576 Expr = LHS; 577 } else if (Add) { 578 if (Off != 0) 579 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 580 else 581 Expr = Add; 582 } else { 583 if (Off != 0) 584 Expr = Off; 585 else 586 Expr = MCConstantExpr::Create(0, *Ctx); 587 } 588 589 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 590 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 591 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 592 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 593 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 594 MI.addOperand(MCOperand::CreateExpr(Expr)); 595 else 596 llvm_unreachable("bad SymbolicOp.VariantKind"); 597 598 return true; 599 } 600 601 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 602 /// referenced by a load instruction with the base register that is the Pc. 603 /// These can often be values in a literal pool near the Address of the 604 /// instruction. The Address of the instruction and its immediate Value are 605 /// used as a possible literal pool entry. The SymbolLookUp call back will 606 /// return the name of a symbol referenced by the the literal pool's entry if 607 /// the referenced address is that of a symbol. Or it will return a pointer to 608 /// a literal 'C' string if the referenced address of the literal pool's entry 609 /// is an address into a section with 'C' string literals. 610 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 611 const void *Decoder) { 612 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 613 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 614 if (SymbolLookUp) { 615 void *DisInfo = Dis->getDisInfoBlock(); 616 uint64_t ReferenceType; 617 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 618 const char *ReferenceName; 619 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 620 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 621 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 622 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 623 } 624 } 625 626 // Thumb1 instructions don't have explicit S bits. Rather, they 627 // implicitly set CPSR. Since it's not represented in the encoding, the 628 // auto-generated decoder won't inject the CPSR operand. We need to fix 629 // that as a post-pass. 630 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 631 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 632 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 633 MCInst::iterator I = MI.begin(); 634 for (unsigned i = 0; i < NumOps; ++i, ++I) { 635 if (I == MI.end()) break; 636 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 637 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 639 return; 640 } 641 } 642 643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 644 } 645 646 // Most Thumb instructions don't have explicit predicates in the 647 // encoding, but rather get their predicates from IT context. We need 648 // to fix up the predicate operands using this context information as a 649 // post-pass. 650 MCDisassembler::DecodeStatus 651 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 652 MCDisassembler::DecodeStatus S = Success; 653 654 // A few instructions actually have predicates encoded in them. Don't 655 // try to overwrite it if we're seeing one of those. 656 switch (MI.getOpcode()) { 657 case ARM::tBcc: 658 case ARM::t2Bcc: 659 case ARM::tCBZ: 660 case ARM::tCBNZ: 661 case ARM::tCPS: 662 case ARM::t2CPS3p: 663 case ARM::t2CPS2p: 664 case ARM::t2CPS1p: 665 case ARM::tMOVSr: 666 case ARM::tSETEND: 667 // Some instructions (mostly conditional branches) are not 668 // allowed in IT blocks. 669 if (ITBlock.instrInITBlock()) 670 S = SoftFail; 671 else 672 return Success; 673 break; 674 case ARM::tB: 675 case ARM::t2B: 676 case ARM::t2TBB: 677 case ARM::t2TBH: 678 // Some instructions (mostly unconditional branches) can 679 // only appears at the end of, or outside of, an IT. 680 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 681 S = SoftFail; 682 break; 683 default: 684 break; 685 } 686 687 // If we're in an IT block, base the predicate on that. Otherwise, 688 // assume a predicate of AL. 689 unsigned CC; 690 CC = ITBlock.getITCC(); 691 if (CC == 0xF) 692 CC = ARMCC::AL; 693 if (ITBlock.instrInITBlock()) 694 ITBlock.advanceITState(); 695 696 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 697 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 698 MCInst::iterator I = MI.begin(); 699 for (unsigned i = 0; i < NumOps; ++i, ++I) { 700 if (I == MI.end()) break; 701 if (OpInfo[i].isPredicate()) { 702 I = MI.insert(I, MCOperand::CreateImm(CC)); 703 ++I; 704 if (CC == ARMCC::AL) 705 MI.insert(I, MCOperand::CreateReg(0)); 706 else 707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 708 return S; 709 } 710 } 711 712 I = MI.insert(I, MCOperand::CreateImm(CC)); 713 ++I; 714 if (CC == ARMCC::AL) 715 MI.insert(I, MCOperand::CreateReg(0)); 716 else 717 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 718 719 return S; 720 } 721 722 // Thumb VFP instructions are a special case. Because we share their 723 // encodings between ARM and Thumb modes, and they are predicable in ARM 724 // mode, the auto-generated decoder will give them an (incorrect) 725 // predicate operand. We need to rewrite these operands based on the IT 726 // context as a post-pass. 727 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 728 unsigned CC; 729 CC = ITBlock.getITCC(); 730 if (ITBlock.instrInITBlock()) 731 ITBlock.advanceITState(); 732 733 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 734 MCInst::iterator I = MI.begin(); 735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 736 for (unsigned i = 0; i < NumOps; ++i, ++I) { 737 if (OpInfo[i].isPredicate() ) { 738 I->setImm(CC); 739 ++I; 740 if (CC == ARMCC::AL) 741 I->setReg(0); 742 else 743 I->setReg(ARM::CPSR); 744 return; 745 } 746 } 747 } 748 749 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 750 const MemoryObject &Region, 751 uint64_t Address, 752 raw_ostream &os, 753 raw_ostream &cs) const { 754 CommentStream = &cs; 755 756 uint8_t bytes[4]; 757 758 assert((STI.getFeatureBits() & ARM::ModeThumb) && 759 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 760 761 // We want to read exactly 2 bytes of data. 762 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 763 Size = 0; 764 return MCDisassembler::Fail; 765 } 766 767 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 768 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 769 if (result != MCDisassembler::Fail) { 770 Size = 2; 771 Check(result, AddThumbPredicate(MI)); 772 return result; 773 } 774 775 MI.clear(); 776 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 777 if (result) { 778 Size = 2; 779 bool InITBlock = ITBlock.instrInITBlock(); 780 Check(result, AddThumbPredicate(MI)); 781 AddThumb1SBit(MI, InITBlock); 782 return result; 783 } 784 785 MI.clear(); 786 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 787 if (result != MCDisassembler::Fail) { 788 Size = 2; 789 790 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 791 // the Thumb predicate. 792 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 793 result = MCDisassembler::SoftFail; 794 795 Check(result, AddThumbPredicate(MI)); 796 797 // If we find an IT instruction, we need to parse its condition 798 // code and mask operands so that we can apply them correctly 799 // to the subsequent instructions. 800 if (MI.getOpcode() == ARM::t2IT) { 801 802 unsigned Firstcond = MI.getOperand(0).getImm(); 803 unsigned Mask = MI.getOperand(1).getImm(); 804 ITBlock.setITState(Firstcond, Mask); 805 } 806 807 return result; 808 } 809 810 // We want to read exactly 4 bytes of data. 811 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 812 Size = 0; 813 return MCDisassembler::Fail; 814 } 815 816 uint32_t insn32 = (bytes[3] << 8) | 817 (bytes[2] << 0) | 818 (bytes[1] << 24) | 819 (bytes[0] << 16); 820 MI.clear(); 821 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 822 if (result != MCDisassembler::Fail) { 823 Size = 4; 824 bool InITBlock = ITBlock.instrInITBlock(); 825 Check(result, AddThumbPredicate(MI)); 826 AddThumb1SBit(MI, InITBlock); 827 return result; 828 } 829 830 MI.clear(); 831 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 Check(result, AddThumbPredicate(MI)); 835 return result; 836 } 837 838 MI.clear(); 839 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 840 if (result != MCDisassembler::Fail) { 841 Size = 4; 842 UpdateThumbVFPPredicate(MI); 843 return result; 844 } 845 846 MI.clear(); 847 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 848 if (result != MCDisassembler::Fail) { 849 Size = 4; 850 Check(result, AddThumbPredicate(MI)); 851 return result; 852 } 853 854 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 855 MI.clear(); 856 uint32_t NEONLdStInsn = insn32; 857 NEONLdStInsn &= 0xF0FFFFFF; 858 NEONLdStInsn |= 0x04000000; 859 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 860 if (result != MCDisassembler::Fail) { 861 Size = 4; 862 Check(result, AddThumbPredicate(MI)); 863 return result; 864 } 865 } 866 867 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 868 MI.clear(); 869 uint32_t NEONDataInsn = insn32; 870 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 871 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 872 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 873 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 874 if (result != MCDisassembler::Fail) { 875 Size = 4; 876 Check(result, AddThumbPredicate(MI)); 877 return result; 878 } 879 } 880 881 Size = 0; 882 return MCDisassembler::Fail; 883 } 884 885 886 extern "C" void LLVMInitializeARMDisassembler() { 887 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 888 createARMDisassembler); 889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 890 createThumbDisassembler); 891 } 892 893 static const uint16_t GPRDecoderTable[] = { 894 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 895 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 896 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 897 ARM::R12, ARM::SP, ARM::LR, ARM::PC 898 }; 899 900 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 if (RegNo > 15) 903 return MCDisassembler::Fail; 904 905 unsigned Register = GPRDecoderTable[RegNo]; 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static DecodeStatus 911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo == 15) 916 S = MCDisassembler::SoftFail; 917 918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 919 920 return S; 921 } 922 923 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 7) 926 return MCDisassembler::Fail; 927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 928 } 929 930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 unsigned Register = 0; 933 switch (RegNo) { 934 case 0: 935 Register = ARM::R0; 936 break; 937 case 1: 938 Register = ARM::R1; 939 break; 940 case 2: 941 Register = ARM::R2; 942 break; 943 case 3: 944 Register = ARM::R3; 945 break; 946 case 9: 947 Register = ARM::R9; 948 break; 949 case 12: 950 Register = ARM::R12; 951 break; 952 default: 953 return MCDisassembler::Fail; 954 } 955 956 Inst.addOperand(MCOperand::CreateReg(Register)); 957 return MCDisassembler::Success; 958 } 959 960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 964 } 965 966 static const uint16_t SPRDecoderTable[] = { 967 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 968 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 969 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 970 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 971 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 972 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 973 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 974 ARM::S28, ARM::S29, ARM::S30, ARM::S31 975 }; 976 977 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 if (RegNo > 31) 980 return MCDisassembler::Fail; 981 982 unsigned Register = SPRDecoderTable[RegNo]; 983 Inst.addOperand(MCOperand::CreateReg(Register)); 984 return MCDisassembler::Success; 985 } 986 987 static const uint16_t DPRDecoderTable[] = { 988 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 989 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 990 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 991 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 992 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 993 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 994 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 995 ARM::D28, ARM::D29, ARM::D30, ARM::D31 996 }; 997 998 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 999 uint64_t Address, const void *Decoder) { 1000 if (RegNo > 31) 1001 return MCDisassembler::Fail; 1002 1003 unsigned Register = DPRDecoderTable[RegNo]; 1004 Inst.addOperand(MCOperand::CreateReg(Register)); 1005 return MCDisassembler::Success; 1006 } 1007 1008 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 7) 1011 return MCDisassembler::Fail; 1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1013 } 1014 1015 static DecodeStatus 1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1017 uint64_t Address, const void *Decoder) { 1018 if (RegNo > 15) 1019 return MCDisassembler::Fail; 1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1021 } 1022 1023 static const uint16_t QPRDecoderTable[] = { 1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1028 }; 1029 1030 1031 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1032 uint64_t Address, const void *Decoder) { 1033 if (RegNo > 31) 1034 return MCDisassembler::Fail; 1035 RegNo >>= 1; 1036 1037 unsigned Register = QPRDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040 } 1041 1042 static const uint16_t DPairDecoderTable[] = { 1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1048 ARM::Q15 1049 }; 1050 1051 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1052 uint64_t Address, const void *Decoder) { 1053 if (RegNo > 30) 1054 return MCDisassembler::Fail; 1055 1056 unsigned Register = DPairDecoderTable[RegNo]; 1057 Inst.addOperand(MCOperand::CreateReg(Register)); 1058 return MCDisassembler::Success; 1059 } 1060 1061 static const uint16_t DPairSpacedDecoderTable[] = { 1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1069 ARM::D28_D30, ARM::D29_D31 1070 }; 1071 1072 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1073 unsigned RegNo, 1074 uint64_t Address, 1075 const void *Decoder) { 1076 if (RegNo > 29) 1077 return MCDisassembler::Fail; 1078 1079 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1080 Inst.addOperand(MCOperand::CreateReg(Register)); 1081 return MCDisassembler::Success; 1082 } 1083 1084 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1085 uint64_t Address, const void *Decoder) { 1086 if (Val == 0xF) return MCDisassembler::Fail; 1087 // AL predicate is not allowed on Thumb1 branches. 1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1089 return MCDisassembler::Fail; 1090 Inst.addOperand(MCOperand::CreateImm(Val)); 1091 if (Val == ARMCC::AL) { 1092 Inst.addOperand(MCOperand::CreateReg(0)); 1093 } else 1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val) 1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1102 else 1103 Inst.addOperand(MCOperand::CreateReg(0)); 1104 return MCDisassembler::Success; 1105 } 1106 1107 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1108 uint64_t Address, const void *Decoder) { 1109 uint32_t imm = Val & 0xFF; 1110 uint32_t rot = (Val & 0xF00) >> 7; 1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1112 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 1120 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1121 unsigned type = fieldFromInstruction32(Val, 5, 2); 1122 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1123 1124 // Register-immediate 1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1126 return MCDisassembler::Fail; 1127 1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1129 switch (type) { 1130 case 0: 1131 Shift = ARM_AM::lsl; 1132 break; 1133 case 1: 1134 Shift = ARM_AM::lsr; 1135 break; 1136 case 2: 1137 Shift = ARM_AM::asr; 1138 break; 1139 case 3: 1140 Shift = ARM_AM::ror; 1141 break; 1142 } 1143 1144 if (Shift == ARM_AM::ror && imm == 0) 1145 Shift = ARM_AM::rrx; 1146 1147 unsigned Op = Shift | (imm << 3); 1148 Inst.addOperand(MCOperand::CreateImm(Op)); 1149 1150 return S; 1151 } 1152 1153 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1154 uint64_t Address, const void *Decoder) { 1155 DecodeStatus S = MCDisassembler::Success; 1156 1157 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1158 unsigned type = fieldFromInstruction32(Val, 5, 2); 1159 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1160 1161 // Register-register 1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1165 return MCDisassembler::Fail; 1166 1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1168 switch (type) { 1169 case 0: 1170 Shift = ARM_AM::lsl; 1171 break; 1172 case 1: 1173 Shift = ARM_AM::lsr; 1174 break; 1175 case 2: 1176 Shift = ARM_AM::asr; 1177 break; 1178 case 3: 1179 Shift = ARM_AM::ror; 1180 break; 1181 } 1182 1183 Inst.addOperand(MCOperand::CreateImm(Shift)); 1184 1185 return S; 1186 } 1187 1188 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 bool writebackLoad = false; 1193 unsigned writebackReg = 0; 1194 switch (Inst.getOpcode()) { 1195 default: 1196 break; 1197 case ARM::LDMIA_UPD: 1198 case ARM::LDMDB_UPD: 1199 case ARM::LDMIB_UPD: 1200 case ARM::LDMDA_UPD: 1201 case ARM::t2LDMIA_UPD: 1202 case ARM::t2LDMDB_UPD: 1203 writebackLoad = true; 1204 writebackReg = Inst.getOperand(0).getReg(); 1205 break; 1206 } 1207 1208 // Empty register lists are not allowed. 1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1210 for (unsigned i = 0; i < 16; ++i) { 1211 if (Val & (1 << i)) { 1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1213 return MCDisassembler::Fail; 1214 // Writeback not allowed if Rn is in the target list. 1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1216 Check(S, MCDisassembler::SoftFail); 1217 } 1218 } 1219 1220 return S; 1221 } 1222 1223 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 unsigned Vd = fieldFromInstruction32(Val, 8, 5); 1228 unsigned regs = fieldFromInstruction32(Val, 0, 8); 1229 1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < (regs - 1); ++i) { 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 } 1236 1237 return S; 1238 } 1239 1240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1241 uint64_t Address, const void *Decoder) { 1242 DecodeStatus S = MCDisassembler::Success; 1243 1244 unsigned Vd = fieldFromInstruction32(Val, 8, 5); 1245 unsigned regs = fieldFromInstruction32(Val, 0, 8); 1246 1247 regs = regs >> 1; 1248 1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 for (unsigned i = 0; i < (regs - 1); ++i) { 1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1253 return MCDisassembler::Fail; 1254 } 1255 1256 return S; 1257 } 1258 1259 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1260 uint64_t Address, const void *Decoder) { 1261 // This operand encodes a mask of contiguous zeros between a specified MSB 1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1263 // the mask of all bits LSB-and-lower, and then xor them to create 1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1265 // create the final mask. 1266 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1267 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1268 1269 DecodeStatus S = MCDisassembler::Success; 1270 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1271 1272 uint32_t msb_mask = 0xFFFFFFFF; 1273 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1274 uint32_t lsb_mask = (1U << lsb) - 1; 1275 1276 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1277 return S; 1278 } 1279 1280 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1281 uint64_t Address, const void *Decoder) { 1282 DecodeStatus S = MCDisassembler::Success; 1283 1284 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1285 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1286 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1287 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1288 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1289 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1290 1291 switch (Inst.getOpcode()) { 1292 case ARM::LDC_OFFSET: 1293 case ARM::LDC_PRE: 1294 case ARM::LDC_POST: 1295 case ARM::LDC_OPTION: 1296 case ARM::LDCL_OFFSET: 1297 case ARM::LDCL_PRE: 1298 case ARM::LDCL_POST: 1299 case ARM::LDCL_OPTION: 1300 case ARM::STC_OFFSET: 1301 case ARM::STC_PRE: 1302 case ARM::STC_POST: 1303 case ARM::STC_OPTION: 1304 case ARM::STCL_OFFSET: 1305 case ARM::STCL_PRE: 1306 case ARM::STCL_POST: 1307 case ARM::STCL_OPTION: 1308 case ARM::t2LDC_OFFSET: 1309 case ARM::t2LDC_PRE: 1310 case ARM::t2LDC_POST: 1311 case ARM::t2LDC_OPTION: 1312 case ARM::t2LDCL_OFFSET: 1313 case ARM::t2LDCL_PRE: 1314 case ARM::t2LDCL_POST: 1315 case ARM::t2LDCL_OPTION: 1316 case ARM::t2STC_OFFSET: 1317 case ARM::t2STC_PRE: 1318 case ARM::t2STC_POST: 1319 case ARM::t2STC_OPTION: 1320 case ARM::t2STCL_OFFSET: 1321 case ARM::t2STCL_PRE: 1322 case ARM::t2STCL_POST: 1323 case ARM::t2STCL_OPTION: 1324 if (coproc == 0xA || coproc == 0xB) 1325 return MCDisassembler::Fail; 1326 break; 1327 default: 1328 break; 1329 } 1330 1331 Inst.addOperand(MCOperand::CreateImm(coproc)); 1332 Inst.addOperand(MCOperand::CreateImm(CRd)); 1333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1334 return MCDisassembler::Fail; 1335 1336 switch (Inst.getOpcode()) { 1337 case ARM::t2LDC2_OFFSET: 1338 case ARM::t2LDC2L_OFFSET: 1339 case ARM::t2LDC2_PRE: 1340 case ARM::t2LDC2L_PRE: 1341 case ARM::t2STC2_OFFSET: 1342 case ARM::t2STC2L_OFFSET: 1343 case ARM::t2STC2_PRE: 1344 case ARM::t2STC2L_PRE: 1345 case ARM::LDC2_OFFSET: 1346 case ARM::LDC2L_OFFSET: 1347 case ARM::LDC2_PRE: 1348 case ARM::LDC2L_PRE: 1349 case ARM::STC2_OFFSET: 1350 case ARM::STC2L_OFFSET: 1351 case ARM::STC2_PRE: 1352 case ARM::STC2L_PRE: 1353 case ARM::t2LDC_OFFSET: 1354 case ARM::t2LDCL_OFFSET: 1355 case ARM::t2LDC_PRE: 1356 case ARM::t2LDCL_PRE: 1357 case ARM::t2STC_OFFSET: 1358 case ARM::t2STCL_OFFSET: 1359 case ARM::t2STC_PRE: 1360 case ARM::t2STCL_PRE: 1361 case ARM::LDC_OFFSET: 1362 case ARM::LDCL_OFFSET: 1363 case ARM::LDC_PRE: 1364 case ARM::LDCL_PRE: 1365 case ARM::STC_OFFSET: 1366 case ARM::STCL_OFFSET: 1367 case ARM::STC_PRE: 1368 case ARM::STCL_PRE: 1369 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1370 Inst.addOperand(MCOperand::CreateImm(imm)); 1371 break; 1372 case ARM::t2LDC2_POST: 1373 case ARM::t2LDC2L_POST: 1374 case ARM::t2STC2_POST: 1375 case ARM::t2STC2L_POST: 1376 case ARM::LDC2_POST: 1377 case ARM::LDC2L_POST: 1378 case ARM::STC2_POST: 1379 case ARM::STC2L_POST: 1380 case ARM::t2LDC_POST: 1381 case ARM::t2LDCL_POST: 1382 case ARM::t2STC_POST: 1383 case ARM::t2STCL_POST: 1384 case ARM::LDC_POST: 1385 case ARM::LDCL_POST: 1386 case ARM::STC_POST: 1387 case ARM::STCL_POST: 1388 imm |= U << 8; 1389 // fall through. 1390 default: 1391 // The 'option' variant doesn't encode 'U' in the immediate since 1392 // the immediate is unsigned [0,255]. 1393 Inst.addOperand(MCOperand::CreateImm(imm)); 1394 break; 1395 } 1396 1397 switch (Inst.getOpcode()) { 1398 case ARM::LDC_OFFSET: 1399 case ARM::LDC_PRE: 1400 case ARM::LDC_POST: 1401 case ARM::LDC_OPTION: 1402 case ARM::LDCL_OFFSET: 1403 case ARM::LDCL_PRE: 1404 case ARM::LDCL_POST: 1405 case ARM::LDCL_OPTION: 1406 case ARM::STC_OFFSET: 1407 case ARM::STC_PRE: 1408 case ARM::STC_POST: 1409 case ARM::STC_OPTION: 1410 case ARM::STCL_OFFSET: 1411 case ARM::STCL_PRE: 1412 case ARM::STCL_POST: 1413 case ARM::STCL_OPTION: 1414 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1415 return MCDisassembler::Fail; 1416 break; 1417 default: 1418 break; 1419 } 1420 1421 return S; 1422 } 1423 1424 static DecodeStatus 1425 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1426 uint64_t Address, const void *Decoder) { 1427 DecodeStatus S = MCDisassembler::Success; 1428 1429 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1430 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1431 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1432 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1433 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1434 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1435 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1436 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1437 1438 // On stores, the writeback operand precedes Rt. 1439 switch (Inst.getOpcode()) { 1440 case ARM::STR_POST_IMM: 1441 case ARM::STR_POST_REG: 1442 case ARM::STRB_POST_IMM: 1443 case ARM::STRB_POST_REG: 1444 case ARM::STRT_POST_REG: 1445 case ARM::STRT_POST_IMM: 1446 case ARM::STRBT_POST_REG: 1447 case ARM::STRBT_POST_IMM: 1448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1449 return MCDisassembler::Fail; 1450 break; 1451 default: 1452 break; 1453 } 1454 1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1456 return MCDisassembler::Fail; 1457 1458 // On loads, the writeback operand comes after Rt. 1459 switch (Inst.getOpcode()) { 1460 case ARM::LDR_POST_IMM: 1461 case ARM::LDR_POST_REG: 1462 case ARM::LDRB_POST_IMM: 1463 case ARM::LDRB_POST_REG: 1464 case ARM::LDRBT_POST_REG: 1465 case ARM::LDRBT_POST_IMM: 1466 case ARM::LDRT_POST_REG: 1467 case ARM::LDRT_POST_IMM: 1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1469 return MCDisassembler::Fail; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1476 return MCDisassembler::Fail; 1477 1478 ARM_AM::AddrOpc Op = ARM_AM::add; 1479 if (!fieldFromInstruction32(Insn, 23, 1)) 1480 Op = ARM_AM::sub; 1481 1482 bool writeback = (P == 0) || (W == 1); 1483 unsigned idx_mode = 0; 1484 if (P && writeback) 1485 idx_mode = ARMII::IndexModePre; 1486 else if (!P && writeback) 1487 idx_mode = ARMII::IndexModePost; 1488 1489 if (writeback && (Rn == 15 || Rn == Rt)) 1490 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1491 1492 if (reg) { 1493 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1494 return MCDisassembler::Fail; 1495 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1496 switch( fieldFromInstruction32(Insn, 5, 2)) { 1497 case 0: 1498 Opc = ARM_AM::lsl; 1499 break; 1500 case 1: 1501 Opc = ARM_AM::lsr; 1502 break; 1503 case 2: 1504 Opc = ARM_AM::asr; 1505 break; 1506 case 3: 1507 Opc = ARM_AM::ror; 1508 break; 1509 default: 1510 return MCDisassembler::Fail; 1511 } 1512 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1513 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1514 1515 Inst.addOperand(MCOperand::CreateImm(imm)); 1516 } else { 1517 Inst.addOperand(MCOperand::CreateReg(0)); 1518 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1519 Inst.addOperand(MCOperand::CreateImm(tmp)); 1520 } 1521 1522 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1523 return MCDisassembler::Fail; 1524 1525 return S; 1526 } 1527 1528 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1529 uint64_t Address, const void *Decoder) { 1530 DecodeStatus S = MCDisassembler::Success; 1531 1532 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1533 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1534 unsigned type = fieldFromInstruction32(Val, 5, 2); 1535 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1536 unsigned U = fieldFromInstruction32(Val, 12, 1); 1537 1538 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1539 switch (type) { 1540 case 0: 1541 ShOp = ARM_AM::lsl; 1542 break; 1543 case 1: 1544 ShOp = ARM_AM::lsr; 1545 break; 1546 case 2: 1547 ShOp = ARM_AM::asr; 1548 break; 1549 case 3: 1550 ShOp = ARM_AM::ror; 1551 break; 1552 } 1553 1554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1555 return MCDisassembler::Fail; 1556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1557 return MCDisassembler::Fail; 1558 unsigned shift; 1559 if (U) 1560 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1561 else 1562 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1563 Inst.addOperand(MCOperand::CreateImm(shift)); 1564 1565 return S; 1566 } 1567 1568 static DecodeStatus 1569 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1570 uint64_t Address, const void *Decoder) { 1571 DecodeStatus S = MCDisassembler::Success; 1572 1573 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1576 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1577 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1578 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1579 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1580 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1581 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1582 unsigned Rt2 = Rt + 1; 1583 1584 bool writeback = (W == 1) | (P == 0); 1585 1586 // For {LD,ST}RD, Rt must be even, else undefined. 1587 switch (Inst.getOpcode()) { 1588 case ARM::STRD: 1589 case ARM::STRD_PRE: 1590 case ARM::STRD_POST: 1591 case ARM::LDRD: 1592 case ARM::LDRD_PRE: 1593 case ARM::LDRD_POST: 1594 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1595 break; 1596 default: 1597 break; 1598 } 1599 switch (Inst.getOpcode()) { 1600 case ARM::STRD: 1601 case ARM::STRD_PRE: 1602 case ARM::STRD_POST: 1603 if (P == 0 && W == 1) 1604 S = MCDisassembler::SoftFail; 1605 1606 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1607 S = MCDisassembler::SoftFail; 1608 if (type && Rm == 15) 1609 S = MCDisassembler::SoftFail; 1610 if (Rt2 == 15) 1611 S = MCDisassembler::SoftFail; 1612 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1613 S = MCDisassembler::SoftFail; 1614 break; 1615 case ARM::STRH: 1616 case ARM::STRH_PRE: 1617 case ARM::STRH_POST: 1618 if (Rt == 15) 1619 S = MCDisassembler::SoftFail; 1620 if (writeback && (Rn == 15 || Rn == Rt)) 1621 S = MCDisassembler::SoftFail; 1622 if (!type && Rm == 15) 1623 S = MCDisassembler::SoftFail; 1624 break; 1625 case ARM::LDRD: 1626 case ARM::LDRD_PRE: 1627 case ARM::LDRD_POST: 1628 if (type && Rn == 15){ 1629 if (Rt2 == 15) 1630 S = MCDisassembler::SoftFail; 1631 break; 1632 } 1633 if (P == 0 && W == 1) 1634 S = MCDisassembler::SoftFail; 1635 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1636 S = MCDisassembler::SoftFail; 1637 if (!type && writeback && Rn == 15) 1638 S = MCDisassembler::SoftFail; 1639 if (writeback && (Rn == Rt || Rn == Rt2)) 1640 S = MCDisassembler::SoftFail; 1641 break; 1642 case ARM::LDRH: 1643 case ARM::LDRH_PRE: 1644 case ARM::LDRH_POST: 1645 if (type && Rn == 15){ 1646 if (Rt == 15) 1647 S = MCDisassembler::SoftFail; 1648 break; 1649 } 1650 if (Rt == 15) 1651 S = MCDisassembler::SoftFail; 1652 if (!type && Rm == 15) 1653 S = MCDisassembler::SoftFail; 1654 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1655 S = MCDisassembler::SoftFail; 1656 break; 1657 case ARM::LDRSH: 1658 case ARM::LDRSH_PRE: 1659 case ARM::LDRSH_POST: 1660 case ARM::LDRSB: 1661 case ARM::LDRSB_PRE: 1662 case ARM::LDRSB_POST: 1663 if (type && Rn == 15){ 1664 if (Rt == 15) 1665 S = MCDisassembler::SoftFail; 1666 break; 1667 } 1668 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1669 S = MCDisassembler::SoftFail; 1670 if (!type && (Rt == 15 || Rm == 15)) 1671 S = MCDisassembler::SoftFail; 1672 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1673 S = MCDisassembler::SoftFail; 1674 break; 1675 default: 1676 break; 1677 } 1678 1679 if (writeback) { // Writeback 1680 if (P) 1681 U |= ARMII::IndexModePre << 9; 1682 else 1683 U |= ARMII::IndexModePost << 9; 1684 1685 // On stores, the writeback operand precedes Rt. 1686 switch (Inst.getOpcode()) { 1687 case ARM::STRD: 1688 case ARM::STRD_PRE: 1689 case ARM::STRD_POST: 1690 case ARM::STRH: 1691 case ARM::STRH_PRE: 1692 case ARM::STRH_POST: 1693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1694 return MCDisassembler::Fail; 1695 break; 1696 default: 1697 break; 1698 } 1699 } 1700 1701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1702 return MCDisassembler::Fail; 1703 switch (Inst.getOpcode()) { 1704 case ARM::STRD: 1705 case ARM::STRD_PRE: 1706 case ARM::STRD_POST: 1707 case ARM::LDRD: 1708 case ARM::LDRD_PRE: 1709 case ARM::LDRD_POST: 1710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1711 return MCDisassembler::Fail; 1712 break; 1713 default: 1714 break; 1715 } 1716 1717 if (writeback) { 1718 // On loads, the writeback operand comes after Rt. 1719 switch (Inst.getOpcode()) { 1720 case ARM::LDRD: 1721 case ARM::LDRD_PRE: 1722 case ARM::LDRD_POST: 1723 case ARM::LDRH: 1724 case ARM::LDRH_PRE: 1725 case ARM::LDRH_POST: 1726 case ARM::LDRSH: 1727 case ARM::LDRSH_PRE: 1728 case ARM::LDRSH_POST: 1729 case ARM::LDRSB: 1730 case ARM::LDRSB_PRE: 1731 case ARM::LDRSB_POST: 1732 case ARM::LDRHTr: 1733 case ARM::LDRSBTr: 1734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1735 return MCDisassembler::Fail; 1736 break; 1737 default: 1738 break; 1739 } 1740 } 1741 1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1743 return MCDisassembler::Fail; 1744 1745 if (type) { 1746 Inst.addOperand(MCOperand::CreateReg(0)); 1747 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1748 } else { 1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1750 return MCDisassembler::Fail; 1751 Inst.addOperand(MCOperand::CreateImm(U)); 1752 } 1753 1754 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1755 return MCDisassembler::Fail; 1756 1757 return S; 1758 } 1759 1760 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1761 uint64_t Address, const void *Decoder) { 1762 DecodeStatus S = MCDisassembler::Success; 1763 1764 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1765 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1766 1767 switch (mode) { 1768 case 0: 1769 mode = ARM_AM::da; 1770 break; 1771 case 1: 1772 mode = ARM_AM::ia; 1773 break; 1774 case 2: 1775 mode = ARM_AM::db; 1776 break; 1777 case 3: 1778 mode = ARM_AM::ib; 1779 break; 1780 } 1781 1782 Inst.addOperand(MCOperand::CreateImm(mode)); 1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1784 return MCDisassembler::Fail; 1785 1786 return S; 1787 } 1788 1789 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1790 unsigned Insn, 1791 uint64_t Address, const void *Decoder) { 1792 DecodeStatus S = MCDisassembler::Success; 1793 1794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1795 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1796 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1797 1798 if (pred == 0xF) { 1799 switch (Inst.getOpcode()) { 1800 case ARM::LDMDA: 1801 Inst.setOpcode(ARM::RFEDA); 1802 break; 1803 case ARM::LDMDA_UPD: 1804 Inst.setOpcode(ARM::RFEDA_UPD); 1805 break; 1806 case ARM::LDMDB: 1807 Inst.setOpcode(ARM::RFEDB); 1808 break; 1809 case ARM::LDMDB_UPD: 1810 Inst.setOpcode(ARM::RFEDB_UPD); 1811 break; 1812 case ARM::LDMIA: 1813 Inst.setOpcode(ARM::RFEIA); 1814 break; 1815 case ARM::LDMIA_UPD: 1816 Inst.setOpcode(ARM::RFEIA_UPD); 1817 break; 1818 case ARM::LDMIB: 1819 Inst.setOpcode(ARM::RFEIB); 1820 break; 1821 case ARM::LDMIB_UPD: 1822 Inst.setOpcode(ARM::RFEIB_UPD); 1823 break; 1824 case ARM::STMDA: 1825 Inst.setOpcode(ARM::SRSDA); 1826 break; 1827 case ARM::STMDA_UPD: 1828 Inst.setOpcode(ARM::SRSDA_UPD); 1829 break; 1830 case ARM::STMDB: 1831 Inst.setOpcode(ARM::SRSDB); 1832 break; 1833 case ARM::STMDB_UPD: 1834 Inst.setOpcode(ARM::SRSDB_UPD); 1835 break; 1836 case ARM::STMIA: 1837 Inst.setOpcode(ARM::SRSIA); 1838 break; 1839 case ARM::STMIA_UPD: 1840 Inst.setOpcode(ARM::SRSIA_UPD); 1841 break; 1842 case ARM::STMIB: 1843 Inst.setOpcode(ARM::SRSIB); 1844 break; 1845 case ARM::STMIB_UPD: 1846 Inst.setOpcode(ARM::SRSIB_UPD); 1847 break; 1848 default: 1849 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1850 } 1851 1852 // For stores (which become SRS's, the only operand is the mode. 1853 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1854 Inst.addOperand( 1855 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1856 return S; 1857 } 1858 1859 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1860 } 1861 1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1863 return MCDisassembler::Fail; 1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1865 return MCDisassembler::Fail; // Tied 1866 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1869 return MCDisassembler::Fail; 1870 1871 return S; 1872 } 1873 1874 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1875 uint64_t Address, const void *Decoder) { 1876 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1877 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1878 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1879 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1880 1881 DecodeStatus S = MCDisassembler::Success; 1882 1883 // imod == '01' --> UNPREDICTABLE 1884 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1885 // return failure here. The '01' imod value is unprintable, so there's 1886 // nothing useful we could do even if we returned UNPREDICTABLE. 1887 1888 if (imod == 1) return MCDisassembler::Fail; 1889 1890 if (imod && M) { 1891 Inst.setOpcode(ARM::CPS3p); 1892 Inst.addOperand(MCOperand::CreateImm(imod)); 1893 Inst.addOperand(MCOperand::CreateImm(iflags)); 1894 Inst.addOperand(MCOperand::CreateImm(mode)); 1895 } else if (imod && !M) { 1896 Inst.setOpcode(ARM::CPS2p); 1897 Inst.addOperand(MCOperand::CreateImm(imod)); 1898 Inst.addOperand(MCOperand::CreateImm(iflags)); 1899 if (mode) S = MCDisassembler::SoftFail; 1900 } else if (!imod && M) { 1901 Inst.setOpcode(ARM::CPS1p); 1902 Inst.addOperand(MCOperand::CreateImm(mode)); 1903 if (iflags) S = MCDisassembler::SoftFail; 1904 } else { 1905 // imod == '00' && M == '0' --> UNPREDICTABLE 1906 Inst.setOpcode(ARM::CPS1p); 1907 Inst.addOperand(MCOperand::CreateImm(mode)); 1908 S = MCDisassembler::SoftFail; 1909 } 1910 1911 return S; 1912 } 1913 1914 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1915 uint64_t Address, const void *Decoder) { 1916 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1917 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1918 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1919 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1920 1921 DecodeStatus S = MCDisassembler::Success; 1922 1923 // imod == '01' --> UNPREDICTABLE 1924 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1925 // return failure here. The '01' imod value is unprintable, so there's 1926 // nothing useful we could do even if we returned UNPREDICTABLE. 1927 1928 if (imod == 1) return MCDisassembler::Fail; 1929 1930 if (imod && M) { 1931 Inst.setOpcode(ARM::t2CPS3p); 1932 Inst.addOperand(MCOperand::CreateImm(imod)); 1933 Inst.addOperand(MCOperand::CreateImm(iflags)); 1934 Inst.addOperand(MCOperand::CreateImm(mode)); 1935 } else if (imod && !M) { 1936 Inst.setOpcode(ARM::t2CPS2p); 1937 Inst.addOperand(MCOperand::CreateImm(imod)); 1938 Inst.addOperand(MCOperand::CreateImm(iflags)); 1939 if (mode) S = MCDisassembler::SoftFail; 1940 } else if (!imod && M) { 1941 Inst.setOpcode(ARM::t2CPS1p); 1942 Inst.addOperand(MCOperand::CreateImm(mode)); 1943 if (iflags) S = MCDisassembler::SoftFail; 1944 } else { 1945 // imod == '00' && M == '0' --> UNPREDICTABLE 1946 Inst.setOpcode(ARM::t2CPS1p); 1947 Inst.addOperand(MCOperand::CreateImm(mode)); 1948 S = MCDisassembler::SoftFail; 1949 } 1950 1951 return S; 1952 } 1953 1954 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1955 uint64_t Address, const void *Decoder) { 1956 DecodeStatus S = MCDisassembler::Success; 1957 1958 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1959 unsigned imm = 0; 1960 1961 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1962 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1963 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1964 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1965 1966 if (Inst.getOpcode() == ARM::t2MOVTi16) 1967 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1970 return MCDisassembler::Fail; 1971 1972 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1973 Inst.addOperand(MCOperand::CreateImm(imm)); 1974 1975 return S; 1976 } 1977 1978 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1979 uint64_t Address, const void *Decoder) { 1980 DecodeStatus S = MCDisassembler::Success; 1981 1982 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1983 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1984 unsigned imm = 0; 1985 1986 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1987 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1988 1989 if (Inst.getOpcode() == ARM::MOVTi16) 1990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1991 return MCDisassembler::Fail; 1992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1993 return MCDisassembler::Fail; 1994 1995 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1996 Inst.addOperand(MCOperand::CreateImm(imm)); 1997 1998 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1999 return MCDisassembler::Fail; 2000 2001 return S; 2002 } 2003 2004 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2005 uint64_t Address, const void *Decoder) { 2006 DecodeStatus S = MCDisassembler::Success; 2007 2008 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 2009 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 2010 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 2011 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 2012 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2013 2014 if (pred == 0xF) 2015 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2016 2017 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2018 return MCDisassembler::Fail; 2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2020 return MCDisassembler::Fail; 2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2022 return MCDisassembler::Fail; 2023 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 2026 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2027 return MCDisassembler::Fail; 2028 2029 return S; 2030 } 2031 2032 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2033 uint64_t Address, const void *Decoder) { 2034 DecodeStatus S = MCDisassembler::Success; 2035 2036 unsigned add = fieldFromInstruction32(Val, 12, 1); 2037 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2038 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2039 2040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2041 return MCDisassembler::Fail; 2042 2043 if (!add) imm *= -1; 2044 if (imm == 0 && !add) imm = INT32_MIN; 2045 Inst.addOperand(MCOperand::CreateImm(imm)); 2046 if (Rn == 15) 2047 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2048 2049 return S; 2050 } 2051 2052 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2053 uint64_t Address, const void *Decoder) { 2054 DecodeStatus S = MCDisassembler::Success; 2055 2056 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2057 unsigned U = fieldFromInstruction32(Val, 8, 1); 2058 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2059 2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 2063 if (U) 2064 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2065 else 2066 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2067 2068 return S; 2069 } 2070 2071 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2072 uint64_t Address, const void *Decoder) { 2073 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2074 } 2075 2076 static DecodeStatus 2077 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2078 uint64_t Address, const void *Decoder) { 2079 DecodeStatus S = MCDisassembler::Success; 2080 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) | 2081 (fieldFromInstruction32(Insn, 11, 1) << 18) | 2082 (fieldFromInstruction32(Insn, 13, 1) << 17) | 2083 (fieldFromInstruction32(Insn, 16, 6) << 11) | 2084 (fieldFromInstruction32(Insn, 26, 1) << 19); 2085 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4, 2086 true, 4, Inst, Decoder)) 2087 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1))); 2088 return S; 2089 } 2090 2091 static DecodeStatus 2092 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2093 uint64_t Address, const void *Decoder) { 2094 DecodeStatus S = MCDisassembler::Success; 2095 2096 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2097 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2098 2099 if (pred == 0xF) { 2100 Inst.setOpcode(ARM::BLXi); 2101 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2102 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2103 true, 4, Inst, Decoder)) 2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2105 return S; 2106 } 2107 2108 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2109 true, 4, Inst, Decoder)) 2110 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 2114 return S; 2115 } 2116 2117 2118 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2119 uint64_t Address, const void *Decoder) { 2120 DecodeStatus S = MCDisassembler::Success; 2121 2122 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2123 unsigned align = fieldFromInstruction32(Val, 4, 2); 2124 2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 if (!align) 2128 Inst.addOperand(MCOperand::CreateImm(0)); 2129 else 2130 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2131 2132 return S; 2133 } 2134 2135 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2136 uint64_t Address, const void *Decoder) { 2137 DecodeStatus S = MCDisassembler::Success; 2138 2139 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2140 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2141 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2142 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2143 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2144 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2145 2146 // First output register 2147 switch (Inst.getOpcode()) { 2148 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2149 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2150 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2151 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2152 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2153 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2154 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2155 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2156 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2157 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 break; 2160 case ARM::VLD2b16: 2161 case ARM::VLD2b32: 2162 case ARM::VLD2b8: 2163 case ARM::VLD2b16wb_fixed: 2164 case ARM::VLD2b16wb_register: 2165 case ARM::VLD2b32wb_fixed: 2166 case ARM::VLD2b32wb_register: 2167 case ARM::VLD2b8wb_fixed: 2168 case ARM::VLD2b8wb_register: 2169 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2170 return MCDisassembler::Fail; 2171 break; 2172 default: 2173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 } 2176 2177 // Second output register 2178 switch (Inst.getOpcode()) { 2179 case ARM::VLD3d8: 2180 case ARM::VLD3d16: 2181 case ARM::VLD3d32: 2182 case ARM::VLD3d8_UPD: 2183 case ARM::VLD3d16_UPD: 2184 case ARM::VLD3d32_UPD: 2185 case ARM::VLD4d8: 2186 case ARM::VLD4d16: 2187 case ARM::VLD4d32: 2188 case ARM::VLD4d8_UPD: 2189 case ARM::VLD4d16_UPD: 2190 case ARM::VLD4d32_UPD: 2191 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2192 return MCDisassembler::Fail; 2193 break; 2194 case ARM::VLD3q8: 2195 case ARM::VLD3q16: 2196 case ARM::VLD3q32: 2197 case ARM::VLD3q8_UPD: 2198 case ARM::VLD3q16_UPD: 2199 case ARM::VLD3q32_UPD: 2200 case ARM::VLD4q8: 2201 case ARM::VLD4q16: 2202 case ARM::VLD4q32: 2203 case ARM::VLD4q8_UPD: 2204 case ARM::VLD4q16_UPD: 2205 case ARM::VLD4q32_UPD: 2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 default: 2209 break; 2210 } 2211 2212 // Third output register 2213 switch(Inst.getOpcode()) { 2214 case ARM::VLD3d8: 2215 case ARM::VLD3d16: 2216 case ARM::VLD3d32: 2217 case ARM::VLD3d8_UPD: 2218 case ARM::VLD3d16_UPD: 2219 case ARM::VLD3d32_UPD: 2220 case ARM::VLD4d8: 2221 case ARM::VLD4d16: 2222 case ARM::VLD4d32: 2223 case ARM::VLD4d8_UPD: 2224 case ARM::VLD4d16_UPD: 2225 case ARM::VLD4d32_UPD: 2226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2227 return MCDisassembler::Fail; 2228 break; 2229 case ARM::VLD3q8: 2230 case ARM::VLD3q16: 2231 case ARM::VLD3q32: 2232 case ARM::VLD3q8_UPD: 2233 case ARM::VLD3q16_UPD: 2234 case ARM::VLD3q32_UPD: 2235 case ARM::VLD4q8: 2236 case ARM::VLD4q16: 2237 case ARM::VLD4q32: 2238 case ARM::VLD4q8_UPD: 2239 case ARM::VLD4q16_UPD: 2240 case ARM::VLD4q32_UPD: 2241 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2242 return MCDisassembler::Fail; 2243 break; 2244 default: 2245 break; 2246 } 2247 2248 // Fourth output register 2249 switch (Inst.getOpcode()) { 2250 case ARM::VLD4d8: 2251 case ARM::VLD4d16: 2252 case ARM::VLD4d32: 2253 case ARM::VLD4d8_UPD: 2254 case ARM::VLD4d16_UPD: 2255 case ARM::VLD4d32_UPD: 2256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2257 return MCDisassembler::Fail; 2258 break; 2259 case ARM::VLD4q8: 2260 case ARM::VLD4q16: 2261 case ARM::VLD4q32: 2262 case ARM::VLD4q8_UPD: 2263 case ARM::VLD4q16_UPD: 2264 case ARM::VLD4q32_UPD: 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 break; 2268 default: 2269 break; 2270 } 2271 2272 // Writeback operand 2273 switch (Inst.getOpcode()) { 2274 case ARM::VLD1d8wb_fixed: 2275 case ARM::VLD1d16wb_fixed: 2276 case ARM::VLD1d32wb_fixed: 2277 case ARM::VLD1d64wb_fixed: 2278 case ARM::VLD1d8wb_register: 2279 case ARM::VLD1d16wb_register: 2280 case ARM::VLD1d32wb_register: 2281 case ARM::VLD1d64wb_register: 2282 case ARM::VLD1q8wb_fixed: 2283 case ARM::VLD1q16wb_fixed: 2284 case ARM::VLD1q32wb_fixed: 2285 case ARM::VLD1q64wb_fixed: 2286 case ARM::VLD1q8wb_register: 2287 case ARM::VLD1q16wb_register: 2288 case ARM::VLD1q32wb_register: 2289 case ARM::VLD1q64wb_register: 2290 case ARM::VLD1d8Twb_fixed: 2291 case ARM::VLD1d8Twb_register: 2292 case ARM::VLD1d16Twb_fixed: 2293 case ARM::VLD1d16Twb_register: 2294 case ARM::VLD1d32Twb_fixed: 2295 case ARM::VLD1d32Twb_register: 2296 case ARM::VLD1d64Twb_fixed: 2297 case ARM::VLD1d64Twb_register: 2298 case ARM::VLD1d8Qwb_fixed: 2299 case ARM::VLD1d8Qwb_register: 2300 case ARM::VLD1d16Qwb_fixed: 2301 case ARM::VLD1d16Qwb_register: 2302 case ARM::VLD1d32Qwb_fixed: 2303 case ARM::VLD1d32Qwb_register: 2304 case ARM::VLD1d64Qwb_fixed: 2305 case ARM::VLD1d64Qwb_register: 2306 case ARM::VLD2d8wb_fixed: 2307 case ARM::VLD2d16wb_fixed: 2308 case ARM::VLD2d32wb_fixed: 2309 case ARM::VLD2q8wb_fixed: 2310 case ARM::VLD2q16wb_fixed: 2311 case ARM::VLD2q32wb_fixed: 2312 case ARM::VLD2d8wb_register: 2313 case ARM::VLD2d16wb_register: 2314 case ARM::VLD2d32wb_register: 2315 case ARM::VLD2q8wb_register: 2316 case ARM::VLD2q16wb_register: 2317 case ARM::VLD2q32wb_register: 2318 case ARM::VLD2b8wb_fixed: 2319 case ARM::VLD2b16wb_fixed: 2320 case ARM::VLD2b32wb_fixed: 2321 case ARM::VLD2b8wb_register: 2322 case ARM::VLD2b16wb_register: 2323 case ARM::VLD2b32wb_register: 2324 Inst.addOperand(MCOperand::CreateImm(0)); 2325 break; 2326 case ARM::VLD3d8_UPD: 2327 case ARM::VLD3d16_UPD: 2328 case ARM::VLD3d32_UPD: 2329 case ARM::VLD3q8_UPD: 2330 case ARM::VLD3q16_UPD: 2331 case ARM::VLD3q32_UPD: 2332 case ARM::VLD4d8_UPD: 2333 case ARM::VLD4d16_UPD: 2334 case ARM::VLD4d32_UPD: 2335 case ARM::VLD4q8_UPD: 2336 case ARM::VLD4q16_UPD: 2337 case ARM::VLD4q32_UPD: 2338 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2339 return MCDisassembler::Fail; 2340 break; 2341 default: 2342 break; 2343 } 2344 2345 // AddrMode6 Base (register+alignment) 2346 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2347 return MCDisassembler::Fail; 2348 2349 // AddrMode6 Offset (register) 2350 switch (Inst.getOpcode()) { 2351 default: 2352 // The below have been updated to have explicit am6offset split 2353 // between fixed and register offset. For those instructions not 2354 // yet updated, we need to add an additional reg0 operand for the 2355 // fixed variant. 2356 // 2357 // The fixed offset encodes as Rm == 0xd, so we check for that. 2358 if (Rm == 0xd) { 2359 Inst.addOperand(MCOperand::CreateReg(0)); 2360 break; 2361 } 2362 // Fall through to handle the register offset variant. 2363 case ARM::VLD1d8wb_fixed: 2364 case ARM::VLD1d16wb_fixed: 2365 case ARM::VLD1d32wb_fixed: 2366 case ARM::VLD1d64wb_fixed: 2367 case ARM::VLD1d8Twb_fixed: 2368 case ARM::VLD1d16Twb_fixed: 2369 case ARM::VLD1d32Twb_fixed: 2370 case ARM::VLD1d64Twb_fixed: 2371 case ARM::VLD1d8Qwb_fixed: 2372 case ARM::VLD1d16Qwb_fixed: 2373 case ARM::VLD1d32Qwb_fixed: 2374 case ARM::VLD1d64Qwb_fixed: 2375 case ARM::VLD1d8wb_register: 2376 case ARM::VLD1d16wb_register: 2377 case ARM::VLD1d32wb_register: 2378 case ARM::VLD1d64wb_register: 2379 case ARM::VLD1q8wb_fixed: 2380 case ARM::VLD1q16wb_fixed: 2381 case ARM::VLD1q32wb_fixed: 2382 case ARM::VLD1q64wb_fixed: 2383 case ARM::VLD1q8wb_register: 2384 case ARM::VLD1q16wb_register: 2385 case ARM::VLD1q32wb_register: 2386 case ARM::VLD1q64wb_register: 2387 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2388 // variant encodes Rm == 0xf. Anything else is a register offset post- 2389 // increment and we need to add the register operand to the instruction. 2390 if (Rm != 0xD && Rm != 0xF && 2391 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2392 return MCDisassembler::Fail; 2393 break; 2394 case ARM::VLD2d8wb_fixed: 2395 case ARM::VLD2d16wb_fixed: 2396 case ARM::VLD2d32wb_fixed: 2397 case ARM::VLD2b8wb_fixed: 2398 case ARM::VLD2b16wb_fixed: 2399 case ARM::VLD2b32wb_fixed: 2400 case ARM::VLD2q8wb_fixed: 2401 case ARM::VLD2q16wb_fixed: 2402 case ARM::VLD2q32wb_fixed: 2403 break; 2404 } 2405 2406 return S; 2407 } 2408 2409 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2410 uint64_t Address, const void *Decoder) { 2411 DecodeStatus S = MCDisassembler::Success; 2412 2413 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2414 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2415 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2416 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2417 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2418 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2419 2420 // Writeback Operand 2421 switch (Inst.getOpcode()) { 2422 case ARM::VST1d8wb_fixed: 2423 case ARM::VST1d16wb_fixed: 2424 case ARM::VST1d32wb_fixed: 2425 case ARM::VST1d64wb_fixed: 2426 case ARM::VST1d8wb_register: 2427 case ARM::VST1d16wb_register: 2428 case ARM::VST1d32wb_register: 2429 case ARM::VST1d64wb_register: 2430 case ARM::VST1q8wb_fixed: 2431 case ARM::VST1q16wb_fixed: 2432 case ARM::VST1q32wb_fixed: 2433 case ARM::VST1q64wb_fixed: 2434 case ARM::VST1q8wb_register: 2435 case ARM::VST1q16wb_register: 2436 case ARM::VST1q32wb_register: 2437 case ARM::VST1q64wb_register: 2438 case ARM::VST1d8Twb_fixed: 2439 case ARM::VST1d16Twb_fixed: 2440 case ARM::VST1d32Twb_fixed: 2441 case ARM::VST1d64Twb_fixed: 2442 case ARM::VST1d8Twb_register: 2443 case ARM::VST1d16Twb_register: 2444 case ARM::VST1d32Twb_register: 2445 case ARM::VST1d64Twb_register: 2446 case ARM::VST1d8Qwb_fixed: 2447 case ARM::VST1d16Qwb_fixed: 2448 case ARM::VST1d32Qwb_fixed: 2449 case ARM::VST1d64Qwb_fixed: 2450 case ARM::VST1d8Qwb_register: 2451 case ARM::VST1d16Qwb_register: 2452 case ARM::VST1d32Qwb_register: 2453 case ARM::VST1d64Qwb_register: 2454 case ARM::VST2d8wb_fixed: 2455 case ARM::VST2d16wb_fixed: 2456 case ARM::VST2d32wb_fixed: 2457 case ARM::VST2d8wb_register: 2458 case ARM::VST2d16wb_register: 2459 case ARM::VST2d32wb_register: 2460 case ARM::VST2q8wb_fixed: 2461 case ARM::VST2q16wb_fixed: 2462 case ARM::VST2q32wb_fixed: 2463 case ARM::VST2q8wb_register: 2464 case ARM::VST2q16wb_register: 2465 case ARM::VST2q32wb_register: 2466 case ARM::VST2b8wb_fixed: 2467 case ARM::VST2b16wb_fixed: 2468 case ARM::VST2b32wb_fixed: 2469 case ARM::VST2b8wb_register: 2470 case ARM::VST2b16wb_register: 2471 case ARM::VST2b32wb_register: 2472 if (Rm == 0xF) 2473 return MCDisassembler::Fail; 2474 Inst.addOperand(MCOperand::CreateImm(0)); 2475 break; 2476 case ARM::VST3d8_UPD: 2477 case ARM::VST3d16_UPD: 2478 case ARM::VST3d32_UPD: 2479 case ARM::VST3q8_UPD: 2480 case ARM::VST3q16_UPD: 2481 case ARM::VST3q32_UPD: 2482 case ARM::VST4d8_UPD: 2483 case ARM::VST4d16_UPD: 2484 case ARM::VST4d32_UPD: 2485 case ARM::VST4q8_UPD: 2486 case ARM::VST4q16_UPD: 2487 case ARM::VST4q32_UPD: 2488 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 break; 2491 default: 2492 break; 2493 } 2494 2495 // AddrMode6 Base (register+alignment) 2496 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2497 return MCDisassembler::Fail; 2498 2499 // AddrMode6 Offset (register) 2500 switch (Inst.getOpcode()) { 2501 default: 2502 if (Rm == 0xD) 2503 Inst.addOperand(MCOperand::CreateReg(0)); 2504 else if (Rm != 0xF) { 2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 } 2508 break; 2509 case ARM::VST1d8wb_fixed: 2510 case ARM::VST1d16wb_fixed: 2511 case ARM::VST1d32wb_fixed: 2512 case ARM::VST1d64wb_fixed: 2513 case ARM::VST1q8wb_fixed: 2514 case ARM::VST1q16wb_fixed: 2515 case ARM::VST1q32wb_fixed: 2516 case ARM::VST1q64wb_fixed: 2517 case ARM::VST1d8Twb_fixed: 2518 case ARM::VST1d16Twb_fixed: 2519 case ARM::VST1d32Twb_fixed: 2520 case ARM::VST1d64Twb_fixed: 2521 case ARM::VST1d8Qwb_fixed: 2522 case ARM::VST1d16Qwb_fixed: 2523 case ARM::VST1d32Qwb_fixed: 2524 case ARM::VST1d64Qwb_fixed: 2525 case ARM::VST2d8wb_fixed: 2526 case ARM::VST2d16wb_fixed: 2527 case ARM::VST2d32wb_fixed: 2528 case ARM::VST2q8wb_fixed: 2529 case ARM::VST2q16wb_fixed: 2530 case ARM::VST2q32wb_fixed: 2531 case ARM::VST2b8wb_fixed: 2532 case ARM::VST2b16wb_fixed: 2533 case ARM::VST2b32wb_fixed: 2534 break; 2535 } 2536 2537 2538 // First input register 2539 switch (Inst.getOpcode()) { 2540 case ARM::VST1q16: 2541 case ARM::VST1q32: 2542 case ARM::VST1q64: 2543 case ARM::VST1q8: 2544 case ARM::VST1q16wb_fixed: 2545 case ARM::VST1q16wb_register: 2546 case ARM::VST1q32wb_fixed: 2547 case ARM::VST1q32wb_register: 2548 case ARM::VST1q64wb_fixed: 2549 case ARM::VST1q64wb_register: 2550 case ARM::VST1q8wb_fixed: 2551 case ARM::VST1q8wb_register: 2552 case ARM::VST2d16: 2553 case ARM::VST2d32: 2554 case ARM::VST2d8: 2555 case ARM::VST2d16wb_fixed: 2556 case ARM::VST2d16wb_register: 2557 case ARM::VST2d32wb_fixed: 2558 case ARM::VST2d32wb_register: 2559 case ARM::VST2d8wb_fixed: 2560 case ARM::VST2d8wb_register: 2561 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2562 return MCDisassembler::Fail; 2563 break; 2564 case ARM::VST2b16: 2565 case ARM::VST2b32: 2566 case ARM::VST2b8: 2567 case ARM::VST2b16wb_fixed: 2568 case ARM::VST2b16wb_register: 2569 case ARM::VST2b32wb_fixed: 2570 case ARM::VST2b32wb_register: 2571 case ARM::VST2b8wb_fixed: 2572 case ARM::VST2b8wb_register: 2573 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2574 return MCDisassembler::Fail; 2575 break; 2576 default: 2577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2578 return MCDisassembler::Fail; 2579 } 2580 2581 // Second input register 2582 switch (Inst.getOpcode()) { 2583 case ARM::VST3d8: 2584 case ARM::VST3d16: 2585 case ARM::VST3d32: 2586 case ARM::VST3d8_UPD: 2587 case ARM::VST3d16_UPD: 2588 case ARM::VST3d32_UPD: 2589 case ARM::VST4d8: 2590 case ARM::VST4d16: 2591 case ARM::VST4d32: 2592 case ARM::VST4d8_UPD: 2593 case ARM::VST4d16_UPD: 2594 case ARM::VST4d32_UPD: 2595 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 break; 2598 case ARM::VST3q8: 2599 case ARM::VST3q16: 2600 case ARM::VST3q32: 2601 case ARM::VST3q8_UPD: 2602 case ARM::VST3q16_UPD: 2603 case ARM::VST3q32_UPD: 2604 case ARM::VST4q8: 2605 case ARM::VST4q16: 2606 case ARM::VST4q32: 2607 case ARM::VST4q8_UPD: 2608 case ARM::VST4q16_UPD: 2609 case ARM::VST4q32_UPD: 2610 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2611 return MCDisassembler::Fail; 2612 break; 2613 default: 2614 break; 2615 } 2616 2617 // Third input register 2618 switch (Inst.getOpcode()) { 2619 case ARM::VST3d8: 2620 case ARM::VST3d16: 2621 case ARM::VST3d32: 2622 case ARM::VST3d8_UPD: 2623 case ARM::VST3d16_UPD: 2624 case ARM::VST3d32_UPD: 2625 case ARM::VST4d8: 2626 case ARM::VST4d16: 2627 case ARM::VST4d32: 2628 case ARM::VST4d8_UPD: 2629 case ARM::VST4d16_UPD: 2630 case ARM::VST4d32_UPD: 2631 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2632 return MCDisassembler::Fail; 2633 break; 2634 case ARM::VST3q8: 2635 case ARM::VST3q16: 2636 case ARM::VST3q32: 2637 case ARM::VST3q8_UPD: 2638 case ARM::VST3q16_UPD: 2639 case ARM::VST3q32_UPD: 2640 case ARM::VST4q8: 2641 case ARM::VST4q16: 2642 case ARM::VST4q32: 2643 case ARM::VST4q8_UPD: 2644 case ARM::VST4q16_UPD: 2645 case ARM::VST4q32_UPD: 2646 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2647 return MCDisassembler::Fail; 2648 break; 2649 default: 2650 break; 2651 } 2652 2653 // Fourth input register 2654 switch (Inst.getOpcode()) { 2655 case ARM::VST4d8: 2656 case ARM::VST4d16: 2657 case ARM::VST4d32: 2658 case ARM::VST4d8_UPD: 2659 case ARM::VST4d16_UPD: 2660 case ARM::VST4d32_UPD: 2661 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2662 return MCDisassembler::Fail; 2663 break; 2664 case ARM::VST4q8: 2665 case ARM::VST4q16: 2666 case ARM::VST4q32: 2667 case ARM::VST4q8_UPD: 2668 case ARM::VST4q16_UPD: 2669 case ARM::VST4q32_UPD: 2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 break; 2673 default: 2674 break; 2675 } 2676 2677 return S; 2678 } 2679 2680 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2681 uint64_t Address, const void *Decoder) { 2682 DecodeStatus S = MCDisassembler::Success; 2683 2684 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2685 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2686 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2687 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2688 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2689 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2690 2691 align *= (1 << size); 2692 2693 switch (Inst.getOpcode()) { 2694 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2695 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2696 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2697 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2698 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 break; 2701 default: 2702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2703 return MCDisassembler::Fail; 2704 break; 2705 } 2706 if (Rm != 0xF) { 2707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2708 return MCDisassembler::Fail; 2709 } 2710 2711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2712 return MCDisassembler::Fail; 2713 Inst.addOperand(MCOperand::CreateImm(align)); 2714 2715 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2716 // variant encodes Rm == 0xf. Anything else is a register offset post- 2717 // increment and we need to add the register operand to the instruction. 2718 if (Rm != 0xD && Rm != 0xF && 2719 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 2722 return S; 2723 } 2724 2725 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2726 uint64_t Address, const void *Decoder) { 2727 DecodeStatus S = MCDisassembler::Success; 2728 2729 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2730 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2731 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2732 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2733 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2734 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2735 align *= 2*size; 2736 2737 switch (Inst.getOpcode()) { 2738 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2739 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2740 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2741 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2742 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2743 return MCDisassembler::Fail; 2744 break; 2745 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2746 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2747 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2748 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2749 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2750 return MCDisassembler::Fail; 2751 break; 2752 default: 2753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 break; 2756 } 2757 2758 if (Rm != 0xF) 2759 Inst.addOperand(MCOperand::CreateImm(0)); 2760 2761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2762 return MCDisassembler::Fail; 2763 Inst.addOperand(MCOperand::CreateImm(align)); 2764 2765 if (Rm != 0xD && Rm != 0xF) { 2766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2767 return MCDisassembler::Fail; 2768 } 2769 2770 return S; 2771 } 2772 2773 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2774 uint64_t Address, const void *Decoder) { 2775 DecodeStatus S = MCDisassembler::Success; 2776 2777 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2778 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2779 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2780 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2781 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2782 2783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 if (Rm != 0xF) { 2790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2791 return MCDisassembler::Fail; 2792 } 2793 2794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 Inst.addOperand(MCOperand::CreateImm(0)); 2797 2798 if (Rm == 0xD) 2799 Inst.addOperand(MCOperand::CreateReg(0)); 2800 else if (Rm != 0xF) { 2801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 } 2804 2805 return S; 2806 } 2807 2808 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2809 uint64_t Address, const void *Decoder) { 2810 DecodeStatus S = MCDisassembler::Success; 2811 2812 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2813 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2814 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2815 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2816 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2817 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2818 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2819 2820 if (size == 0x3) { 2821 size = 4; 2822 align = 16; 2823 } else { 2824 if (size == 2) { 2825 size = 1 << size; 2826 align *= 8; 2827 } else { 2828 size = 1 << size; 2829 align *= 4*size; 2830 } 2831 } 2832 2833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2838 return MCDisassembler::Fail; 2839 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2840 return MCDisassembler::Fail; 2841 if (Rm != 0xF) { 2842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2843 return MCDisassembler::Fail; 2844 } 2845 2846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 Inst.addOperand(MCOperand::CreateImm(align)); 2849 2850 if (Rm == 0xD) 2851 Inst.addOperand(MCOperand::CreateReg(0)); 2852 else if (Rm != 0xF) { 2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 } 2856 2857 return S; 2858 } 2859 2860 static DecodeStatus 2861 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2862 uint64_t Address, const void *Decoder) { 2863 DecodeStatus S = MCDisassembler::Success; 2864 2865 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2866 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2867 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2868 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2869 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2870 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2871 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2872 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2873 2874 if (Q) { 2875 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2876 return MCDisassembler::Fail; 2877 } else { 2878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 } 2881 2882 Inst.addOperand(MCOperand::CreateImm(imm)); 2883 2884 switch (Inst.getOpcode()) { 2885 case ARM::VORRiv4i16: 2886 case ARM::VORRiv2i32: 2887 case ARM::VBICiv4i16: 2888 case ARM::VBICiv2i32: 2889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 break; 2892 case ARM::VORRiv8i16: 2893 case ARM::VORRiv4i32: 2894 case ARM::VBICiv8i16: 2895 case ARM::VBICiv4i32: 2896 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 break; 2899 default: 2900 break; 2901 } 2902 2903 return S; 2904 } 2905 2906 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2907 uint64_t Address, const void *Decoder) { 2908 DecodeStatus S = MCDisassembler::Success; 2909 2910 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2911 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2912 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2913 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2914 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2915 2916 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2919 return MCDisassembler::Fail; 2920 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2921 2922 return S; 2923 } 2924 2925 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2926 uint64_t Address, const void *Decoder) { 2927 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2928 return MCDisassembler::Success; 2929 } 2930 2931 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2932 uint64_t Address, const void *Decoder) { 2933 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2934 return MCDisassembler::Success; 2935 } 2936 2937 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2938 uint64_t Address, const void *Decoder) { 2939 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2940 return MCDisassembler::Success; 2941 } 2942 2943 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2944 uint64_t Address, const void *Decoder) { 2945 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2946 return MCDisassembler::Success; 2947 } 2948 2949 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2950 uint64_t Address, const void *Decoder) { 2951 DecodeStatus S = MCDisassembler::Success; 2952 2953 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2954 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2955 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2956 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2957 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2958 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2959 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2960 2961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 if (op) { 2964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2965 return MCDisassembler::Fail; // Writeback 2966 } 2967 2968 switch (Inst.getOpcode()) { 2969 case ARM::VTBL2: 2970 case ARM::VTBX2: 2971 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2972 return MCDisassembler::Fail; 2973 break; 2974 default: 2975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2976 return MCDisassembler::Fail; 2977 } 2978 2979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 2982 return S; 2983 } 2984 2985 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2986 uint64_t Address, const void *Decoder) { 2987 DecodeStatus S = MCDisassembler::Success; 2988 2989 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2990 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2991 2992 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2993 return MCDisassembler::Fail; 2994 2995 switch(Inst.getOpcode()) { 2996 default: 2997 return MCDisassembler::Fail; 2998 case ARM::tADR: 2999 break; // tADR does not explicitly represent the PC as an operand. 3000 case ARM::tADDrSPi: 3001 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3002 break; 3003 } 3004 3005 Inst.addOperand(MCOperand::CreateImm(imm)); 3006 return S; 3007 } 3008 3009 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3010 uint64_t Address, const void *Decoder) { 3011 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3012 true, 2, Inst, Decoder)) 3013 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3014 return MCDisassembler::Success; 3015 } 3016 3017 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3018 uint64_t Address, const void *Decoder) { 3019 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3020 true, 4, Inst, Decoder)) 3021 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3022 return MCDisassembler::Success; 3023 } 3024 3025 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3026 uint64_t Address, const void *Decoder) { 3027 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 3028 true, 2, Inst, Decoder)) 3029 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 3030 return MCDisassembler::Success; 3031 } 3032 3033 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3034 uint64_t Address, const void *Decoder) { 3035 DecodeStatus S = MCDisassembler::Success; 3036 3037 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 3038 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 3039 3040 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3041 return MCDisassembler::Fail; 3042 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3043 return MCDisassembler::Fail; 3044 3045 return S; 3046 } 3047 3048 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3049 uint64_t Address, const void *Decoder) { 3050 DecodeStatus S = MCDisassembler::Success; 3051 3052 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 3053 unsigned imm = fieldFromInstruction32(Val, 3, 5); 3054 3055 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3056 return MCDisassembler::Fail; 3057 Inst.addOperand(MCOperand::CreateImm(imm)); 3058 3059 return S; 3060 } 3061 3062 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3063 uint64_t Address, const void *Decoder) { 3064 unsigned imm = Val << 2; 3065 3066 Inst.addOperand(MCOperand::CreateImm(imm)); 3067 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3068 3069 return MCDisassembler::Success; 3070 } 3071 3072 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3073 uint64_t Address, const void *Decoder) { 3074 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3075 Inst.addOperand(MCOperand::CreateImm(Val)); 3076 3077 return MCDisassembler::Success; 3078 } 3079 3080 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3081 uint64_t Address, const void *Decoder) { 3082 DecodeStatus S = MCDisassembler::Success; 3083 3084 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3085 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3086 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3087 3088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3091 return MCDisassembler::Fail; 3092 Inst.addOperand(MCOperand::CreateImm(imm)); 3093 3094 return S; 3095 } 3096 3097 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3098 uint64_t Address, const void *Decoder) { 3099 DecodeStatus S = MCDisassembler::Success; 3100 3101 switch (Inst.getOpcode()) { 3102 case ARM::t2PLDs: 3103 case ARM::t2PLDWs: 3104 case ARM::t2PLIs: 3105 break; 3106 default: { 3107 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3108 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 } 3111 } 3112 3113 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3114 if (Rn == 0xF) { 3115 switch (Inst.getOpcode()) { 3116 case ARM::t2LDRBs: 3117 Inst.setOpcode(ARM::t2LDRBpci); 3118 break; 3119 case ARM::t2LDRHs: 3120 Inst.setOpcode(ARM::t2LDRHpci); 3121 break; 3122 case ARM::t2LDRSHs: 3123 Inst.setOpcode(ARM::t2LDRSHpci); 3124 break; 3125 case ARM::t2LDRSBs: 3126 Inst.setOpcode(ARM::t2LDRSBpci); 3127 break; 3128 case ARM::t2PLDs: 3129 Inst.setOpcode(ARM::t2PLDi12); 3130 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3131 break; 3132 default: 3133 return MCDisassembler::Fail; 3134 } 3135 3136 int imm = fieldFromInstruction32(Insn, 0, 12); 3137 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3138 Inst.addOperand(MCOperand::CreateImm(imm)); 3139 3140 return S; 3141 } 3142 3143 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3144 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3145 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3146 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3147 return MCDisassembler::Fail; 3148 3149 return S; 3150 } 3151 3152 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3153 uint64_t Address, const void *Decoder) { 3154 int imm = Val & 0xFF; 3155 if (!(Val & 0x100)) imm *= -1; 3156 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3157 3158 return MCDisassembler::Success; 3159 } 3160 3161 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3162 uint64_t Address, const void *Decoder) { 3163 DecodeStatus S = MCDisassembler::Success; 3164 3165 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3166 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3167 3168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3171 return MCDisassembler::Fail; 3172 3173 return S; 3174 } 3175 3176 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3177 uint64_t Address, const void *Decoder) { 3178 DecodeStatus S = MCDisassembler::Success; 3179 3180 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3181 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3182 3183 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3184 return MCDisassembler::Fail; 3185 3186 Inst.addOperand(MCOperand::CreateImm(imm)); 3187 3188 return S; 3189 } 3190 3191 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3192 uint64_t Address, const void *Decoder) { 3193 int imm = Val & 0xFF; 3194 if (Val == 0) 3195 imm = INT32_MIN; 3196 else if (!(Val & 0x100)) 3197 imm *= -1; 3198 Inst.addOperand(MCOperand::CreateImm(imm)); 3199 3200 return MCDisassembler::Success; 3201 } 3202 3203 3204 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3205 uint64_t Address, const void *Decoder) { 3206 DecodeStatus S = MCDisassembler::Success; 3207 3208 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3209 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3210 3211 // Some instructions always use an additive offset. 3212 switch (Inst.getOpcode()) { 3213 case ARM::t2LDRT: 3214 case ARM::t2LDRBT: 3215 case ARM::t2LDRHT: 3216 case ARM::t2LDRSBT: 3217 case ARM::t2LDRSHT: 3218 case ARM::t2STRT: 3219 case ARM::t2STRBT: 3220 case ARM::t2STRHT: 3221 imm |= 0x100; 3222 break; 3223 default: 3224 break; 3225 } 3226 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 3232 return S; 3233 } 3234 3235 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3236 uint64_t Address, const void *Decoder) { 3237 DecodeStatus S = MCDisassembler::Success; 3238 3239 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3240 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3241 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3242 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3243 addr |= Rn << 9; 3244 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3245 3246 if (!load) { 3247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3248 return MCDisassembler::Fail; 3249 } 3250 3251 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3252 return MCDisassembler::Fail; 3253 3254 if (load) { 3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3256 return MCDisassembler::Fail; 3257 } 3258 3259 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 3262 return S; 3263 } 3264 3265 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3266 uint64_t Address, const void *Decoder) { 3267 DecodeStatus S = MCDisassembler::Success; 3268 3269 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3270 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3271 3272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3273 return MCDisassembler::Fail; 3274 Inst.addOperand(MCOperand::CreateImm(imm)); 3275 3276 return S; 3277 } 3278 3279 3280 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3281 uint64_t Address, const void *Decoder) { 3282 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3283 3284 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3285 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3286 Inst.addOperand(MCOperand::CreateImm(imm)); 3287 3288 return MCDisassembler::Success; 3289 } 3290 3291 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3292 uint64_t Address, const void *Decoder) { 3293 DecodeStatus S = MCDisassembler::Success; 3294 3295 if (Inst.getOpcode() == ARM::tADDrSP) { 3296 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3297 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3298 3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3303 return MCDisassembler::Fail; 3304 } else if (Inst.getOpcode() == ARM::tADDspr) { 3305 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3306 3307 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3308 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 } 3312 3313 return S; 3314 } 3315 3316 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3317 uint64_t Address, const void *Decoder) { 3318 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3319 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3320 3321 Inst.addOperand(MCOperand::CreateImm(imod)); 3322 Inst.addOperand(MCOperand::CreateImm(flags)); 3323 3324 return MCDisassembler::Success; 3325 } 3326 3327 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3328 uint64_t Address, const void *Decoder) { 3329 DecodeStatus S = MCDisassembler::Success; 3330 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3331 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3332 3333 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 Inst.addOperand(MCOperand::CreateImm(add)); 3336 3337 return S; 3338 } 3339 3340 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3341 uint64_t Address, const void *Decoder) { 3342 if (!tryAddingSymbolicOperand(Address, 3343 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3344 true, 4, Inst, Decoder)) 3345 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3346 return MCDisassembler::Success; 3347 } 3348 3349 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3350 uint64_t Address, const void *Decoder) { 3351 if (Val == 0xA || Val == 0xB) 3352 return MCDisassembler::Fail; 3353 3354 Inst.addOperand(MCOperand::CreateImm(Val)); 3355 return MCDisassembler::Success; 3356 } 3357 3358 static DecodeStatus 3359 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3360 uint64_t Address, const void *Decoder) { 3361 DecodeStatus S = MCDisassembler::Success; 3362 3363 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3364 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3365 3366 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 return S; 3372 } 3373 3374 static DecodeStatus 3375 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3376 uint64_t Address, const void *Decoder) { 3377 DecodeStatus S = MCDisassembler::Success; 3378 3379 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3380 if (pred == 0xE || pred == 0xF) { 3381 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3382 switch (opc) { 3383 default: 3384 return MCDisassembler::Fail; 3385 case 0xf3bf8f4: 3386 Inst.setOpcode(ARM::t2DSB); 3387 break; 3388 case 0xf3bf8f5: 3389 Inst.setOpcode(ARM::t2DMB); 3390 break; 3391 case 0xf3bf8f6: 3392 Inst.setOpcode(ARM::t2ISB); 3393 break; 3394 } 3395 3396 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3397 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3398 } 3399 3400 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3401 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3402 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3403 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3404 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3405 3406 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3407 return MCDisassembler::Fail; 3408 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 3411 return S; 3412 } 3413 3414 // Decode a shifted immediate operand. These basically consist 3415 // of an 8-bit value, and a 4-bit directive that specifies either 3416 // a splat operation or a rotation. 3417 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3418 uint64_t Address, const void *Decoder) { 3419 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3420 if (ctrl == 0) { 3421 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3422 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3423 switch (byte) { 3424 case 0: 3425 Inst.addOperand(MCOperand::CreateImm(imm)); 3426 break; 3427 case 1: 3428 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3429 break; 3430 case 2: 3431 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3432 break; 3433 case 3: 3434 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3435 (imm << 8) | imm)); 3436 break; 3437 } 3438 } else { 3439 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3440 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3441 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3442 Inst.addOperand(MCOperand::CreateImm(imm)); 3443 } 3444 3445 return MCDisassembler::Success; 3446 } 3447 3448 static DecodeStatus 3449 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3450 uint64_t Address, const void *Decoder){ 3451 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4, 3452 true, 2, Inst, Decoder)) 3453 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1))); 3454 return MCDisassembler::Success; 3455 } 3456 3457 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3458 uint64_t Address, const void *Decoder){ 3459 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3460 true, 4, Inst, Decoder)) 3461 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3462 return MCDisassembler::Success; 3463 } 3464 3465 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3466 uint64_t Address, const void *Decoder) { 3467 switch (Val) { 3468 default: 3469 return MCDisassembler::Fail; 3470 case 0xF: // SY 3471 case 0xE: // ST 3472 case 0xB: // ISH 3473 case 0xA: // ISHST 3474 case 0x7: // NSH 3475 case 0x6: // NSHST 3476 case 0x3: // OSH 3477 case 0x2: // OSHST 3478 break; 3479 } 3480 3481 Inst.addOperand(MCOperand::CreateImm(Val)); 3482 return MCDisassembler::Success; 3483 } 3484 3485 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3486 uint64_t Address, const void *Decoder) { 3487 if (!Val) return MCDisassembler::Fail; 3488 Inst.addOperand(MCOperand::CreateImm(Val)); 3489 return MCDisassembler::Success; 3490 } 3491 3492 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3493 uint64_t Address, const void *Decoder) { 3494 DecodeStatus S = MCDisassembler::Success; 3495 3496 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3497 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3498 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3499 3500 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3501 3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3505 return MCDisassembler::Fail; 3506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3507 return MCDisassembler::Fail; 3508 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 3511 return S; 3512 } 3513 3514 3515 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3516 uint64_t Address, const void *Decoder){ 3517 DecodeStatus S = MCDisassembler::Success; 3518 3519 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3520 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3521 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3522 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3523 3524 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 3527 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3528 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3529 3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3533 return MCDisassembler::Fail; 3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3537 return MCDisassembler::Fail; 3538 3539 return S; 3540 } 3541 3542 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3543 uint64_t Address, const void *Decoder) { 3544 DecodeStatus S = MCDisassembler::Success; 3545 3546 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3547 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3548 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3549 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3550 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3551 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3552 3553 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3554 3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 3564 return S; 3565 } 3566 3567 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3568 uint64_t Address, const void *Decoder) { 3569 DecodeStatus S = MCDisassembler::Success; 3570 3571 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3572 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3573 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3574 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3575 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3576 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3577 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3578 3579 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3580 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3581 3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3585 return MCDisassembler::Fail; 3586 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3587 return MCDisassembler::Fail; 3588 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 3591 return S; 3592 } 3593 3594 3595 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3596 uint64_t Address, const void *Decoder) { 3597 DecodeStatus S = MCDisassembler::Success; 3598 3599 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3600 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3601 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3602 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3603 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3604 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3605 3606 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3607 3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3611 return MCDisassembler::Fail; 3612 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 3617 return S; 3618 } 3619 3620 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3621 uint64_t Address, const void *Decoder) { 3622 DecodeStatus S = MCDisassembler::Success; 3623 3624 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3625 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3626 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3627 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3628 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3629 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3630 3631 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3632 3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3640 return MCDisassembler::Fail; 3641 3642 return S; 3643 } 3644 3645 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3646 uint64_t Address, const void *Decoder) { 3647 DecodeStatus S = MCDisassembler::Success; 3648 3649 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3650 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3651 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3652 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3653 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3654 3655 unsigned align = 0; 3656 unsigned index = 0; 3657 switch (size) { 3658 default: 3659 return MCDisassembler::Fail; 3660 case 0: 3661 if (fieldFromInstruction32(Insn, 4, 1)) 3662 return MCDisassembler::Fail; // UNDEFINED 3663 index = fieldFromInstruction32(Insn, 5, 3); 3664 break; 3665 case 1: 3666 if (fieldFromInstruction32(Insn, 5, 1)) 3667 return MCDisassembler::Fail; // UNDEFINED 3668 index = fieldFromInstruction32(Insn, 6, 2); 3669 if (fieldFromInstruction32(Insn, 4, 1)) 3670 align = 2; 3671 break; 3672 case 2: 3673 if (fieldFromInstruction32(Insn, 6, 1)) 3674 return MCDisassembler::Fail; // UNDEFINED 3675 index = fieldFromInstruction32(Insn, 7, 1); 3676 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3677 align = 4; 3678 } 3679 3680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 if (Rm != 0xF) { // Writeback 3683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3684 return MCDisassembler::Fail; 3685 } 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 Inst.addOperand(MCOperand::CreateImm(align)); 3689 if (Rm != 0xF) { 3690 if (Rm != 0xD) { 3691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 } else 3694 Inst.addOperand(MCOperand::CreateReg(0)); 3695 } 3696 3697 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 Inst.addOperand(MCOperand::CreateImm(index)); 3700 3701 return S; 3702 } 3703 3704 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3705 uint64_t Address, const void *Decoder) { 3706 DecodeStatus S = MCDisassembler::Success; 3707 3708 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3709 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3710 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3711 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3712 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3713 3714 unsigned align = 0; 3715 unsigned index = 0; 3716 switch (size) { 3717 default: 3718 return MCDisassembler::Fail; 3719 case 0: 3720 if (fieldFromInstruction32(Insn, 4, 1)) 3721 return MCDisassembler::Fail; // UNDEFINED 3722 index = fieldFromInstruction32(Insn, 5, 3); 3723 break; 3724 case 1: 3725 if (fieldFromInstruction32(Insn, 5, 1)) 3726 return MCDisassembler::Fail; // UNDEFINED 3727 index = fieldFromInstruction32(Insn, 6, 2); 3728 if (fieldFromInstruction32(Insn, 4, 1)) 3729 align = 2; 3730 break; 3731 case 2: 3732 if (fieldFromInstruction32(Insn, 6, 1)) 3733 return MCDisassembler::Fail; // UNDEFINED 3734 index = fieldFromInstruction32(Insn, 7, 1); 3735 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3736 align = 4; 3737 } 3738 3739 if (Rm != 0xF) { // Writeback 3740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3741 return MCDisassembler::Fail; 3742 } 3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 Inst.addOperand(MCOperand::CreateImm(align)); 3746 if (Rm != 0xF) { 3747 if (Rm != 0xD) { 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 } else 3751 Inst.addOperand(MCOperand::CreateReg(0)); 3752 } 3753 3754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3755 return MCDisassembler::Fail; 3756 Inst.addOperand(MCOperand::CreateImm(index)); 3757 3758 return S; 3759 } 3760 3761 3762 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3763 uint64_t Address, const void *Decoder) { 3764 DecodeStatus S = MCDisassembler::Success; 3765 3766 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3767 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3768 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3769 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3770 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3771 3772 unsigned align = 0; 3773 unsigned index = 0; 3774 unsigned inc = 1; 3775 switch (size) { 3776 default: 3777 return MCDisassembler::Fail; 3778 case 0: 3779 index = fieldFromInstruction32(Insn, 5, 3); 3780 if (fieldFromInstruction32(Insn, 4, 1)) 3781 align = 2; 3782 break; 3783 case 1: 3784 index = fieldFromInstruction32(Insn, 6, 2); 3785 if (fieldFromInstruction32(Insn, 4, 1)) 3786 align = 4; 3787 if (fieldFromInstruction32(Insn, 5, 1)) 3788 inc = 2; 3789 break; 3790 case 2: 3791 if (fieldFromInstruction32(Insn, 5, 1)) 3792 return MCDisassembler::Fail; // UNDEFINED 3793 index = fieldFromInstruction32(Insn, 7, 1); 3794 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3795 align = 8; 3796 if (fieldFromInstruction32(Insn, 6, 1)) 3797 inc = 2; 3798 break; 3799 } 3800 3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3802 return MCDisassembler::Fail; 3803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3804 return MCDisassembler::Fail; 3805 if (Rm != 0xF) { // Writeback 3806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3807 return MCDisassembler::Fail; 3808 } 3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 Inst.addOperand(MCOperand::CreateImm(align)); 3812 if (Rm != 0xF) { 3813 if (Rm != 0xD) { 3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3815 return MCDisassembler::Fail; 3816 } else 3817 Inst.addOperand(MCOperand::CreateReg(0)); 3818 } 3819 3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3821 return MCDisassembler::Fail; 3822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3823 return MCDisassembler::Fail; 3824 Inst.addOperand(MCOperand::CreateImm(index)); 3825 3826 return S; 3827 } 3828 3829 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3830 uint64_t Address, const void *Decoder) { 3831 DecodeStatus S = MCDisassembler::Success; 3832 3833 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3834 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3835 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3836 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3837 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3838 3839 unsigned align = 0; 3840 unsigned index = 0; 3841 unsigned inc = 1; 3842 switch (size) { 3843 default: 3844 return MCDisassembler::Fail; 3845 case 0: 3846 index = fieldFromInstruction32(Insn, 5, 3); 3847 if (fieldFromInstruction32(Insn, 4, 1)) 3848 align = 2; 3849 break; 3850 case 1: 3851 index = fieldFromInstruction32(Insn, 6, 2); 3852 if (fieldFromInstruction32(Insn, 4, 1)) 3853 align = 4; 3854 if (fieldFromInstruction32(Insn, 5, 1)) 3855 inc = 2; 3856 break; 3857 case 2: 3858 if (fieldFromInstruction32(Insn, 5, 1)) 3859 return MCDisassembler::Fail; // UNDEFINED 3860 index = fieldFromInstruction32(Insn, 7, 1); 3861 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3862 align = 8; 3863 if (fieldFromInstruction32(Insn, 6, 1)) 3864 inc = 2; 3865 break; 3866 } 3867 3868 if (Rm != 0xF) { // Writeback 3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 } 3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3873 return MCDisassembler::Fail; 3874 Inst.addOperand(MCOperand::CreateImm(align)); 3875 if (Rm != 0xF) { 3876 if (Rm != 0xD) { 3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 } else 3880 Inst.addOperand(MCOperand::CreateReg(0)); 3881 } 3882 3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3884 return MCDisassembler::Fail; 3885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3886 return MCDisassembler::Fail; 3887 Inst.addOperand(MCOperand::CreateImm(index)); 3888 3889 return S; 3890 } 3891 3892 3893 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3894 uint64_t Address, const void *Decoder) { 3895 DecodeStatus S = MCDisassembler::Success; 3896 3897 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3898 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3899 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3900 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3901 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3902 3903 unsigned align = 0; 3904 unsigned index = 0; 3905 unsigned inc = 1; 3906 switch (size) { 3907 default: 3908 return MCDisassembler::Fail; 3909 case 0: 3910 if (fieldFromInstruction32(Insn, 4, 1)) 3911 return MCDisassembler::Fail; // UNDEFINED 3912 index = fieldFromInstruction32(Insn, 5, 3); 3913 break; 3914 case 1: 3915 if (fieldFromInstruction32(Insn, 4, 1)) 3916 return MCDisassembler::Fail; // UNDEFINED 3917 index = fieldFromInstruction32(Insn, 6, 2); 3918 if (fieldFromInstruction32(Insn, 5, 1)) 3919 inc = 2; 3920 break; 3921 case 2: 3922 if (fieldFromInstruction32(Insn, 4, 2)) 3923 return MCDisassembler::Fail; // UNDEFINED 3924 index = fieldFromInstruction32(Insn, 7, 1); 3925 if (fieldFromInstruction32(Insn, 6, 1)) 3926 inc = 2; 3927 break; 3928 } 3929 3930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3931 return MCDisassembler::Fail; 3932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3933 return MCDisassembler::Fail; 3934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3935 return MCDisassembler::Fail; 3936 3937 if (Rm != 0xF) { // Writeback 3938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3939 return MCDisassembler::Fail; 3940 } 3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3942 return MCDisassembler::Fail; 3943 Inst.addOperand(MCOperand::CreateImm(align)); 3944 if (Rm != 0xF) { 3945 if (Rm != 0xD) { 3946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 } else 3949 Inst.addOperand(MCOperand::CreateReg(0)); 3950 } 3951 3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3955 return MCDisassembler::Fail; 3956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3957 return MCDisassembler::Fail; 3958 Inst.addOperand(MCOperand::CreateImm(index)); 3959 3960 return S; 3961 } 3962 3963 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 3964 uint64_t Address, const void *Decoder) { 3965 DecodeStatus S = MCDisassembler::Success; 3966 3967 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3968 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3969 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3970 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3971 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3972 3973 unsigned align = 0; 3974 unsigned index = 0; 3975 unsigned inc = 1; 3976 switch (size) { 3977 default: 3978 return MCDisassembler::Fail; 3979 case 0: 3980 if (fieldFromInstruction32(Insn, 4, 1)) 3981 return MCDisassembler::Fail; // UNDEFINED 3982 index = fieldFromInstruction32(Insn, 5, 3); 3983 break; 3984 case 1: 3985 if (fieldFromInstruction32(Insn, 4, 1)) 3986 return MCDisassembler::Fail; // UNDEFINED 3987 index = fieldFromInstruction32(Insn, 6, 2); 3988 if (fieldFromInstruction32(Insn, 5, 1)) 3989 inc = 2; 3990 break; 3991 case 2: 3992 if (fieldFromInstruction32(Insn, 4, 2)) 3993 return MCDisassembler::Fail; // UNDEFINED 3994 index = fieldFromInstruction32(Insn, 7, 1); 3995 if (fieldFromInstruction32(Insn, 6, 1)) 3996 inc = 2; 3997 break; 3998 } 3999 4000 if (Rm != 0xF) { // Writeback 4001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 } 4004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 Inst.addOperand(MCOperand::CreateImm(align)); 4007 if (Rm != 0xF) { 4008 if (Rm != 0xD) { 4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 } else 4012 Inst.addOperand(MCOperand::CreateReg(0)); 4013 } 4014 4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 Inst.addOperand(MCOperand::CreateImm(index)); 4022 4023 return S; 4024 } 4025 4026 4027 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 4031 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4032 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4033 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4034 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4035 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4036 4037 unsigned align = 0; 4038 unsigned index = 0; 4039 unsigned inc = 1; 4040 switch (size) { 4041 default: 4042 return MCDisassembler::Fail; 4043 case 0: 4044 if (fieldFromInstruction32(Insn, 4, 1)) 4045 align = 4; 4046 index = fieldFromInstruction32(Insn, 5, 3); 4047 break; 4048 case 1: 4049 if (fieldFromInstruction32(Insn, 4, 1)) 4050 align = 8; 4051 index = fieldFromInstruction32(Insn, 6, 2); 4052 if (fieldFromInstruction32(Insn, 5, 1)) 4053 inc = 2; 4054 break; 4055 case 2: 4056 if (fieldFromInstruction32(Insn, 4, 2)) 4057 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4058 index = fieldFromInstruction32(Insn, 7, 1); 4059 if (fieldFromInstruction32(Insn, 6, 1)) 4060 inc = 2; 4061 break; 4062 } 4063 4064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4065 return MCDisassembler::Fail; 4066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4067 return MCDisassembler::Fail; 4068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4069 return MCDisassembler::Fail; 4070 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4071 return MCDisassembler::Fail; 4072 4073 if (Rm != 0xF) { // Writeback 4074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4075 return MCDisassembler::Fail; 4076 } 4077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4078 return MCDisassembler::Fail; 4079 Inst.addOperand(MCOperand::CreateImm(align)); 4080 if (Rm != 0xF) { 4081 if (Rm != 0xD) { 4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 } else 4085 Inst.addOperand(MCOperand::CreateReg(0)); 4086 } 4087 4088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4089 return MCDisassembler::Fail; 4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4095 return MCDisassembler::Fail; 4096 Inst.addOperand(MCOperand::CreateImm(index)); 4097 4098 return S; 4099 } 4100 4101 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4102 uint64_t Address, const void *Decoder) { 4103 DecodeStatus S = MCDisassembler::Success; 4104 4105 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4106 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4107 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4108 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4109 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4110 4111 unsigned align = 0; 4112 unsigned index = 0; 4113 unsigned inc = 1; 4114 switch (size) { 4115 default: 4116 return MCDisassembler::Fail; 4117 case 0: 4118 if (fieldFromInstruction32(Insn, 4, 1)) 4119 align = 4; 4120 index = fieldFromInstruction32(Insn, 5, 3); 4121 break; 4122 case 1: 4123 if (fieldFromInstruction32(Insn, 4, 1)) 4124 align = 8; 4125 index = fieldFromInstruction32(Insn, 6, 2); 4126 if (fieldFromInstruction32(Insn, 5, 1)) 4127 inc = 2; 4128 break; 4129 case 2: 4130 if (fieldFromInstruction32(Insn, 4, 2)) 4131 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4132 index = fieldFromInstruction32(Insn, 7, 1); 4133 if (fieldFromInstruction32(Insn, 6, 1)) 4134 inc = 2; 4135 break; 4136 } 4137 4138 if (Rm != 0xF) { // Writeback 4139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4140 return MCDisassembler::Fail; 4141 } 4142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4143 return MCDisassembler::Fail; 4144 Inst.addOperand(MCOperand::CreateImm(align)); 4145 if (Rm != 0xF) { 4146 if (Rm != 0xD) { 4147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4148 return MCDisassembler::Fail; 4149 } else 4150 Inst.addOperand(MCOperand::CreateReg(0)); 4151 } 4152 4153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4154 return MCDisassembler::Fail; 4155 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4156 return MCDisassembler::Fail; 4157 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4158 return MCDisassembler::Fail; 4159 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 Inst.addOperand(MCOperand::CreateImm(index)); 4162 4163 return S; 4164 } 4165 4166 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4167 uint64_t Address, const void *Decoder) { 4168 DecodeStatus S = MCDisassembler::Success; 4169 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4170 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4171 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4172 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4173 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4174 4175 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4176 S = MCDisassembler::SoftFail; 4177 4178 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4179 return MCDisassembler::Fail; 4180 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 4189 return S; 4190 } 4191 4192 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4193 uint64_t Address, const void *Decoder) { 4194 DecodeStatus S = MCDisassembler::Success; 4195 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4196 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4197 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4198 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4199 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4200 4201 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4202 S = MCDisassembler::SoftFail; 4203 4204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4205 return MCDisassembler::Fail; 4206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4207 return MCDisassembler::Fail; 4208 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4209 return MCDisassembler::Fail; 4210 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4211 return MCDisassembler::Fail; 4212 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4213 return MCDisassembler::Fail; 4214 4215 return S; 4216 } 4217 4218 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4219 uint64_t Address, const void *Decoder) { 4220 DecodeStatus S = MCDisassembler::Success; 4221 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4222 unsigned mask = fieldFromInstruction16(Insn, 0, 4); 4223 4224 if (pred == 0xF) { 4225 pred = 0xE; 4226 S = MCDisassembler::SoftFail; 4227 } 4228 4229 if (mask == 0x0) { 4230 mask |= 0x8; 4231 S = MCDisassembler::SoftFail; 4232 } 4233 4234 Inst.addOperand(MCOperand::CreateImm(pred)); 4235 Inst.addOperand(MCOperand::CreateImm(mask)); 4236 return S; 4237 } 4238 4239 static DecodeStatus 4240 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4241 uint64_t Address, const void *Decoder) { 4242 DecodeStatus S = MCDisassembler::Success; 4243 4244 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4245 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4247 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4248 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4249 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4250 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4251 bool writeback = (W == 1) | (P == 0); 4252 4253 addr |= (U << 8) | (Rn << 9); 4254 4255 if (writeback && (Rn == Rt || Rn == Rt2)) 4256 Check(S, MCDisassembler::SoftFail); 4257 if (Rt == Rt2) 4258 Check(S, MCDisassembler::SoftFail); 4259 4260 // Rt 4261 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 // Rt2 4264 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 // Writeback operand 4267 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 // addr 4270 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4271 return MCDisassembler::Fail; 4272 4273 return S; 4274 } 4275 4276 static DecodeStatus 4277 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4278 uint64_t Address, const void *Decoder) { 4279 DecodeStatus S = MCDisassembler::Success; 4280 4281 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4282 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4283 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4284 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4285 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4286 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4287 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4288 bool writeback = (W == 1) | (P == 0); 4289 4290 addr |= (U << 8) | (Rn << 9); 4291 4292 if (writeback && (Rn == Rt || Rn == Rt2)) 4293 Check(S, MCDisassembler::SoftFail); 4294 4295 // Writeback operand 4296 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 // Rt 4299 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 // Rt2 4302 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4303 return MCDisassembler::Fail; 4304 // addr 4305 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 4308 return S; 4309 } 4310 4311 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4312 uint64_t Address, const void *Decoder) { 4313 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4314 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4315 if (sign1 != sign2) return MCDisassembler::Fail; 4316 4317 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4318 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4319 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4320 Val |= sign1 << 12; 4321 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4322 4323 return MCDisassembler::Success; 4324 } 4325 4326 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4327 uint64_t Address, 4328 const void *Decoder) { 4329 DecodeStatus S = MCDisassembler::Success; 4330 4331 // Shift of "asr #32" is not allowed in Thumb2 mode. 4332 if (Val == 0x20) S = MCDisassembler::SoftFail; 4333 Inst.addOperand(MCOperand::CreateImm(Val)); 4334 return S; 4335 } 4336 4337 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4338 uint64_t Address, const void *Decoder) { 4339 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4340 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4341 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4342 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4343 4344 if (pred == 0xF) 4345 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4346 4347 DecodeStatus S = MCDisassembler::Success; 4348 4349 if (Rt == Rn || Rn == Rt2) 4350 S = MCDisassembler::SoftFail; 4351 4352 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4353 return MCDisassembler::Fail; 4354 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4355 return MCDisassembler::Fail; 4356 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 4361 return S; 4362 } 4363 4364 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4365 uint64_t Address, const void *Decoder) { 4366 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4367 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4368 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4369 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4370 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4371 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4372 4373 DecodeStatus S = MCDisassembler::Success; 4374 4375 // VMOVv2f32 is ambiguous with these decodings. 4376 if (!(imm & 0x38) && cmode == 0xF) { 4377 Inst.setOpcode(ARM::VMOVv2f32); 4378 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4379 } 4380 4381 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4382 4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4384 return MCDisassembler::Fail; 4385 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4386 return MCDisassembler::Fail; 4387 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4388 4389 return S; 4390 } 4391 4392 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4393 uint64_t Address, const void *Decoder) { 4394 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4395 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4396 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4397 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4398 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4399 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4400 4401 DecodeStatus S = MCDisassembler::Success; 4402 4403 // VMOVv4f32 is ambiguous with these decodings. 4404 if (!(imm & 0x38) && cmode == 0xF) { 4405 Inst.setOpcode(ARM::VMOVv4f32); 4406 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4407 } 4408 4409 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4410 4411 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4412 return MCDisassembler::Fail; 4413 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4414 return MCDisassembler::Fail; 4415 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4416 4417 return S; 4418 } 4419 4420 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4421 uint64_t Address, const void *Decoder) { 4422 DecodeStatus S = MCDisassembler::Success; 4423 4424 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4425 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4426 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4427 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4428 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4429 4430 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4431 S = MCDisassembler::SoftFail; 4432 4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4440 return MCDisassembler::Fail; 4441 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4442 return MCDisassembler::Fail; 4443 4444 return S; 4445 } 4446 4447 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4448 uint64_t Address, const void *Decoder) { 4449 4450 DecodeStatus S = MCDisassembler::Success; 4451 4452 unsigned CRm = fieldFromInstruction32(Val, 0, 4); 4453 unsigned opc1 = fieldFromInstruction32(Val, 4, 4); 4454 unsigned cop = fieldFromInstruction32(Val, 8, 4); 4455 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4456 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4); 4457 4458 if ((cop & ~0x1) == 0xa) 4459 return MCDisassembler::Fail; 4460 4461 if (Rt == Rt2) 4462 S = MCDisassembler::SoftFail; 4463 4464 Inst.addOperand(MCOperand::CreateImm(cop)); 4465 Inst.addOperand(MCOperand::CreateImm(opc1)); 4466 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4469 return MCDisassembler::Fail; 4470 Inst.addOperand(MCOperand::CreateImm(CRm)); 4471 4472 return S; 4473 } 4474 4475