1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 const EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 const EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 llvm_unreachable("Invalid DecodeStatus!"); 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 132 unsigned RegNo, uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 146 uint64_t Address, const void *Decoder); 147 148 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 153 unsigned Insn, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 165 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 166 unsigned Insn, 167 uint64_t Adddress, 168 const void *Decoder); 169 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 262 263 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 326 static DecodeStatus DecodeLDR(llvm::MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 #include "ARMGenDisassemblerTables.inc" 329 #include "ARMGenInstrInfo.inc" 330 #include "ARMGenEDInfo.inc" 331 332 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 333 return new ARMDisassembler(STI); 334 } 335 336 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 337 return new ThumbDisassembler(STI); 338 } 339 340 const EDInstInfo *ARMDisassembler::getEDInfo() const { 341 return instInfoARM; 342 } 343 344 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 345 return instInfoARM; 346 } 347 348 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 349 const MemoryObject &Region, 350 uint64_t Address, 351 raw_ostream &os, 352 raw_ostream &cs) const { 353 CommentStream = &cs; 354 355 uint8_t bytes[4]; 356 357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 359 360 // We want to read exactly 4 bytes of data. 361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 362 Size = 0; 363 return MCDisassembler::Fail; 364 } 365 366 // Encoded as a small-endian 32-bit word in the stream. 367 uint32_t insn = (bytes[3] << 24) | 368 (bytes[2] << 16) | 369 (bytes[1] << 8) | 370 (bytes[0] << 0); 371 372 // Calling the auto-generated decoder function. 373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 374 if (result != MCDisassembler::Fail) { 375 Size = 4; 376 return result; 377 } 378 379 // VFP and NEON instructions, similarly, are shared between ARM 380 // and Thumb modes. 381 MI.clear(); 382 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 return result; 386 } 387 388 MI.clear(); 389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 390 if (result != MCDisassembler::Fail) { 391 Size = 4; 392 // Add a fake predicate operand, because we share these instruction 393 // definitions with Thumb2 where these instructions are predicable. 394 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 395 return MCDisassembler::Fail; 396 return result; 397 } 398 399 MI.clear(); 400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 401 if (result != MCDisassembler::Fail) { 402 Size = 4; 403 // Add a fake predicate operand, because we share these instruction 404 // definitions with Thumb2 where these instructions are predicable. 405 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 406 return MCDisassembler::Fail; 407 return result; 408 } 409 410 MI.clear(); 411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 412 if (result != MCDisassembler::Fail) { 413 Size = 4; 414 // Add a fake predicate operand, because we share these instruction 415 // definitions with Thumb2 where these instructions are predicable. 416 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 417 return MCDisassembler::Fail; 418 return result; 419 } 420 421 MI.clear(); 422 423 Size = 0; 424 return MCDisassembler::Fail; 425 } 426 427 namespace llvm { 428 extern const MCInstrDesc ARMInsts[]; 429 } 430 431 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 432 /// immediate Value in the MCInst. The immediate Value has had any PC 433 /// adjustment made by the caller. If the instruction is a branch instruction 434 /// then isBranch is true, else false. If the getOpInfo() function was set as 435 /// part of the setupForSymbolicDisassembly() call then that function is called 436 /// to get any symbolic information at the Address for this instruction. If 437 /// that returns non-zero then the symbolic information it returns is used to 438 /// create an MCExpr and that is added as an operand to the MCInst. If 439 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 440 /// Value is done and if a symbol is found an MCExpr is created with that, else 441 /// an MCExpr with Value is created. This function returns true if it adds an 442 /// operand to the MCInst and false otherwise. 443 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 444 bool isBranch, uint64_t InstSize, 445 MCInst &MI, const void *Decoder) { 446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 448 struct LLVMOpInfo1 SymbolicOp; 449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 450 SymbolicOp.Value = Value; 451 void *DisInfo = Dis->getDisInfoBlock(); 452 453 if (!getOpInfo || 454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 455 // Clear SymbolicOp.Value from above and also all other fields. 456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 458 if (!SymbolLookUp) 459 return false; 460 uint64_t ReferenceType; 461 if (isBranch) 462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 463 else 464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 465 const char *ReferenceName; 466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 467 &ReferenceName); 468 if (Name) { 469 SymbolicOp.AddSymbol.Name = Name; 470 SymbolicOp.AddSymbol.Present = true; 471 } 472 // For branches always create an MCExpr so it gets printed as hex address. 473 else if (isBranch) { 474 SymbolicOp.Value = Value; 475 } 476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 478 if (!Name && !isBranch) 479 return false; 480 } 481 482 MCContext *Ctx = Dis->getMCContext(); 483 const MCExpr *Add = NULL; 484 if (SymbolicOp.AddSymbol.Present) { 485 if (SymbolicOp.AddSymbol.Name) { 486 StringRef Name(SymbolicOp.AddSymbol.Name); 487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 488 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 489 } else { 490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 491 } 492 } 493 494 const MCExpr *Sub = NULL; 495 if (SymbolicOp.SubtractSymbol.Present) { 496 if (SymbolicOp.SubtractSymbol.Name) { 497 StringRef Name(SymbolicOp.SubtractSymbol.Name); 498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 500 } else { 501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 502 } 503 } 504 505 const MCExpr *Off = NULL; 506 if (SymbolicOp.Value != 0) 507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 508 509 const MCExpr *Expr; 510 if (Sub) { 511 const MCExpr *LHS; 512 if (Add) 513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 514 else 515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 516 if (Off != 0) 517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 518 else 519 Expr = LHS; 520 } else if (Add) { 521 if (Off != 0) 522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 523 else 524 Expr = Add; 525 } else { 526 if (Off != 0) 527 Expr = Off; 528 else 529 Expr = MCConstantExpr::Create(0, *Ctx); 530 } 531 532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 537 MI.addOperand(MCOperand::CreateExpr(Expr)); 538 else 539 llvm_unreachable("bad SymbolicOp.VariantKind"); 540 541 return true; 542 } 543 544 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 545 /// referenced by a load instruction with the base register that is the Pc. 546 /// These can often be values in a literal pool near the Address of the 547 /// instruction. The Address of the instruction and its immediate Value are 548 /// used as a possible literal pool entry. The SymbolLookUp call back will 549 /// return the name of a symbol referenced by the the literal pool's entry if 550 /// the referenced address is that of a symbol. Or it will return a pointer to 551 /// a literal 'C' string if the referenced address of the literal pool's entry 552 /// is an address into a section with 'C' string literals. 553 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 554 const void *Decoder) { 555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 557 if (SymbolLookUp) { 558 void *DisInfo = Dis->getDisInfoBlock(); 559 uint64_t ReferenceType; 560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 561 const char *ReferenceName; 562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 566 } 567 } 568 569 // Thumb1 instructions don't have explicit S bits. Rather, they 570 // implicitly set CPSR. Since it's not represented in the encoding, the 571 // auto-generated decoder won't inject the CPSR operand. We need to fix 572 // that as a post-pass. 573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 576 MCInst::iterator I = MI.begin(); 577 for (unsigned i = 0; i < NumOps; ++i, ++I) { 578 if (I == MI.end()) break; 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 580 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 582 return; 583 } 584 } 585 586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 587 } 588 589 // Most Thumb instructions don't have explicit predicates in the 590 // encoding, but rather get their predicates from IT context. We need 591 // to fix up the predicate operands using this context information as a 592 // post-pass. 593 MCDisassembler::DecodeStatus 594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 595 MCDisassembler::DecodeStatus S = Success; 596 597 // A few instructions actually have predicates encoded in them. Don't 598 // try to overwrite it if we're seeing one of those. 599 switch (MI.getOpcode()) { 600 case ARM::tBcc: 601 case ARM::t2Bcc: 602 case ARM::tCBZ: 603 case ARM::tCBNZ: 604 case ARM::tCPS: 605 case ARM::t2CPS3p: 606 case ARM::t2CPS2p: 607 case ARM::t2CPS1p: 608 case ARM::tMOVSr: 609 case ARM::tSETEND: 610 // Some instructions (mostly conditional branches) are not 611 // allowed in IT blocks. 612 if (!ITBlock.empty()) 613 S = SoftFail; 614 else 615 return Success; 616 break; 617 case ARM::tB: 618 case ARM::t2B: 619 case ARM::t2TBB: 620 case ARM::t2TBH: 621 // Some instructions (mostly unconditional branches) can 622 // only appears at the end of, or outside of, an IT. 623 if (ITBlock.size() > 1) 624 S = SoftFail; 625 break; 626 default: 627 break; 628 } 629 630 // If we're in an IT block, base the predicate on that. Otherwise, 631 // assume a predicate of AL. 632 unsigned CC; 633 if (!ITBlock.empty()) { 634 CC = ITBlock.back(); 635 if (CC == 0xF) 636 CC = ARMCC::AL; 637 ITBlock.pop_back(); 638 } else 639 CC = ARMCC::AL; 640 641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 643 MCInst::iterator I = MI.begin(); 644 for (unsigned i = 0; i < NumOps; ++i, ++I) { 645 if (I == MI.end()) break; 646 if (OpInfo[i].isPredicate()) { 647 I = MI.insert(I, MCOperand::CreateImm(CC)); 648 ++I; 649 if (CC == ARMCC::AL) 650 MI.insert(I, MCOperand::CreateReg(0)); 651 else 652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 653 return S; 654 } 655 } 656 657 I = MI.insert(I, MCOperand::CreateImm(CC)); 658 ++I; 659 if (CC == ARMCC::AL) 660 MI.insert(I, MCOperand::CreateReg(0)); 661 else 662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 663 664 return S; 665 } 666 667 // Thumb VFP instructions are a special case. Because we share their 668 // encodings between ARM and Thumb modes, and they are predicable in ARM 669 // mode, the auto-generated decoder will give them an (incorrect) 670 // predicate operand. We need to rewrite these operands based on the IT 671 // context as a post-pass. 672 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 673 unsigned CC; 674 if (!ITBlock.empty()) { 675 CC = ITBlock.back(); 676 ITBlock.pop_back(); 677 } else 678 CC = ARMCC::AL; 679 680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 681 MCInst::iterator I = MI.begin(); 682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 683 for (unsigned i = 0; i < NumOps; ++i, ++I) { 684 if (OpInfo[i].isPredicate() ) { 685 I->setImm(CC); 686 ++I; 687 if (CC == ARMCC::AL) 688 I->setReg(0); 689 else 690 I->setReg(ARM::CPSR); 691 return; 692 } 693 } 694 } 695 696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 697 const MemoryObject &Region, 698 uint64_t Address, 699 raw_ostream &os, 700 raw_ostream &cs) const { 701 CommentStream = &cs; 702 703 uint8_t bytes[4]; 704 705 assert((STI.getFeatureBits() & ARM::ModeThumb) && 706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 707 708 // We want to read exactly 2 bytes of data. 709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 710 Size = 0; 711 return MCDisassembler::Fail; 712 } 713 714 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 716 if (result != MCDisassembler::Fail) { 717 Size = 2; 718 Check(result, AddThumbPredicate(MI)); 719 return result; 720 } 721 722 MI.clear(); 723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 724 if (result) { 725 Size = 2; 726 bool InITBlock = !ITBlock.empty(); 727 Check(result, AddThumbPredicate(MI)); 728 AddThumb1SBit(MI, InITBlock); 729 return result; 730 } 731 732 MI.clear(); 733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 734 if (result != MCDisassembler::Fail) { 735 Size = 2; 736 737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 738 // the Thumb predicate. 739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 740 result = MCDisassembler::SoftFail; 741 742 Check(result, AddThumbPredicate(MI)); 743 744 // If we find an IT instruction, we need to parse its condition 745 // code and mask operands so that we can apply them correctly 746 // to the subsequent instructions. 747 if (MI.getOpcode() == ARM::t2IT) { 748 749 // (3 - the number of trailing zeros) is the number of then / else. 750 unsigned firstcond = MI.getOperand(0).getImm(); 751 unsigned Mask = MI.getOperand(1).getImm(); 752 unsigned CondBit0 = Mask >> 4 & 1; 753 unsigned NumTZ = CountTrailingZeros_32(Mask); 754 assert(NumTZ <= 3 && "Invalid IT mask!"); 755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 756 bool T = ((Mask >> Pos) & 1) == CondBit0; 757 if (T) 758 ITBlock.insert(ITBlock.begin(), firstcond); 759 else 760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 761 } 762 763 ITBlock.push_back(firstcond); 764 } 765 766 return result; 767 } 768 769 // We want to read exactly 4 bytes of data. 770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 771 Size = 0; 772 return MCDisassembler::Fail; 773 } 774 775 uint32_t insn32 = (bytes[3] << 8) | 776 (bytes[2] << 0) | 777 (bytes[1] << 24) | 778 (bytes[0] << 16); 779 MI.clear(); 780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 781 if (result != MCDisassembler::Fail) { 782 Size = 4; 783 bool InITBlock = ITBlock.size(); 784 Check(result, AddThumbPredicate(MI)); 785 AddThumb1SBit(MI, InITBlock); 786 return result; 787 } 788 789 MI.clear(); 790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 791 if (result != MCDisassembler::Fail) { 792 Size = 4; 793 Check(result, AddThumbPredicate(MI)); 794 return result; 795 } 796 797 MI.clear(); 798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 799 if (result != MCDisassembler::Fail) { 800 Size = 4; 801 UpdateThumbVFPPredicate(MI); 802 return result; 803 } 804 805 MI.clear(); 806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 807 if (result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(result, AddThumbPredicate(MI)); 810 return result; 811 } 812 813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 814 MI.clear(); 815 uint32_t NEONLdStInsn = insn32; 816 NEONLdStInsn &= 0xF0FFFFFF; 817 NEONLdStInsn |= 0x04000000; 818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 819 if (result != MCDisassembler::Fail) { 820 Size = 4; 821 Check(result, AddThumbPredicate(MI)); 822 return result; 823 } 824 } 825 826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 827 MI.clear(); 828 uint32_t NEONDataInsn = insn32; 829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 833 if (result != MCDisassembler::Fail) { 834 Size = 4; 835 Check(result, AddThumbPredicate(MI)); 836 return result; 837 } 838 } 839 840 Size = 0; 841 return MCDisassembler::Fail; 842 } 843 844 845 extern "C" void LLVMInitializeARMDisassembler() { 846 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 847 createARMDisassembler); 848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 849 createThumbDisassembler); 850 } 851 852 static const uint16_t GPRDecoderTable[] = { 853 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 854 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 855 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 856 ARM::R12, ARM::SP, ARM::LR, ARM::PC 857 }; 858 859 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 860 uint64_t Address, const void *Decoder) { 861 if (RegNo > 15) 862 return MCDisassembler::Fail; 863 864 unsigned Register = GPRDecoderTable[RegNo]; 865 Inst.addOperand(MCOperand::CreateReg(Register)); 866 return MCDisassembler::Success; 867 } 868 869 static DecodeStatus 870 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 871 uint64_t Address, const void *Decoder) { 872 DecodeStatus S = MCDisassembler::Success; 873 874 if (RegNo == 15) 875 S = MCDisassembler::SoftFail; 876 877 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 878 879 return S; 880 } 881 882 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 883 uint64_t Address, const void *Decoder) { 884 if (RegNo > 7) 885 return MCDisassembler::Fail; 886 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 887 } 888 889 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 890 uint64_t Address, const void *Decoder) { 891 unsigned Register = 0; 892 switch (RegNo) { 893 case 0: 894 Register = ARM::R0; 895 break; 896 case 1: 897 Register = ARM::R1; 898 break; 899 case 2: 900 Register = ARM::R2; 901 break; 902 case 3: 903 Register = ARM::R3; 904 break; 905 case 9: 906 Register = ARM::R9; 907 break; 908 case 12: 909 Register = ARM::R12; 910 break; 911 default: 912 return MCDisassembler::Fail; 913 } 914 915 Inst.addOperand(MCOperand::CreateReg(Register)); 916 return MCDisassembler::Success; 917 } 918 919 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 920 uint64_t Address, const void *Decoder) { 921 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 922 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 923 } 924 925 static const uint16_t SPRDecoderTable[] = { 926 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 927 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 928 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 929 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 930 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 931 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 932 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 933 ARM::S28, ARM::S29, ARM::S30, ARM::S31 934 }; 935 936 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 937 uint64_t Address, const void *Decoder) { 938 if (RegNo > 31) 939 return MCDisassembler::Fail; 940 941 unsigned Register = SPRDecoderTable[RegNo]; 942 Inst.addOperand(MCOperand::CreateReg(Register)); 943 return MCDisassembler::Success; 944 } 945 946 static const uint16_t DPRDecoderTable[] = { 947 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 948 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 949 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 950 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 951 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 952 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 953 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 954 ARM::D28, ARM::D29, ARM::D30, ARM::D31 955 }; 956 957 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 958 uint64_t Address, const void *Decoder) { 959 if (RegNo > 31) 960 return MCDisassembler::Fail; 961 962 unsigned Register = DPRDecoderTable[RegNo]; 963 Inst.addOperand(MCOperand::CreateReg(Register)); 964 return MCDisassembler::Success; 965 } 966 967 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 968 uint64_t Address, const void *Decoder) { 969 if (RegNo > 7) 970 return MCDisassembler::Fail; 971 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 972 } 973 974 static DecodeStatus 975 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 976 uint64_t Address, const void *Decoder) { 977 if (RegNo > 15) 978 return MCDisassembler::Fail; 979 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 980 } 981 982 static const uint16_t QPRDecoderTable[] = { 983 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 984 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 985 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 986 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 987 }; 988 989 990 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 991 uint64_t Address, const void *Decoder) { 992 if (RegNo > 31) 993 return MCDisassembler::Fail; 994 RegNo >>= 1; 995 996 unsigned Register = QPRDecoderTable[RegNo]; 997 Inst.addOperand(MCOperand::CreateReg(Register)); 998 return MCDisassembler::Success; 999 } 1000 1001 static const uint16_t DPairDecoderTable[] = { 1002 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1003 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1004 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1005 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1006 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1007 ARM::Q15 1008 }; 1009 1010 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 1011 uint64_t Address, const void *Decoder) { 1012 if (RegNo > 30) 1013 return MCDisassembler::Fail; 1014 1015 unsigned Register = DPairDecoderTable[RegNo]; 1016 Inst.addOperand(MCOperand::CreateReg(Register)); 1017 return MCDisassembler::Success; 1018 } 1019 1020 static const uint16_t DPairSpacedDecoderTable[] = { 1021 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1022 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1023 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1024 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1025 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1026 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1027 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1028 ARM::D28_D30, ARM::D29_D31 1029 }; 1030 1031 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 1032 unsigned RegNo, 1033 uint64_t Address, 1034 const void *Decoder) { 1035 if (RegNo > 29) 1036 return MCDisassembler::Fail; 1037 1038 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1039 Inst.addOperand(MCOperand::CreateReg(Register)); 1040 return MCDisassembler::Success; 1041 } 1042 1043 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 1044 uint64_t Address, const void *Decoder) { 1045 if (Val == 0xF) return MCDisassembler::Fail; 1046 // AL predicate is not allowed on Thumb1 branches. 1047 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1048 return MCDisassembler::Fail; 1049 Inst.addOperand(MCOperand::CreateImm(Val)); 1050 if (Val == ARMCC::AL) { 1051 Inst.addOperand(MCOperand::CreateReg(0)); 1052 } else 1053 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1054 return MCDisassembler::Success; 1055 } 1056 1057 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1058 uint64_t Address, const void *Decoder) { 1059 if (Val) 1060 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1061 else 1062 Inst.addOperand(MCOperand::CreateReg(0)); 1063 return MCDisassembler::Success; 1064 } 1065 1066 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1067 uint64_t Address, const void *Decoder) { 1068 uint32_t imm = Val & 0xFF; 1069 uint32_t rot = (Val & 0xF00) >> 7; 1070 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1071 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1072 return MCDisassembler::Success; 1073 } 1074 1075 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1076 uint64_t Address, const void *Decoder) { 1077 DecodeStatus S = MCDisassembler::Success; 1078 1079 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1080 unsigned type = fieldFromInstruction32(Val, 5, 2); 1081 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1082 1083 // Register-immediate 1084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1085 return MCDisassembler::Fail; 1086 1087 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1088 switch (type) { 1089 case 0: 1090 Shift = ARM_AM::lsl; 1091 break; 1092 case 1: 1093 Shift = ARM_AM::lsr; 1094 break; 1095 case 2: 1096 Shift = ARM_AM::asr; 1097 break; 1098 case 3: 1099 Shift = ARM_AM::ror; 1100 break; 1101 } 1102 1103 if (Shift == ARM_AM::ror && imm == 0) 1104 Shift = ARM_AM::rrx; 1105 1106 unsigned Op = Shift | (imm << 3); 1107 Inst.addOperand(MCOperand::CreateImm(Op)); 1108 1109 return S; 1110 } 1111 1112 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 DecodeStatus S = MCDisassembler::Success; 1115 1116 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1117 unsigned type = fieldFromInstruction32(Val, 5, 2); 1118 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1119 1120 // Register-register 1121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1122 return MCDisassembler::Fail; 1123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1124 return MCDisassembler::Fail; 1125 1126 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1127 switch (type) { 1128 case 0: 1129 Shift = ARM_AM::lsl; 1130 break; 1131 case 1: 1132 Shift = ARM_AM::lsr; 1133 break; 1134 case 2: 1135 Shift = ARM_AM::asr; 1136 break; 1137 case 3: 1138 Shift = ARM_AM::ror; 1139 break; 1140 } 1141 1142 Inst.addOperand(MCOperand::CreateImm(Shift)); 1143 1144 return S; 1145 } 1146 1147 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1148 uint64_t Address, const void *Decoder) { 1149 DecodeStatus S = MCDisassembler::Success; 1150 1151 bool writebackLoad = false; 1152 unsigned writebackReg = 0; 1153 switch (Inst.getOpcode()) { 1154 default: 1155 break; 1156 case ARM::LDMIA_UPD: 1157 case ARM::LDMDB_UPD: 1158 case ARM::LDMIB_UPD: 1159 case ARM::LDMDA_UPD: 1160 case ARM::t2LDMIA_UPD: 1161 case ARM::t2LDMDB_UPD: 1162 writebackLoad = true; 1163 writebackReg = Inst.getOperand(0).getReg(); 1164 break; 1165 } 1166 1167 // Empty register lists are not allowed. 1168 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1169 for (unsigned i = 0; i < 16; ++i) { 1170 if (Val & (1 << i)) { 1171 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1172 return MCDisassembler::Fail; 1173 // Writeback not allowed if Rn is in the target list. 1174 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1175 Check(S, MCDisassembler::SoftFail); 1176 } 1177 } 1178 1179 return S; 1180 } 1181 1182 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1183 uint64_t Address, const void *Decoder) { 1184 DecodeStatus S = MCDisassembler::Success; 1185 1186 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1187 unsigned regs = Val & 0xFF; 1188 1189 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1190 return MCDisassembler::Fail; 1191 for (unsigned i = 0; i < (regs - 1); ++i) { 1192 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1193 return MCDisassembler::Fail; 1194 } 1195 1196 return S; 1197 } 1198 1199 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1200 uint64_t Address, const void *Decoder) { 1201 DecodeStatus S = MCDisassembler::Success; 1202 1203 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1204 unsigned regs = (Val & 0xFF) / 2; 1205 1206 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1207 return MCDisassembler::Fail; 1208 for (unsigned i = 0; i < (regs - 1); ++i) { 1209 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1210 return MCDisassembler::Fail; 1211 } 1212 1213 return S; 1214 } 1215 1216 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1217 uint64_t Address, const void *Decoder) { 1218 // This operand encodes a mask of contiguous zeros between a specified MSB 1219 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1220 // the mask of all bits LSB-and-lower, and then xor them to create 1221 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1222 // create the final mask. 1223 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1224 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1225 1226 DecodeStatus S = MCDisassembler::Success; 1227 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1228 1229 uint32_t msb_mask = 0xFFFFFFFF; 1230 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1231 uint32_t lsb_mask = (1U << lsb) - 1; 1232 1233 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1234 return S; 1235 } 1236 1237 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1238 uint64_t Address, const void *Decoder) { 1239 DecodeStatus S = MCDisassembler::Success; 1240 1241 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1242 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1243 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1244 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1245 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1246 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1247 1248 switch (Inst.getOpcode()) { 1249 case ARM::LDC_OFFSET: 1250 case ARM::LDC_PRE: 1251 case ARM::LDC_POST: 1252 case ARM::LDC_OPTION: 1253 case ARM::LDCL_OFFSET: 1254 case ARM::LDCL_PRE: 1255 case ARM::LDCL_POST: 1256 case ARM::LDCL_OPTION: 1257 case ARM::STC_OFFSET: 1258 case ARM::STC_PRE: 1259 case ARM::STC_POST: 1260 case ARM::STC_OPTION: 1261 case ARM::STCL_OFFSET: 1262 case ARM::STCL_PRE: 1263 case ARM::STCL_POST: 1264 case ARM::STCL_OPTION: 1265 case ARM::t2LDC_OFFSET: 1266 case ARM::t2LDC_PRE: 1267 case ARM::t2LDC_POST: 1268 case ARM::t2LDC_OPTION: 1269 case ARM::t2LDCL_OFFSET: 1270 case ARM::t2LDCL_PRE: 1271 case ARM::t2LDCL_POST: 1272 case ARM::t2LDCL_OPTION: 1273 case ARM::t2STC_OFFSET: 1274 case ARM::t2STC_PRE: 1275 case ARM::t2STC_POST: 1276 case ARM::t2STC_OPTION: 1277 case ARM::t2STCL_OFFSET: 1278 case ARM::t2STCL_PRE: 1279 case ARM::t2STCL_POST: 1280 case ARM::t2STCL_OPTION: 1281 if (coproc == 0xA || coproc == 0xB) 1282 return MCDisassembler::Fail; 1283 break; 1284 default: 1285 break; 1286 } 1287 1288 Inst.addOperand(MCOperand::CreateImm(coproc)); 1289 Inst.addOperand(MCOperand::CreateImm(CRd)); 1290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1291 return MCDisassembler::Fail; 1292 1293 switch (Inst.getOpcode()) { 1294 case ARM::t2LDC2_OFFSET: 1295 case ARM::t2LDC2L_OFFSET: 1296 case ARM::t2LDC2_PRE: 1297 case ARM::t2LDC2L_PRE: 1298 case ARM::t2STC2_OFFSET: 1299 case ARM::t2STC2L_OFFSET: 1300 case ARM::t2STC2_PRE: 1301 case ARM::t2STC2L_PRE: 1302 case ARM::LDC2_OFFSET: 1303 case ARM::LDC2L_OFFSET: 1304 case ARM::LDC2_PRE: 1305 case ARM::LDC2L_PRE: 1306 case ARM::STC2_OFFSET: 1307 case ARM::STC2L_OFFSET: 1308 case ARM::STC2_PRE: 1309 case ARM::STC2L_PRE: 1310 case ARM::t2LDC_OFFSET: 1311 case ARM::t2LDCL_OFFSET: 1312 case ARM::t2LDC_PRE: 1313 case ARM::t2LDCL_PRE: 1314 case ARM::t2STC_OFFSET: 1315 case ARM::t2STCL_OFFSET: 1316 case ARM::t2STC_PRE: 1317 case ARM::t2STCL_PRE: 1318 case ARM::LDC_OFFSET: 1319 case ARM::LDCL_OFFSET: 1320 case ARM::LDC_PRE: 1321 case ARM::LDCL_PRE: 1322 case ARM::STC_OFFSET: 1323 case ARM::STCL_OFFSET: 1324 case ARM::STC_PRE: 1325 case ARM::STCL_PRE: 1326 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1327 Inst.addOperand(MCOperand::CreateImm(imm)); 1328 break; 1329 case ARM::t2LDC2_POST: 1330 case ARM::t2LDC2L_POST: 1331 case ARM::t2STC2_POST: 1332 case ARM::t2STC2L_POST: 1333 case ARM::LDC2_POST: 1334 case ARM::LDC2L_POST: 1335 case ARM::STC2_POST: 1336 case ARM::STC2L_POST: 1337 case ARM::t2LDC_POST: 1338 case ARM::t2LDCL_POST: 1339 case ARM::t2STC_POST: 1340 case ARM::t2STCL_POST: 1341 case ARM::LDC_POST: 1342 case ARM::LDCL_POST: 1343 case ARM::STC_POST: 1344 case ARM::STCL_POST: 1345 imm |= U << 8; 1346 // fall through. 1347 default: 1348 // The 'option' variant doesn't encode 'U' in the immediate since 1349 // the immediate is unsigned [0,255]. 1350 Inst.addOperand(MCOperand::CreateImm(imm)); 1351 break; 1352 } 1353 1354 switch (Inst.getOpcode()) { 1355 case ARM::LDC_OFFSET: 1356 case ARM::LDC_PRE: 1357 case ARM::LDC_POST: 1358 case ARM::LDC_OPTION: 1359 case ARM::LDCL_OFFSET: 1360 case ARM::LDCL_PRE: 1361 case ARM::LDCL_POST: 1362 case ARM::LDCL_OPTION: 1363 case ARM::STC_OFFSET: 1364 case ARM::STC_PRE: 1365 case ARM::STC_POST: 1366 case ARM::STC_OPTION: 1367 case ARM::STCL_OFFSET: 1368 case ARM::STCL_PRE: 1369 case ARM::STCL_POST: 1370 case ARM::STCL_OPTION: 1371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1372 return MCDisassembler::Fail; 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 return S; 1379 } 1380 1381 static DecodeStatus 1382 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1383 uint64_t Address, const void *Decoder) { 1384 DecodeStatus S = MCDisassembler::Success; 1385 1386 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1387 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1388 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1389 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1390 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1391 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1392 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1393 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1394 1395 // On stores, the writeback operand precedes Rt. 1396 switch (Inst.getOpcode()) { 1397 case ARM::STR_POST_IMM: 1398 case ARM::STR_POST_REG: 1399 case ARM::STRB_POST_IMM: 1400 case ARM::STRB_POST_REG: 1401 case ARM::STRT_POST_REG: 1402 case ARM::STRT_POST_IMM: 1403 case ARM::STRBT_POST_REG: 1404 case ARM::STRBT_POST_IMM: 1405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1406 return MCDisassembler::Fail; 1407 break; 1408 default: 1409 break; 1410 } 1411 1412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1413 return MCDisassembler::Fail; 1414 1415 // On loads, the writeback operand comes after Rt. 1416 switch (Inst.getOpcode()) { 1417 case ARM::LDR_POST_IMM: 1418 case ARM::LDR_POST_REG: 1419 case ARM::LDRB_POST_IMM: 1420 case ARM::LDRB_POST_REG: 1421 case ARM::LDRBT_POST_REG: 1422 case ARM::LDRBT_POST_IMM: 1423 case ARM::LDRT_POST_REG: 1424 case ARM::LDRT_POST_IMM: 1425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1426 return MCDisassembler::Fail; 1427 break; 1428 default: 1429 break; 1430 } 1431 1432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1433 return MCDisassembler::Fail; 1434 1435 ARM_AM::AddrOpc Op = ARM_AM::add; 1436 if (!fieldFromInstruction32(Insn, 23, 1)) 1437 Op = ARM_AM::sub; 1438 1439 bool writeback = (P == 0) || (W == 1); 1440 unsigned idx_mode = 0; 1441 if (P && writeback) 1442 idx_mode = ARMII::IndexModePre; 1443 else if (!P && writeback) 1444 idx_mode = ARMII::IndexModePost; 1445 1446 if (writeback && (Rn == 15 || Rn == Rt)) 1447 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1448 1449 if (reg) { 1450 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1451 return MCDisassembler::Fail; 1452 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1453 switch( fieldFromInstruction32(Insn, 5, 2)) { 1454 case 0: 1455 Opc = ARM_AM::lsl; 1456 break; 1457 case 1: 1458 Opc = ARM_AM::lsr; 1459 break; 1460 case 2: 1461 Opc = ARM_AM::asr; 1462 break; 1463 case 3: 1464 Opc = ARM_AM::ror; 1465 break; 1466 default: 1467 return MCDisassembler::Fail; 1468 } 1469 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1470 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1471 1472 Inst.addOperand(MCOperand::CreateImm(imm)); 1473 } else { 1474 Inst.addOperand(MCOperand::CreateReg(0)); 1475 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1476 Inst.addOperand(MCOperand::CreateImm(tmp)); 1477 } 1478 1479 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1480 return MCDisassembler::Fail; 1481 1482 return S; 1483 } 1484 1485 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1486 uint64_t Address, const void *Decoder) { 1487 DecodeStatus S = MCDisassembler::Success; 1488 1489 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1490 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1491 unsigned type = fieldFromInstruction32(Val, 5, 2); 1492 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1493 unsigned U = fieldFromInstruction32(Val, 12, 1); 1494 1495 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1496 switch (type) { 1497 case 0: 1498 ShOp = ARM_AM::lsl; 1499 break; 1500 case 1: 1501 ShOp = ARM_AM::lsr; 1502 break; 1503 case 2: 1504 ShOp = ARM_AM::asr; 1505 break; 1506 case 3: 1507 ShOp = ARM_AM::ror; 1508 break; 1509 } 1510 1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1512 return MCDisassembler::Fail; 1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1514 return MCDisassembler::Fail; 1515 unsigned shift; 1516 if (U) 1517 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1518 else 1519 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1520 Inst.addOperand(MCOperand::CreateImm(shift)); 1521 1522 return S; 1523 } 1524 1525 static DecodeStatus 1526 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1527 uint64_t Address, const void *Decoder) { 1528 DecodeStatus S = MCDisassembler::Success; 1529 1530 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1531 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1532 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1533 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1534 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1535 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1536 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1537 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1538 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1539 unsigned Rt2 = Rt + 1; 1540 1541 bool writeback = (W == 1) | (P == 0); 1542 1543 // For {LD,ST}RD, Rt must be even, else undefined. 1544 switch (Inst.getOpcode()) { 1545 case ARM::STRD: 1546 case ARM::STRD_PRE: 1547 case ARM::STRD_POST: 1548 case ARM::LDRD: 1549 case ARM::LDRD_PRE: 1550 case ARM::LDRD_POST: 1551 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1552 break; 1553 default: 1554 break; 1555 } 1556 switch (Inst.getOpcode()) { 1557 case ARM::STRD: 1558 case ARM::STRD_PRE: 1559 case ARM::STRD_POST: 1560 if (P == 0 && W == 1) 1561 S = MCDisassembler::SoftFail; 1562 1563 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1564 S = MCDisassembler::SoftFail; 1565 if (type && Rm == 15) 1566 S = MCDisassembler::SoftFail; 1567 if (Rt2 == 15) 1568 S = MCDisassembler::SoftFail; 1569 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1570 S = MCDisassembler::SoftFail; 1571 break; 1572 case ARM::STRH: 1573 case ARM::STRH_PRE: 1574 case ARM::STRH_POST: 1575 if (Rt == 15) 1576 S = MCDisassembler::SoftFail; 1577 if (writeback && (Rn == 15 || Rn == Rt)) 1578 S = MCDisassembler::SoftFail; 1579 if (!type && Rm == 15) 1580 S = MCDisassembler::SoftFail; 1581 break; 1582 case ARM::LDRD: 1583 case ARM::LDRD_PRE: 1584 case ARM::LDRD_POST: 1585 if (type && Rn == 15){ 1586 if (Rt2 == 15) 1587 S = MCDisassembler::SoftFail; 1588 break; 1589 } 1590 if (P == 0 && W == 1) 1591 S = MCDisassembler::SoftFail; 1592 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1593 S = MCDisassembler::SoftFail; 1594 if (!type && writeback && Rn == 15) 1595 S = MCDisassembler::SoftFail; 1596 if (writeback && (Rn == Rt || Rn == Rt2)) 1597 S = MCDisassembler::SoftFail; 1598 break; 1599 case ARM::LDRH: 1600 case ARM::LDRH_PRE: 1601 case ARM::LDRH_POST: 1602 if (type && Rn == 15){ 1603 if (Rt == 15) 1604 S = MCDisassembler::SoftFail; 1605 break; 1606 } 1607 if (Rt == 15) 1608 S = MCDisassembler::SoftFail; 1609 if (!type && Rm == 15) 1610 S = MCDisassembler::SoftFail; 1611 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1612 S = MCDisassembler::SoftFail; 1613 break; 1614 case ARM::LDRSH: 1615 case ARM::LDRSH_PRE: 1616 case ARM::LDRSH_POST: 1617 case ARM::LDRSB: 1618 case ARM::LDRSB_PRE: 1619 case ARM::LDRSB_POST: 1620 if (type && Rn == 15){ 1621 if (Rt == 15) 1622 S = MCDisassembler::SoftFail; 1623 break; 1624 } 1625 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1626 S = MCDisassembler::SoftFail; 1627 if (!type && (Rt == 15 || Rm == 15)) 1628 S = MCDisassembler::SoftFail; 1629 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1630 S = MCDisassembler::SoftFail; 1631 break; 1632 default: 1633 break; 1634 } 1635 1636 if (writeback) { // Writeback 1637 if (P) 1638 U |= ARMII::IndexModePre << 9; 1639 else 1640 U |= ARMII::IndexModePost << 9; 1641 1642 // On stores, the writeback operand precedes Rt. 1643 switch (Inst.getOpcode()) { 1644 case ARM::STRD: 1645 case ARM::STRD_PRE: 1646 case ARM::STRD_POST: 1647 case ARM::STRH: 1648 case ARM::STRH_PRE: 1649 case ARM::STRH_POST: 1650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1651 return MCDisassembler::Fail; 1652 break; 1653 default: 1654 break; 1655 } 1656 } 1657 1658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1659 return MCDisassembler::Fail; 1660 switch (Inst.getOpcode()) { 1661 case ARM::STRD: 1662 case ARM::STRD_PRE: 1663 case ARM::STRD_POST: 1664 case ARM::LDRD: 1665 case ARM::LDRD_PRE: 1666 case ARM::LDRD_POST: 1667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1668 return MCDisassembler::Fail; 1669 break; 1670 default: 1671 break; 1672 } 1673 1674 if (writeback) { 1675 // On loads, the writeback operand comes after Rt. 1676 switch (Inst.getOpcode()) { 1677 case ARM::LDRD: 1678 case ARM::LDRD_PRE: 1679 case ARM::LDRD_POST: 1680 case ARM::LDRH: 1681 case ARM::LDRH_PRE: 1682 case ARM::LDRH_POST: 1683 case ARM::LDRSH: 1684 case ARM::LDRSH_PRE: 1685 case ARM::LDRSH_POST: 1686 case ARM::LDRSB: 1687 case ARM::LDRSB_PRE: 1688 case ARM::LDRSB_POST: 1689 case ARM::LDRHTr: 1690 case ARM::LDRSBTr: 1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1692 return MCDisassembler::Fail; 1693 break; 1694 default: 1695 break; 1696 } 1697 } 1698 1699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1700 return MCDisassembler::Fail; 1701 1702 if (type) { 1703 Inst.addOperand(MCOperand::CreateReg(0)); 1704 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1705 } else { 1706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1707 return MCDisassembler::Fail; 1708 Inst.addOperand(MCOperand::CreateImm(U)); 1709 } 1710 1711 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1712 return MCDisassembler::Fail; 1713 1714 return S; 1715 } 1716 1717 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1718 uint64_t Address, const void *Decoder) { 1719 DecodeStatus S = MCDisassembler::Success; 1720 1721 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1722 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1723 1724 switch (mode) { 1725 case 0: 1726 mode = ARM_AM::da; 1727 break; 1728 case 1: 1729 mode = ARM_AM::ia; 1730 break; 1731 case 2: 1732 mode = ARM_AM::db; 1733 break; 1734 case 3: 1735 mode = ARM_AM::ib; 1736 break; 1737 } 1738 1739 Inst.addOperand(MCOperand::CreateImm(mode)); 1740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1741 return MCDisassembler::Fail; 1742 1743 return S; 1744 } 1745 1746 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1747 unsigned Insn, 1748 uint64_t Address, const void *Decoder) { 1749 DecodeStatus S = MCDisassembler::Success; 1750 1751 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1752 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1753 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1754 1755 if (pred == 0xF) { 1756 switch (Inst.getOpcode()) { 1757 case ARM::LDMDA: 1758 Inst.setOpcode(ARM::RFEDA); 1759 break; 1760 case ARM::LDMDA_UPD: 1761 Inst.setOpcode(ARM::RFEDA_UPD); 1762 break; 1763 case ARM::LDMDB: 1764 Inst.setOpcode(ARM::RFEDB); 1765 break; 1766 case ARM::LDMDB_UPD: 1767 Inst.setOpcode(ARM::RFEDB_UPD); 1768 break; 1769 case ARM::LDMIA: 1770 Inst.setOpcode(ARM::RFEIA); 1771 break; 1772 case ARM::LDMIA_UPD: 1773 Inst.setOpcode(ARM::RFEIA_UPD); 1774 break; 1775 case ARM::LDMIB: 1776 Inst.setOpcode(ARM::RFEIB); 1777 break; 1778 case ARM::LDMIB_UPD: 1779 Inst.setOpcode(ARM::RFEIB_UPD); 1780 break; 1781 case ARM::STMDA: 1782 Inst.setOpcode(ARM::SRSDA); 1783 break; 1784 case ARM::STMDA_UPD: 1785 Inst.setOpcode(ARM::SRSDA_UPD); 1786 break; 1787 case ARM::STMDB: 1788 Inst.setOpcode(ARM::SRSDB); 1789 break; 1790 case ARM::STMDB_UPD: 1791 Inst.setOpcode(ARM::SRSDB_UPD); 1792 break; 1793 case ARM::STMIA: 1794 Inst.setOpcode(ARM::SRSIA); 1795 break; 1796 case ARM::STMIA_UPD: 1797 Inst.setOpcode(ARM::SRSIA_UPD); 1798 break; 1799 case ARM::STMIB: 1800 Inst.setOpcode(ARM::SRSIB); 1801 break; 1802 case ARM::STMIB_UPD: 1803 Inst.setOpcode(ARM::SRSIB_UPD); 1804 break; 1805 default: 1806 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1807 } 1808 1809 // For stores (which become SRS's, the only operand is the mode. 1810 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1811 Inst.addOperand( 1812 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1813 return S; 1814 } 1815 1816 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1817 } 1818 1819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1820 return MCDisassembler::Fail; 1821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1822 return MCDisassembler::Fail; // Tied 1823 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1824 return MCDisassembler::Fail; 1825 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1826 return MCDisassembler::Fail; 1827 1828 return S; 1829 } 1830 1831 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1832 uint64_t Address, const void *Decoder) { 1833 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1834 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1835 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1836 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1837 1838 DecodeStatus S = MCDisassembler::Success; 1839 1840 // imod == '01' --> UNPREDICTABLE 1841 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1842 // return failure here. The '01' imod value is unprintable, so there's 1843 // nothing useful we could do even if we returned UNPREDICTABLE. 1844 1845 if (imod == 1) return MCDisassembler::Fail; 1846 1847 if (imod && M) { 1848 Inst.setOpcode(ARM::CPS3p); 1849 Inst.addOperand(MCOperand::CreateImm(imod)); 1850 Inst.addOperand(MCOperand::CreateImm(iflags)); 1851 Inst.addOperand(MCOperand::CreateImm(mode)); 1852 } else if (imod && !M) { 1853 Inst.setOpcode(ARM::CPS2p); 1854 Inst.addOperand(MCOperand::CreateImm(imod)); 1855 Inst.addOperand(MCOperand::CreateImm(iflags)); 1856 if (mode) S = MCDisassembler::SoftFail; 1857 } else if (!imod && M) { 1858 Inst.setOpcode(ARM::CPS1p); 1859 Inst.addOperand(MCOperand::CreateImm(mode)); 1860 if (iflags) S = MCDisassembler::SoftFail; 1861 } else { 1862 // imod == '00' && M == '0' --> UNPREDICTABLE 1863 Inst.setOpcode(ARM::CPS1p); 1864 Inst.addOperand(MCOperand::CreateImm(mode)); 1865 S = MCDisassembler::SoftFail; 1866 } 1867 1868 return S; 1869 } 1870 1871 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1872 uint64_t Address, const void *Decoder) { 1873 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1874 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1875 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1876 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1877 1878 DecodeStatus S = MCDisassembler::Success; 1879 1880 // imod == '01' --> UNPREDICTABLE 1881 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1882 // return failure here. The '01' imod value is unprintable, so there's 1883 // nothing useful we could do even if we returned UNPREDICTABLE. 1884 1885 if (imod == 1) return MCDisassembler::Fail; 1886 1887 if (imod && M) { 1888 Inst.setOpcode(ARM::t2CPS3p); 1889 Inst.addOperand(MCOperand::CreateImm(imod)); 1890 Inst.addOperand(MCOperand::CreateImm(iflags)); 1891 Inst.addOperand(MCOperand::CreateImm(mode)); 1892 } else if (imod && !M) { 1893 Inst.setOpcode(ARM::t2CPS2p); 1894 Inst.addOperand(MCOperand::CreateImm(imod)); 1895 Inst.addOperand(MCOperand::CreateImm(iflags)); 1896 if (mode) S = MCDisassembler::SoftFail; 1897 } else if (!imod && M) { 1898 Inst.setOpcode(ARM::t2CPS1p); 1899 Inst.addOperand(MCOperand::CreateImm(mode)); 1900 if (iflags) S = MCDisassembler::SoftFail; 1901 } else { 1902 // imod == '00' && M == '0' --> UNPREDICTABLE 1903 Inst.setOpcode(ARM::t2CPS1p); 1904 Inst.addOperand(MCOperand::CreateImm(mode)); 1905 S = MCDisassembler::SoftFail; 1906 } 1907 1908 return S; 1909 } 1910 1911 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1912 uint64_t Address, const void *Decoder) { 1913 DecodeStatus S = MCDisassembler::Success; 1914 1915 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1916 unsigned imm = 0; 1917 1918 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1919 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1920 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1921 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1922 1923 if (Inst.getOpcode() == ARM::t2MOVTi16) 1924 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1925 return MCDisassembler::Fail; 1926 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1927 return MCDisassembler::Fail; 1928 1929 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1930 Inst.addOperand(MCOperand::CreateImm(imm)); 1931 1932 return S; 1933 } 1934 1935 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1936 uint64_t Address, const void *Decoder) { 1937 DecodeStatus S = MCDisassembler::Success; 1938 1939 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1940 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1941 unsigned imm = 0; 1942 1943 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1944 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1945 1946 if (Inst.getOpcode() == ARM::MOVTi16) 1947 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1948 return MCDisassembler::Fail; 1949 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1950 return MCDisassembler::Fail; 1951 1952 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1953 Inst.addOperand(MCOperand::CreateImm(imm)); 1954 1955 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1956 return MCDisassembler::Fail; 1957 1958 return S; 1959 } 1960 1961 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1962 uint64_t Address, const void *Decoder) { 1963 DecodeStatus S = MCDisassembler::Success; 1964 1965 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1966 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1967 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1968 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1969 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1970 1971 if (pred == 0xF) 1972 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1973 1974 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1975 return MCDisassembler::Fail; 1976 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1977 return MCDisassembler::Fail; 1978 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 1983 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1984 return MCDisassembler::Fail; 1985 1986 return S; 1987 } 1988 1989 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1990 uint64_t Address, const void *Decoder) { 1991 DecodeStatus S = MCDisassembler::Success; 1992 1993 unsigned add = fieldFromInstruction32(Val, 12, 1); 1994 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1995 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1996 1997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1998 return MCDisassembler::Fail; 1999 2000 if (!add) imm *= -1; 2001 if (imm == 0 && !add) imm = INT32_MIN; 2002 Inst.addOperand(MCOperand::CreateImm(imm)); 2003 if (Rn == 15) 2004 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2005 2006 return S; 2007 } 2008 2009 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 2010 uint64_t Address, const void *Decoder) { 2011 DecodeStatus S = MCDisassembler::Success; 2012 2013 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2014 unsigned U = fieldFromInstruction32(Val, 8, 1); 2015 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2016 2017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2018 return MCDisassembler::Fail; 2019 2020 if (U) 2021 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2022 else 2023 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2024 2025 return S; 2026 } 2027 2028 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 2029 uint64_t Address, const void *Decoder) { 2030 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2031 } 2032 2033 static DecodeStatus 2034 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2035 uint64_t Address, const void *Decoder) { 2036 DecodeStatus S = MCDisassembler::Success; 2037 2038 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2039 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2040 2041 if (pred == 0xF) { 2042 Inst.setOpcode(ARM::BLXi); 2043 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2044 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2045 true, 4, Inst, Decoder)) 2046 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2047 return S; 2048 } 2049 2050 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2051 true, 4, Inst, Decoder)) 2052 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2053 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 2056 return S; 2057 } 2058 2059 2060 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 2061 uint64_t Address, const void *Decoder) { 2062 DecodeStatus S = MCDisassembler::Success; 2063 2064 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2065 unsigned align = fieldFromInstruction32(Val, 4, 2); 2066 2067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 if (!align) 2070 Inst.addOperand(MCOperand::CreateImm(0)); 2071 else 2072 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2073 2074 return S; 2075 } 2076 2077 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 2078 uint64_t Address, const void *Decoder) { 2079 DecodeStatus S = MCDisassembler::Success; 2080 2081 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2082 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2083 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2084 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2085 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2086 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2087 2088 // First output register 2089 switch (Inst.getOpcode()) { 2090 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2091 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2092 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2093 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2094 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2095 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2096 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2097 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2098 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2099 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 break; 2102 case ARM::VLD2b16: 2103 case ARM::VLD2b32: 2104 case ARM::VLD2b8: 2105 case ARM::VLD2b16wb_fixed: 2106 case ARM::VLD2b16wb_register: 2107 case ARM::VLD2b32wb_fixed: 2108 case ARM::VLD2b32wb_register: 2109 case ARM::VLD2b8wb_fixed: 2110 case ARM::VLD2b8wb_register: 2111 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 break; 2114 default: 2115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2116 return MCDisassembler::Fail; 2117 } 2118 2119 // Second output register 2120 switch (Inst.getOpcode()) { 2121 case ARM::VLD3d8: 2122 case ARM::VLD3d16: 2123 case ARM::VLD3d32: 2124 case ARM::VLD3d8_UPD: 2125 case ARM::VLD3d16_UPD: 2126 case ARM::VLD3d32_UPD: 2127 case ARM::VLD4d8: 2128 case ARM::VLD4d16: 2129 case ARM::VLD4d32: 2130 case ARM::VLD4d8_UPD: 2131 case ARM::VLD4d16_UPD: 2132 case ARM::VLD4d32_UPD: 2133 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2134 return MCDisassembler::Fail; 2135 break; 2136 case ARM::VLD3q8: 2137 case ARM::VLD3q16: 2138 case ARM::VLD3q32: 2139 case ARM::VLD3q8_UPD: 2140 case ARM::VLD3q16_UPD: 2141 case ARM::VLD3q32_UPD: 2142 case ARM::VLD4q8: 2143 case ARM::VLD4q16: 2144 case ARM::VLD4q32: 2145 case ARM::VLD4q8_UPD: 2146 case ARM::VLD4q16_UPD: 2147 case ARM::VLD4q32_UPD: 2148 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2149 return MCDisassembler::Fail; 2150 default: 2151 break; 2152 } 2153 2154 // Third output register 2155 switch(Inst.getOpcode()) { 2156 case ARM::VLD3d8: 2157 case ARM::VLD3d16: 2158 case ARM::VLD3d32: 2159 case ARM::VLD3d8_UPD: 2160 case ARM::VLD3d16_UPD: 2161 case ARM::VLD3d32_UPD: 2162 case ARM::VLD4d8: 2163 case ARM::VLD4d16: 2164 case ARM::VLD4d32: 2165 case ARM::VLD4d8_UPD: 2166 case ARM::VLD4d16_UPD: 2167 case ARM::VLD4d32_UPD: 2168 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2169 return MCDisassembler::Fail; 2170 break; 2171 case ARM::VLD3q8: 2172 case ARM::VLD3q16: 2173 case ARM::VLD3q32: 2174 case ARM::VLD3q8_UPD: 2175 case ARM::VLD3q16_UPD: 2176 case ARM::VLD3q32_UPD: 2177 case ARM::VLD4q8: 2178 case ARM::VLD4q16: 2179 case ARM::VLD4q32: 2180 case ARM::VLD4q8_UPD: 2181 case ARM::VLD4q16_UPD: 2182 case ARM::VLD4q32_UPD: 2183 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 break; 2186 default: 2187 break; 2188 } 2189 2190 // Fourth output register 2191 switch (Inst.getOpcode()) { 2192 case ARM::VLD4d8: 2193 case ARM::VLD4d16: 2194 case ARM::VLD4d32: 2195 case ARM::VLD4d8_UPD: 2196 case ARM::VLD4d16_UPD: 2197 case ARM::VLD4d32_UPD: 2198 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2199 return MCDisassembler::Fail; 2200 break; 2201 case ARM::VLD4q8: 2202 case ARM::VLD4q16: 2203 case ARM::VLD4q32: 2204 case ARM::VLD4q8_UPD: 2205 case ARM::VLD4q16_UPD: 2206 case ARM::VLD4q32_UPD: 2207 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2208 return MCDisassembler::Fail; 2209 break; 2210 default: 2211 break; 2212 } 2213 2214 // Writeback operand 2215 switch (Inst.getOpcode()) { 2216 case ARM::VLD1d8wb_fixed: 2217 case ARM::VLD1d16wb_fixed: 2218 case ARM::VLD1d32wb_fixed: 2219 case ARM::VLD1d64wb_fixed: 2220 case ARM::VLD1d8wb_register: 2221 case ARM::VLD1d16wb_register: 2222 case ARM::VLD1d32wb_register: 2223 case ARM::VLD1d64wb_register: 2224 case ARM::VLD1q8wb_fixed: 2225 case ARM::VLD1q16wb_fixed: 2226 case ARM::VLD1q32wb_fixed: 2227 case ARM::VLD1q64wb_fixed: 2228 case ARM::VLD1q8wb_register: 2229 case ARM::VLD1q16wb_register: 2230 case ARM::VLD1q32wb_register: 2231 case ARM::VLD1q64wb_register: 2232 case ARM::VLD1d8Twb_fixed: 2233 case ARM::VLD1d8Twb_register: 2234 case ARM::VLD1d16Twb_fixed: 2235 case ARM::VLD1d16Twb_register: 2236 case ARM::VLD1d32Twb_fixed: 2237 case ARM::VLD1d32Twb_register: 2238 case ARM::VLD1d64Twb_fixed: 2239 case ARM::VLD1d64Twb_register: 2240 case ARM::VLD1d8Qwb_fixed: 2241 case ARM::VLD1d8Qwb_register: 2242 case ARM::VLD1d16Qwb_fixed: 2243 case ARM::VLD1d16Qwb_register: 2244 case ARM::VLD1d32Qwb_fixed: 2245 case ARM::VLD1d32Qwb_register: 2246 case ARM::VLD1d64Qwb_fixed: 2247 case ARM::VLD1d64Qwb_register: 2248 case ARM::VLD2d8wb_fixed: 2249 case ARM::VLD2d16wb_fixed: 2250 case ARM::VLD2d32wb_fixed: 2251 case ARM::VLD2q8wb_fixed: 2252 case ARM::VLD2q16wb_fixed: 2253 case ARM::VLD2q32wb_fixed: 2254 case ARM::VLD2d8wb_register: 2255 case ARM::VLD2d16wb_register: 2256 case ARM::VLD2d32wb_register: 2257 case ARM::VLD2q8wb_register: 2258 case ARM::VLD2q16wb_register: 2259 case ARM::VLD2q32wb_register: 2260 case ARM::VLD2b8wb_fixed: 2261 case ARM::VLD2b16wb_fixed: 2262 case ARM::VLD2b32wb_fixed: 2263 case ARM::VLD2b8wb_register: 2264 case ARM::VLD2b16wb_register: 2265 case ARM::VLD2b32wb_register: 2266 case ARM::VLD3d8_UPD: 2267 case ARM::VLD3d16_UPD: 2268 case ARM::VLD3d32_UPD: 2269 case ARM::VLD3q8_UPD: 2270 case ARM::VLD3q16_UPD: 2271 case ARM::VLD3q32_UPD: 2272 case ARM::VLD4d8_UPD: 2273 case ARM::VLD4d16_UPD: 2274 case ARM::VLD4d32_UPD: 2275 case ARM::VLD4q8_UPD: 2276 case ARM::VLD4q16_UPD: 2277 case ARM::VLD4q32_UPD: 2278 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2279 return MCDisassembler::Fail; 2280 break; 2281 default: 2282 break; 2283 } 2284 2285 // AddrMode6 Base (register+alignment) 2286 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2287 return MCDisassembler::Fail; 2288 2289 // AddrMode6 Offset (register) 2290 switch (Inst.getOpcode()) { 2291 default: 2292 // The below have been updated to have explicit am6offset split 2293 // between fixed and register offset. For those instructions not 2294 // yet updated, we need to add an additional reg0 operand for the 2295 // fixed variant. 2296 // 2297 // The fixed offset encodes as Rm == 0xd, so we check for that. 2298 if (Rm == 0xd) { 2299 Inst.addOperand(MCOperand::CreateReg(0)); 2300 break; 2301 } 2302 // Fall through to handle the register offset variant. 2303 case ARM::VLD1d8wb_fixed: 2304 case ARM::VLD1d16wb_fixed: 2305 case ARM::VLD1d32wb_fixed: 2306 case ARM::VLD1d64wb_fixed: 2307 case ARM::VLD1d8Twb_fixed: 2308 case ARM::VLD1d16Twb_fixed: 2309 case ARM::VLD1d32Twb_fixed: 2310 case ARM::VLD1d64Twb_fixed: 2311 case ARM::VLD1d8Qwb_fixed: 2312 case ARM::VLD1d16Qwb_fixed: 2313 case ARM::VLD1d32Qwb_fixed: 2314 case ARM::VLD1d64Qwb_fixed: 2315 case ARM::VLD1d8wb_register: 2316 case ARM::VLD1d16wb_register: 2317 case ARM::VLD1d32wb_register: 2318 case ARM::VLD1d64wb_register: 2319 case ARM::VLD1q8wb_fixed: 2320 case ARM::VLD1q16wb_fixed: 2321 case ARM::VLD1q32wb_fixed: 2322 case ARM::VLD1q64wb_fixed: 2323 case ARM::VLD1q8wb_register: 2324 case ARM::VLD1q16wb_register: 2325 case ARM::VLD1q32wb_register: 2326 case ARM::VLD1q64wb_register: 2327 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2328 // variant encodes Rm == 0xf. Anything else is a register offset post- 2329 // increment and we need to add the register operand to the instruction. 2330 if (Rm != 0xD && Rm != 0xF && 2331 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2332 return MCDisassembler::Fail; 2333 break; 2334 } 2335 2336 return S; 2337 } 2338 2339 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2340 uint64_t Address, const void *Decoder) { 2341 DecodeStatus S = MCDisassembler::Success; 2342 2343 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2344 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2345 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2346 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2347 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2348 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2349 2350 // Writeback Operand 2351 switch (Inst.getOpcode()) { 2352 case ARM::VST1d8wb_fixed: 2353 case ARM::VST1d16wb_fixed: 2354 case ARM::VST1d32wb_fixed: 2355 case ARM::VST1d64wb_fixed: 2356 case ARM::VST1d8wb_register: 2357 case ARM::VST1d16wb_register: 2358 case ARM::VST1d32wb_register: 2359 case ARM::VST1d64wb_register: 2360 case ARM::VST1q8wb_fixed: 2361 case ARM::VST1q16wb_fixed: 2362 case ARM::VST1q32wb_fixed: 2363 case ARM::VST1q64wb_fixed: 2364 case ARM::VST1q8wb_register: 2365 case ARM::VST1q16wb_register: 2366 case ARM::VST1q32wb_register: 2367 case ARM::VST1q64wb_register: 2368 case ARM::VST1d8Twb_fixed: 2369 case ARM::VST1d16Twb_fixed: 2370 case ARM::VST1d32Twb_fixed: 2371 case ARM::VST1d64Twb_fixed: 2372 case ARM::VST1d8Twb_register: 2373 case ARM::VST1d16Twb_register: 2374 case ARM::VST1d32Twb_register: 2375 case ARM::VST1d64Twb_register: 2376 case ARM::VST1d8Qwb_fixed: 2377 case ARM::VST1d16Qwb_fixed: 2378 case ARM::VST1d32Qwb_fixed: 2379 case ARM::VST1d64Qwb_fixed: 2380 case ARM::VST1d8Qwb_register: 2381 case ARM::VST1d16Qwb_register: 2382 case ARM::VST1d32Qwb_register: 2383 case ARM::VST1d64Qwb_register: 2384 case ARM::VST2d8wb_fixed: 2385 case ARM::VST2d16wb_fixed: 2386 case ARM::VST2d32wb_fixed: 2387 case ARM::VST2d8wb_register: 2388 case ARM::VST2d16wb_register: 2389 case ARM::VST2d32wb_register: 2390 case ARM::VST2q8wb_fixed: 2391 case ARM::VST2q16wb_fixed: 2392 case ARM::VST2q32wb_fixed: 2393 case ARM::VST2q8wb_register: 2394 case ARM::VST2q16wb_register: 2395 case ARM::VST2q32wb_register: 2396 case ARM::VST2b8wb_fixed: 2397 case ARM::VST2b16wb_fixed: 2398 case ARM::VST2b32wb_fixed: 2399 case ARM::VST2b8wb_register: 2400 case ARM::VST2b16wb_register: 2401 case ARM::VST2b32wb_register: 2402 Inst.addOperand(MCOperand::CreateImm(0)); 2403 break; 2404 case ARM::VST3d8_UPD: 2405 case ARM::VST3d16_UPD: 2406 case ARM::VST3d32_UPD: 2407 case ARM::VST3q8_UPD: 2408 case ARM::VST3q16_UPD: 2409 case ARM::VST3q32_UPD: 2410 case ARM::VST4d8_UPD: 2411 case ARM::VST4d16_UPD: 2412 case ARM::VST4d32_UPD: 2413 case ARM::VST4q8_UPD: 2414 case ARM::VST4q16_UPD: 2415 case ARM::VST4q32_UPD: 2416 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2417 return MCDisassembler::Fail; 2418 break; 2419 default: 2420 break; 2421 } 2422 2423 // AddrMode6 Base (register+alignment) 2424 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2425 return MCDisassembler::Fail; 2426 2427 // AddrMode6 Offset (register) 2428 switch (Inst.getOpcode()) { 2429 default: 2430 if (Rm == 0xD) 2431 Inst.addOperand(MCOperand::CreateReg(0)); 2432 else if (Rm != 0xF) { 2433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2434 return MCDisassembler::Fail; 2435 } 2436 break; 2437 case ARM::VST1d8wb_fixed: 2438 case ARM::VST1d16wb_fixed: 2439 case ARM::VST1d32wb_fixed: 2440 case ARM::VST1d64wb_fixed: 2441 case ARM::VST1q8wb_fixed: 2442 case ARM::VST1q16wb_fixed: 2443 case ARM::VST1q32wb_fixed: 2444 case ARM::VST1q64wb_fixed: 2445 case ARM::VST1d8Twb_fixed: 2446 case ARM::VST1d16Twb_fixed: 2447 case ARM::VST1d32Twb_fixed: 2448 case ARM::VST1d64Twb_fixed: 2449 case ARM::VST1d8Qwb_fixed: 2450 case ARM::VST1d16Qwb_fixed: 2451 case ARM::VST1d32Qwb_fixed: 2452 case ARM::VST1d64Qwb_fixed: 2453 case ARM::VST2d8wb_fixed: 2454 case ARM::VST2d16wb_fixed: 2455 case ARM::VST2d32wb_fixed: 2456 case ARM::VST2q8wb_fixed: 2457 case ARM::VST2q16wb_fixed: 2458 case ARM::VST2q32wb_fixed: 2459 case ARM::VST2b8wb_fixed: 2460 case ARM::VST2b16wb_fixed: 2461 case ARM::VST2b32wb_fixed: 2462 break; 2463 } 2464 2465 2466 // First input register 2467 switch (Inst.getOpcode()) { 2468 case ARM::VST1q16: 2469 case ARM::VST1q32: 2470 case ARM::VST1q64: 2471 case ARM::VST1q8: 2472 case ARM::VST1q16wb_fixed: 2473 case ARM::VST1q16wb_register: 2474 case ARM::VST1q32wb_fixed: 2475 case ARM::VST1q32wb_register: 2476 case ARM::VST1q64wb_fixed: 2477 case ARM::VST1q64wb_register: 2478 case ARM::VST1q8wb_fixed: 2479 case ARM::VST1q8wb_register: 2480 case ARM::VST2d16: 2481 case ARM::VST2d32: 2482 case ARM::VST2d8: 2483 case ARM::VST2d16wb_fixed: 2484 case ARM::VST2d16wb_register: 2485 case ARM::VST2d32wb_fixed: 2486 case ARM::VST2d32wb_register: 2487 case ARM::VST2d8wb_fixed: 2488 case ARM::VST2d8wb_register: 2489 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2490 return MCDisassembler::Fail; 2491 break; 2492 case ARM::VST2b16: 2493 case ARM::VST2b32: 2494 case ARM::VST2b8: 2495 case ARM::VST2b16wb_fixed: 2496 case ARM::VST2b16wb_register: 2497 case ARM::VST2b32wb_fixed: 2498 case ARM::VST2b32wb_register: 2499 case ARM::VST2b8wb_fixed: 2500 case ARM::VST2b8wb_register: 2501 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2502 return MCDisassembler::Fail; 2503 break; 2504 default: 2505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 } 2508 2509 // Second input register 2510 switch (Inst.getOpcode()) { 2511 case ARM::VST3d8: 2512 case ARM::VST3d16: 2513 case ARM::VST3d32: 2514 case ARM::VST3d8_UPD: 2515 case ARM::VST3d16_UPD: 2516 case ARM::VST3d32_UPD: 2517 case ARM::VST4d8: 2518 case ARM::VST4d16: 2519 case ARM::VST4d32: 2520 case ARM::VST4d8_UPD: 2521 case ARM::VST4d16_UPD: 2522 case ARM::VST4d32_UPD: 2523 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2524 return MCDisassembler::Fail; 2525 break; 2526 case ARM::VST3q8: 2527 case ARM::VST3q16: 2528 case ARM::VST3q32: 2529 case ARM::VST3q8_UPD: 2530 case ARM::VST3q16_UPD: 2531 case ARM::VST3q32_UPD: 2532 case ARM::VST4q8: 2533 case ARM::VST4q16: 2534 case ARM::VST4q32: 2535 case ARM::VST4q8_UPD: 2536 case ARM::VST4q16_UPD: 2537 case ARM::VST4q32_UPD: 2538 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2539 return MCDisassembler::Fail; 2540 break; 2541 default: 2542 break; 2543 } 2544 2545 // Third input register 2546 switch (Inst.getOpcode()) { 2547 case ARM::VST3d8: 2548 case ARM::VST3d16: 2549 case ARM::VST3d32: 2550 case ARM::VST3d8_UPD: 2551 case ARM::VST3d16_UPD: 2552 case ARM::VST3d32_UPD: 2553 case ARM::VST4d8: 2554 case ARM::VST4d16: 2555 case ARM::VST4d32: 2556 case ARM::VST4d8_UPD: 2557 case ARM::VST4d16_UPD: 2558 case ARM::VST4d32_UPD: 2559 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2560 return MCDisassembler::Fail; 2561 break; 2562 case ARM::VST3q8: 2563 case ARM::VST3q16: 2564 case ARM::VST3q32: 2565 case ARM::VST3q8_UPD: 2566 case ARM::VST3q16_UPD: 2567 case ARM::VST3q32_UPD: 2568 case ARM::VST4q8: 2569 case ARM::VST4q16: 2570 case ARM::VST4q32: 2571 case ARM::VST4q8_UPD: 2572 case ARM::VST4q16_UPD: 2573 case ARM::VST4q32_UPD: 2574 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2575 return MCDisassembler::Fail; 2576 break; 2577 default: 2578 break; 2579 } 2580 2581 // Fourth input register 2582 switch (Inst.getOpcode()) { 2583 case ARM::VST4d8: 2584 case ARM::VST4d16: 2585 case ARM::VST4d32: 2586 case ARM::VST4d8_UPD: 2587 case ARM::VST4d16_UPD: 2588 case ARM::VST4d32_UPD: 2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2590 return MCDisassembler::Fail; 2591 break; 2592 case ARM::VST4q8: 2593 case ARM::VST4q16: 2594 case ARM::VST4q32: 2595 case ARM::VST4q8_UPD: 2596 case ARM::VST4q16_UPD: 2597 case ARM::VST4q32_UPD: 2598 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2599 return MCDisassembler::Fail; 2600 break; 2601 default: 2602 break; 2603 } 2604 2605 return S; 2606 } 2607 2608 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2609 uint64_t Address, const void *Decoder) { 2610 DecodeStatus S = MCDisassembler::Success; 2611 2612 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2613 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2614 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2615 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2616 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2617 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2618 2619 align *= (1 << size); 2620 2621 switch (Inst.getOpcode()) { 2622 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2623 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2624 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2625 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2626 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2627 return MCDisassembler::Fail; 2628 break; 2629 default: 2630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2631 return MCDisassembler::Fail; 2632 break; 2633 } 2634 if (Rm != 0xF) { 2635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2636 return MCDisassembler::Fail; 2637 } 2638 2639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2640 return MCDisassembler::Fail; 2641 Inst.addOperand(MCOperand::CreateImm(align)); 2642 2643 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2644 // variant encodes Rm == 0xf. Anything else is a register offset post- 2645 // increment and we need to add the register operand to the instruction. 2646 if (Rm != 0xD && Rm != 0xF && 2647 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 2650 return S; 2651 } 2652 2653 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2654 uint64_t Address, const void *Decoder) { 2655 DecodeStatus S = MCDisassembler::Success; 2656 2657 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2658 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2659 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2660 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2661 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2662 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2663 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2664 align *= 2*size; 2665 2666 switch (Inst.getOpcode()) { 2667 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2668 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2669 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2670 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2671 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2672 return MCDisassembler::Fail; 2673 break; 2674 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2675 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2676 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2677 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2678 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 break; 2681 default: 2682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2683 return MCDisassembler::Fail; 2684 break; 2685 } 2686 2687 if (Rm != 0xF) 2688 Inst.addOperand(MCOperand::CreateImm(0)); 2689 2690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2691 return MCDisassembler::Fail; 2692 Inst.addOperand(MCOperand::CreateImm(align)); 2693 2694 if (Rm == 0xD) 2695 Inst.addOperand(MCOperand::CreateReg(0)); 2696 else if (Rm != 0xF) { 2697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2698 return MCDisassembler::Fail; 2699 } 2700 2701 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 2704 return S; 2705 } 2706 2707 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2708 uint64_t Address, const void *Decoder) { 2709 DecodeStatus S = MCDisassembler::Success; 2710 2711 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2712 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2713 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2714 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2715 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2716 2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 if (Rm != 0xF) { 2724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 } 2727 2728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 Inst.addOperand(MCOperand::CreateImm(0)); 2731 2732 if (Rm == 0xD) 2733 Inst.addOperand(MCOperand::CreateReg(0)); 2734 else if (Rm != 0xF) { 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 } 2738 2739 return S; 2740 } 2741 2742 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2743 uint64_t Address, const void *Decoder) { 2744 DecodeStatus S = MCDisassembler::Success; 2745 2746 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2747 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2748 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2749 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2750 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2751 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2752 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2753 2754 if (size == 0x3) { 2755 size = 4; 2756 align = 16; 2757 } else { 2758 if (size == 2) { 2759 size = 1 << size; 2760 align *= 8; 2761 } else { 2762 size = 1 << size; 2763 align *= 4*size; 2764 } 2765 } 2766 2767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2768 return MCDisassembler::Fail; 2769 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2770 return MCDisassembler::Fail; 2771 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2772 return MCDisassembler::Fail; 2773 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 if (Rm != 0xF) { 2776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2777 return MCDisassembler::Fail; 2778 } 2779 2780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2781 return MCDisassembler::Fail; 2782 Inst.addOperand(MCOperand::CreateImm(align)); 2783 2784 if (Rm == 0xD) 2785 Inst.addOperand(MCOperand::CreateReg(0)); 2786 else if (Rm != 0xF) { 2787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 } 2790 2791 return S; 2792 } 2793 2794 static DecodeStatus 2795 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2796 uint64_t Address, const void *Decoder) { 2797 DecodeStatus S = MCDisassembler::Success; 2798 2799 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2800 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2801 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2802 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2803 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2804 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2805 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2806 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2807 2808 if (Q) { 2809 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 } else { 2812 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2813 return MCDisassembler::Fail; 2814 } 2815 2816 Inst.addOperand(MCOperand::CreateImm(imm)); 2817 2818 switch (Inst.getOpcode()) { 2819 case ARM::VORRiv4i16: 2820 case ARM::VORRiv2i32: 2821 case ARM::VBICiv4i16: 2822 case ARM::VBICiv2i32: 2823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 break; 2826 case ARM::VORRiv8i16: 2827 case ARM::VORRiv4i32: 2828 case ARM::VBICiv8i16: 2829 case ARM::VBICiv4i32: 2830 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 break; 2833 default: 2834 break; 2835 } 2836 2837 return S; 2838 } 2839 2840 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2841 uint64_t Address, const void *Decoder) { 2842 DecodeStatus S = MCDisassembler::Success; 2843 2844 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2845 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2846 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2847 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2848 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2849 2850 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2851 return MCDisassembler::Fail; 2852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2853 return MCDisassembler::Fail; 2854 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2855 2856 return S; 2857 } 2858 2859 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2860 uint64_t Address, const void *Decoder) { 2861 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2862 return MCDisassembler::Success; 2863 } 2864 2865 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2866 uint64_t Address, const void *Decoder) { 2867 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2868 return MCDisassembler::Success; 2869 } 2870 2871 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2872 uint64_t Address, const void *Decoder) { 2873 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2874 return MCDisassembler::Success; 2875 } 2876 2877 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2878 uint64_t Address, const void *Decoder) { 2879 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2880 return MCDisassembler::Success; 2881 } 2882 2883 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2884 uint64_t Address, const void *Decoder) { 2885 DecodeStatus S = MCDisassembler::Success; 2886 2887 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2888 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2890 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2891 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2892 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2893 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2894 2895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2896 return MCDisassembler::Fail; 2897 if (op) { 2898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2899 return MCDisassembler::Fail; // Writeback 2900 } 2901 2902 switch (Inst.getOpcode()) { 2903 case ARM::VTBL2: 2904 case ARM::VTBX2: 2905 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 break; 2908 default: 2909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2910 return MCDisassembler::Fail; 2911 } 2912 2913 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2914 return MCDisassembler::Fail; 2915 2916 return S; 2917 } 2918 2919 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2920 uint64_t Address, const void *Decoder) { 2921 DecodeStatus S = MCDisassembler::Success; 2922 2923 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2924 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2925 2926 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 2929 switch(Inst.getOpcode()) { 2930 default: 2931 return MCDisassembler::Fail; 2932 case ARM::tADR: 2933 break; // tADR does not explicitly represent the PC as an operand. 2934 case ARM::tADDrSPi: 2935 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2936 break; 2937 } 2938 2939 Inst.addOperand(MCOperand::CreateImm(imm)); 2940 return S; 2941 } 2942 2943 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2944 uint64_t Address, const void *Decoder) { 2945 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2946 return MCDisassembler::Success; 2947 } 2948 2949 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2950 uint64_t Address, const void *Decoder) { 2951 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2952 return MCDisassembler::Success; 2953 } 2954 2955 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2956 uint64_t Address, const void *Decoder) { 2957 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2958 return MCDisassembler::Success; 2959 } 2960 2961 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2962 uint64_t Address, const void *Decoder) { 2963 DecodeStatus S = MCDisassembler::Success; 2964 2965 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2966 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2967 2968 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 2973 return S; 2974 } 2975 2976 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2977 uint64_t Address, const void *Decoder) { 2978 DecodeStatus S = MCDisassembler::Success; 2979 2980 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2981 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2982 2983 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 Inst.addOperand(MCOperand::CreateImm(imm)); 2986 2987 return S; 2988 } 2989 2990 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2991 uint64_t Address, const void *Decoder) { 2992 unsigned imm = Val << 2; 2993 2994 Inst.addOperand(MCOperand::CreateImm(imm)); 2995 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2996 2997 return MCDisassembler::Success; 2998 } 2999 3000 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 3001 uint64_t Address, const void *Decoder) { 3002 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3003 Inst.addOperand(MCOperand::CreateImm(Val)); 3004 3005 return MCDisassembler::Success; 3006 } 3007 3008 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 3009 uint64_t Address, const void *Decoder) { 3010 DecodeStatus S = MCDisassembler::Success; 3011 3012 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3013 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3014 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3015 3016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3017 return MCDisassembler::Fail; 3018 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3019 return MCDisassembler::Fail; 3020 Inst.addOperand(MCOperand::CreateImm(imm)); 3021 3022 return S; 3023 } 3024 3025 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 3026 uint64_t Address, const void *Decoder) { 3027 DecodeStatus S = MCDisassembler::Success; 3028 3029 switch (Inst.getOpcode()) { 3030 case ARM::t2PLDs: 3031 case ARM::t2PLDWs: 3032 case ARM::t2PLIs: 3033 break; 3034 default: { 3035 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3036 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 } 3039 } 3040 3041 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3042 if (Rn == 0xF) { 3043 switch (Inst.getOpcode()) { 3044 case ARM::t2LDRBs: 3045 Inst.setOpcode(ARM::t2LDRBpci); 3046 break; 3047 case ARM::t2LDRHs: 3048 Inst.setOpcode(ARM::t2LDRHpci); 3049 break; 3050 case ARM::t2LDRSHs: 3051 Inst.setOpcode(ARM::t2LDRSHpci); 3052 break; 3053 case ARM::t2LDRSBs: 3054 Inst.setOpcode(ARM::t2LDRSBpci); 3055 break; 3056 case ARM::t2PLDs: 3057 Inst.setOpcode(ARM::t2PLDi12); 3058 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3059 break; 3060 default: 3061 return MCDisassembler::Fail; 3062 } 3063 3064 int imm = fieldFromInstruction32(Insn, 0, 12); 3065 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3066 Inst.addOperand(MCOperand::CreateImm(imm)); 3067 3068 return S; 3069 } 3070 3071 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3072 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3073 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3074 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3075 return MCDisassembler::Fail; 3076 3077 return S; 3078 } 3079 3080 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 3081 uint64_t Address, const void *Decoder) { 3082 int imm = Val & 0xFF; 3083 if (!(Val & 0x100)) imm *= -1; 3084 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3085 3086 return MCDisassembler::Success; 3087 } 3088 3089 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 3090 uint64_t Address, const void *Decoder) { 3091 DecodeStatus S = MCDisassembler::Success; 3092 3093 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3094 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3095 3096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3099 return MCDisassembler::Fail; 3100 3101 return S; 3102 } 3103 3104 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 3105 uint64_t Address, const void *Decoder) { 3106 DecodeStatus S = MCDisassembler::Success; 3107 3108 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3109 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3110 3111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3112 return MCDisassembler::Fail; 3113 3114 Inst.addOperand(MCOperand::CreateImm(imm)); 3115 3116 return S; 3117 } 3118 3119 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 3120 uint64_t Address, const void *Decoder) { 3121 int imm = Val & 0xFF; 3122 if (Val == 0) 3123 imm = INT32_MIN; 3124 else if (!(Val & 0x100)) 3125 imm *= -1; 3126 Inst.addOperand(MCOperand::CreateImm(imm)); 3127 3128 return MCDisassembler::Success; 3129 } 3130 3131 3132 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 3133 uint64_t Address, const void *Decoder) { 3134 DecodeStatus S = MCDisassembler::Success; 3135 3136 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3137 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3138 3139 // Some instructions always use an additive offset. 3140 switch (Inst.getOpcode()) { 3141 case ARM::t2LDRT: 3142 case ARM::t2LDRBT: 3143 case ARM::t2LDRHT: 3144 case ARM::t2LDRSBT: 3145 case ARM::t2LDRSHT: 3146 case ARM::t2STRT: 3147 case ARM::t2STRBT: 3148 case ARM::t2STRHT: 3149 imm |= 0x100; 3150 break; 3151 default: 3152 break; 3153 } 3154 3155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3156 return MCDisassembler::Fail; 3157 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3158 return MCDisassembler::Fail; 3159 3160 return S; 3161 } 3162 3163 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 3164 uint64_t Address, const void *Decoder) { 3165 DecodeStatus S = MCDisassembler::Success; 3166 3167 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3168 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3169 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3170 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3171 addr |= Rn << 9; 3172 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3173 3174 if (!load) { 3175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3176 return MCDisassembler::Fail; 3177 } 3178 3179 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 3182 if (load) { 3183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3184 return MCDisassembler::Fail; 3185 } 3186 3187 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 3190 return S; 3191 } 3192 3193 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 3194 uint64_t Address, const void *Decoder) { 3195 DecodeStatus S = MCDisassembler::Success; 3196 3197 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3198 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3199 3200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3201 return MCDisassembler::Fail; 3202 Inst.addOperand(MCOperand::CreateImm(imm)); 3203 3204 return S; 3205 } 3206 3207 3208 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 3209 uint64_t Address, const void *Decoder) { 3210 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3211 3212 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3213 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3214 Inst.addOperand(MCOperand::CreateImm(imm)); 3215 3216 return MCDisassembler::Success; 3217 } 3218 3219 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3220 uint64_t Address, const void *Decoder) { 3221 DecodeStatus S = MCDisassembler::Success; 3222 3223 if (Inst.getOpcode() == ARM::tADDrSP) { 3224 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3225 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3226 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3232 } else if (Inst.getOpcode() == ARM::tADDspr) { 3233 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3234 3235 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3236 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3238 return MCDisassembler::Fail; 3239 } 3240 3241 return S; 3242 } 3243 3244 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3245 uint64_t Address, const void *Decoder) { 3246 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3247 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3248 3249 Inst.addOperand(MCOperand::CreateImm(imod)); 3250 Inst.addOperand(MCOperand::CreateImm(flags)); 3251 3252 return MCDisassembler::Success; 3253 } 3254 3255 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3256 uint64_t Address, const void *Decoder) { 3257 DecodeStatus S = MCDisassembler::Success; 3258 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3259 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3260 3261 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3262 return MCDisassembler::Fail; 3263 Inst.addOperand(MCOperand::CreateImm(add)); 3264 3265 return S; 3266 } 3267 3268 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3269 uint64_t Address, const void *Decoder) { 3270 if (!tryAddingSymbolicOperand(Address, 3271 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3272 true, 4, Inst, Decoder)) 3273 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3274 return MCDisassembler::Success; 3275 } 3276 3277 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3278 uint64_t Address, const void *Decoder) { 3279 if (Val == 0xA || Val == 0xB) 3280 return MCDisassembler::Fail; 3281 3282 Inst.addOperand(MCOperand::CreateImm(Val)); 3283 return MCDisassembler::Success; 3284 } 3285 3286 static DecodeStatus 3287 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3288 uint64_t Address, const void *Decoder) { 3289 DecodeStatus S = MCDisassembler::Success; 3290 3291 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3292 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3293 3294 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3296 return MCDisassembler::Fail; 3297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 return S; 3300 } 3301 3302 static DecodeStatus 3303 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3304 uint64_t Address, const void *Decoder) { 3305 DecodeStatus S = MCDisassembler::Success; 3306 3307 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3308 if (pred == 0xE || pred == 0xF) { 3309 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3310 switch (opc) { 3311 default: 3312 return MCDisassembler::Fail; 3313 case 0xf3bf8f4: 3314 Inst.setOpcode(ARM::t2DSB); 3315 break; 3316 case 0xf3bf8f5: 3317 Inst.setOpcode(ARM::t2DMB); 3318 break; 3319 case 0xf3bf8f6: 3320 Inst.setOpcode(ARM::t2ISB); 3321 break; 3322 } 3323 3324 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3325 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3326 } 3327 3328 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3329 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3330 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3331 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3332 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3333 3334 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3335 return MCDisassembler::Fail; 3336 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3337 return MCDisassembler::Fail; 3338 3339 return S; 3340 } 3341 3342 // Decode a shifted immediate operand. These basically consist 3343 // of an 8-bit value, and a 4-bit directive that specifies either 3344 // a splat operation or a rotation. 3345 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3346 uint64_t Address, const void *Decoder) { 3347 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3348 if (ctrl == 0) { 3349 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3350 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3351 switch (byte) { 3352 case 0: 3353 Inst.addOperand(MCOperand::CreateImm(imm)); 3354 break; 3355 case 1: 3356 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3357 break; 3358 case 2: 3359 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3360 break; 3361 case 3: 3362 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3363 (imm << 8) | imm)); 3364 break; 3365 } 3366 } else { 3367 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3368 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3369 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3370 Inst.addOperand(MCOperand::CreateImm(imm)); 3371 } 3372 3373 return MCDisassembler::Success; 3374 } 3375 3376 static DecodeStatus 3377 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3378 uint64_t Address, const void *Decoder){ 3379 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3380 return MCDisassembler::Success; 3381 } 3382 3383 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3384 uint64_t Address, const void *Decoder){ 3385 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3386 true, 4, Inst, Decoder)) 3387 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3388 return MCDisassembler::Success; 3389 } 3390 3391 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3392 uint64_t Address, const void *Decoder) { 3393 switch (Val) { 3394 default: 3395 return MCDisassembler::Fail; 3396 case 0xF: // SY 3397 case 0xE: // ST 3398 case 0xB: // ISH 3399 case 0xA: // ISHST 3400 case 0x7: // NSH 3401 case 0x6: // NSHST 3402 case 0x3: // OSH 3403 case 0x2: // OSHST 3404 break; 3405 } 3406 3407 Inst.addOperand(MCOperand::CreateImm(Val)); 3408 return MCDisassembler::Success; 3409 } 3410 3411 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3412 uint64_t Address, const void *Decoder) { 3413 if (!Val) return MCDisassembler::Fail; 3414 Inst.addOperand(MCOperand::CreateImm(Val)); 3415 return MCDisassembler::Success; 3416 } 3417 3418 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3419 uint64_t Address, const void *Decoder) { 3420 DecodeStatus S = MCDisassembler::Success; 3421 3422 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3423 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3424 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3425 3426 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3427 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3433 return MCDisassembler::Fail; 3434 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3435 return MCDisassembler::Fail; 3436 3437 return S; 3438 } 3439 3440 3441 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3442 uint64_t Address, const void *Decoder){ 3443 DecodeStatus S = MCDisassembler::Success; 3444 3445 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3446 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3447 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3448 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3449 3450 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3451 return MCDisassembler::Fail; 3452 3453 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3454 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3455 3456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3457 return MCDisassembler::Fail; 3458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 3465 return S; 3466 } 3467 3468 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3469 uint64_t Address, const void *Decoder) { 3470 DecodeStatus S = MCDisassembler::Success; 3471 3472 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3473 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3474 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3475 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3476 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3477 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3478 3479 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3480 3481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3484 return MCDisassembler::Fail; 3485 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 3490 return S; 3491 } 3492 3493 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3494 uint64_t Address, const void *Decoder) { 3495 DecodeStatus S = MCDisassembler::Success; 3496 3497 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3498 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3499 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3500 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3501 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3502 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3503 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3504 3505 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3506 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3507 3508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3511 return MCDisassembler::Fail; 3512 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 3517 return S; 3518 } 3519 3520 3521 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3522 uint64_t Address, const void *Decoder) { 3523 DecodeStatus S = MCDisassembler::Success; 3524 3525 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3526 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3527 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3528 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3529 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3530 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3531 3532 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3533 3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3537 return MCDisassembler::Fail; 3538 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3541 return MCDisassembler::Fail; 3542 3543 return S; 3544 } 3545 3546 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3547 uint64_t Address, const void *Decoder) { 3548 DecodeStatus S = MCDisassembler::Success; 3549 3550 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3551 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3552 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3553 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3554 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3555 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3556 3557 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3558 3559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3564 return MCDisassembler::Fail; 3565 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 3568 return S; 3569 } 3570 3571 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3572 uint64_t Address, const void *Decoder) { 3573 DecodeStatus S = MCDisassembler::Success; 3574 3575 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3576 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3577 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3578 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3579 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3580 3581 unsigned align = 0; 3582 unsigned index = 0; 3583 switch (size) { 3584 default: 3585 return MCDisassembler::Fail; 3586 case 0: 3587 if (fieldFromInstruction32(Insn, 4, 1)) 3588 return MCDisassembler::Fail; // UNDEFINED 3589 index = fieldFromInstruction32(Insn, 5, 3); 3590 break; 3591 case 1: 3592 if (fieldFromInstruction32(Insn, 5, 1)) 3593 return MCDisassembler::Fail; // UNDEFINED 3594 index = fieldFromInstruction32(Insn, 6, 2); 3595 if (fieldFromInstruction32(Insn, 4, 1)) 3596 align = 2; 3597 break; 3598 case 2: 3599 if (fieldFromInstruction32(Insn, 6, 1)) 3600 return MCDisassembler::Fail; // UNDEFINED 3601 index = fieldFromInstruction32(Insn, 7, 1); 3602 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3603 align = 4; 3604 } 3605 3606 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 if (Rm != 0xF) { // Writeback 3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 } 3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 Inst.addOperand(MCOperand::CreateImm(align)); 3615 if (Rm != 0xF) { 3616 if (Rm != 0xD) { 3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 } else 3620 Inst.addOperand(MCOperand::CreateReg(0)); 3621 } 3622 3623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 Inst.addOperand(MCOperand::CreateImm(index)); 3626 3627 return S; 3628 } 3629 3630 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3631 uint64_t Address, const void *Decoder) { 3632 DecodeStatus S = MCDisassembler::Success; 3633 3634 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3635 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3636 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3637 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3638 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3639 3640 unsigned align = 0; 3641 unsigned index = 0; 3642 switch (size) { 3643 default: 3644 return MCDisassembler::Fail; 3645 case 0: 3646 if (fieldFromInstruction32(Insn, 4, 1)) 3647 return MCDisassembler::Fail; // UNDEFINED 3648 index = fieldFromInstruction32(Insn, 5, 3); 3649 break; 3650 case 1: 3651 if (fieldFromInstruction32(Insn, 5, 1)) 3652 return MCDisassembler::Fail; // UNDEFINED 3653 index = fieldFromInstruction32(Insn, 6, 2); 3654 if (fieldFromInstruction32(Insn, 4, 1)) 3655 align = 2; 3656 break; 3657 case 2: 3658 if (fieldFromInstruction32(Insn, 6, 1)) 3659 return MCDisassembler::Fail; // UNDEFINED 3660 index = fieldFromInstruction32(Insn, 7, 1); 3661 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3662 align = 4; 3663 } 3664 3665 if (Rm != 0xF) { // Writeback 3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3667 return MCDisassembler::Fail; 3668 } 3669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3670 return MCDisassembler::Fail; 3671 Inst.addOperand(MCOperand::CreateImm(align)); 3672 if (Rm != 0xF) { 3673 if (Rm != 0xD) { 3674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3675 return MCDisassembler::Fail; 3676 } else 3677 Inst.addOperand(MCOperand::CreateReg(0)); 3678 } 3679 3680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 Inst.addOperand(MCOperand::CreateImm(index)); 3683 3684 return S; 3685 } 3686 3687 3688 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3689 uint64_t Address, const void *Decoder) { 3690 DecodeStatus S = MCDisassembler::Success; 3691 3692 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3693 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3694 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3695 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3696 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3697 3698 unsigned align = 0; 3699 unsigned index = 0; 3700 unsigned inc = 1; 3701 switch (size) { 3702 default: 3703 return MCDisassembler::Fail; 3704 case 0: 3705 index = fieldFromInstruction32(Insn, 5, 3); 3706 if (fieldFromInstruction32(Insn, 4, 1)) 3707 align = 2; 3708 break; 3709 case 1: 3710 index = fieldFromInstruction32(Insn, 6, 2); 3711 if (fieldFromInstruction32(Insn, 4, 1)) 3712 align = 4; 3713 if (fieldFromInstruction32(Insn, 5, 1)) 3714 inc = 2; 3715 break; 3716 case 2: 3717 if (fieldFromInstruction32(Insn, 5, 1)) 3718 return MCDisassembler::Fail; // UNDEFINED 3719 index = fieldFromInstruction32(Insn, 7, 1); 3720 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3721 align = 8; 3722 if (fieldFromInstruction32(Insn, 6, 1)) 3723 inc = 2; 3724 break; 3725 } 3726 3727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 if (Rm != 0xF) { // Writeback 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 } 3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3736 return MCDisassembler::Fail; 3737 Inst.addOperand(MCOperand::CreateImm(align)); 3738 if (Rm != 0xF) { 3739 if (Rm != 0xD) { 3740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3741 return MCDisassembler::Fail; 3742 } else 3743 Inst.addOperand(MCOperand::CreateReg(0)); 3744 } 3745 3746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3747 return MCDisassembler::Fail; 3748 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 Inst.addOperand(MCOperand::CreateImm(index)); 3751 3752 return S; 3753 } 3754 3755 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3756 uint64_t Address, const void *Decoder) { 3757 DecodeStatus S = MCDisassembler::Success; 3758 3759 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3760 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3761 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3762 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3763 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3764 3765 unsigned align = 0; 3766 unsigned index = 0; 3767 unsigned inc = 1; 3768 switch (size) { 3769 default: 3770 return MCDisassembler::Fail; 3771 case 0: 3772 index = fieldFromInstruction32(Insn, 5, 3); 3773 if (fieldFromInstruction32(Insn, 4, 1)) 3774 align = 2; 3775 break; 3776 case 1: 3777 index = fieldFromInstruction32(Insn, 6, 2); 3778 if (fieldFromInstruction32(Insn, 4, 1)) 3779 align = 4; 3780 if (fieldFromInstruction32(Insn, 5, 1)) 3781 inc = 2; 3782 break; 3783 case 2: 3784 if (fieldFromInstruction32(Insn, 5, 1)) 3785 return MCDisassembler::Fail; // UNDEFINED 3786 index = fieldFromInstruction32(Insn, 7, 1); 3787 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3788 align = 8; 3789 if (fieldFromInstruction32(Insn, 6, 1)) 3790 inc = 2; 3791 break; 3792 } 3793 3794 if (Rm != 0xF) { // Writeback 3795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3796 return MCDisassembler::Fail; 3797 } 3798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 Inst.addOperand(MCOperand::CreateImm(align)); 3801 if (Rm != 0xF) { 3802 if (Rm != 0xD) { 3803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3804 return MCDisassembler::Fail; 3805 } else 3806 Inst.addOperand(MCOperand::CreateReg(0)); 3807 } 3808 3809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3812 return MCDisassembler::Fail; 3813 Inst.addOperand(MCOperand::CreateImm(index)); 3814 3815 return S; 3816 } 3817 3818 3819 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3820 uint64_t Address, const void *Decoder) { 3821 DecodeStatus S = MCDisassembler::Success; 3822 3823 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3824 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3825 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3826 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3827 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3828 3829 unsigned align = 0; 3830 unsigned index = 0; 3831 unsigned inc = 1; 3832 switch (size) { 3833 default: 3834 return MCDisassembler::Fail; 3835 case 0: 3836 if (fieldFromInstruction32(Insn, 4, 1)) 3837 return MCDisassembler::Fail; // UNDEFINED 3838 index = fieldFromInstruction32(Insn, 5, 3); 3839 break; 3840 case 1: 3841 if (fieldFromInstruction32(Insn, 4, 1)) 3842 return MCDisassembler::Fail; // UNDEFINED 3843 index = fieldFromInstruction32(Insn, 6, 2); 3844 if (fieldFromInstruction32(Insn, 5, 1)) 3845 inc = 2; 3846 break; 3847 case 2: 3848 if (fieldFromInstruction32(Insn, 4, 2)) 3849 return MCDisassembler::Fail; // UNDEFINED 3850 index = fieldFromInstruction32(Insn, 7, 1); 3851 if (fieldFromInstruction32(Insn, 6, 1)) 3852 inc = 2; 3853 break; 3854 } 3855 3856 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3857 return MCDisassembler::Fail; 3858 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3861 return MCDisassembler::Fail; 3862 3863 if (Rm != 0xF) { // Writeback 3864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3865 return MCDisassembler::Fail; 3866 } 3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 Inst.addOperand(MCOperand::CreateImm(align)); 3870 if (Rm != 0xF) { 3871 if (Rm != 0xD) { 3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3873 return MCDisassembler::Fail; 3874 } else 3875 Inst.addOperand(MCOperand::CreateReg(0)); 3876 } 3877 3878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3881 return MCDisassembler::Fail; 3882 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3883 return MCDisassembler::Fail; 3884 Inst.addOperand(MCOperand::CreateImm(index)); 3885 3886 return S; 3887 } 3888 3889 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3890 uint64_t Address, const void *Decoder) { 3891 DecodeStatus S = MCDisassembler::Success; 3892 3893 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3894 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3895 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3896 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3897 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3898 3899 unsigned align = 0; 3900 unsigned index = 0; 3901 unsigned inc = 1; 3902 switch (size) { 3903 default: 3904 return MCDisassembler::Fail; 3905 case 0: 3906 if (fieldFromInstruction32(Insn, 4, 1)) 3907 return MCDisassembler::Fail; // UNDEFINED 3908 index = fieldFromInstruction32(Insn, 5, 3); 3909 break; 3910 case 1: 3911 if (fieldFromInstruction32(Insn, 4, 1)) 3912 return MCDisassembler::Fail; // UNDEFINED 3913 index = fieldFromInstruction32(Insn, 6, 2); 3914 if (fieldFromInstruction32(Insn, 5, 1)) 3915 inc = 2; 3916 break; 3917 case 2: 3918 if (fieldFromInstruction32(Insn, 4, 2)) 3919 return MCDisassembler::Fail; // UNDEFINED 3920 index = fieldFromInstruction32(Insn, 7, 1); 3921 if (fieldFromInstruction32(Insn, 6, 1)) 3922 inc = 2; 3923 break; 3924 } 3925 3926 if (Rm != 0xF) { // Writeback 3927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3928 return MCDisassembler::Fail; 3929 } 3930 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3931 return MCDisassembler::Fail; 3932 Inst.addOperand(MCOperand::CreateImm(align)); 3933 if (Rm != 0xF) { 3934 if (Rm != 0xD) { 3935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3936 return MCDisassembler::Fail; 3937 } else 3938 Inst.addOperand(MCOperand::CreateReg(0)); 3939 } 3940 3941 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3942 return MCDisassembler::Fail; 3943 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3946 return MCDisassembler::Fail; 3947 Inst.addOperand(MCOperand::CreateImm(index)); 3948 3949 return S; 3950 } 3951 3952 3953 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3954 uint64_t Address, const void *Decoder) { 3955 DecodeStatus S = MCDisassembler::Success; 3956 3957 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3958 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3960 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3961 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3962 3963 unsigned align = 0; 3964 unsigned index = 0; 3965 unsigned inc = 1; 3966 switch (size) { 3967 default: 3968 return MCDisassembler::Fail; 3969 case 0: 3970 if (fieldFromInstruction32(Insn, 4, 1)) 3971 align = 4; 3972 index = fieldFromInstruction32(Insn, 5, 3); 3973 break; 3974 case 1: 3975 if (fieldFromInstruction32(Insn, 4, 1)) 3976 align = 8; 3977 index = fieldFromInstruction32(Insn, 6, 2); 3978 if (fieldFromInstruction32(Insn, 5, 1)) 3979 inc = 2; 3980 break; 3981 case 2: 3982 if (fieldFromInstruction32(Insn, 4, 2)) 3983 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3984 index = fieldFromInstruction32(Insn, 7, 1); 3985 if (fieldFromInstruction32(Insn, 6, 1)) 3986 inc = 2; 3987 break; 3988 } 3989 3990 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3993 return MCDisassembler::Fail; 3994 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3995 return MCDisassembler::Fail; 3996 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 3999 if (Rm != 0xF) { // Writeback 4000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 } 4003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4004 return MCDisassembler::Fail; 4005 Inst.addOperand(MCOperand::CreateImm(align)); 4006 if (Rm != 0xF) { 4007 if (Rm != 0xD) { 4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 } else 4011 Inst.addOperand(MCOperand::CreateReg(0)); 4012 } 4013 4014 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4017 return MCDisassembler::Fail; 4018 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4019 return MCDisassembler::Fail; 4020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 Inst.addOperand(MCOperand::CreateImm(index)); 4023 4024 return S; 4025 } 4026 4027 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 4031 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4032 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4033 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4034 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4035 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4036 4037 unsigned align = 0; 4038 unsigned index = 0; 4039 unsigned inc = 1; 4040 switch (size) { 4041 default: 4042 return MCDisassembler::Fail; 4043 case 0: 4044 if (fieldFromInstruction32(Insn, 4, 1)) 4045 align = 4; 4046 index = fieldFromInstruction32(Insn, 5, 3); 4047 break; 4048 case 1: 4049 if (fieldFromInstruction32(Insn, 4, 1)) 4050 align = 8; 4051 index = fieldFromInstruction32(Insn, 6, 2); 4052 if (fieldFromInstruction32(Insn, 5, 1)) 4053 inc = 2; 4054 break; 4055 case 2: 4056 if (fieldFromInstruction32(Insn, 4, 2)) 4057 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4058 index = fieldFromInstruction32(Insn, 7, 1); 4059 if (fieldFromInstruction32(Insn, 6, 1)) 4060 inc = 2; 4061 break; 4062 } 4063 4064 if (Rm != 0xF) { // Writeback 4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4066 return MCDisassembler::Fail; 4067 } 4068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4069 return MCDisassembler::Fail; 4070 Inst.addOperand(MCOperand::CreateImm(align)); 4071 if (Rm != 0xF) { 4072 if (Rm != 0xD) { 4073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4074 return MCDisassembler::Fail; 4075 } else 4076 Inst.addOperand(MCOperand::CreateReg(0)); 4077 } 4078 4079 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4082 return MCDisassembler::Fail; 4083 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4084 return MCDisassembler::Fail; 4085 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 Inst.addOperand(MCOperand::CreateImm(index)); 4088 4089 return S; 4090 } 4091 4092 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 4093 uint64_t Address, const void *Decoder) { 4094 DecodeStatus S = MCDisassembler::Success; 4095 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4096 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4097 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4098 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4099 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4100 4101 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4102 S = MCDisassembler::SoftFail; 4103 4104 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4105 return MCDisassembler::Fail; 4106 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4107 return MCDisassembler::Fail; 4108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4109 return MCDisassembler::Fail; 4110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4111 return MCDisassembler::Fail; 4112 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4113 return MCDisassembler::Fail; 4114 4115 return S; 4116 } 4117 4118 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 4119 uint64_t Address, const void *Decoder) { 4120 DecodeStatus S = MCDisassembler::Success; 4121 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4122 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4123 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4124 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4125 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4126 4127 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4128 S = MCDisassembler::SoftFail; 4129 4130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4131 return MCDisassembler::Fail; 4132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4133 return MCDisassembler::Fail; 4134 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4135 return MCDisassembler::Fail; 4136 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4137 return MCDisassembler::Fail; 4138 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4139 return MCDisassembler::Fail; 4140 4141 return S; 4142 } 4143 4144 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 4145 uint64_t Address, const void *Decoder) { 4146 DecodeStatus S = MCDisassembler::Success; 4147 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4148 // The InstPrinter needs to have the low bit of the predicate in 4149 // the mask operand to be able to print it properly. 4150 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4151 4152 if (pred == 0xF) { 4153 pred = 0xE; 4154 S = MCDisassembler::SoftFail; 4155 } 4156 4157 if ((mask & 0xF) == 0) { 4158 // Preserve the high bit of the mask, which is the low bit of 4159 // the predicate. 4160 mask &= 0x10; 4161 mask |= 0x8; 4162 S = MCDisassembler::SoftFail; 4163 } 4164 4165 Inst.addOperand(MCOperand::CreateImm(pred)); 4166 Inst.addOperand(MCOperand::CreateImm(mask)); 4167 return S; 4168 } 4169 4170 static DecodeStatus 4171 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4172 uint64_t Address, const void *Decoder) { 4173 DecodeStatus S = MCDisassembler::Success; 4174 4175 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4176 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4177 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4178 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4179 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4180 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4181 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4182 bool writeback = (W == 1) | (P == 0); 4183 4184 addr |= (U << 8) | (Rn << 9); 4185 4186 if (writeback && (Rn == Rt || Rn == Rt2)) 4187 Check(S, MCDisassembler::SoftFail); 4188 if (Rt == Rt2) 4189 Check(S, MCDisassembler::SoftFail); 4190 4191 // Rt 4192 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4193 return MCDisassembler::Fail; 4194 // Rt2 4195 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4196 return MCDisassembler::Fail; 4197 // Writeback operand 4198 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4199 return MCDisassembler::Fail; 4200 // addr 4201 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4202 return MCDisassembler::Fail; 4203 4204 return S; 4205 } 4206 4207 static DecodeStatus 4208 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4209 uint64_t Address, const void *Decoder) { 4210 DecodeStatus S = MCDisassembler::Success; 4211 4212 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4213 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4214 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4215 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4216 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4217 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4218 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4219 bool writeback = (W == 1) | (P == 0); 4220 4221 addr |= (U << 8) | (Rn << 9); 4222 4223 if (writeback && (Rn == Rt || Rn == Rt2)) 4224 Check(S, MCDisassembler::SoftFail); 4225 4226 // Writeback operand 4227 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4228 return MCDisassembler::Fail; 4229 // Rt 4230 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 // Rt2 4233 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 // addr 4236 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 4239 return S; 4240 } 4241 4242 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4243 uint64_t Address, const void *Decoder) { 4244 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4245 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4246 if (sign1 != sign2) return MCDisassembler::Fail; 4247 4248 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4249 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4250 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4251 Val |= sign1 << 12; 4252 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4253 4254 return MCDisassembler::Success; 4255 } 4256 4257 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4258 uint64_t Address, 4259 const void *Decoder) { 4260 DecodeStatus S = MCDisassembler::Success; 4261 4262 // Shift of "asr #32" is not allowed in Thumb2 mode. 4263 if (Val == 0x20) S = MCDisassembler::SoftFail; 4264 Inst.addOperand(MCOperand::CreateImm(Val)); 4265 return S; 4266 } 4267 4268 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4269 uint64_t Address, const void *Decoder) { 4270 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4271 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4272 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4273 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4274 4275 if (pred == 0xF) 4276 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4277 4278 DecodeStatus S = MCDisassembler::Success; 4279 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4280 return MCDisassembler::Fail; 4281 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4282 return MCDisassembler::Fail; 4283 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4284 return MCDisassembler::Fail; 4285 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4286 return MCDisassembler::Fail; 4287 4288 return S; 4289 } 4290 4291 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4292 uint64_t Address, const void *Decoder) { 4293 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4294 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4295 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4296 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4297 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4298 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4299 4300 DecodeStatus S = MCDisassembler::Success; 4301 4302 // VMOVv2f32 is ambiguous with these decodings. 4303 if (!(imm & 0x38) && cmode == 0xF) { 4304 Inst.setOpcode(ARM::VMOVv2f32); 4305 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4306 } 4307 4308 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4309 4310 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4315 4316 return S; 4317 } 4318 4319 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4320 uint64_t Address, const void *Decoder) { 4321 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4322 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4323 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4324 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4325 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4326 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4327 4328 DecodeStatus S = MCDisassembler::Success; 4329 4330 // VMOVv4f32 is ambiguous with these decodings. 4331 if (!(imm & 0x38) && cmode == 0xF) { 4332 Inst.setOpcode(ARM::VMOVv4f32); 4333 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4334 } 4335 4336 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4337 4338 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4339 return MCDisassembler::Fail; 4340 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4343 4344 return S; 4345 } 4346 4347 static DecodeStatus DecodeLDR(llvm::MCInst &Inst, unsigned Val, 4348 uint64_t Address, const void *Decoder) { 4349 DecodeStatus S = MCDisassembler::Success; 4350 4351 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4352 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4353 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4354 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4355 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4356 4357 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4358 S = MCDisassembler::SoftFail; 4359 4360 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4361 return MCDisassembler::Fail; 4362 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4365 return MCDisassembler::Fail; 4366 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4367 return MCDisassembler::Fail; 4368 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 4371 return S; 4372 } 4373 4374