1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "llvm/MC/EDInstInfo.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <vector> 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 // Handles the condition code status of instructions in IT blocks 35 class ITStatus 36 { 37 public: 38 // Returns the condition code for instruction in IT block 39 unsigned getITCC() { 40 unsigned CC = ARMCC::AL; 41 if (instrInITBlock()) 42 CC = ITStates.back(); 43 return CC; 44 } 45 46 // Advances the IT block state to the next T or E 47 void advanceITState() { 48 ITStates.pop_back(); 49 } 50 51 // Returns true if the current instruction is in an IT block 52 bool instrInITBlock() { 53 return !ITStates.empty(); 54 } 55 56 // Returns true if current instruction is the last instruction in an IT block 57 bool instrLastInITBlock() { 58 return ITStates.size() == 1; 59 } 60 61 // Called when decoding an IT instruction. Sets the IT state for the following 62 // instructions that for the IT block. Firstcond and Mask correspond to the 63 // fields in the IT instruction encoding. 64 void setITState(char Firstcond, char Mask) { 65 // (3 - the number of trailing zeros) is the number of then / else. 66 unsigned CondBit0 = Firstcond & 1; 67 unsigned NumTZ = CountTrailingZeros_32(Mask); 68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 69 assert(NumTZ <= 3 && "Invalid IT mask!"); 70 // push condition codes onto the stack the correct order for the pops 71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72 bool T = ((Mask >> Pos) & 1) == CondBit0; 73 if (T) 74 ITStates.push_back(CCBits); 75 else 76 ITStates.push_back(CCBits ^ 1); 77 } 78 ITStates.push_back(CCBits); 79 } 80 81 private: 82 std::vector<unsigned char> ITStates; 83 }; 84 } 85 86 namespace { 87 /// ARMDisassembler - ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 /// Constructor - Initializes the disassembler. 91 /// 92 ARMDisassembler(const MCSubtargetInfo &STI) : 93 MCDisassembler(STI) { 94 } 95 96 ~ARMDisassembler() { 97 } 98 99 /// getInstruction - See MCDisassembler. 100 DecodeStatus getInstruction(MCInst &instr, 101 uint64_t &size, 102 const MemoryObject ®ion, 103 uint64_t address, 104 raw_ostream &vStream, 105 raw_ostream &cStream) const; 106 107 /// getEDInfo - See MCDisassembler. 108 const EDInstInfo *getEDInfo() const; 109 private: 110 }; 111 112 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 113 class ThumbDisassembler : public MCDisassembler { 114 public: 115 /// Constructor - Initializes the disassembler. 116 /// 117 ThumbDisassembler(const MCSubtargetInfo &STI) : 118 MCDisassembler(STI) { 119 } 120 121 ~ThumbDisassembler() { 122 } 123 124 /// getInstruction - See MCDisassembler. 125 DecodeStatus getInstruction(MCInst &instr, 126 uint64_t &size, 127 const MemoryObject ®ion, 128 uint64_t address, 129 raw_ostream &vStream, 130 raw_ostream &cStream) const; 131 132 /// getEDInfo - See MCDisassembler. 133 const EDInstInfo *getEDInfo() const; 134 private: 135 mutable ITStatus ITBlock; 136 DecodeStatus AddThumbPredicate(MCInst&) const; 137 void UpdateThumbVFPPredicate(MCInst&) const; 138 }; 139 } 140 141 static bool Check(DecodeStatus &Out, DecodeStatus In) { 142 switch (In) { 143 case MCDisassembler::Success: 144 // Out stays the same. 145 return true; 146 case MCDisassembler::SoftFail: 147 Out = In; 148 return true; 149 case MCDisassembler::Fail: 150 Out = In; 151 return false; 152 } 153 llvm_unreachable("Invalid DecodeStatus!"); 154 } 155 156 157 // Forward declare these because the autogenerated code will reference them. 158 // Definitions are further down. 159 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 162 unsigned RegNo, uint64_t Address, 163 const void *Decoder); 164 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 317 318 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 381 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 #include "ARMGenDisassemblerTables.inc" 386 #include "ARMGenInstrInfo.inc" 387 #include "ARMGenEDInfo.inc" 388 389 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 390 return new ARMDisassembler(STI); 391 } 392 393 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 394 return new ThumbDisassembler(STI); 395 } 396 397 const EDInstInfo *ARMDisassembler::getEDInfo() const { 398 return instInfoARM; 399 } 400 401 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 402 return instInfoARM; 403 } 404 405 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 const MemoryObject &Region, 407 uint64_t Address, 408 raw_ostream &os, 409 raw_ostream &cs) const { 410 CommentStream = &cs; 411 412 uint8_t bytes[4]; 413 414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 416 417 // We want to read exactly 4 bytes of data. 418 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 419 Size = 0; 420 return MCDisassembler::Fail; 421 } 422 423 // Encoded as a small-endian 32-bit word in the stream. 424 uint32_t insn = (bytes[3] << 24) | 425 (bytes[2] << 16) | 426 (bytes[1] << 8) | 427 (bytes[0] << 0); 428 429 // Calling the auto-generated decoder function. 430 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 431 if (result != MCDisassembler::Fail) { 432 Size = 4; 433 return result; 434 } 435 436 // VFP and NEON instructions, similarly, are shared between ARM 437 // and Thumb modes. 438 MI.clear(); 439 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 440 if (result != MCDisassembler::Fail) { 441 Size = 4; 442 return result; 443 } 444 445 MI.clear(); 446 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 447 if (result != MCDisassembler::Fail) { 448 Size = 4; 449 // Add a fake predicate operand, because we share these instruction 450 // definitions with Thumb2 where these instructions are predicable. 451 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 452 return MCDisassembler::Fail; 453 return result; 454 } 455 456 MI.clear(); 457 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 458 if (result != MCDisassembler::Fail) { 459 Size = 4; 460 // Add a fake predicate operand, because we share these instruction 461 // definitions with Thumb2 where these instructions are predicable. 462 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 463 return MCDisassembler::Fail; 464 return result; 465 } 466 467 MI.clear(); 468 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 469 if (result != MCDisassembler::Fail) { 470 Size = 4; 471 // Add a fake predicate operand, because we share these instruction 472 // definitions with Thumb2 where these instructions are predicable. 473 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 474 return MCDisassembler::Fail; 475 return result; 476 } 477 478 MI.clear(); 479 480 Size = 0; 481 return MCDisassembler::Fail; 482 } 483 484 namespace llvm { 485 extern const MCInstrDesc ARMInsts[]; 486 } 487 488 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 489 /// immediate Value in the MCInst. The immediate Value has had any PC 490 /// adjustment made by the caller. If the instruction is a branch instruction 491 /// then isBranch is true, else false. If the getOpInfo() function was set as 492 /// part of the setupForSymbolicDisassembly() call then that function is called 493 /// to get any symbolic information at the Address for this instruction. If 494 /// that returns non-zero then the symbolic information it returns is used to 495 /// create an MCExpr and that is added as an operand to the MCInst. If 496 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 497 /// Value is done and if a symbol is found an MCExpr is created with that, else 498 /// an MCExpr with Value is created. This function returns true if it adds an 499 /// operand to the MCInst and false otherwise. 500 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 501 bool isBranch, uint64_t InstSize, 502 MCInst &MI, const void *Decoder) { 503 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 504 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 505 struct LLVMOpInfo1 SymbolicOp; 506 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 507 SymbolicOp.Value = Value; 508 void *DisInfo = Dis->getDisInfoBlock(); 509 510 if (!getOpInfo || 511 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 512 // Clear SymbolicOp.Value from above and also all other fields. 513 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 514 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 515 if (!SymbolLookUp) 516 return false; 517 uint64_t ReferenceType; 518 if (isBranch) 519 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 520 else 521 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 522 const char *ReferenceName; 523 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 524 &ReferenceName); 525 if (Name) { 526 SymbolicOp.AddSymbol.Name = Name; 527 SymbolicOp.AddSymbol.Present = true; 528 } 529 // For branches always create an MCExpr so it gets printed as hex address. 530 else if (isBranch) { 531 SymbolicOp.Value = Value; 532 } 533 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 534 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 535 if (!Name && !isBranch) 536 return false; 537 } 538 539 MCContext *Ctx = Dis->getMCContext(); 540 const MCExpr *Add = NULL; 541 if (SymbolicOp.AddSymbol.Present) { 542 if (SymbolicOp.AddSymbol.Name) { 543 StringRef Name(SymbolicOp.AddSymbol.Name); 544 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 545 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 546 } else { 547 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 548 } 549 } 550 551 const MCExpr *Sub = NULL; 552 if (SymbolicOp.SubtractSymbol.Present) { 553 if (SymbolicOp.SubtractSymbol.Name) { 554 StringRef Name(SymbolicOp.SubtractSymbol.Name); 555 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 556 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 557 } else { 558 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 559 } 560 } 561 562 const MCExpr *Off = NULL; 563 if (SymbolicOp.Value != 0) 564 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 565 566 const MCExpr *Expr; 567 if (Sub) { 568 const MCExpr *LHS; 569 if (Add) 570 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 571 else 572 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 573 if (Off != 0) 574 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 575 else 576 Expr = LHS; 577 } else if (Add) { 578 if (Off != 0) 579 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 580 else 581 Expr = Add; 582 } else { 583 if (Off != 0) 584 Expr = Off; 585 else 586 Expr = MCConstantExpr::Create(0, *Ctx); 587 } 588 589 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 590 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 591 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 592 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 593 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 594 MI.addOperand(MCOperand::CreateExpr(Expr)); 595 else 596 llvm_unreachable("bad SymbolicOp.VariantKind"); 597 598 return true; 599 } 600 601 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 602 /// referenced by a load instruction with the base register that is the Pc. 603 /// These can often be values in a literal pool near the Address of the 604 /// instruction. The Address of the instruction and its immediate Value are 605 /// used as a possible literal pool entry. The SymbolLookUp call back will 606 /// return the name of a symbol referenced by the the literal pool's entry if 607 /// the referenced address is that of a symbol. Or it will return a pointer to 608 /// a literal 'C' string if the referenced address of the literal pool's entry 609 /// is an address into a section with 'C' string literals. 610 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 611 const void *Decoder) { 612 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 613 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 614 if (SymbolLookUp) { 615 void *DisInfo = Dis->getDisInfoBlock(); 616 uint64_t ReferenceType; 617 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 618 const char *ReferenceName; 619 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 620 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 621 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 622 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 623 } 624 } 625 626 // Thumb1 instructions don't have explicit S bits. Rather, they 627 // implicitly set CPSR. Since it's not represented in the encoding, the 628 // auto-generated decoder won't inject the CPSR operand. We need to fix 629 // that as a post-pass. 630 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 631 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 632 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 633 MCInst::iterator I = MI.begin(); 634 for (unsigned i = 0; i < NumOps; ++i, ++I) { 635 if (I == MI.end()) break; 636 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 637 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 639 return; 640 } 641 } 642 643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 644 } 645 646 // Most Thumb instructions don't have explicit predicates in the 647 // encoding, but rather get their predicates from IT context. We need 648 // to fix up the predicate operands using this context information as a 649 // post-pass. 650 MCDisassembler::DecodeStatus 651 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 652 MCDisassembler::DecodeStatus S = Success; 653 654 // A few instructions actually have predicates encoded in them. Don't 655 // try to overwrite it if we're seeing one of those. 656 switch (MI.getOpcode()) { 657 case ARM::tBcc: 658 case ARM::t2Bcc: 659 case ARM::tCBZ: 660 case ARM::tCBNZ: 661 case ARM::tCPS: 662 case ARM::t2CPS3p: 663 case ARM::t2CPS2p: 664 case ARM::t2CPS1p: 665 case ARM::tMOVSr: 666 case ARM::tSETEND: 667 // Some instructions (mostly conditional branches) are not 668 // allowed in IT blocks. 669 if (ITBlock.instrInITBlock()) 670 S = SoftFail; 671 else 672 return Success; 673 break; 674 case ARM::tB: 675 case ARM::t2B: 676 case ARM::t2TBB: 677 case ARM::t2TBH: 678 // Some instructions (mostly unconditional branches) can 679 // only appears at the end of, or outside of, an IT. 680 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 681 S = SoftFail; 682 break; 683 default: 684 break; 685 } 686 687 // If we're in an IT block, base the predicate on that. Otherwise, 688 // assume a predicate of AL. 689 unsigned CC; 690 CC = ITBlock.getITCC(); 691 if (CC == 0xF) 692 CC = ARMCC::AL; 693 if (ITBlock.instrInITBlock()) 694 ITBlock.advanceITState(); 695 696 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 697 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 698 MCInst::iterator I = MI.begin(); 699 for (unsigned i = 0; i < NumOps; ++i, ++I) { 700 if (I == MI.end()) break; 701 if (OpInfo[i].isPredicate()) { 702 I = MI.insert(I, MCOperand::CreateImm(CC)); 703 ++I; 704 if (CC == ARMCC::AL) 705 MI.insert(I, MCOperand::CreateReg(0)); 706 else 707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 708 return S; 709 } 710 } 711 712 I = MI.insert(I, MCOperand::CreateImm(CC)); 713 ++I; 714 if (CC == ARMCC::AL) 715 MI.insert(I, MCOperand::CreateReg(0)); 716 else 717 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 718 719 return S; 720 } 721 722 // Thumb VFP instructions are a special case. Because we share their 723 // encodings between ARM and Thumb modes, and they are predicable in ARM 724 // mode, the auto-generated decoder will give them an (incorrect) 725 // predicate operand. We need to rewrite these operands based on the IT 726 // context as a post-pass. 727 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 728 unsigned CC; 729 CC = ITBlock.getITCC(); 730 if (ITBlock.instrInITBlock()) 731 ITBlock.advanceITState(); 732 733 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 734 MCInst::iterator I = MI.begin(); 735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 736 for (unsigned i = 0; i < NumOps; ++i, ++I) { 737 if (OpInfo[i].isPredicate() ) { 738 I->setImm(CC); 739 ++I; 740 if (CC == ARMCC::AL) 741 I->setReg(0); 742 else 743 I->setReg(ARM::CPSR); 744 return; 745 } 746 } 747 } 748 749 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 750 const MemoryObject &Region, 751 uint64_t Address, 752 raw_ostream &os, 753 raw_ostream &cs) const { 754 CommentStream = &cs; 755 756 uint8_t bytes[4]; 757 758 assert((STI.getFeatureBits() & ARM::ModeThumb) && 759 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 760 761 // We want to read exactly 2 bytes of data. 762 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 763 Size = 0; 764 return MCDisassembler::Fail; 765 } 766 767 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 768 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 769 if (result != MCDisassembler::Fail) { 770 Size = 2; 771 Check(result, AddThumbPredicate(MI)); 772 return result; 773 } 774 775 MI.clear(); 776 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 777 if (result) { 778 Size = 2; 779 bool InITBlock = ITBlock.instrInITBlock(); 780 Check(result, AddThumbPredicate(MI)); 781 AddThumb1SBit(MI, InITBlock); 782 return result; 783 } 784 785 MI.clear(); 786 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 787 if (result != MCDisassembler::Fail) { 788 Size = 2; 789 790 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 791 // the Thumb predicate. 792 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 793 result = MCDisassembler::SoftFail; 794 795 Check(result, AddThumbPredicate(MI)); 796 797 // If we find an IT instruction, we need to parse its condition 798 // code and mask operands so that we can apply them correctly 799 // to the subsequent instructions. 800 if (MI.getOpcode() == ARM::t2IT) { 801 802 unsigned Firstcond = MI.getOperand(0).getImm(); 803 unsigned Mask = MI.getOperand(1).getImm(); 804 ITBlock.setITState(Firstcond, Mask); 805 } 806 807 return result; 808 } 809 810 // We want to read exactly 4 bytes of data. 811 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 812 Size = 0; 813 return MCDisassembler::Fail; 814 } 815 816 uint32_t insn32 = (bytes[3] << 8) | 817 (bytes[2] << 0) | 818 (bytes[1] << 24) | 819 (bytes[0] << 16); 820 MI.clear(); 821 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 822 if (result != MCDisassembler::Fail) { 823 Size = 4; 824 bool InITBlock = ITBlock.instrInITBlock(); 825 Check(result, AddThumbPredicate(MI)); 826 AddThumb1SBit(MI, InITBlock); 827 return result; 828 } 829 830 MI.clear(); 831 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 Check(result, AddThumbPredicate(MI)); 835 return result; 836 } 837 838 MI.clear(); 839 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 840 if (result != MCDisassembler::Fail) { 841 Size = 4; 842 UpdateThumbVFPPredicate(MI); 843 return result; 844 } 845 846 MI.clear(); 847 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 848 if (result != MCDisassembler::Fail) { 849 Size = 4; 850 Check(result, AddThumbPredicate(MI)); 851 return result; 852 } 853 854 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 855 MI.clear(); 856 uint32_t NEONLdStInsn = insn32; 857 NEONLdStInsn &= 0xF0FFFFFF; 858 NEONLdStInsn |= 0x04000000; 859 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 860 if (result != MCDisassembler::Fail) { 861 Size = 4; 862 Check(result, AddThumbPredicate(MI)); 863 return result; 864 } 865 } 866 867 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 868 MI.clear(); 869 uint32_t NEONDataInsn = insn32; 870 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 871 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 872 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 873 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 874 if (result != MCDisassembler::Fail) { 875 Size = 4; 876 Check(result, AddThumbPredicate(MI)); 877 return result; 878 } 879 } 880 881 Size = 0; 882 return MCDisassembler::Fail; 883 } 884 885 886 extern "C" void LLVMInitializeARMDisassembler() { 887 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 888 createARMDisassembler); 889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 890 createThumbDisassembler); 891 } 892 893 static const uint16_t GPRDecoderTable[] = { 894 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 895 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 896 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 897 ARM::R12, ARM::SP, ARM::LR, ARM::PC 898 }; 899 900 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 if (RegNo > 15) 903 return MCDisassembler::Fail; 904 905 unsigned Register = GPRDecoderTable[RegNo]; 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static DecodeStatus 911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo == 15) 916 S = MCDisassembler::SoftFail; 917 918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 919 920 return S; 921 } 922 923 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 7) 926 return MCDisassembler::Fail; 927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 928 } 929 930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 unsigned Register = 0; 933 switch (RegNo) { 934 case 0: 935 Register = ARM::R0; 936 break; 937 case 1: 938 Register = ARM::R1; 939 break; 940 case 2: 941 Register = ARM::R2; 942 break; 943 case 3: 944 Register = ARM::R3; 945 break; 946 case 9: 947 Register = ARM::R9; 948 break; 949 case 12: 950 Register = ARM::R12; 951 break; 952 default: 953 return MCDisassembler::Fail; 954 } 955 956 Inst.addOperand(MCOperand::CreateReg(Register)); 957 return MCDisassembler::Success; 958 } 959 960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 964 } 965 966 static const uint16_t SPRDecoderTable[] = { 967 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 968 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 969 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 970 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 971 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 972 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 973 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 974 ARM::S28, ARM::S29, ARM::S30, ARM::S31 975 }; 976 977 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 if (RegNo > 31) 980 return MCDisassembler::Fail; 981 982 unsigned Register = SPRDecoderTable[RegNo]; 983 Inst.addOperand(MCOperand::CreateReg(Register)); 984 return MCDisassembler::Success; 985 } 986 987 static const uint16_t DPRDecoderTable[] = { 988 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 989 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 990 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 991 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 992 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 993 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 994 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 995 ARM::D28, ARM::D29, ARM::D30, ARM::D31 996 }; 997 998 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 999 uint64_t Address, const void *Decoder) { 1000 if (RegNo > 31) 1001 return MCDisassembler::Fail; 1002 1003 unsigned Register = DPRDecoderTable[RegNo]; 1004 Inst.addOperand(MCOperand::CreateReg(Register)); 1005 return MCDisassembler::Success; 1006 } 1007 1008 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 7) 1011 return MCDisassembler::Fail; 1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1013 } 1014 1015 static DecodeStatus 1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1017 uint64_t Address, const void *Decoder) { 1018 if (RegNo > 15) 1019 return MCDisassembler::Fail; 1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1021 } 1022 1023 static const uint16_t QPRDecoderTable[] = { 1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1028 }; 1029 1030 1031 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1032 uint64_t Address, const void *Decoder) { 1033 if (RegNo > 31) 1034 return MCDisassembler::Fail; 1035 RegNo >>= 1; 1036 1037 unsigned Register = QPRDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040 } 1041 1042 static const uint16_t DPairDecoderTable[] = { 1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1048 ARM::Q15 1049 }; 1050 1051 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1052 uint64_t Address, const void *Decoder) { 1053 if (RegNo > 30) 1054 return MCDisassembler::Fail; 1055 1056 unsigned Register = DPairDecoderTable[RegNo]; 1057 Inst.addOperand(MCOperand::CreateReg(Register)); 1058 return MCDisassembler::Success; 1059 } 1060 1061 static const uint16_t DPairSpacedDecoderTable[] = { 1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1069 ARM::D28_D30, ARM::D29_D31 1070 }; 1071 1072 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1073 unsigned RegNo, 1074 uint64_t Address, 1075 const void *Decoder) { 1076 if (RegNo > 29) 1077 return MCDisassembler::Fail; 1078 1079 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1080 Inst.addOperand(MCOperand::CreateReg(Register)); 1081 return MCDisassembler::Success; 1082 } 1083 1084 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1085 uint64_t Address, const void *Decoder) { 1086 if (Val == 0xF) return MCDisassembler::Fail; 1087 // AL predicate is not allowed on Thumb1 branches. 1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1089 return MCDisassembler::Fail; 1090 Inst.addOperand(MCOperand::CreateImm(Val)); 1091 if (Val == ARMCC::AL) { 1092 Inst.addOperand(MCOperand::CreateReg(0)); 1093 } else 1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val) 1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1102 else 1103 Inst.addOperand(MCOperand::CreateReg(0)); 1104 return MCDisassembler::Success; 1105 } 1106 1107 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1108 uint64_t Address, const void *Decoder) { 1109 uint32_t imm = Val & 0xFF; 1110 uint32_t rot = (Val & 0xF00) >> 7; 1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1112 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 1120 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1121 unsigned type = fieldFromInstruction32(Val, 5, 2); 1122 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1123 1124 // Register-immediate 1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1126 return MCDisassembler::Fail; 1127 1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1129 switch (type) { 1130 case 0: 1131 Shift = ARM_AM::lsl; 1132 break; 1133 case 1: 1134 Shift = ARM_AM::lsr; 1135 break; 1136 case 2: 1137 Shift = ARM_AM::asr; 1138 break; 1139 case 3: 1140 Shift = ARM_AM::ror; 1141 break; 1142 } 1143 1144 if (Shift == ARM_AM::ror && imm == 0) 1145 Shift = ARM_AM::rrx; 1146 1147 unsigned Op = Shift | (imm << 3); 1148 Inst.addOperand(MCOperand::CreateImm(Op)); 1149 1150 return S; 1151 } 1152 1153 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1154 uint64_t Address, const void *Decoder) { 1155 DecodeStatus S = MCDisassembler::Success; 1156 1157 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1158 unsigned type = fieldFromInstruction32(Val, 5, 2); 1159 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1160 1161 // Register-register 1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1165 return MCDisassembler::Fail; 1166 1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1168 switch (type) { 1169 case 0: 1170 Shift = ARM_AM::lsl; 1171 break; 1172 case 1: 1173 Shift = ARM_AM::lsr; 1174 break; 1175 case 2: 1176 Shift = ARM_AM::asr; 1177 break; 1178 case 3: 1179 Shift = ARM_AM::ror; 1180 break; 1181 } 1182 1183 Inst.addOperand(MCOperand::CreateImm(Shift)); 1184 1185 return S; 1186 } 1187 1188 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 bool writebackLoad = false; 1193 unsigned writebackReg = 0; 1194 switch (Inst.getOpcode()) { 1195 default: 1196 break; 1197 case ARM::LDMIA_UPD: 1198 case ARM::LDMDB_UPD: 1199 case ARM::LDMIB_UPD: 1200 case ARM::LDMDA_UPD: 1201 case ARM::t2LDMIA_UPD: 1202 case ARM::t2LDMDB_UPD: 1203 writebackLoad = true; 1204 writebackReg = Inst.getOperand(0).getReg(); 1205 break; 1206 } 1207 1208 // Empty register lists are not allowed. 1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1210 for (unsigned i = 0; i < 16; ++i) { 1211 if (Val & (1 << i)) { 1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1213 return MCDisassembler::Fail; 1214 // Writeback not allowed if Rn is in the target list. 1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1216 Check(S, MCDisassembler::SoftFail); 1217 } 1218 } 1219 1220 return S; 1221 } 1222 1223 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1228 unsigned regs = Val & 0xFF; 1229 1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < (regs - 1); ++i) { 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 } 1236 1237 return S; 1238 } 1239 1240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1241 uint64_t Address, const void *Decoder) { 1242 DecodeStatus S = MCDisassembler::Success; 1243 1244 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1245 unsigned regs = (Val & 0xFF) / 2; 1246 1247 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1248 return MCDisassembler::Fail; 1249 for (unsigned i = 0; i < (regs - 1); ++i) { 1250 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1251 return MCDisassembler::Fail; 1252 } 1253 1254 return S; 1255 } 1256 1257 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1258 uint64_t Address, const void *Decoder) { 1259 // This operand encodes a mask of contiguous zeros between a specified MSB 1260 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1261 // the mask of all bits LSB-and-lower, and then xor them to create 1262 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1263 // create the final mask. 1264 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1265 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1266 1267 DecodeStatus S = MCDisassembler::Success; 1268 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1269 1270 uint32_t msb_mask = 0xFFFFFFFF; 1271 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1272 uint32_t lsb_mask = (1U << lsb) - 1; 1273 1274 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1275 return S; 1276 } 1277 1278 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1279 uint64_t Address, const void *Decoder) { 1280 DecodeStatus S = MCDisassembler::Success; 1281 1282 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1283 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1284 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1285 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1286 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1287 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1288 1289 switch (Inst.getOpcode()) { 1290 case ARM::LDC_OFFSET: 1291 case ARM::LDC_PRE: 1292 case ARM::LDC_POST: 1293 case ARM::LDC_OPTION: 1294 case ARM::LDCL_OFFSET: 1295 case ARM::LDCL_PRE: 1296 case ARM::LDCL_POST: 1297 case ARM::LDCL_OPTION: 1298 case ARM::STC_OFFSET: 1299 case ARM::STC_PRE: 1300 case ARM::STC_POST: 1301 case ARM::STC_OPTION: 1302 case ARM::STCL_OFFSET: 1303 case ARM::STCL_PRE: 1304 case ARM::STCL_POST: 1305 case ARM::STCL_OPTION: 1306 case ARM::t2LDC_OFFSET: 1307 case ARM::t2LDC_PRE: 1308 case ARM::t2LDC_POST: 1309 case ARM::t2LDC_OPTION: 1310 case ARM::t2LDCL_OFFSET: 1311 case ARM::t2LDCL_PRE: 1312 case ARM::t2LDCL_POST: 1313 case ARM::t2LDCL_OPTION: 1314 case ARM::t2STC_OFFSET: 1315 case ARM::t2STC_PRE: 1316 case ARM::t2STC_POST: 1317 case ARM::t2STC_OPTION: 1318 case ARM::t2STCL_OFFSET: 1319 case ARM::t2STCL_PRE: 1320 case ARM::t2STCL_POST: 1321 case ARM::t2STCL_OPTION: 1322 if (coproc == 0xA || coproc == 0xB) 1323 return MCDisassembler::Fail; 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 Inst.addOperand(MCOperand::CreateImm(coproc)); 1330 Inst.addOperand(MCOperand::CreateImm(CRd)); 1331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1332 return MCDisassembler::Fail; 1333 1334 switch (Inst.getOpcode()) { 1335 case ARM::t2LDC2_OFFSET: 1336 case ARM::t2LDC2L_OFFSET: 1337 case ARM::t2LDC2_PRE: 1338 case ARM::t2LDC2L_PRE: 1339 case ARM::t2STC2_OFFSET: 1340 case ARM::t2STC2L_OFFSET: 1341 case ARM::t2STC2_PRE: 1342 case ARM::t2STC2L_PRE: 1343 case ARM::LDC2_OFFSET: 1344 case ARM::LDC2L_OFFSET: 1345 case ARM::LDC2_PRE: 1346 case ARM::LDC2L_PRE: 1347 case ARM::STC2_OFFSET: 1348 case ARM::STC2L_OFFSET: 1349 case ARM::STC2_PRE: 1350 case ARM::STC2L_PRE: 1351 case ARM::t2LDC_OFFSET: 1352 case ARM::t2LDCL_OFFSET: 1353 case ARM::t2LDC_PRE: 1354 case ARM::t2LDCL_PRE: 1355 case ARM::t2STC_OFFSET: 1356 case ARM::t2STCL_OFFSET: 1357 case ARM::t2STC_PRE: 1358 case ARM::t2STCL_PRE: 1359 case ARM::LDC_OFFSET: 1360 case ARM::LDCL_OFFSET: 1361 case ARM::LDC_PRE: 1362 case ARM::LDCL_PRE: 1363 case ARM::STC_OFFSET: 1364 case ARM::STCL_OFFSET: 1365 case ARM::STC_PRE: 1366 case ARM::STCL_PRE: 1367 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1368 Inst.addOperand(MCOperand::CreateImm(imm)); 1369 break; 1370 case ARM::t2LDC2_POST: 1371 case ARM::t2LDC2L_POST: 1372 case ARM::t2STC2_POST: 1373 case ARM::t2STC2L_POST: 1374 case ARM::LDC2_POST: 1375 case ARM::LDC2L_POST: 1376 case ARM::STC2_POST: 1377 case ARM::STC2L_POST: 1378 case ARM::t2LDC_POST: 1379 case ARM::t2LDCL_POST: 1380 case ARM::t2STC_POST: 1381 case ARM::t2STCL_POST: 1382 case ARM::LDC_POST: 1383 case ARM::LDCL_POST: 1384 case ARM::STC_POST: 1385 case ARM::STCL_POST: 1386 imm |= U << 8; 1387 // fall through. 1388 default: 1389 // The 'option' variant doesn't encode 'U' in the immediate since 1390 // the immediate is unsigned [0,255]. 1391 Inst.addOperand(MCOperand::CreateImm(imm)); 1392 break; 1393 } 1394 1395 switch (Inst.getOpcode()) { 1396 case ARM::LDC_OFFSET: 1397 case ARM::LDC_PRE: 1398 case ARM::LDC_POST: 1399 case ARM::LDC_OPTION: 1400 case ARM::LDCL_OFFSET: 1401 case ARM::LDCL_PRE: 1402 case ARM::LDCL_POST: 1403 case ARM::LDCL_OPTION: 1404 case ARM::STC_OFFSET: 1405 case ARM::STC_PRE: 1406 case ARM::STC_POST: 1407 case ARM::STC_OPTION: 1408 case ARM::STCL_OFFSET: 1409 case ARM::STCL_PRE: 1410 case ARM::STCL_POST: 1411 case ARM::STCL_OPTION: 1412 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1413 return MCDisassembler::Fail; 1414 break; 1415 default: 1416 break; 1417 } 1418 1419 return S; 1420 } 1421 1422 static DecodeStatus 1423 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1424 uint64_t Address, const void *Decoder) { 1425 DecodeStatus S = MCDisassembler::Success; 1426 1427 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1428 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1429 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1430 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1431 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1432 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1433 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1434 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1435 1436 // On stores, the writeback operand precedes Rt. 1437 switch (Inst.getOpcode()) { 1438 case ARM::STR_POST_IMM: 1439 case ARM::STR_POST_REG: 1440 case ARM::STRB_POST_IMM: 1441 case ARM::STRB_POST_REG: 1442 case ARM::STRT_POST_REG: 1443 case ARM::STRT_POST_IMM: 1444 case ARM::STRBT_POST_REG: 1445 case ARM::STRBT_POST_IMM: 1446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1447 return MCDisassembler::Fail; 1448 break; 1449 default: 1450 break; 1451 } 1452 1453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1454 return MCDisassembler::Fail; 1455 1456 // On loads, the writeback operand comes after Rt. 1457 switch (Inst.getOpcode()) { 1458 case ARM::LDR_POST_IMM: 1459 case ARM::LDR_POST_REG: 1460 case ARM::LDRB_POST_IMM: 1461 case ARM::LDRB_POST_REG: 1462 case ARM::LDRBT_POST_REG: 1463 case ARM::LDRBT_POST_IMM: 1464 case ARM::LDRT_POST_REG: 1465 case ARM::LDRT_POST_IMM: 1466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1467 return MCDisassembler::Fail; 1468 break; 1469 default: 1470 break; 1471 } 1472 1473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1474 return MCDisassembler::Fail; 1475 1476 ARM_AM::AddrOpc Op = ARM_AM::add; 1477 if (!fieldFromInstruction32(Insn, 23, 1)) 1478 Op = ARM_AM::sub; 1479 1480 bool writeback = (P == 0) || (W == 1); 1481 unsigned idx_mode = 0; 1482 if (P && writeback) 1483 idx_mode = ARMII::IndexModePre; 1484 else if (!P && writeback) 1485 idx_mode = ARMII::IndexModePost; 1486 1487 if (writeback && (Rn == 15 || Rn == Rt)) 1488 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1489 1490 if (reg) { 1491 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1492 return MCDisassembler::Fail; 1493 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1494 switch( fieldFromInstruction32(Insn, 5, 2)) { 1495 case 0: 1496 Opc = ARM_AM::lsl; 1497 break; 1498 case 1: 1499 Opc = ARM_AM::lsr; 1500 break; 1501 case 2: 1502 Opc = ARM_AM::asr; 1503 break; 1504 case 3: 1505 Opc = ARM_AM::ror; 1506 break; 1507 default: 1508 return MCDisassembler::Fail; 1509 } 1510 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1511 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1512 1513 Inst.addOperand(MCOperand::CreateImm(imm)); 1514 } else { 1515 Inst.addOperand(MCOperand::CreateReg(0)); 1516 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1517 Inst.addOperand(MCOperand::CreateImm(tmp)); 1518 } 1519 1520 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1521 return MCDisassembler::Fail; 1522 1523 return S; 1524 } 1525 1526 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1527 uint64_t Address, const void *Decoder) { 1528 DecodeStatus S = MCDisassembler::Success; 1529 1530 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1531 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1532 unsigned type = fieldFromInstruction32(Val, 5, 2); 1533 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1534 unsigned U = fieldFromInstruction32(Val, 12, 1); 1535 1536 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1537 switch (type) { 1538 case 0: 1539 ShOp = ARM_AM::lsl; 1540 break; 1541 case 1: 1542 ShOp = ARM_AM::lsr; 1543 break; 1544 case 2: 1545 ShOp = ARM_AM::asr; 1546 break; 1547 case 3: 1548 ShOp = ARM_AM::ror; 1549 break; 1550 } 1551 1552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1553 return MCDisassembler::Fail; 1554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1555 return MCDisassembler::Fail; 1556 unsigned shift; 1557 if (U) 1558 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1559 else 1560 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1561 Inst.addOperand(MCOperand::CreateImm(shift)); 1562 1563 return S; 1564 } 1565 1566 static DecodeStatus 1567 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1568 uint64_t Address, const void *Decoder) { 1569 DecodeStatus S = MCDisassembler::Success; 1570 1571 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1572 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1573 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1574 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1575 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1576 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1577 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1578 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1579 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1580 unsigned Rt2 = Rt + 1; 1581 1582 bool writeback = (W == 1) | (P == 0); 1583 1584 // For {LD,ST}RD, Rt must be even, else undefined. 1585 switch (Inst.getOpcode()) { 1586 case ARM::STRD: 1587 case ARM::STRD_PRE: 1588 case ARM::STRD_POST: 1589 case ARM::LDRD: 1590 case ARM::LDRD_PRE: 1591 case ARM::LDRD_POST: 1592 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1593 break; 1594 default: 1595 break; 1596 } 1597 switch (Inst.getOpcode()) { 1598 case ARM::STRD: 1599 case ARM::STRD_PRE: 1600 case ARM::STRD_POST: 1601 if (P == 0 && W == 1) 1602 S = MCDisassembler::SoftFail; 1603 1604 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1605 S = MCDisassembler::SoftFail; 1606 if (type && Rm == 15) 1607 S = MCDisassembler::SoftFail; 1608 if (Rt2 == 15) 1609 S = MCDisassembler::SoftFail; 1610 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1611 S = MCDisassembler::SoftFail; 1612 break; 1613 case ARM::STRH: 1614 case ARM::STRH_PRE: 1615 case ARM::STRH_POST: 1616 if (Rt == 15) 1617 S = MCDisassembler::SoftFail; 1618 if (writeback && (Rn == 15 || Rn == Rt)) 1619 S = MCDisassembler::SoftFail; 1620 if (!type && Rm == 15) 1621 S = MCDisassembler::SoftFail; 1622 break; 1623 case ARM::LDRD: 1624 case ARM::LDRD_PRE: 1625 case ARM::LDRD_POST: 1626 if (type && Rn == 15){ 1627 if (Rt2 == 15) 1628 S = MCDisassembler::SoftFail; 1629 break; 1630 } 1631 if (P == 0 && W == 1) 1632 S = MCDisassembler::SoftFail; 1633 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1634 S = MCDisassembler::SoftFail; 1635 if (!type && writeback && Rn == 15) 1636 S = MCDisassembler::SoftFail; 1637 if (writeback && (Rn == Rt || Rn == Rt2)) 1638 S = MCDisassembler::SoftFail; 1639 break; 1640 case ARM::LDRH: 1641 case ARM::LDRH_PRE: 1642 case ARM::LDRH_POST: 1643 if (type && Rn == 15){ 1644 if (Rt == 15) 1645 S = MCDisassembler::SoftFail; 1646 break; 1647 } 1648 if (Rt == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (!type && Rm == 15) 1651 S = MCDisassembler::SoftFail; 1652 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1653 S = MCDisassembler::SoftFail; 1654 break; 1655 case ARM::LDRSH: 1656 case ARM::LDRSH_PRE: 1657 case ARM::LDRSH_POST: 1658 case ARM::LDRSB: 1659 case ARM::LDRSB_PRE: 1660 case ARM::LDRSB_POST: 1661 if (type && Rn == 15){ 1662 if (Rt == 15) 1663 S = MCDisassembler::SoftFail; 1664 break; 1665 } 1666 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1667 S = MCDisassembler::SoftFail; 1668 if (!type && (Rt == 15 || Rm == 15)) 1669 S = MCDisassembler::SoftFail; 1670 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1671 S = MCDisassembler::SoftFail; 1672 break; 1673 default: 1674 break; 1675 } 1676 1677 if (writeback) { // Writeback 1678 if (P) 1679 U |= ARMII::IndexModePre << 9; 1680 else 1681 U |= ARMII::IndexModePost << 9; 1682 1683 // On stores, the writeback operand precedes Rt. 1684 switch (Inst.getOpcode()) { 1685 case ARM::STRD: 1686 case ARM::STRD_PRE: 1687 case ARM::STRD_POST: 1688 case ARM::STRH: 1689 case ARM::STRH_PRE: 1690 case ARM::STRH_POST: 1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1692 return MCDisassembler::Fail; 1693 break; 1694 default: 1695 break; 1696 } 1697 } 1698 1699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1700 return MCDisassembler::Fail; 1701 switch (Inst.getOpcode()) { 1702 case ARM::STRD: 1703 case ARM::STRD_PRE: 1704 case ARM::STRD_POST: 1705 case ARM::LDRD: 1706 case ARM::LDRD_PRE: 1707 case ARM::LDRD_POST: 1708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1709 return MCDisassembler::Fail; 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 if (writeback) { 1716 // On loads, the writeback operand comes after Rt. 1717 switch (Inst.getOpcode()) { 1718 case ARM::LDRD: 1719 case ARM::LDRD_PRE: 1720 case ARM::LDRD_POST: 1721 case ARM::LDRH: 1722 case ARM::LDRH_PRE: 1723 case ARM::LDRH_POST: 1724 case ARM::LDRSH: 1725 case ARM::LDRSH_PRE: 1726 case ARM::LDRSH_POST: 1727 case ARM::LDRSB: 1728 case ARM::LDRSB_PRE: 1729 case ARM::LDRSB_POST: 1730 case ARM::LDRHTr: 1731 case ARM::LDRSBTr: 1732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1733 return MCDisassembler::Fail; 1734 break; 1735 default: 1736 break; 1737 } 1738 } 1739 1740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1741 return MCDisassembler::Fail; 1742 1743 if (type) { 1744 Inst.addOperand(MCOperand::CreateReg(0)); 1745 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1746 } else { 1747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1748 return MCDisassembler::Fail; 1749 Inst.addOperand(MCOperand::CreateImm(U)); 1750 } 1751 1752 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 1755 return S; 1756 } 1757 1758 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1759 uint64_t Address, const void *Decoder) { 1760 DecodeStatus S = MCDisassembler::Success; 1761 1762 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1763 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1764 1765 switch (mode) { 1766 case 0: 1767 mode = ARM_AM::da; 1768 break; 1769 case 1: 1770 mode = ARM_AM::ia; 1771 break; 1772 case 2: 1773 mode = ARM_AM::db; 1774 break; 1775 case 3: 1776 mode = ARM_AM::ib; 1777 break; 1778 } 1779 1780 Inst.addOperand(MCOperand::CreateImm(mode)); 1781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1782 return MCDisassembler::Fail; 1783 1784 return S; 1785 } 1786 1787 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1788 unsigned Insn, 1789 uint64_t Address, const void *Decoder) { 1790 DecodeStatus S = MCDisassembler::Success; 1791 1792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1793 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1794 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1795 1796 if (pred == 0xF) { 1797 switch (Inst.getOpcode()) { 1798 case ARM::LDMDA: 1799 Inst.setOpcode(ARM::RFEDA); 1800 break; 1801 case ARM::LDMDA_UPD: 1802 Inst.setOpcode(ARM::RFEDA_UPD); 1803 break; 1804 case ARM::LDMDB: 1805 Inst.setOpcode(ARM::RFEDB); 1806 break; 1807 case ARM::LDMDB_UPD: 1808 Inst.setOpcode(ARM::RFEDB_UPD); 1809 break; 1810 case ARM::LDMIA: 1811 Inst.setOpcode(ARM::RFEIA); 1812 break; 1813 case ARM::LDMIA_UPD: 1814 Inst.setOpcode(ARM::RFEIA_UPD); 1815 break; 1816 case ARM::LDMIB: 1817 Inst.setOpcode(ARM::RFEIB); 1818 break; 1819 case ARM::LDMIB_UPD: 1820 Inst.setOpcode(ARM::RFEIB_UPD); 1821 break; 1822 case ARM::STMDA: 1823 Inst.setOpcode(ARM::SRSDA); 1824 break; 1825 case ARM::STMDA_UPD: 1826 Inst.setOpcode(ARM::SRSDA_UPD); 1827 break; 1828 case ARM::STMDB: 1829 Inst.setOpcode(ARM::SRSDB); 1830 break; 1831 case ARM::STMDB_UPD: 1832 Inst.setOpcode(ARM::SRSDB_UPD); 1833 break; 1834 case ARM::STMIA: 1835 Inst.setOpcode(ARM::SRSIA); 1836 break; 1837 case ARM::STMIA_UPD: 1838 Inst.setOpcode(ARM::SRSIA_UPD); 1839 break; 1840 case ARM::STMIB: 1841 Inst.setOpcode(ARM::SRSIB); 1842 break; 1843 case ARM::STMIB_UPD: 1844 Inst.setOpcode(ARM::SRSIB_UPD); 1845 break; 1846 default: 1847 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1848 } 1849 1850 // For stores (which become SRS's, the only operand is the mode. 1851 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1852 Inst.addOperand( 1853 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1854 return S; 1855 } 1856 1857 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1858 } 1859 1860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1861 return MCDisassembler::Fail; 1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1863 return MCDisassembler::Fail; // Tied 1864 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1865 return MCDisassembler::Fail; 1866 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 1869 return S; 1870 } 1871 1872 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1873 uint64_t Address, const void *Decoder) { 1874 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1875 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1876 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1877 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1878 1879 DecodeStatus S = MCDisassembler::Success; 1880 1881 // imod == '01' --> UNPREDICTABLE 1882 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1883 // return failure here. The '01' imod value is unprintable, so there's 1884 // nothing useful we could do even if we returned UNPREDICTABLE. 1885 1886 if (imod == 1) return MCDisassembler::Fail; 1887 1888 if (imod && M) { 1889 Inst.setOpcode(ARM::CPS3p); 1890 Inst.addOperand(MCOperand::CreateImm(imod)); 1891 Inst.addOperand(MCOperand::CreateImm(iflags)); 1892 Inst.addOperand(MCOperand::CreateImm(mode)); 1893 } else if (imod && !M) { 1894 Inst.setOpcode(ARM::CPS2p); 1895 Inst.addOperand(MCOperand::CreateImm(imod)); 1896 Inst.addOperand(MCOperand::CreateImm(iflags)); 1897 if (mode) S = MCDisassembler::SoftFail; 1898 } else if (!imod && M) { 1899 Inst.setOpcode(ARM::CPS1p); 1900 Inst.addOperand(MCOperand::CreateImm(mode)); 1901 if (iflags) S = MCDisassembler::SoftFail; 1902 } else { 1903 // imod == '00' && M == '0' --> UNPREDICTABLE 1904 Inst.setOpcode(ARM::CPS1p); 1905 Inst.addOperand(MCOperand::CreateImm(mode)); 1906 S = MCDisassembler::SoftFail; 1907 } 1908 1909 return S; 1910 } 1911 1912 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1913 uint64_t Address, const void *Decoder) { 1914 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1915 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1916 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1917 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1918 1919 DecodeStatus S = MCDisassembler::Success; 1920 1921 // imod == '01' --> UNPREDICTABLE 1922 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1923 // return failure here. The '01' imod value is unprintable, so there's 1924 // nothing useful we could do even if we returned UNPREDICTABLE. 1925 1926 if (imod == 1) return MCDisassembler::Fail; 1927 1928 if (imod && M) { 1929 Inst.setOpcode(ARM::t2CPS3p); 1930 Inst.addOperand(MCOperand::CreateImm(imod)); 1931 Inst.addOperand(MCOperand::CreateImm(iflags)); 1932 Inst.addOperand(MCOperand::CreateImm(mode)); 1933 } else if (imod && !M) { 1934 Inst.setOpcode(ARM::t2CPS2p); 1935 Inst.addOperand(MCOperand::CreateImm(imod)); 1936 Inst.addOperand(MCOperand::CreateImm(iflags)); 1937 if (mode) S = MCDisassembler::SoftFail; 1938 } else if (!imod && M) { 1939 Inst.setOpcode(ARM::t2CPS1p); 1940 Inst.addOperand(MCOperand::CreateImm(mode)); 1941 if (iflags) S = MCDisassembler::SoftFail; 1942 } else { 1943 // imod == '00' && M == '0' --> UNPREDICTABLE 1944 Inst.setOpcode(ARM::t2CPS1p); 1945 Inst.addOperand(MCOperand::CreateImm(mode)); 1946 S = MCDisassembler::SoftFail; 1947 } 1948 1949 return S; 1950 } 1951 1952 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1953 uint64_t Address, const void *Decoder) { 1954 DecodeStatus S = MCDisassembler::Success; 1955 1956 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1957 unsigned imm = 0; 1958 1959 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1960 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1961 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1962 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1963 1964 if (Inst.getOpcode() == ARM::t2MOVTi16) 1965 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1966 return MCDisassembler::Fail; 1967 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 1970 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1971 Inst.addOperand(MCOperand::CreateImm(imm)); 1972 1973 return S; 1974 } 1975 1976 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1977 uint64_t Address, const void *Decoder) { 1978 DecodeStatus S = MCDisassembler::Success; 1979 1980 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1981 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1982 unsigned imm = 0; 1983 1984 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1985 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1986 1987 if (Inst.getOpcode() == ARM::MOVTi16) 1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1991 return MCDisassembler::Fail; 1992 1993 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1994 Inst.addOperand(MCOperand::CreateImm(imm)); 1995 1996 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1997 return MCDisassembler::Fail; 1998 1999 return S; 2000 } 2001 2002 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2003 uint64_t Address, const void *Decoder) { 2004 DecodeStatus S = MCDisassembler::Success; 2005 2006 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 2007 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 2008 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 2009 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 2010 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2011 2012 if (pred == 0xF) 2013 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2014 2015 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2016 return MCDisassembler::Fail; 2017 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2018 return MCDisassembler::Fail; 2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2020 return MCDisassembler::Fail; 2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2022 return MCDisassembler::Fail; 2023 2024 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2025 return MCDisassembler::Fail; 2026 2027 return S; 2028 } 2029 2030 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2031 uint64_t Address, const void *Decoder) { 2032 DecodeStatus S = MCDisassembler::Success; 2033 2034 unsigned add = fieldFromInstruction32(Val, 12, 1); 2035 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2036 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2037 2038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 2041 if (!add) imm *= -1; 2042 if (imm == 0 && !add) imm = INT32_MIN; 2043 Inst.addOperand(MCOperand::CreateImm(imm)); 2044 if (Rn == 15) 2045 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2046 2047 return S; 2048 } 2049 2050 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2051 uint64_t Address, const void *Decoder) { 2052 DecodeStatus S = MCDisassembler::Success; 2053 2054 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2055 unsigned U = fieldFromInstruction32(Val, 8, 1); 2056 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2057 2058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 2061 if (U) 2062 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2063 else 2064 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2065 2066 return S; 2067 } 2068 2069 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2070 uint64_t Address, const void *Decoder) { 2071 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2072 } 2073 2074 static DecodeStatus 2075 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2076 uint64_t Address, const void *Decoder) { 2077 DecodeStatus S = MCDisassembler::Success; 2078 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) | 2079 (fieldFromInstruction32(Insn, 11, 1) << 18) | 2080 (fieldFromInstruction32(Insn, 13, 1) << 17) | 2081 (fieldFromInstruction32(Insn, 16, 6) << 11) | 2082 (fieldFromInstruction32(Insn, 26, 1) << 19); 2083 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4, 2084 true, 4, Inst, Decoder)) 2085 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1))); 2086 return S; 2087 } 2088 2089 static DecodeStatus 2090 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2091 uint64_t Address, const void *Decoder) { 2092 DecodeStatus S = MCDisassembler::Success; 2093 2094 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2095 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2096 2097 if (pred == 0xF) { 2098 Inst.setOpcode(ARM::BLXi); 2099 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2100 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2101 true, 4, Inst, Decoder)) 2102 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2103 return S; 2104 } 2105 2106 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2107 true, 4, Inst, Decoder)) 2108 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 2112 return S; 2113 } 2114 2115 2116 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2117 uint64_t Address, const void *Decoder) { 2118 DecodeStatus S = MCDisassembler::Success; 2119 2120 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2121 unsigned align = fieldFromInstruction32(Val, 4, 2); 2122 2123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2124 return MCDisassembler::Fail; 2125 if (!align) 2126 Inst.addOperand(MCOperand::CreateImm(0)); 2127 else 2128 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2129 2130 return S; 2131 } 2132 2133 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2134 uint64_t Address, const void *Decoder) { 2135 DecodeStatus S = MCDisassembler::Success; 2136 2137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2139 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2140 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2141 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2142 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2143 2144 // First output register 2145 switch (Inst.getOpcode()) { 2146 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2147 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2148 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2149 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2150 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2151 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2152 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2153 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2154 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2155 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2156 return MCDisassembler::Fail; 2157 break; 2158 case ARM::VLD2b16: 2159 case ARM::VLD2b32: 2160 case ARM::VLD2b8: 2161 case ARM::VLD2b16wb_fixed: 2162 case ARM::VLD2b16wb_register: 2163 case ARM::VLD2b32wb_fixed: 2164 case ARM::VLD2b32wb_register: 2165 case ARM::VLD2b8wb_fixed: 2166 case ARM::VLD2b8wb_register: 2167 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2168 return MCDisassembler::Fail; 2169 break; 2170 default: 2171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 } 2174 2175 // Second output register 2176 switch (Inst.getOpcode()) { 2177 case ARM::VLD3d8: 2178 case ARM::VLD3d16: 2179 case ARM::VLD3d32: 2180 case ARM::VLD3d8_UPD: 2181 case ARM::VLD3d16_UPD: 2182 case ARM::VLD3d32_UPD: 2183 case ARM::VLD4d8: 2184 case ARM::VLD4d16: 2185 case ARM::VLD4d32: 2186 case ARM::VLD4d8_UPD: 2187 case ARM::VLD4d16_UPD: 2188 case ARM::VLD4d32_UPD: 2189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2190 return MCDisassembler::Fail; 2191 break; 2192 case ARM::VLD3q8: 2193 case ARM::VLD3q16: 2194 case ARM::VLD3q32: 2195 case ARM::VLD3q8_UPD: 2196 case ARM::VLD3q16_UPD: 2197 case ARM::VLD3q32_UPD: 2198 case ARM::VLD4q8: 2199 case ARM::VLD4q16: 2200 case ARM::VLD4q32: 2201 case ARM::VLD4q8_UPD: 2202 case ARM::VLD4q16_UPD: 2203 case ARM::VLD4q32_UPD: 2204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 default: 2207 break; 2208 } 2209 2210 // Third output register 2211 switch(Inst.getOpcode()) { 2212 case ARM::VLD3d8: 2213 case ARM::VLD3d16: 2214 case ARM::VLD3d32: 2215 case ARM::VLD3d8_UPD: 2216 case ARM::VLD3d16_UPD: 2217 case ARM::VLD3d32_UPD: 2218 case ARM::VLD4d8: 2219 case ARM::VLD4d16: 2220 case ARM::VLD4d32: 2221 case ARM::VLD4d8_UPD: 2222 case ARM::VLD4d16_UPD: 2223 case ARM::VLD4d32_UPD: 2224 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 break; 2227 case ARM::VLD3q8: 2228 case ARM::VLD3q16: 2229 case ARM::VLD3q32: 2230 case ARM::VLD3q8_UPD: 2231 case ARM::VLD3q16_UPD: 2232 case ARM::VLD3q32_UPD: 2233 case ARM::VLD4q8: 2234 case ARM::VLD4q16: 2235 case ARM::VLD4q32: 2236 case ARM::VLD4q8_UPD: 2237 case ARM::VLD4q16_UPD: 2238 case ARM::VLD4q32_UPD: 2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 break; 2242 default: 2243 break; 2244 } 2245 2246 // Fourth output register 2247 switch (Inst.getOpcode()) { 2248 case ARM::VLD4d8: 2249 case ARM::VLD4d16: 2250 case ARM::VLD4d32: 2251 case ARM::VLD4d8_UPD: 2252 case ARM::VLD4d16_UPD: 2253 case ARM::VLD4d32_UPD: 2254 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2255 return MCDisassembler::Fail; 2256 break; 2257 case ARM::VLD4q8: 2258 case ARM::VLD4q16: 2259 case ARM::VLD4q32: 2260 case ARM::VLD4q8_UPD: 2261 case ARM::VLD4q16_UPD: 2262 case ARM::VLD4q32_UPD: 2263 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2264 return MCDisassembler::Fail; 2265 break; 2266 default: 2267 break; 2268 } 2269 2270 // Writeback operand 2271 switch (Inst.getOpcode()) { 2272 case ARM::VLD1d8wb_fixed: 2273 case ARM::VLD1d16wb_fixed: 2274 case ARM::VLD1d32wb_fixed: 2275 case ARM::VLD1d64wb_fixed: 2276 case ARM::VLD1d8wb_register: 2277 case ARM::VLD1d16wb_register: 2278 case ARM::VLD1d32wb_register: 2279 case ARM::VLD1d64wb_register: 2280 case ARM::VLD1q8wb_fixed: 2281 case ARM::VLD1q16wb_fixed: 2282 case ARM::VLD1q32wb_fixed: 2283 case ARM::VLD1q64wb_fixed: 2284 case ARM::VLD1q8wb_register: 2285 case ARM::VLD1q16wb_register: 2286 case ARM::VLD1q32wb_register: 2287 case ARM::VLD1q64wb_register: 2288 case ARM::VLD1d8Twb_fixed: 2289 case ARM::VLD1d8Twb_register: 2290 case ARM::VLD1d16Twb_fixed: 2291 case ARM::VLD1d16Twb_register: 2292 case ARM::VLD1d32Twb_fixed: 2293 case ARM::VLD1d32Twb_register: 2294 case ARM::VLD1d64Twb_fixed: 2295 case ARM::VLD1d64Twb_register: 2296 case ARM::VLD1d8Qwb_fixed: 2297 case ARM::VLD1d8Qwb_register: 2298 case ARM::VLD1d16Qwb_fixed: 2299 case ARM::VLD1d16Qwb_register: 2300 case ARM::VLD1d32Qwb_fixed: 2301 case ARM::VLD1d32Qwb_register: 2302 case ARM::VLD1d64Qwb_fixed: 2303 case ARM::VLD1d64Qwb_register: 2304 case ARM::VLD2d8wb_fixed: 2305 case ARM::VLD2d16wb_fixed: 2306 case ARM::VLD2d32wb_fixed: 2307 case ARM::VLD2q8wb_fixed: 2308 case ARM::VLD2q16wb_fixed: 2309 case ARM::VLD2q32wb_fixed: 2310 case ARM::VLD2d8wb_register: 2311 case ARM::VLD2d16wb_register: 2312 case ARM::VLD2d32wb_register: 2313 case ARM::VLD2q8wb_register: 2314 case ARM::VLD2q16wb_register: 2315 case ARM::VLD2q32wb_register: 2316 case ARM::VLD2b8wb_fixed: 2317 case ARM::VLD2b16wb_fixed: 2318 case ARM::VLD2b32wb_fixed: 2319 case ARM::VLD2b8wb_register: 2320 case ARM::VLD2b16wb_register: 2321 case ARM::VLD2b32wb_register: 2322 Inst.addOperand(MCOperand::CreateImm(0)); 2323 break; 2324 case ARM::VLD3d8_UPD: 2325 case ARM::VLD3d16_UPD: 2326 case ARM::VLD3d32_UPD: 2327 case ARM::VLD3q8_UPD: 2328 case ARM::VLD3q16_UPD: 2329 case ARM::VLD3q32_UPD: 2330 case ARM::VLD4d8_UPD: 2331 case ARM::VLD4d16_UPD: 2332 case ARM::VLD4d32_UPD: 2333 case ARM::VLD4q8_UPD: 2334 case ARM::VLD4q16_UPD: 2335 case ARM::VLD4q32_UPD: 2336 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2337 return MCDisassembler::Fail; 2338 break; 2339 default: 2340 break; 2341 } 2342 2343 // AddrMode6 Base (register+alignment) 2344 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2345 return MCDisassembler::Fail; 2346 2347 // AddrMode6 Offset (register) 2348 switch (Inst.getOpcode()) { 2349 default: 2350 // The below have been updated to have explicit am6offset split 2351 // between fixed and register offset. For those instructions not 2352 // yet updated, we need to add an additional reg0 operand for the 2353 // fixed variant. 2354 // 2355 // The fixed offset encodes as Rm == 0xd, so we check for that. 2356 if (Rm == 0xd) { 2357 Inst.addOperand(MCOperand::CreateReg(0)); 2358 break; 2359 } 2360 // Fall through to handle the register offset variant. 2361 case ARM::VLD1d8wb_fixed: 2362 case ARM::VLD1d16wb_fixed: 2363 case ARM::VLD1d32wb_fixed: 2364 case ARM::VLD1d64wb_fixed: 2365 case ARM::VLD1d8Twb_fixed: 2366 case ARM::VLD1d16Twb_fixed: 2367 case ARM::VLD1d32Twb_fixed: 2368 case ARM::VLD1d64Twb_fixed: 2369 case ARM::VLD1d8Qwb_fixed: 2370 case ARM::VLD1d16Qwb_fixed: 2371 case ARM::VLD1d32Qwb_fixed: 2372 case ARM::VLD1d64Qwb_fixed: 2373 case ARM::VLD1d8wb_register: 2374 case ARM::VLD1d16wb_register: 2375 case ARM::VLD1d32wb_register: 2376 case ARM::VLD1d64wb_register: 2377 case ARM::VLD1q8wb_fixed: 2378 case ARM::VLD1q16wb_fixed: 2379 case ARM::VLD1q32wb_fixed: 2380 case ARM::VLD1q64wb_fixed: 2381 case ARM::VLD1q8wb_register: 2382 case ARM::VLD1q16wb_register: 2383 case ARM::VLD1q32wb_register: 2384 case ARM::VLD1q64wb_register: 2385 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2386 // variant encodes Rm == 0xf. Anything else is a register offset post- 2387 // increment and we need to add the register operand to the instruction. 2388 if (Rm != 0xD && Rm != 0xF && 2389 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2390 return MCDisassembler::Fail; 2391 break; 2392 case ARM::VLD2d8wb_fixed: 2393 case ARM::VLD2d16wb_fixed: 2394 case ARM::VLD2d32wb_fixed: 2395 case ARM::VLD2b8wb_fixed: 2396 case ARM::VLD2b16wb_fixed: 2397 case ARM::VLD2b32wb_fixed: 2398 case ARM::VLD2q8wb_fixed: 2399 case ARM::VLD2q16wb_fixed: 2400 case ARM::VLD2q32wb_fixed: 2401 break; 2402 } 2403 2404 return S; 2405 } 2406 2407 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2408 uint64_t Address, const void *Decoder) { 2409 DecodeStatus S = MCDisassembler::Success; 2410 2411 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2412 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2413 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2414 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2415 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2416 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2417 2418 // Writeback Operand 2419 switch (Inst.getOpcode()) { 2420 case ARM::VST1d8wb_fixed: 2421 case ARM::VST1d16wb_fixed: 2422 case ARM::VST1d32wb_fixed: 2423 case ARM::VST1d64wb_fixed: 2424 case ARM::VST1d8wb_register: 2425 case ARM::VST1d16wb_register: 2426 case ARM::VST1d32wb_register: 2427 case ARM::VST1d64wb_register: 2428 case ARM::VST1q8wb_fixed: 2429 case ARM::VST1q16wb_fixed: 2430 case ARM::VST1q32wb_fixed: 2431 case ARM::VST1q64wb_fixed: 2432 case ARM::VST1q8wb_register: 2433 case ARM::VST1q16wb_register: 2434 case ARM::VST1q32wb_register: 2435 case ARM::VST1q64wb_register: 2436 case ARM::VST1d8Twb_fixed: 2437 case ARM::VST1d16Twb_fixed: 2438 case ARM::VST1d32Twb_fixed: 2439 case ARM::VST1d64Twb_fixed: 2440 case ARM::VST1d8Twb_register: 2441 case ARM::VST1d16Twb_register: 2442 case ARM::VST1d32Twb_register: 2443 case ARM::VST1d64Twb_register: 2444 case ARM::VST1d8Qwb_fixed: 2445 case ARM::VST1d16Qwb_fixed: 2446 case ARM::VST1d32Qwb_fixed: 2447 case ARM::VST1d64Qwb_fixed: 2448 case ARM::VST1d8Qwb_register: 2449 case ARM::VST1d16Qwb_register: 2450 case ARM::VST1d32Qwb_register: 2451 case ARM::VST1d64Qwb_register: 2452 case ARM::VST2d8wb_fixed: 2453 case ARM::VST2d16wb_fixed: 2454 case ARM::VST2d32wb_fixed: 2455 case ARM::VST2d8wb_register: 2456 case ARM::VST2d16wb_register: 2457 case ARM::VST2d32wb_register: 2458 case ARM::VST2q8wb_fixed: 2459 case ARM::VST2q16wb_fixed: 2460 case ARM::VST2q32wb_fixed: 2461 case ARM::VST2q8wb_register: 2462 case ARM::VST2q16wb_register: 2463 case ARM::VST2q32wb_register: 2464 case ARM::VST2b8wb_fixed: 2465 case ARM::VST2b16wb_fixed: 2466 case ARM::VST2b32wb_fixed: 2467 case ARM::VST2b8wb_register: 2468 case ARM::VST2b16wb_register: 2469 case ARM::VST2b32wb_register: 2470 if (Rm == 0xF) 2471 return MCDisassembler::Fail; 2472 Inst.addOperand(MCOperand::CreateImm(0)); 2473 break; 2474 case ARM::VST3d8_UPD: 2475 case ARM::VST3d16_UPD: 2476 case ARM::VST3d32_UPD: 2477 case ARM::VST3q8_UPD: 2478 case ARM::VST3q16_UPD: 2479 case ARM::VST3q32_UPD: 2480 case ARM::VST4d8_UPD: 2481 case ARM::VST4d16_UPD: 2482 case ARM::VST4d32_UPD: 2483 case ARM::VST4q8_UPD: 2484 case ARM::VST4q16_UPD: 2485 case ARM::VST4q32_UPD: 2486 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2487 return MCDisassembler::Fail; 2488 break; 2489 default: 2490 break; 2491 } 2492 2493 // AddrMode6 Base (register+alignment) 2494 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2495 return MCDisassembler::Fail; 2496 2497 // AddrMode6 Offset (register) 2498 switch (Inst.getOpcode()) { 2499 default: 2500 if (Rm == 0xD) 2501 Inst.addOperand(MCOperand::CreateReg(0)); 2502 else if (Rm != 0xF) { 2503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2504 return MCDisassembler::Fail; 2505 } 2506 break; 2507 case ARM::VST1d8wb_fixed: 2508 case ARM::VST1d16wb_fixed: 2509 case ARM::VST1d32wb_fixed: 2510 case ARM::VST1d64wb_fixed: 2511 case ARM::VST1q8wb_fixed: 2512 case ARM::VST1q16wb_fixed: 2513 case ARM::VST1q32wb_fixed: 2514 case ARM::VST1q64wb_fixed: 2515 case ARM::VST1d8Twb_fixed: 2516 case ARM::VST1d16Twb_fixed: 2517 case ARM::VST1d32Twb_fixed: 2518 case ARM::VST1d64Twb_fixed: 2519 case ARM::VST1d8Qwb_fixed: 2520 case ARM::VST1d16Qwb_fixed: 2521 case ARM::VST1d32Qwb_fixed: 2522 case ARM::VST1d64Qwb_fixed: 2523 case ARM::VST2d8wb_fixed: 2524 case ARM::VST2d16wb_fixed: 2525 case ARM::VST2d32wb_fixed: 2526 case ARM::VST2q8wb_fixed: 2527 case ARM::VST2q16wb_fixed: 2528 case ARM::VST2q32wb_fixed: 2529 case ARM::VST2b8wb_fixed: 2530 case ARM::VST2b16wb_fixed: 2531 case ARM::VST2b32wb_fixed: 2532 break; 2533 } 2534 2535 2536 // First input register 2537 switch (Inst.getOpcode()) { 2538 case ARM::VST1q16: 2539 case ARM::VST1q32: 2540 case ARM::VST1q64: 2541 case ARM::VST1q8: 2542 case ARM::VST1q16wb_fixed: 2543 case ARM::VST1q16wb_register: 2544 case ARM::VST1q32wb_fixed: 2545 case ARM::VST1q32wb_register: 2546 case ARM::VST1q64wb_fixed: 2547 case ARM::VST1q64wb_register: 2548 case ARM::VST1q8wb_fixed: 2549 case ARM::VST1q8wb_register: 2550 case ARM::VST2d16: 2551 case ARM::VST2d32: 2552 case ARM::VST2d8: 2553 case ARM::VST2d16wb_fixed: 2554 case ARM::VST2d16wb_register: 2555 case ARM::VST2d32wb_fixed: 2556 case ARM::VST2d32wb_register: 2557 case ARM::VST2d8wb_fixed: 2558 case ARM::VST2d8wb_register: 2559 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2560 return MCDisassembler::Fail; 2561 break; 2562 case ARM::VST2b16: 2563 case ARM::VST2b32: 2564 case ARM::VST2b8: 2565 case ARM::VST2b16wb_fixed: 2566 case ARM::VST2b16wb_register: 2567 case ARM::VST2b32wb_fixed: 2568 case ARM::VST2b32wb_register: 2569 case ARM::VST2b8wb_fixed: 2570 case ARM::VST2b8wb_register: 2571 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2572 return MCDisassembler::Fail; 2573 break; 2574 default: 2575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 } 2578 2579 // Second input register 2580 switch (Inst.getOpcode()) { 2581 case ARM::VST3d8: 2582 case ARM::VST3d16: 2583 case ARM::VST3d32: 2584 case ARM::VST3d8_UPD: 2585 case ARM::VST3d16_UPD: 2586 case ARM::VST3d32_UPD: 2587 case ARM::VST4d8: 2588 case ARM::VST4d16: 2589 case ARM::VST4d32: 2590 case ARM::VST4d8_UPD: 2591 case ARM::VST4d16_UPD: 2592 case ARM::VST4d32_UPD: 2593 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2594 return MCDisassembler::Fail; 2595 break; 2596 case ARM::VST3q8: 2597 case ARM::VST3q16: 2598 case ARM::VST3q32: 2599 case ARM::VST3q8_UPD: 2600 case ARM::VST3q16_UPD: 2601 case ARM::VST3q32_UPD: 2602 case ARM::VST4q8: 2603 case ARM::VST4q16: 2604 case ARM::VST4q32: 2605 case ARM::VST4q8_UPD: 2606 case ARM::VST4q16_UPD: 2607 case ARM::VST4q32_UPD: 2608 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2609 return MCDisassembler::Fail; 2610 break; 2611 default: 2612 break; 2613 } 2614 2615 // Third input register 2616 switch (Inst.getOpcode()) { 2617 case ARM::VST3d8: 2618 case ARM::VST3d16: 2619 case ARM::VST3d32: 2620 case ARM::VST3d8_UPD: 2621 case ARM::VST3d16_UPD: 2622 case ARM::VST3d32_UPD: 2623 case ARM::VST4d8: 2624 case ARM::VST4d16: 2625 case ARM::VST4d32: 2626 case ARM::VST4d8_UPD: 2627 case ARM::VST4d16_UPD: 2628 case ARM::VST4d32_UPD: 2629 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2630 return MCDisassembler::Fail; 2631 break; 2632 case ARM::VST3q8: 2633 case ARM::VST3q16: 2634 case ARM::VST3q32: 2635 case ARM::VST3q8_UPD: 2636 case ARM::VST3q16_UPD: 2637 case ARM::VST3q32_UPD: 2638 case ARM::VST4q8: 2639 case ARM::VST4q16: 2640 case ARM::VST4q32: 2641 case ARM::VST4q8_UPD: 2642 case ARM::VST4q16_UPD: 2643 case ARM::VST4q32_UPD: 2644 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2645 return MCDisassembler::Fail; 2646 break; 2647 default: 2648 break; 2649 } 2650 2651 // Fourth input register 2652 switch (Inst.getOpcode()) { 2653 case ARM::VST4d8: 2654 case ARM::VST4d16: 2655 case ARM::VST4d32: 2656 case ARM::VST4d8_UPD: 2657 case ARM::VST4d16_UPD: 2658 case ARM::VST4d32_UPD: 2659 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2660 return MCDisassembler::Fail; 2661 break; 2662 case ARM::VST4q8: 2663 case ARM::VST4q16: 2664 case ARM::VST4q32: 2665 case ARM::VST4q8_UPD: 2666 case ARM::VST4q16_UPD: 2667 case ARM::VST4q32_UPD: 2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2669 return MCDisassembler::Fail; 2670 break; 2671 default: 2672 break; 2673 } 2674 2675 return S; 2676 } 2677 2678 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2679 uint64_t Address, const void *Decoder) { 2680 DecodeStatus S = MCDisassembler::Success; 2681 2682 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2683 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2684 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2685 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2686 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2687 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2688 2689 align *= (1 << size); 2690 2691 switch (Inst.getOpcode()) { 2692 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2693 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2694 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2695 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2696 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 break; 2699 default: 2700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 break; 2703 } 2704 if (Rm != 0xF) { 2705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2706 return MCDisassembler::Fail; 2707 } 2708 2709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2710 return MCDisassembler::Fail; 2711 Inst.addOperand(MCOperand::CreateImm(align)); 2712 2713 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2714 // variant encodes Rm == 0xf. Anything else is a register offset post- 2715 // increment and we need to add the register operand to the instruction. 2716 if (Rm != 0xD && Rm != 0xF && 2717 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 2720 return S; 2721 } 2722 2723 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2724 uint64_t Address, const void *Decoder) { 2725 DecodeStatus S = MCDisassembler::Success; 2726 2727 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2728 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2729 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2730 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2731 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2732 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2733 align *= 2*size; 2734 2735 switch (Inst.getOpcode()) { 2736 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2737 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2738 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2739 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2740 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 break; 2743 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2744 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2745 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2746 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2747 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 break; 2750 default: 2751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 break; 2754 } 2755 2756 if (Rm != 0xF) 2757 Inst.addOperand(MCOperand::CreateImm(0)); 2758 2759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2760 return MCDisassembler::Fail; 2761 Inst.addOperand(MCOperand::CreateImm(align)); 2762 2763 if (Rm != 0xD && Rm != 0xF) { 2764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2765 return MCDisassembler::Fail; 2766 } 2767 2768 return S; 2769 } 2770 2771 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2772 uint64_t Address, const void *Decoder) { 2773 DecodeStatus S = MCDisassembler::Success; 2774 2775 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2776 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2777 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2778 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2779 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2780 2781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 if (Rm != 0xF) { 2788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 } 2791 2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 Inst.addOperand(MCOperand::CreateImm(0)); 2795 2796 if (Rm == 0xD) 2797 Inst.addOperand(MCOperand::CreateReg(0)); 2798 else if (Rm != 0xF) { 2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 } 2802 2803 return S; 2804 } 2805 2806 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2807 uint64_t Address, const void *Decoder) { 2808 DecodeStatus S = MCDisassembler::Success; 2809 2810 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2811 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2812 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2813 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2814 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2815 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2816 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2817 2818 if (size == 0x3) { 2819 size = 4; 2820 align = 16; 2821 } else { 2822 if (size == 2) { 2823 size = 1 << size; 2824 align *= 8; 2825 } else { 2826 size = 1 << size; 2827 align *= 4*size; 2828 } 2829 } 2830 2831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2832 return MCDisassembler::Fail; 2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2838 return MCDisassembler::Fail; 2839 if (Rm != 0xF) { 2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2841 return MCDisassembler::Fail; 2842 } 2843 2844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2845 return MCDisassembler::Fail; 2846 Inst.addOperand(MCOperand::CreateImm(align)); 2847 2848 if (Rm == 0xD) 2849 Inst.addOperand(MCOperand::CreateReg(0)); 2850 else if (Rm != 0xF) { 2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2852 return MCDisassembler::Fail; 2853 } 2854 2855 return S; 2856 } 2857 2858 static DecodeStatus 2859 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2860 uint64_t Address, const void *Decoder) { 2861 DecodeStatus S = MCDisassembler::Success; 2862 2863 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2864 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2865 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2866 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2867 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2868 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2869 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2870 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2871 2872 if (Q) { 2873 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2874 return MCDisassembler::Fail; 2875 } else { 2876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 } 2879 2880 Inst.addOperand(MCOperand::CreateImm(imm)); 2881 2882 switch (Inst.getOpcode()) { 2883 case ARM::VORRiv4i16: 2884 case ARM::VORRiv2i32: 2885 case ARM::VBICiv4i16: 2886 case ARM::VBICiv2i32: 2887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 break; 2890 case ARM::VORRiv8i16: 2891 case ARM::VORRiv4i32: 2892 case ARM::VBICiv8i16: 2893 case ARM::VBICiv4i32: 2894 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 break; 2897 default: 2898 break; 2899 } 2900 2901 return S; 2902 } 2903 2904 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2905 uint64_t Address, const void *Decoder) { 2906 DecodeStatus S = MCDisassembler::Success; 2907 2908 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2909 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2910 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2911 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2912 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2913 2914 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2915 return MCDisassembler::Fail; 2916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2919 2920 return S; 2921 } 2922 2923 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2924 uint64_t Address, const void *Decoder) { 2925 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2926 return MCDisassembler::Success; 2927 } 2928 2929 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2930 uint64_t Address, const void *Decoder) { 2931 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2932 return MCDisassembler::Success; 2933 } 2934 2935 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2936 uint64_t Address, const void *Decoder) { 2937 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2938 return MCDisassembler::Success; 2939 } 2940 2941 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2942 uint64_t Address, const void *Decoder) { 2943 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2944 return MCDisassembler::Success; 2945 } 2946 2947 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2948 uint64_t Address, const void *Decoder) { 2949 DecodeStatus S = MCDisassembler::Success; 2950 2951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2953 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2954 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2955 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2956 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2957 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2958 2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 if (op) { 2962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2963 return MCDisassembler::Fail; // Writeback 2964 } 2965 2966 switch (Inst.getOpcode()) { 2967 case ARM::VTBL2: 2968 case ARM::VTBX2: 2969 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2970 return MCDisassembler::Fail; 2971 break; 2972 default: 2973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2974 return MCDisassembler::Fail; 2975 } 2976 2977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 2980 return S; 2981 } 2982 2983 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2984 uint64_t Address, const void *Decoder) { 2985 DecodeStatus S = MCDisassembler::Success; 2986 2987 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2988 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2989 2990 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 2993 switch(Inst.getOpcode()) { 2994 default: 2995 return MCDisassembler::Fail; 2996 case ARM::tADR: 2997 break; // tADR does not explicitly represent the PC as an operand. 2998 case ARM::tADDrSPi: 2999 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3000 break; 3001 } 3002 3003 Inst.addOperand(MCOperand::CreateImm(imm)); 3004 return S; 3005 } 3006 3007 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3008 uint64_t Address, const void *Decoder) { 3009 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3010 true, 2, Inst, Decoder)) 3011 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3012 return MCDisassembler::Success; 3013 } 3014 3015 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3016 uint64_t Address, const void *Decoder) { 3017 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3018 true, 4, Inst, Decoder)) 3019 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3020 return MCDisassembler::Success; 3021 } 3022 3023 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3024 uint64_t Address, const void *Decoder) { 3025 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 3026 true, 2, Inst, Decoder)) 3027 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 3028 return MCDisassembler::Success; 3029 } 3030 3031 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3032 uint64_t Address, const void *Decoder) { 3033 DecodeStatus S = MCDisassembler::Success; 3034 3035 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 3036 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 3037 3038 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3039 return MCDisassembler::Fail; 3040 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3041 return MCDisassembler::Fail; 3042 3043 return S; 3044 } 3045 3046 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3047 uint64_t Address, const void *Decoder) { 3048 DecodeStatus S = MCDisassembler::Success; 3049 3050 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 3051 unsigned imm = fieldFromInstruction32(Val, 3, 5); 3052 3053 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 Inst.addOperand(MCOperand::CreateImm(imm)); 3056 3057 return S; 3058 } 3059 3060 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3061 uint64_t Address, const void *Decoder) { 3062 unsigned imm = Val << 2; 3063 3064 Inst.addOperand(MCOperand::CreateImm(imm)); 3065 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3066 3067 return MCDisassembler::Success; 3068 } 3069 3070 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3071 uint64_t Address, const void *Decoder) { 3072 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3073 Inst.addOperand(MCOperand::CreateImm(Val)); 3074 3075 return MCDisassembler::Success; 3076 } 3077 3078 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3079 uint64_t Address, const void *Decoder) { 3080 DecodeStatus S = MCDisassembler::Success; 3081 3082 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3083 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3084 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3085 3086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3087 return MCDisassembler::Fail; 3088 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 Inst.addOperand(MCOperand::CreateImm(imm)); 3091 3092 return S; 3093 } 3094 3095 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3096 uint64_t Address, const void *Decoder) { 3097 DecodeStatus S = MCDisassembler::Success; 3098 3099 switch (Inst.getOpcode()) { 3100 case ARM::t2PLDs: 3101 case ARM::t2PLDWs: 3102 case ARM::t2PLIs: 3103 break; 3104 default: { 3105 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3106 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3107 return MCDisassembler::Fail; 3108 } 3109 } 3110 3111 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3112 if (Rn == 0xF) { 3113 switch (Inst.getOpcode()) { 3114 case ARM::t2LDRBs: 3115 Inst.setOpcode(ARM::t2LDRBpci); 3116 break; 3117 case ARM::t2LDRHs: 3118 Inst.setOpcode(ARM::t2LDRHpci); 3119 break; 3120 case ARM::t2LDRSHs: 3121 Inst.setOpcode(ARM::t2LDRSHpci); 3122 break; 3123 case ARM::t2LDRSBs: 3124 Inst.setOpcode(ARM::t2LDRSBpci); 3125 break; 3126 case ARM::t2PLDs: 3127 Inst.setOpcode(ARM::t2PLDi12); 3128 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3129 break; 3130 default: 3131 return MCDisassembler::Fail; 3132 } 3133 3134 int imm = fieldFromInstruction32(Insn, 0, 12); 3135 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3136 Inst.addOperand(MCOperand::CreateImm(imm)); 3137 3138 return S; 3139 } 3140 3141 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3142 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3143 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3144 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3145 return MCDisassembler::Fail; 3146 3147 return S; 3148 } 3149 3150 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3151 uint64_t Address, const void *Decoder) { 3152 int imm = Val & 0xFF; 3153 if (!(Val & 0x100)) imm *= -1; 3154 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3155 3156 return MCDisassembler::Success; 3157 } 3158 3159 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3160 uint64_t Address, const void *Decoder) { 3161 DecodeStatus S = MCDisassembler::Success; 3162 3163 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3164 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3165 3166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3167 return MCDisassembler::Fail; 3168 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 3171 return S; 3172 } 3173 3174 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3175 uint64_t Address, const void *Decoder) { 3176 DecodeStatus S = MCDisassembler::Success; 3177 3178 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3179 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3180 3181 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 3184 Inst.addOperand(MCOperand::CreateImm(imm)); 3185 3186 return S; 3187 } 3188 3189 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3190 uint64_t Address, const void *Decoder) { 3191 int imm = Val & 0xFF; 3192 if (Val == 0) 3193 imm = INT32_MIN; 3194 else if (!(Val & 0x100)) 3195 imm *= -1; 3196 Inst.addOperand(MCOperand::CreateImm(imm)); 3197 3198 return MCDisassembler::Success; 3199 } 3200 3201 3202 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3203 uint64_t Address, const void *Decoder) { 3204 DecodeStatus S = MCDisassembler::Success; 3205 3206 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3207 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3208 3209 // Some instructions always use an additive offset. 3210 switch (Inst.getOpcode()) { 3211 case ARM::t2LDRT: 3212 case ARM::t2LDRBT: 3213 case ARM::t2LDRHT: 3214 case ARM::t2LDRSBT: 3215 case ARM::t2LDRSHT: 3216 case ARM::t2STRT: 3217 case ARM::t2STRBT: 3218 case ARM::t2STRHT: 3219 imm |= 0x100; 3220 break; 3221 default: 3222 break; 3223 } 3224 3225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 3230 return S; 3231 } 3232 3233 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3234 uint64_t Address, const void *Decoder) { 3235 DecodeStatus S = MCDisassembler::Success; 3236 3237 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3238 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3239 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3240 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3241 addr |= Rn << 9; 3242 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3243 3244 if (!load) { 3245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 } 3248 3249 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3250 return MCDisassembler::Fail; 3251 3252 if (load) { 3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3254 return MCDisassembler::Fail; 3255 } 3256 3257 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 3260 return S; 3261 } 3262 3263 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3264 uint64_t Address, const void *Decoder) { 3265 DecodeStatus S = MCDisassembler::Success; 3266 3267 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3268 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3269 3270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3271 return MCDisassembler::Fail; 3272 Inst.addOperand(MCOperand::CreateImm(imm)); 3273 3274 return S; 3275 } 3276 3277 3278 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3279 uint64_t Address, const void *Decoder) { 3280 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3281 3282 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3283 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3284 Inst.addOperand(MCOperand::CreateImm(imm)); 3285 3286 return MCDisassembler::Success; 3287 } 3288 3289 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3290 uint64_t Address, const void *Decoder) { 3291 DecodeStatus S = MCDisassembler::Success; 3292 3293 if (Inst.getOpcode() == ARM::tADDrSP) { 3294 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3295 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3296 3297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3301 return MCDisassembler::Fail; 3302 } else if (Inst.getOpcode() == ARM::tADDspr) { 3303 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3304 3305 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3306 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 } 3310 3311 return S; 3312 } 3313 3314 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3315 uint64_t Address, const void *Decoder) { 3316 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3317 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3318 3319 Inst.addOperand(MCOperand::CreateImm(imod)); 3320 Inst.addOperand(MCOperand::CreateImm(flags)); 3321 3322 return MCDisassembler::Success; 3323 } 3324 3325 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3326 uint64_t Address, const void *Decoder) { 3327 DecodeStatus S = MCDisassembler::Success; 3328 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3329 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3330 3331 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 Inst.addOperand(MCOperand::CreateImm(add)); 3334 3335 return S; 3336 } 3337 3338 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3339 uint64_t Address, const void *Decoder) { 3340 if (!tryAddingSymbolicOperand(Address, 3341 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3342 true, 4, Inst, Decoder)) 3343 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3344 return MCDisassembler::Success; 3345 } 3346 3347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3348 uint64_t Address, const void *Decoder) { 3349 if (Val == 0xA || Val == 0xB) 3350 return MCDisassembler::Fail; 3351 3352 Inst.addOperand(MCOperand::CreateImm(Val)); 3353 return MCDisassembler::Success; 3354 } 3355 3356 static DecodeStatus 3357 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3358 uint64_t Address, const void *Decoder) { 3359 DecodeStatus S = MCDisassembler::Success; 3360 3361 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3362 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3363 3364 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 return S; 3370 } 3371 3372 static DecodeStatus 3373 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3374 uint64_t Address, const void *Decoder) { 3375 DecodeStatus S = MCDisassembler::Success; 3376 3377 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3378 if (pred == 0xE || pred == 0xF) { 3379 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3380 switch (opc) { 3381 default: 3382 return MCDisassembler::Fail; 3383 case 0xf3bf8f4: 3384 Inst.setOpcode(ARM::t2DSB); 3385 break; 3386 case 0xf3bf8f5: 3387 Inst.setOpcode(ARM::t2DMB); 3388 break; 3389 case 0xf3bf8f6: 3390 Inst.setOpcode(ARM::t2ISB); 3391 break; 3392 } 3393 3394 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3395 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3396 } 3397 3398 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3399 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3400 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3401 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3402 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3403 3404 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3405 return MCDisassembler::Fail; 3406 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3407 return MCDisassembler::Fail; 3408 3409 return S; 3410 } 3411 3412 // Decode a shifted immediate operand. These basically consist 3413 // of an 8-bit value, and a 4-bit directive that specifies either 3414 // a splat operation or a rotation. 3415 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3416 uint64_t Address, const void *Decoder) { 3417 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3418 if (ctrl == 0) { 3419 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3420 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3421 switch (byte) { 3422 case 0: 3423 Inst.addOperand(MCOperand::CreateImm(imm)); 3424 break; 3425 case 1: 3426 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3427 break; 3428 case 2: 3429 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3430 break; 3431 case 3: 3432 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3433 (imm << 8) | imm)); 3434 break; 3435 } 3436 } else { 3437 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3438 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3439 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3440 Inst.addOperand(MCOperand::CreateImm(imm)); 3441 } 3442 3443 return MCDisassembler::Success; 3444 } 3445 3446 static DecodeStatus 3447 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3448 uint64_t Address, const void *Decoder){ 3449 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4, 3450 true, 2, Inst, Decoder)) 3451 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1))); 3452 return MCDisassembler::Success; 3453 } 3454 3455 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3456 uint64_t Address, const void *Decoder){ 3457 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3458 true, 4, Inst, Decoder)) 3459 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3460 return MCDisassembler::Success; 3461 } 3462 3463 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3464 uint64_t Address, const void *Decoder) { 3465 switch (Val) { 3466 default: 3467 return MCDisassembler::Fail; 3468 case 0xF: // SY 3469 case 0xE: // ST 3470 case 0xB: // ISH 3471 case 0xA: // ISHST 3472 case 0x7: // NSH 3473 case 0x6: // NSHST 3474 case 0x3: // OSH 3475 case 0x2: // OSHST 3476 break; 3477 } 3478 3479 Inst.addOperand(MCOperand::CreateImm(Val)); 3480 return MCDisassembler::Success; 3481 } 3482 3483 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3484 uint64_t Address, const void *Decoder) { 3485 if (!Val) return MCDisassembler::Fail; 3486 Inst.addOperand(MCOperand::CreateImm(Val)); 3487 return MCDisassembler::Success; 3488 } 3489 3490 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3491 uint64_t Address, const void *Decoder) { 3492 DecodeStatus S = MCDisassembler::Success; 3493 3494 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3495 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3496 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3497 3498 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3499 3500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3501 return MCDisassembler::Fail; 3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3505 return MCDisassembler::Fail; 3506 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3507 return MCDisassembler::Fail; 3508 3509 return S; 3510 } 3511 3512 3513 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3514 uint64_t Address, const void *Decoder){ 3515 DecodeStatus S = MCDisassembler::Success; 3516 3517 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3518 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3519 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3520 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3521 3522 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 3525 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3526 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3527 3528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3529 return MCDisassembler::Fail; 3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3533 return MCDisassembler::Fail; 3534 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 3537 return S; 3538 } 3539 3540 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3541 uint64_t Address, const void *Decoder) { 3542 DecodeStatus S = MCDisassembler::Success; 3543 3544 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3545 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3546 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3547 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3548 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3549 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3550 3551 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3552 3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3554 return MCDisassembler::Fail; 3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 3562 return S; 3563 } 3564 3565 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3566 uint64_t Address, const void *Decoder) { 3567 DecodeStatus S = MCDisassembler::Success; 3568 3569 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3570 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3571 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3572 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3573 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3574 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3576 3577 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3578 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3579 3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3581 return MCDisassembler::Fail; 3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3585 return MCDisassembler::Fail; 3586 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3587 return MCDisassembler::Fail; 3588 3589 return S; 3590 } 3591 3592 3593 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3594 uint64_t Address, const void *Decoder) { 3595 DecodeStatus S = MCDisassembler::Success; 3596 3597 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3598 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3599 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3600 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3601 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3602 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3603 3604 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3605 3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3611 return MCDisassembler::Fail; 3612 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 3615 return S; 3616 } 3617 3618 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3619 uint64_t Address, const void *Decoder) { 3620 DecodeStatus S = MCDisassembler::Success; 3621 3622 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3623 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3624 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3625 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3626 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3627 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3628 3629 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3630 3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 3640 return S; 3641 } 3642 3643 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3644 uint64_t Address, const void *Decoder) { 3645 DecodeStatus S = MCDisassembler::Success; 3646 3647 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3648 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3649 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3650 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3651 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3652 3653 unsigned align = 0; 3654 unsigned index = 0; 3655 switch (size) { 3656 default: 3657 return MCDisassembler::Fail; 3658 case 0: 3659 if (fieldFromInstruction32(Insn, 4, 1)) 3660 return MCDisassembler::Fail; // UNDEFINED 3661 index = fieldFromInstruction32(Insn, 5, 3); 3662 break; 3663 case 1: 3664 if (fieldFromInstruction32(Insn, 5, 1)) 3665 return MCDisassembler::Fail; // UNDEFINED 3666 index = fieldFromInstruction32(Insn, 6, 2); 3667 if (fieldFromInstruction32(Insn, 4, 1)) 3668 align = 2; 3669 break; 3670 case 2: 3671 if (fieldFromInstruction32(Insn, 6, 1)) 3672 return MCDisassembler::Fail; // UNDEFINED 3673 index = fieldFromInstruction32(Insn, 7, 1); 3674 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3675 align = 4; 3676 } 3677 3678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3679 return MCDisassembler::Fail; 3680 if (Rm != 0xF) { // Writeback 3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3682 return MCDisassembler::Fail; 3683 } 3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 Inst.addOperand(MCOperand::CreateImm(align)); 3687 if (Rm != 0xF) { 3688 if (Rm != 0xD) { 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 } else 3692 Inst.addOperand(MCOperand::CreateReg(0)); 3693 } 3694 3695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 Inst.addOperand(MCOperand::CreateImm(index)); 3698 3699 return S; 3700 } 3701 3702 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3703 uint64_t Address, const void *Decoder) { 3704 DecodeStatus S = MCDisassembler::Success; 3705 3706 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3707 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3708 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3709 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3710 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3711 3712 unsigned align = 0; 3713 unsigned index = 0; 3714 switch (size) { 3715 default: 3716 return MCDisassembler::Fail; 3717 case 0: 3718 if (fieldFromInstruction32(Insn, 4, 1)) 3719 return MCDisassembler::Fail; // UNDEFINED 3720 index = fieldFromInstruction32(Insn, 5, 3); 3721 break; 3722 case 1: 3723 if (fieldFromInstruction32(Insn, 5, 1)) 3724 return MCDisassembler::Fail; // UNDEFINED 3725 index = fieldFromInstruction32(Insn, 6, 2); 3726 if (fieldFromInstruction32(Insn, 4, 1)) 3727 align = 2; 3728 break; 3729 case 2: 3730 if (fieldFromInstruction32(Insn, 6, 1)) 3731 return MCDisassembler::Fail; // UNDEFINED 3732 index = fieldFromInstruction32(Insn, 7, 1); 3733 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3734 align = 4; 3735 } 3736 3737 if (Rm != 0xF) { // Writeback 3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 } 3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3742 return MCDisassembler::Fail; 3743 Inst.addOperand(MCOperand::CreateImm(align)); 3744 if (Rm != 0xF) { 3745 if (Rm != 0xD) { 3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3747 return MCDisassembler::Fail; 3748 } else 3749 Inst.addOperand(MCOperand::CreateReg(0)); 3750 } 3751 3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 Inst.addOperand(MCOperand::CreateImm(index)); 3755 3756 return S; 3757 } 3758 3759 3760 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3761 uint64_t Address, const void *Decoder) { 3762 DecodeStatus S = MCDisassembler::Success; 3763 3764 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3765 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3766 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3767 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3768 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3769 3770 unsigned align = 0; 3771 unsigned index = 0; 3772 unsigned inc = 1; 3773 switch (size) { 3774 default: 3775 return MCDisassembler::Fail; 3776 case 0: 3777 index = fieldFromInstruction32(Insn, 5, 3); 3778 if (fieldFromInstruction32(Insn, 4, 1)) 3779 align = 2; 3780 break; 3781 case 1: 3782 index = fieldFromInstruction32(Insn, 6, 2); 3783 if (fieldFromInstruction32(Insn, 4, 1)) 3784 align = 4; 3785 if (fieldFromInstruction32(Insn, 5, 1)) 3786 inc = 2; 3787 break; 3788 case 2: 3789 if (fieldFromInstruction32(Insn, 5, 1)) 3790 return MCDisassembler::Fail; // UNDEFINED 3791 index = fieldFromInstruction32(Insn, 7, 1); 3792 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3793 align = 8; 3794 if (fieldFromInstruction32(Insn, 6, 1)) 3795 inc = 2; 3796 break; 3797 } 3798 3799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3800 return MCDisassembler::Fail; 3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3802 return MCDisassembler::Fail; 3803 if (Rm != 0xF) { // Writeback 3804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3805 return MCDisassembler::Fail; 3806 } 3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3808 return MCDisassembler::Fail; 3809 Inst.addOperand(MCOperand::CreateImm(align)); 3810 if (Rm != 0xF) { 3811 if (Rm != 0xD) { 3812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3813 return MCDisassembler::Fail; 3814 } else 3815 Inst.addOperand(MCOperand::CreateReg(0)); 3816 } 3817 3818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3821 return MCDisassembler::Fail; 3822 Inst.addOperand(MCOperand::CreateImm(index)); 3823 3824 return S; 3825 } 3826 3827 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3828 uint64_t Address, const void *Decoder) { 3829 DecodeStatus S = MCDisassembler::Success; 3830 3831 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3832 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3833 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3834 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3835 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3836 3837 unsigned align = 0; 3838 unsigned index = 0; 3839 unsigned inc = 1; 3840 switch (size) { 3841 default: 3842 return MCDisassembler::Fail; 3843 case 0: 3844 index = fieldFromInstruction32(Insn, 5, 3); 3845 if (fieldFromInstruction32(Insn, 4, 1)) 3846 align = 2; 3847 break; 3848 case 1: 3849 index = fieldFromInstruction32(Insn, 6, 2); 3850 if (fieldFromInstruction32(Insn, 4, 1)) 3851 align = 4; 3852 if (fieldFromInstruction32(Insn, 5, 1)) 3853 inc = 2; 3854 break; 3855 case 2: 3856 if (fieldFromInstruction32(Insn, 5, 1)) 3857 return MCDisassembler::Fail; // UNDEFINED 3858 index = fieldFromInstruction32(Insn, 7, 1); 3859 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3860 align = 8; 3861 if (fieldFromInstruction32(Insn, 6, 1)) 3862 inc = 2; 3863 break; 3864 } 3865 3866 if (Rm != 0xF) { // Writeback 3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 } 3870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 Inst.addOperand(MCOperand::CreateImm(align)); 3873 if (Rm != 0xF) { 3874 if (Rm != 0xD) { 3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 } else 3878 Inst.addOperand(MCOperand::CreateReg(0)); 3879 } 3880 3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3884 return MCDisassembler::Fail; 3885 Inst.addOperand(MCOperand::CreateImm(index)); 3886 3887 return S; 3888 } 3889 3890 3891 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3892 uint64_t Address, const void *Decoder) { 3893 DecodeStatus S = MCDisassembler::Success; 3894 3895 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3896 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3897 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3898 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3899 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3900 3901 unsigned align = 0; 3902 unsigned index = 0; 3903 unsigned inc = 1; 3904 switch (size) { 3905 default: 3906 return MCDisassembler::Fail; 3907 case 0: 3908 if (fieldFromInstruction32(Insn, 4, 1)) 3909 return MCDisassembler::Fail; // UNDEFINED 3910 index = fieldFromInstruction32(Insn, 5, 3); 3911 break; 3912 case 1: 3913 if (fieldFromInstruction32(Insn, 4, 1)) 3914 return MCDisassembler::Fail; // UNDEFINED 3915 index = fieldFromInstruction32(Insn, 6, 2); 3916 if (fieldFromInstruction32(Insn, 5, 1)) 3917 inc = 2; 3918 break; 3919 case 2: 3920 if (fieldFromInstruction32(Insn, 4, 2)) 3921 return MCDisassembler::Fail; // UNDEFINED 3922 index = fieldFromInstruction32(Insn, 7, 1); 3923 if (fieldFromInstruction32(Insn, 6, 1)) 3924 inc = 2; 3925 break; 3926 } 3927 3928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3929 return MCDisassembler::Fail; 3930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3931 return MCDisassembler::Fail; 3932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3933 return MCDisassembler::Fail; 3934 3935 if (Rm != 0xF) { // Writeback 3936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3937 return MCDisassembler::Fail; 3938 } 3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3940 return MCDisassembler::Fail; 3941 Inst.addOperand(MCOperand::CreateImm(align)); 3942 if (Rm != 0xF) { 3943 if (Rm != 0xD) { 3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 } else 3947 Inst.addOperand(MCOperand::CreateReg(0)); 3948 } 3949 3950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3955 return MCDisassembler::Fail; 3956 Inst.addOperand(MCOperand::CreateImm(index)); 3957 3958 return S; 3959 } 3960 3961 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 3962 uint64_t Address, const void *Decoder) { 3963 DecodeStatus S = MCDisassembler::Success; 3964 3965 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3966 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3967 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3968 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3969 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3970 3971 unsigned align = 0; 3972 unsigned index = 0; 3973 unsigned inc = 1; 3974 switch (size) { 3975 default: 3976 return MCDisassembler::Fail; 3977 case 0: 3978 if (fieldFromInstruction32(Insn, 4, 1)) 3979 return MCDisassembler::Fail; // UNDEFINED 3980 index = fieldFromInstruction32(Insn, 5, 3); 3981 break; 3982 case 1: 3983 if (fieldFromInstruction32(Insn, 4, 1)) 3984 return MCDisassembler::Fail; // UNDEFINED 3985 index = fieldFromInstruction32(Insn, 6, 2); 3986 if (fieldFromInstruction32(Insn, 5, 1)) 3987 inc = 2; 3988 break; 3989 case 2: 3990 if (fieldFromInstruction32(Insn, 4, 2)) 3991 return MCDisassembler::Fail; // UNDEFINED 3992 index = fieldFromInstruction32(Insn, 7, 1); 3993 if (fieldFromInstruction32(Insn, 6, 1)) 3994 inc = 2; 3995 break; 3996 } 3997 3998 if (Rm != 0xF) { // Writeback 3999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 } 4002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 Inst.addOperand(MCOperand::CreateImm(align)); 4005 if (Rm != 0xF) { 4006 if (Rm != 0xD) { 4007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 } else 4010 Inst.addOperand(MCOperand::CreateReg(0)); 4011 } 4012 4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 Inst.addOperand(MCOperand::CreateImm(index)); 4020 4021 return S; 4022 } 4023 4024 4025 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4026 uint64_t Address, const void *Decoder) { 4027 DecodeStatus S = MCDisassembler::Success; 4028 4029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4030 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4031 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4032 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4033 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4034 4035 unsigned align = 0; 4036 unsigned index = 0; 4037 unsigned inc = 1; 4038 switch (size) { 4039 default: 4040 return MCDisassembler::Fail; 4041 case 0: 4042 if (fieldFromInstruction32(Insn, 4, 1)) 4043 align = 4; 4044 index = fieldFromInstruction32(Insn, 5, 3); 4045 break; 4046 case 1: 4047 if (fieldFromInstruction32(Insn, 4, 1)) 4048 align = 8; 4049 index = fieldFromInstruction32(Insn, 6, 2); 4050 if (fieldFromInstruction32(Insn, 5, 1)) 4051 inc = 2; 4052 break; 4053 case 2: 4054 if (fieldFromInstruction32(Insn, 4, 2)) 4055 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4056 index = fieldFromInstruction32(Insn, 7, 1); 4057 if (fieldFromInstruction32(Insn, 6, 1)) 4058 inc = 2; 4059 break; 4060 } 4061 4062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4065 return MCDisassembler::Fail; 4066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4067 return MCDisassembler::Fail; 4068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4069 return MCDisassembler::Fail; 4070 4071 if (Rm != 0xF) { // Writeback 4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4073 return MCDisassembler::Fail; 4074 } 4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4076 return MCDisassembler::Fail; 4077 Inst.addOperand(MCOperand::CreateImm(align)); 4078 if (Rm != 0xF) { 4079 if (Rm != 0xD) { 4080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4081 return MCDisassembler::Fail; 4082 } else 4083 Inst.addOperand(MCOperand::CreateReg(0)); 4084 } 4085 4086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4089 return MCDisassembler::Fail; 4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 Inst.addOperand(MCOperand::CreateImm(index)); 4095 4096 return S; 4097 } 4098 4099 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4100 uint64_t Address, const void *Decoder) { 4101 DecodeStatus S = MCDisassembler::Success; 4102 4103 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4104 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4105 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4106 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4107 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4108 4109 unsigned align = 0; 4110 unsigned index = 0; 4111 unsigned inc = 1; 4112 switch (size) { 4113 default: 4114 return MCDisassembler::Fail; 4115 case 0: 4116 if (fieldFromInstruction32(Insn, 4, 1)) 4117 align = 4; 4118 index = fieldFromInstruction32(Insn, 5, 3); 4119 break; 4120 case 1: 4121 if (fieldFromInstruction32(Insn, 4, 1)) 4122 align = 8; 4123 index = fieldFromInstruction32(Insn, 6, 2); 4124 if (fieldFromInstruction32(Insn, 5, 1)) 4125 inc = 2; 4126 break; 4127 case 2: 4128 if (fieldFromInstruction32(Insn, 4, 2)) 4129 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4130 index = fieldFromInstruction32(Insn, 7, 1); 4131 if (fieldFromInstruction32(Insn, 6, 1)) 4132 inc = 2; 4133 break; 4134 } 4135 4136 if (Rm != 0xF) { // Writeback 4137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4138 return MCDisassembler::Fail; 4139 } 4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 Inst.addOperand(MCOperand::CreateImm(align)); 4143 if (Rm != 0xF) { 4144 if (Rm != 0xD) { 4145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 } else 4148 Inst.addOperand(MCOperand::CreateReg(0)); 4149 } 4150 4151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4154 return MCDisassembler::Fail; 4155 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4156 return MCDisassembler::Fail; 4157 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4158 return MCDisassembler::Fail; 4159 Inst.addOperand(MCOperand::CreateImm(index)); 4160 4161 return S; 4162 } 4163 4164 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4165 uint64_t Address, const void *Decoder) { 4166 DecodeStatus S = MCDisassembler::Success; 4167 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4168 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4169 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4170 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4171 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4172 4173 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4174 S = MCDisassembler::SoftFail; 4175 4176 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4177 return MCDisassembler::Fail; 4178 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4179 return MCDisassembler::Fail; 4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 4187 return S; 4188 } 4189 4190 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4191 uint64_t Address, const void *Decoder) { 4192 DecodeStatus S = MCDisassembler::Success; 4193 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4194 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4195 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4196 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4197 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4198 4199 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4200 S = MCDisassembler::SoftFail; 4201 4202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4203 return MCDisassembler::Fail; 4204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4205 return MCDisassembler::Fail; 4206 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4207 return MCDisassembler::Fail; 4208 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4209 return MCDisassembler::Fail; 4210 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4211 return MCDisassembler::Fail; 4212 4213 return S; 4214 } 4215 4216 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4217 uint64_t Address, const void *Decoder) { 4218 DecodeStatus S = MCDisassembler::Success; 4219 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4220 unsigned mask = fieldFromInstruction16(Insn, 0, 4); 4221 4222 if (pred == 0xF) { 4223 pred = 0xE; 4224 S = MCDisassembler::SoftFail; 4225 } 4226 4227 if (mask == 0x0) { 4228 mask |= 0x8; 4229 S = MCDisassembler::SoftFail; 4230 } 4231 4232 Inst.addOperand(MCOperand::CreateImm(pred)); 4233 Inst.addOperand(MCOperand::CreateImm(mask)); 4234 return S; 4235 } 4236 4237 static DecodeStatus 4238 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4239 uint64_t Address, const void *Decoder) { 4240 DecodeStatus S = MCDisassembler::Success; 4241 4242 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4243 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4244 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4245 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4246 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4247 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4248 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4249 bool writeback = (W == 1) | (P == 0); 4250 4251 addr |= (U << 8) | (Rn << 9); 4252 4253 if (writeback && (Rn == Rt || Rn == Rt2)) 4254 Check(S, MCDisassembler::SoftFail); 4255 if (Rt == Rt2) 4256 Check(S, MCDisassembler::SoftFail); 4257 4258 // Rt 4259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 // Rt2 4262 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 // Writeback operand 4265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 // addr 4268 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 4271 return S; 4272 } 4273 4274 static DecodeStatus 4275 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4276 uint64_t Address, const void *Decoder) { 4277 DecodeStatus S = MCDisassembler::Success; 4278 4279 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4280 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4281 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4282 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4283 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4284 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4285 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4286 bool writeback = (W == 1) | (P == 0); 4287 4288 addr |= (U << 8) | (Rn << 9); 4289 4290 if (writeback && (Rn == Rt || Rn == Rt2)) 4291 Check(S, MCDisassembler::SoftFail); 4292 4293 // Writeback operand 4294 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 // Rt 4297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 // Rt2 4300 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4301 return MCDisassembler::Fail; 4302 // addr 4303 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 4306 return S; 4307 } 4308 4309 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4310 uint64_t Address, const void *Decoder) { 4311 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4312 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4313 if (sign1 != sign2) return MCDisassembler::Fail; 4314 4315 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4316 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4317 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4318 Val |= sign1 << 12; 4319 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4320 4321 return MCDisassembler::Success; 4322 } 4323 4324 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4325 uint64_t Address, 4326 const void *Decoder) { 4327 DecodeStatus S = MCDisassembler::Success; 4328 4329 // Shift of "asr #32" is not allowed in Thumb2 mode. 4330 if (Val == 0x20) S = MCDisassembler::SoftFail; 4331 Inst.addOperand(MCOperand::CreateImm(Val)); 4332 return S; 4333 } 4334 4335 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4336 uint64_t Address, const void *Decoder) { 4337 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4338 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4339 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4340 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4341 4342 if (pred == 0xF) 4343 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4344 4345 DecodeStatus S = MCDisassembler::Success; 4346 4347 if (Rt == Rn || Rn == Rt2) 4348 S = MCDisassembler::SoftFail; 4349 4350 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4353 return MCDisassembler::Fail; 4354 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4355 return MCDisassembler::Fail; 4356 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 4359 return S; 4360 } 4361 4362 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4363 uint64_t Address, const void *Decoder) { 4364 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4365 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4366 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4367 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4368 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4369 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4370 4371 DecodeStatus S = MCDisassembler::Success; 4372 4373 // VMOVv2f32 is ambiguous with these decodings. 4374 if (!(imm & 0x38) && cmode == 0xF) { 4375 Inst.setOpcode(ARM::VMOVv2f32); 4376 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4377 } 4378 4379 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4380 4381 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4382 return MCDisassembler::Fail; 4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4384 return MCDisassembler::Fail; 4385 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4386 4387 return S; 4388 } 4389 4390 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4391 uint64_t Address, const void *Decoder) { 4392 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4393 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4394 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4395 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4396 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4397 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4398 4399 DecodeStatus S = MCDisassembler::Success; 4400 4401 // VMOVv4f32 is ambiguous with these decodings. 4402 if (!(imm & 0x38) && cmode == 0xF) { 4403 Inst.setOpcode(ARM::VMOVv4f32); 4404 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4405 } 4406 4407 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4408 4409 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4410 return MCDisassembler::Fail; 4411 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4412 return MCDisassembler::Fail; 4413 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4414 4415 return S; 4416 } 4417 4418 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4419 uint64_t Address, const void *Decoder) { 4420 DecodeStatus S = MCDisassembler::Success; 4421 4422 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4423 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4424 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4425 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4426 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4427 4428 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4429 S = MCDisassembler::SoftFail; 4430 4431 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4440 return MCDisassembler::Fail; 4441 4442 return S; 4443 } 4444 4445 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4446 uint64_t Address, const void *Decoder) { 4447 4448 DecodeStatus S = MCDisassembler::Success; 4449 4450 unsigned CRm = fieldFromInstruction32(Val, 0, 4); 4451 unsigned opc1 = fieldFromInstruction32(Val, 4, 4); 4452 unsigned cop = fieldFromInstruction32(Val, 8, 4); 4453 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4454 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4); 4455 4456 if ((cop & ~0x1) == 0xa) 4457 return MCDisassembler::Fail; 4458 4459 if (Rt == Rt2) 4460 S = MCDisassembler::SoftFail; 4461 4462 Inst.addOperand(MCOperand::CreateImm(cop)); 4463 Inst.addOperand(MCOperand::CreateImm(opc1)); 4464 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4465 return MCDisassembler::Fail; 4466 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 Inst.addOperand(MCOperand::CreateImm(CRm)); 4469 4470 return S; 4471 } 4472 4473