1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "llvm/MC/EDInstInfo.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 const EDInstInfo *getEDInfo() const; 55 private: 56 }; 57 58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59 class ThumbDisassembler : public MCDisassembler { 60 public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 const EDInstInfo *getEDInfo() const; 80 private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84 }; 85 } 86 87 static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 llvm_unreachable("Invalid DecodeStatus!"); 100 } 101 102 103 // Forward declare these because the autogenerated code will reference them. 104 // Definitions are further down. 105 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 131 unsigned RegNo, uint64_t Address, 132 const void *Decoder); 133 134 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 147 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 148 uint64_t Address, const void *Decoder); 149 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 152 unsigned Insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 164 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 165 unsigned Insn, 166 uint64_t Adddress, 167 const void *Decoder); 168 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 261 262 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 325 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 #include "ARMGenDisassemblerTables.inc" 328 #include "ARMGenInstrInfo.inc" 329 #include "ARMGenEDInfo.inc" 330 331 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 332 return new ARMDisassembler(STI); 333 } 334 335 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 336 return new ThumbDisassembler(STI); 337 } 338 339 const EDInstInfo *ARMDisassembler::getEDInfo() const { 340 return instInfoARM; 341 } 342 343 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 344 return instInfoARM; 345 } 346 347 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 348 const MemoryObject &Region, 349 uint64_t Address, 350 raw_ostream &os, 351 raw_ostream &cs) const { 352 CommentStream = &cs; 353 354 uint8_t bytes[4]; 355 356 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 357 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 358 359 // We want to read exactly 4 bytes of data. 360 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 361 Size = 0; 362 return MCDisassembler::Fail; 363 } 364 365 // Encoded as a small-endian 32-bit word in the stream. 366 uint32_t insn = (bytes[3] << 24) | 367 (bytes[2] << 16) | 368 (bytes[1] << 8) | 369 (bytes[0] << 0); 370 371 // Calling the auto-generated decoder function. 372 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 373 if (result != MCDisassembler::Fail) { 374 Size = 4; 375 return result; 376 } 377 378 // VFP and NEON instructions, similarly, are shared between ARM 379 // and Thumb modes. 380 MI.clear(); 381 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 4; 384 return result; 385 } 386 387 MI.clear(); 388 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 389 if (result != MCDisassembler::Fail) { 390 Size = 4; 391 // Add a fake predicate operand, because we share these instruction 392 // definitions with Thumb2 where these instructions are predicable. 393 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 394 return MCDisassembler::Fail; 395 return result; 396 } 397 398 MI.clear(); 399 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 400 if (result != MCDisassembler::Fail) { 401 Size = 4; 402 // Add a fake predicate operand, because we share these instruction 403 // definitions with Thumb2 where these instructions are predicable. 404 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 405 return MCDisassembler::Fail; 406 return result; 407 } 408 409 MI.clear(); 410 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 411 if (result != MCDisassembler::Fail) { 412 Size = 4; 413 // Add a fake predicate operand, because we share these instruction 414 // definitions with Thumb2 where these instructions are predicable. 415 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 416 return MCDisassembler::Fail; 417 return result; 418 } 419 420 MI.clear(); 421 422 Size = 0; 423 return MCDisassembler::Fail; 424 } 425 426 namespace llvm { 427 extern const MCInstrDesc ARMInsts[]; 428 } 429 430 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 431 /// immediate Value in the MCInst. The immediate Value has had any PC 432 /// adjustment made by the caller. If the instruction is a branch instruction 433 /// then isBranch is true, else false. If the getOpInfo() function was set as 434 /// part of the setupForSymbolicDisassembly() call then that function is called 435 /// to get any symbolic information at the Address for this instruction. If 436 /// that returns non-zero then the symbolic information it returns is used to 437 /// create an MCExpr and that is added as an operand to the MCInst. If 438 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 439 /// Value is done and if a symbol is found an MCExpr is created with that, else 440 /// an MCExpr with Value is created. This function returns true if it adds an 441 /// operand to the MCInst and false otherwise. 442 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 443 bool isBranch, uint64_t InstSize, 444 MCInst &MI, const void *Decoder) { 445 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 446 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 447 struct LLVMOpInfo1 SymbolicOp; 448 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 449 SymbolicOp.Value = Value; 450 void *DisInfo = Dis->getDisInfoBlock(); 451 452 if (!getOpInfo || 453 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 454 // Clear SymbolicOp.Value from above and also all other fields. 455 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 456 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 457 if (!SymbolLookUp) 458 return false; 459 uint64_t ReferenceType; 460 if (isBranch) 461 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 462 else 463 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 464 const char *ReferenceName; 465 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 466 &ReferenceName); 467 if (Name) { 468 SymbolicOp.AddSymbol.Name = Name; 469 SymbolicOp.AddSymbol.Present = true; 470 } 471 // For branches always create an MCExpr so it gets printed as hex address. 472 else if (isBranch) { 473 SymbolicOp.Value = Value; 474 } 475 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 476 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 477 if (!Name && !isBranch) 478 return false; 479 } 480 481 MCContext *Ctx = Dis->getMCContext(); 482 const MCExpr *Add = NULL; 483 if (SymbolicOp.AddSymbol.Present) { 484 if (SymbolicOp.AddSymbol.Name) { 485 StringRef Name(SymbolicOp.AddSymbol.Name); 486 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 487 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 488 } else { 489 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 490 } 491 } 492 493 const MCExpr *Sub = NULL; 494 if (SymbolicOp.SubtractSymbol.Present) { 495 if (SymbolicOp.SubtractSymbol.Name) { 496 StringRef Name(SymbolicOp.SubtractSymbol.Name); 497 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 498 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 499 } else { 500 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 501 } 502 } 503 504 const MCExpr *Off = NULL; 505 if (SymbolicOp.Value != 0) 506 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 507 508 const MCExpr *Expr; 509 if (Sub) { 510 const MCExpr *LHS; 511 if (Add) 512 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 513 else 514 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 515 if (Off != 0) 516 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 517 else 518 Expr = LHS; 519 } else if (Add) { 520 if (Off != 0) 521 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 522 else 523 Expr = Add; 524 } else { 525 if (Off != 0) 526 Expr = Off; 527 else 528 Expr = MCConstantExpr::Create(0, *Ctx); 529 } 530 531 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 532 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 533 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 534 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 535 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 536 MI.addOperand(MCOperand::CreateExpr(Expr)); 537 else 538 llvm_unreachable("bad SymbolicOp.VariantKind"); 539 540 return true; 541 } 542 543 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 544 /// referenced by a load instruction with the base register that is the Pc. 545 /// These can often be values in a literal pool near the Address of the 546 /// instruction. The Address of the instruction and its immediate Value are 547 /// used as a possible literal pool entry. The SymbolLookUp call back will 548 /// return the name of a symbol referenced by the the literal pool's entry if 549 /// the referenced address is that of a symbol. Or it will return a pointer to 550 /// a literal 'C' string if the referenced address of the literal pool's entry 551 /// is an address into a section with 'C' string literals. 552 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 553 const void *Decoder) { 554 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 555 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 556 if (SymbolLookUp) { 557 void *DisInfo = Dis->getDisInfoBlock(); 558 uint64_t ReferenceType; 559 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 560 const char *ReferenceName; 561 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 562 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 563 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 564 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 565 } 566 } 567 568 // Thumb1 instructions don't have explicit S bits. Rather, they 569 // implicitly set CPSR. Since it's not represented in the encoding, the 570 // auto-generated decoder won't inject the CPSR operand. We need to fix 571 // that as a post-pass. 572 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 573 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 574 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 575 MCInst::iterator I = MI.begin(); 576 for (unsigned i = 0; i < NumOps; ++i, ++I) { 577 if (I == MI.end()) break; 578 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 579 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 581 return; 582 } 583 } 584 585 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 586 } 587 588 // Most Thumb instructions don't have explicit predicates in the 589 // encoding, but rather get their predicates from IT context. We need 590 // to fix up the predicate operands using this context information as a 591 // post-pass. 592 MCDisassembler::DecodeStatus 593 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 594 MCDisassembler::DecodeStatus S = Success; 595 596 // A few instructions actually have predicates encoded in them. Don't 597 // try to overwrite it if we're seeing one of those. 598 switch (MI.getOpcode()) { 599 case ARM::tBcc: 600 case ARM::t2Bcc: 601 case ARM::tCBZ: 602 case ARM::tCBNZ: 603 case ARM::tCPS: 604 case ARM::t2CPS3p: 605 case ARM::t2CPS2p: 606 case ARM::t2CPS1p: 607 case ARM::tMOVSr: 608 case ARM::tSETEND: 609 // Some instructions (mostly conditional branches) are not 610 // allowed in IT blocks. 611 if (!ITBlock.empty()) 612 S = SoftFail; 613 else 614 return Success; 615 break; 616 case ARM::tB: 617 case ARM::t2B: 618 case ARM::t2TBB: 619 case ARM::t2TBH: 620 // Some instructions (mostly unconditional branches) can 621 // only appears at the end of, or outside of, an IT. 622 if (ITBlock.size() > 1) 623 S = SoftFail; 624 break; 625 default: 626 break; 627 } 628 629 // If we're in an IT block, base the predicate on that. Otherwise, 630 // assume a predicate of AL. 631 unsigned CC; 632 if (!ITBlock.empty()) { 633 CC = ITBlock.back(); 634 if (CC == 0xF) 635 CC = ARMCC::AL; 636 ITBlock.pop_back(); 637 } else 638 CC = ARMCC::AL; 639 640 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 641 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 642 MCInst::iterator I = MI.begin(); 643 for (unsigned i = 0; i < NumOps; ++i, ++I) { 644 if (I == MI.end()) break; 645 if (OpInfo[i].isPredicate()) { 646 I = MI.insert(I, MCOperand::CreateImm(CC)); 647 ++I; 648 if (CC == ARMCC::AL) 649 MI.insert(I, MCOperand::CreateReg(0)); 650 else 651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 652 return S; 653 } 654 } 655 656 I = MI.insert(I, MCOperand::CreateImm(CC)); 657 ++I; 658 if (CC == ARMCC::AL) 659 MI.insert(I, MCOperand::CreateReg(0)); 660 else 661 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 662 663 return S; 664 } 665 666 // Thumb VFP instructions are a special case. Because we share their 667 // encodings between ARM and Thumb modes, and they are predicable in ARM 668 // mode, the auto-generated decoder will give them an (incorrect) 669 // predicate operand. We need to rewrite these operands based on the IT 670 // context as a post-pass. 671 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 672 unsigned CC; 673 if (!ITBlock.empty()) { 674 CC = ITBlock.back(); 675 ITBlock.pop_back(); 676 } else 677 CC = ARMCC::AL; 678 679 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 680 MCInst::iterator I = MI.begin(); 681 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 682 for (unsigned i = 0; i < NumOps; ++i, ++I) { 683 if (OpInfo[i].isPredicate() ) { 684 I->setImm(CC); 685 ++I; 686 if (CC == ARMCC::AL) 687 I->setReg(0); 688 else 689 I->setReg(ARM::CPSR); 690 return; 691 } 692 } 693 } 694 695 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 696 const MemoryObject &Region, 697 uint64_t Address, 698 raw_ostream &os, 699 raw_ostream &cs) const { 700 CommentStream = &cs; 701 702 uint8_t bytes[4]; 703 704 assert((STI.getFeatureBits() & ARM::ModeThumb) && 705 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 706 707 // We want to read exactly 2 bytes of data. 708 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 709 Size = 0; 710 return MCDisassembler::Fail; 711 } 712 713 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 714 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 715 if (result != MCDisassembler::Fail) { 716 Size = 2; 717 Check(result, AddThumbPredicate(MI)); 718 return result; 719 } 720 721 MI.clear(); 722 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 723 if (result) { 724 Size = 2; 725 bool InITBlock = !ITBlock.empty(); 726 Check(result, AddThumbPredicate(MI)); 727 AddThumb1SBit(MI, InITBlock); 728 return result; 729 } 730 731 MI.clear(); 732 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 733 if (result != MCDisassembler::Fail) { 734 Size = 2; 735 736 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 737 // the Thumb predicate. 738 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 739 result = MCDisassembler::SoftFail; 740 741 Check(result, AddThumbPredicate(MI)); 742 743 // If we find an IT instruction, we need to parse its condition 744 // code and mask operands so that we can apply them correctly 745 // to the subsequent instructions. 746 if (MI.getOpcode() == ARM::t2IT) { 747 748 // (3 - the number of trailing zeros) is the number of then / else. 749 unsigned firstcond = MI.getOperand(0).getImm(); 750 unsigned Mask = MI.getOperand(1).getImm(); 751 unsigned CondBit0 = Mask >> 4 & 1; 752 unsigned NumTZ = CountTrailingZeros_32(Mask); 753 assert(NumTZ <= 3 && "Invalid IT mask!"); 754 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 755 bool T = ((Mask >> Pos) & 1) == CondBit0; 756 if (T) 757 ITBlock.insert(ITBlock.begin(), firstcond); 758 else 759 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 760 } 761 762 ITBlock.push_back(firstcond); 763 } 764 765 return result; 766 } 767 768 // We want to read exactly 4 bytes of data. 769 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 770 Size = 0; 771 return MCDisassembler::Fail; 772 } 773 774 uint32_t insn32 = (bytes[3] << 8) | 775 (bytes[2] << 0) | 776 (bytes[1] << 24) | 777 (bytes[0] << 16); 778 MI.clear(); 779 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 780 if (result != MCDisassembler::Fail) { 781 Size = 4; 782 bool InITBlock = ITBlock.size(); 783 Check(result, AddThumbPredicate(MI)); 784 AddThumb1SBit(MI, InITBlock); 785 return result; 786 } 787 788 MI.clear(); 789 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 790 if (result != MCDisassembler::Fail) { 791 Size = 4; 792 Check(result, AddThumbPredicate(MI)); 793 return result; 794 } 795 796 MI.clear(); 797 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 798 if (result != MCDisassembler::Fail) { 799 Size = 4; 800 UpdateThumbVFPPredicate(MI); 801 return result; 802 } 803 804 MI.clear(); 805 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 806 if (result != MCDisassembler::Fail) { 807 Size = 4; 808 Check(result, AddThumbPredicate(MI)); 809 return result; 810 } 811 812 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 813 MI.clear(); 814 uint32_t NEONLdStInsn = insn32; 815 NEONLdStInsn &= 0xF0FFFFFF; 816 NEONLdStInsn |= 0x04000000; 817 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 818 if (result != MCDisassembler::Fail) { 819 Size = 4; 820 Check(result, AddThumbPredicate(MI)); 821 return result; 822 } 823 } 824 825 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 826 MI.clear(); 827 uint32_t NEONDataInsn = insn32; 828 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 829 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 830 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 831 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 Check(result, AddThumbPredicate(MI)); 835 return result; 836 } 837 } 838 839 Size = 0; 840 return MCDisassembler::Fail; 841 } 842 843 844 extern "C" void LLVMInitializeARMDisassembler() { 845 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 846 createARMDisassembler); 847 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 848 createThumbDisassembler); 849 } 850 851 static const uint16_t GPRDecoderTable[] = { 852 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 853 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 854 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 855 ARM::R12, ARM::SP, ARM::LR, ARM::PC 856 }; 857 858 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 859 uint64_t Address, const void *Decoder) { 860 if (RegNo > 15) 861 return MCDisassembler::Fail; 862 863 unsigned Register = GPRDecoderTable[RegNo]; 864 Inst.addOperand(MCOperand::CreateReg(Register)); 865 return MCDisassembler::Success; 866 } 867 868 static DecodeStatus 869 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 870 uint64_t Address, const void *Decoder) { 871 DecodeStatus S = MCDisassembler::Success; 872 873 if (RegNo == 15) 874 S = MCDisassembler::SoftFail; 875 876 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 877 878 return S; 879 } 880 881 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 882 uint64_t Address, const void *Decoder) { 883 if (RegNo > 7) 884 return MCDisassembler::Fail; 885 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 886 } 887 888 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 889 uint64_t Address, const void *Decoder) { 890 unsigned Register = 0; 891 switch (RegNo) { 892 case 0: 893 Register = ARM::R0; 894 break; 895 case 1: 896 Register = ARM::R1; 897 break; 898 case 2: 899 Register = ARM::R2; 900 break; 901 case 3: 902 Register = ARM::R3; 903 break; 904 case 9: 905 Register = ARM::R9; 906 break; 907 case 12: 908 Register = ARM::R12; 909 break; 910 default: 911 return MCDisassembler::Fail; 912 } 913 914 Inst.addOperand(MCOperand::CreateReg(Register)); 915 return MCDisassembler::Success; 916 } 917 918 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 919 uint64_t Address, const void *Decoder) { 920 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 921 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 922 } 923 924 static const uint16_t SPRDecoderTable[] = { 925 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 926 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 927 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 928 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 929 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 930 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 931 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 932 ARM::S28, ARM::S29, ARM::S30, ARM::S31 933 }; 934 935 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 936 uint64_t Address, const void *Decoder) { 937 if (RegNo > 31) 938 return MCDisassembler::Fail; 939 940 unsigned Register = SPRDecoderTable[RegNo]; 941 Inst.addOperand(MCOperand::CreateReg(Register)); 942 return MCDisassembler::Success; 943 } 944 945 static const uint16_t DPRDecoderTable[] = { 946 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 947 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 948 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 949 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 950 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 951 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 952 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 953 ARM::D28, ARM::D29, ARM::D30, ARM::D31 954 }; 955 956 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 957 uint64_t Address, const void *Decoder) { 958 if (RegNo > 31) 959 return MCDisassembler::Fail; 960 961 unsigned Register = DPRDecoderTable[RegNo]; 962 Inst.addOperand(MCOperand::CreateReg(Register)); 963 return MCDisassembler::Success; 964 } 965 966 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 967 uint64_t Address, const void *Decoder) { 968 if (RegNo > 7) 969 return MCDisassembler::Fail; 970 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 971 } 972 973 static DecodeStatus 974 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 975 uint64_t Address, const void *Decoder) { 976 if (RegNo > 15) 977 return MCDisassembler::Fail; 978 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 979 } 980 981 static const uint16_t QPRDecoderTable[] = { 982 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 983 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 984 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 985 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 986 }; 987 988 989 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 990 uint64_t Address, const void *Decoder) { 991 if (RegNo > 31) 992 return MCDisassembler::Fail; 993 RegNo >>= 1; 994 995 unsigned Register = QPRDecoderTable[RegNo]; 996 Inst.addOperand(MCOperand::CreateReg(Register)); 997 return MCDisassembler::Success; 998 } 999 1000 static const uint16_t DPairDecoderTable[] = { 1001 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1002 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1003 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1004 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1005 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1006 ARM::Q15 1007 }; 1008 1009 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1010 uint64_t Address, const void *Decoder) { 1011 if (RegNo > 30) 1012 return MCDisassembler::Fail; 1013 1014 unsigned Register = DPairDecoderTable[RegNo]; 1015 Inst.addOperand(MCOperand::CreateReg(Register)); 1016 return MCDisassembler::Success; 1017 } 1018 1019 static const uint16_t DPairSpacedDecoderTable[] = { 1020 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1021 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1022 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1023 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1024 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1025 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1026 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1027 ARM::D28_D30, ARM::D29_D31 1028 }; 1029 1030 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1031 unsigned RegNo, 1032 uint64_t Address, 1033 const void *Decoder) { 1034 if (RegNo > 29) 1035 return MCDisassembler::Fail; 1036 1037 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040 } 1041 1042 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1043 uint64_t Address, const void *Decoder) { 1044 if (Val == 0xF) return MCDisassembler::Fail; 1045 // AL predicate is not allowed on Thumb1 branches. 1046 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1047 return MCDisassembler::Fail; 1048 Inst.addOperand(MCOperand::CreateImm(Val)); 1049 if (Val == ARMCC::AL) { 1050 Inst.addOperand(MCOperand::CreateReg(0)); 1051 } else 1052 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1057 uint64_t Address, const void *Decoder) { 1058 if (Val) 1059 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1060 else 1061 Inst.addOperand(MCOperand::CreateReg(0)); 1062 return MCDisassembler::Success; 1063 } 1064 1065 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1066 uint64_t Address, const void *Decoder) { 1067 uint32_t imm = Val & 0xFF; 1068 uint32_t rot = (Val & 0xF00) >> 7; 1069 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1070 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1071 return MCDisassembler::Success; 1072 } 1073 1074 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1075 uint64_t Address, const void *Decoder) { 1076 DecodeStatus S = MCDisassembler::Success; 1077 1078 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1079 unsigned type = fieldFromInstruction32(Val, 5, 2); 1080 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1081 1082 // Register-immediate 1083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1084 return MCDisassembler::Fail; 1085 1086 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1087 switch (type) { 1088 case 0: 1089 Shift = ARM_AM::lsl; 1090 break; 1091 case 1: 1092 Shift = ARM_AM::lsr; 1093 break; 1094 case 2: 1095 Shift = ARM_AM::asr; 1096 break; 1097 case 3: 1098 Shift = ARM_AM::ror; 1099 break; 1100 } 1101 1102 if (Shift == ARM_AM::ror && imm == 0) 1103 Shift = ARM_AM::rrx; 1104 1105 unsigned Op = Shift | (imm << 3); 1106 Inst.addOperand(MCOperand::CreateImm(Op)); 1107 1108 return S; 1109 } 1110 1111 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1112 uint64_t Address, const void *Decoder) { 1113 DecodeStatus S = MCDisassembler::Success; 1114 1115 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1116 unsigned type = fieldFromInstruction32(Val, 5, 2); 1117 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1118 1119 // Register-register 1120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1121 return MCDisassembler::Fail; 1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1123 return MCDisassembler::Fail; 1124 1125 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1126 switch (type) { 1127 case 0: 1128 Shift = ARM_AM::lsl; 1129 break; 1130 case 1: 1131 Shift = ARM_AM::lsr; 1132 break; 1133 case 2: 1134 Shift = ARM_AM::asr; 1135 break; 1136 case 3: 1137 Shift = ARM_AM::ror; 1138 break; 1139 } 1140 1141 Inst.addOperand(MCOperand::CreateImm(Shift)); 1142 1143 return S; 1144 } 1145 1146 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1147 uint64_t Address, const void *Decoder) { 1148 DecodeStatus S = MCDisassembler::Success; 1149 1150 bool writebackLoad = false; 1151 unsigned writebackReg = 0; 1152 switch (Inst.getOpcode()) { 1153 default: 1154 break; 1155 case ARM::LDMIA_UPD: 1156 case ARM::LDMDB_UPD: 1157 case ARM::LDMIB_UPD: 1158 case ARM::LDMDA_UPD: 1159 case ARM::t2LDMIA_UPD: 1160 case ARM::t2LDMDB_UPD: 1161 writebackLoad = true; 1162 writebackReg = Inst.getOperand(0).getReg(); 1163 break; 1164 } 1165 1166 // Empty register lists are not allowed. 1167 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1168 for (unsigned i = 0; i < 16; ++i) { 1169 if (Val & (1 << i)) { 1170 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1171 return MCDisassembler::Fail; 1172 // Writeback not allowed if Rn is in the target list. 1173 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1174 Check(S, MCDisassembler::SoftFail); 1175 } 1176 } 1177 1178 return S; 1179 } 1180 1181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1182 uint64_t Address, const void *Decoder) { 1183 DecodeStatus S = MCDisassembler::Success; 1184 1185 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1186 unsigned regs = Val & 0xFF; 1187 1188 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1189 return MCDisassembler::Fail; 1190 for (unsigned i = 0; i < (regs - 1); ++i) { 1191 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1192 return MCDisassembler::Fail; 1193 } 1194 1195 return S; 1196 } 1197 1198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1199 uint64_t Address, const void *Decoder) { 1200 DecodeStatus S = MCDisassembler::Success; 1201 1202 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1203 unsigned regs = (Val & 0xFF) / 2; 1204 1205 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1206 return MCDisassembler::Fail; 1207 for (unsigned i = 0; i < (regs - 1); ++i) { 1208 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1209 return MCDisassembler::Fail; 1210 } 1211 1212 return S; 1213 } 1214 1215 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1216 uint64_t Address, const void *Decoder) { 1217 // This operand encodes a mask of contiguous zeros between a specified MSB 1218 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1219 // the mask of all bits LSB-and-lower, and then xor them to create 1220 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1221 // create the final mask. 1222 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1223 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1224 1225 DecodeStatus S = MCDisassembler::Success; 1226 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1227 1228 uint32_t msb_mask = 0xFFFFFFFF; 1229 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1230 uint32_t lsb_mask = (1U << lsb) - 1; 1231 1232 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1233 return S; 1234 } 1235 1236 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1237 uint64_t Address, const void *Decoder) { 1238 DecodeStatus S = MCDisassembler::Success; 1239 1240 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1241 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1242 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1243 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1244 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1245 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1246 1247 switch (Inst.getOpcode()) { 1248 case ARM::LDC_OFFSET: 1249 case ARM::LDC_PRE: 1250 case ARM::LDC_POST: 1251 case ARM::LDC_OPTION: 1252 case ARM::LDCL_OFFSET: 1253 case ARM::LDCL_PRE: 1254 case ARM::LDCL_POST: 1255 case ARM::LDCL_OPTION: 1256 case ARM::STC_OFFSET: 1257 case ARM::STC_PRE: 1258 case ARM::STC_POST: 1259 case ARM::STC_OPTION: 1260 case ARM::STCL_OFFSET: 1261 case ARM::STCL_PRE: 1262 case ARM::STCL_POST: 1263 case ARM::STCL_OPTION: 1264 case ARM::t2LDC_OFFSET: 1265 case ARM::t2LDC_PRE: 1266 case ARM::t2LDC_POST: 1267 case ARM::t2LDC_OPTION: 1268 case ARM::t2LDCL_OFFSET: 1269 case ARM::t2LDCL_PRE: 1270 case ARM::t2LDCL_POST: 1271 case ARM::t2LDCL_OPTION: 1272 case ARM::t2STC_OFFSET: 1273 case ARM::t2STC_PRE: 1274 case ARM::t2STC_POST: 1275 case ARM::t2STC_OPTION: 1276 case ARM::t2STCL_OFFSET: 1277 case ARM::t2STCL_PRE: 1278 case ARM::t2STCL_POST: 1279 case ARM::t2STCL_OPTION: 1280 if (coproc == 0xA || coproc == 0xB) 1281 return MCDisassembler::Fail; 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 Inst.addOperand(MCOperand::CreateImm(coproc)); 1288 Inst.addOperand(MCOperand::CreateImm(CRd)); 1289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1290 return MCDisassembler::Fail; 1291 1292 switch (Inst.getOpcode()) { 1293 case ARM::t2LDC2_OFFSET: 1294 case ARM::t2LDC2L_OFFSET: 1295 case ARM::t2LDC2_PRE: 1296 case ARM::t2LDC2L_PRE: 1297 case ARM::t2STC2_OFFSET: 1298 case ARM::t2STC2L_OFFSET: 1299 case ARM::t2STC2_PRE: 1300 case ARM::t2STC2L_PRE: 1301 case ARM::LDC2_OFFSET: 1302 case ARM::LDC2L_OFFSET: 1303 case ARM::LDC2_PRE: 1304 case ARM::LDC2L_PRE: 1305 case ARM::STC2_OFFSET: 1306 case ARM::STC2L_OFFSET: 1307 case ARM::STC2_PRE: 1308 case ARM::STC2L_PRE: 1309 case ARM::t2LDC_OFFSET: 1310 case ARM::t2LDCL_OFFSET: 1311 case ARM::t2LDC_PRE: 1312 case ARM::t2LDCL_PRE: 1313 case ARM::t2STC_OFFSET: 1314 case ARM::t2STCL_OFFSET: 1315 case ARM::t2STC_PRE: 1316 case ARM::t2STCL_PRE: 1317 case ARM::LDC_OFFSET: 1318 case ARM::LDCL_OFFSET: 1319 case ARM::LDC_PRE: 1320 case ARM::LDCL_PRE: 1321 case ARM::STC_OFFSET: 1322 case ARM::STCL_OFFSET: 1323 case ARM::STC_PRE: 1324 case ARM::STCL_PRE: 1325 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1326 Inst.addOperand(MCOperand::CreateImm(imm)); 1327 break; 1328 case ARM::t2LDC2_POST: 1329 case ARM::t2LDC2L_POST: 1330 case ARM::t2STC2_POST: 1331 case ARM::t2STC2L_POST: 1332 case ARM::LDC2_POST: 1333 case ARM::LDC2L_POST: 1334 case ARM::STC2_POST: 1335 case ARM::STC2L_POST: 1336 case ARM::t2LDC_POST: 1337 case ARM::t2LDCL_POST: 1338 case ARM::t2STC_POST: 1339 case ARM::t2STCL_POST: 1340 case ARM::LDC_POST: 1341 case ARM::LDCL_POST: 1342 case ARM::STC_POST: 1343 case ARM::STCL_POST: 1344 imm |= U << 8; 1345 // fall through. 1346 default: 1347 // The 'option' variant doesn't encode 'U' in the immediate since 1348 // the immediate is unsigned [0,255]. 1349 Inst.addOperand(MCOperand::CreateImm(imm)); 1350 break; 1351 } 1352 1353 switch (Inst.getOpcode()) { 1354 case ARM::LDC_OFFSET: 1355 case ARM::LDC_PRE: 1356 case ARM::LDC_POST: 1357 case ARM::LDC_OPTION: 1358 case ARM::LDCL_OFFSET: 1359 case ARM::LDCL_PRE: 1360 case ARM::LDCL_POST: 1361 case ARM::LDCL_OPTION: 1362 case ARM::STC_OFFSET: 1363 case ARM::STC_PRE: 1364 case ARM::STC_POST: 1365 case ARM::STC_OPTION: 1366 case ARM::STCL_OFFSET: 1367 case ARM::STCL_PRE: 1368 case ARM::STCL_POST: 1369 case ARM::STCL_OPTION: 1370 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1371 return MCDisassembler::Fail; 1372 break; 1373 default: 1374 break; 1375 } 1376 1377 return S; 1378 } 1379 1380 static DecodeStatus 1381 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1382 uint64_t Address, const void *Decoder) { 1383 DecodeStatus S = MCDisassembler::Success; 1384 1385 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1386 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1387 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1388 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1389 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1390 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1391 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1392 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1393 1394 // On stores, the writeback operand precedes Rt. 1395 switch (Inst.getOpcode()) { 1396 case ARM::STR_POST_IMM: 1397 case ARM::STR_POST_REG: 1398 case ARM::STRB_POST_IMM: 1399 case ARM::STRB_POST_REG: 1400 case ARM::STRT_POST_REG: 1401 case ARM::STRT_POST_IMM: 1402 case ARM::STRBT_POST_REG: 1403 case ARM::STRBT_POST_IMM: 1404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1405 return MCDisassembler::Fail; 1406 break; 1407 default: 1408 break; 1409 } 1410 1411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1412 return MCDisassembler::Fail; 1413 1414 // On loads, the writeback operand comes after Rt. 1415 switch (Inst.getOpcode()) { 1416 case ARM::LDR_POST_IMM: 1417 case ARM::LDR_POST_REG: 1418 case ARM::LDRB_POST_IMM: 1419 case ARM::LDRB_POST_REG: 1420 case ARM::LDRBT_POST_REG: 1421 case ARM::LDRBT_POST_IMM: 1422 case ARM::LDRT_POST_REG: 1423 case ARM::LDRT_POST_IMM: 1424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1425 return MCDisassembler::Fail; 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1432 return MCDisassembler::Fail; 1433 1434 ARM_AM::AddrOpc Op = ARM_AM::add; 1435 if (!fieldFromInstruction32(Insn, 23, 1)) 1436 Op = ARM_AM::sub; 1437 1438 bool writeback = (P == 0) || (W == 1); 1439 unsigned idx_mode = 0; 1440 if (P && writeback) 1441 idx_mode = ARMII::IndexModePre; 1442 else if (!P && writeback) 1443 idx_mode = ARMII::IndexModePost; 1444 1445 if (writeback && (Rn == 15 || Rn == Rt)) 1446 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1447 1448 if (reg) { 1449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1450 return MCDisassembler::Fail; 1451 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1452 switch( fieldFromInstruction32(Insn, 5, 2)) { 1453 case 0: 1454 Opc = ARM_AM::lsl; 1455 break; 1456 case 1: 1457 Opc = ARM_AM::lsr; 1458 break; 1459 case 2: 1460 Opc = ARM_AM::asr; 1461 break; 1462 case 3: 1463 Opc = ARM_AM::ror; 1464 break; 1465 default: 1466 return MCDisassembler::Fail; 1467 } 1468 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1469 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1470 1471 Inst.addOperand(MCOperand::CreateImm(imm)); 1472 } else { 1473 Inst.addOperand(MCOperand::CreateReg(0)); 1474 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1475 Inst.addOperand(MCOperand::CreateImm(tmp)); 1476 } 1477 1478 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1479 return MCDisassembler::Fail; 1480 1481 return S; 1482 } 1483 1484 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1485 uint64_t Address, const void *Decoder) { 1486 DecodeStatus S = MCDisassembler::Success; 1487 1488 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1489 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1490 unsigned type = fieldFromInstruction32(Val, 5, 2); 1491 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1492 unsigned U = fieldFromInstruction32(Val, 12, 1); 1493 1494 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1495 switch (type) { 1496 case 0: 1497 ShOp = ARM_AM::lsl; 1498 break; 1499 case 1: 1500 ShOp = ARM_AM::lsr; 1501 break; 1502 case 2: 1503 ShOp = ARM_AM::asr; 1504 break; 1505 case 3: 1506 ShOp = ARM_AM::ror; 1507 break; 1508 } 1509 1510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1511 return MCDisassembler::Fail; 1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1513 return MCDisassembler::Fail; 1514 unsigned shift; 1515 if (U) 1516 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1517 else 1518 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1519 Inst.addOperand(MCOperand::CreateImm(shift)); 1520 1521 return S; 1522 } 1523 1524 static DecodeStatus 1525 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1526 uint64_t Address, const void *Decoder) { 1527 DecodeStatus S = MCDisassembler::Success; 1528 1529 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1530 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1531 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1532 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1533 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1534 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1535 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1536 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1537 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1538 unsigned Rt2 = Rt + 1; 1539 1540 bool writeback = (W == 1) | (P == 0); 1541 1542 // For {LD,ST}RD, Rt must be even, else undefined. 1543 switch (Inst.getOpcode()) { 1544 case ARM::STRD: 1545 case ARM::STRD_PRE: 1546 case ARM::STRD_POST: 1547 case ARM::LDRD: 1548 case ARM::LDRD_PRE: 1549 case ARM::LDRD_POST: 1550 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1551 break; 1552 default: 1553 break; 1554 } 1555 switch (Inst.getOpcode()) { 1556 case ARM::STRD: 1557 case ARM::STRD_PRE: 1558 case ARM::STRD_POST: 1559 if (P == 0 && W == 1) 1560 S = MCDisassembler::SoftFail; 1561 1562 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1563 S = MCDisassembler::SoftFail; 1564 if (type && Rm == 15) 1565 S = MCDisassembler::SoftFail; 1566 if (Rt2 == 15) 1567 S = MCDisassembler::SoftFail; 1568 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1569 S = MCDisassembler::SoftFail; 1570 break; 1571 case ARM::STRH: 1572 case ARM::STRH_PRE: 1573 case ARM::STRH_POST: 1574 if (Rt == 15) 1575 S = MCDisassembler::SoftFail; 1576 if (writeback && (Rn == 15 || Rn == Rt)) 1577 S = MCDisassembler::SoftFail; 1578 if (!type && Rm == 15) 1579 S = MCDisassembler::SoftFail; 1580 break; 1581 case ARM::LDRD: 1582 case ARM::LDRD_PRE: 1583 case ARM::LDRD_POST: 1584 if (type && Rn == 15){ 1585 if (Rt2 == 15) 1586 S = MCDisassembler::SoftFail; 1587 break; 1588 } 1589 if (P == 0 && W == 1) 1590 S = MCDisassembler::SoftFail; 1591 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1592 S = MCDisassembler::SoftFail; 1593 if (!type && writeback && Rn == 15) 1594 S = MCDisassembler::SoftFail; 1595 if (writeback && (Rn == Rt || Rn == Rt2)) 1596 S = MCDisassembler::SoftFail; 1597 break; 1598 case ARM::LDRH: 1599 case ARM::LDRH_PRE: 1600 case ARM::LDRH_POST: 1601 if (type && Rn == 15){ 1602 if (Rt == 15) 1603 S = MCDisassembler::SoftFail; 1604 break; 1605 } 1606 if (Rt == 15) 1607 S = MCDisassembler::SoftFail; 1608 if (!type && Rm == 15) 1609 S = MCDisassembler::SoftFail; 1610 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1611 S = MCDisassembler::SoftFail; 1612 break; 1613 case ARM::LDRSH: 1614 case ARM::LDRSH_PRE: 1615 case ARM::LDRSH_POST: 1616 case ARM::LDRSB: 1617 case ARM::LDRSB_PRE: 1618 case ARM::LDRSB_POST: 1619 if (type && Rn == 15){ 1620 if (Rt == 15) 1621 S = MCDisassembler::SoftFail; 1622 break; 1623 } 1624 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1625 S = MCDisassembler::SoftFail; 1626 if (!type && (Rt == 15 || Rm == 15)) 1627 S = MCDisassembler::SoftFail; 1628 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1629 S = MCDisassembler::SoftFail; 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 if (writeback) { // Writeback 1636 if (P) 1637 U |= ARMII::IndexModePre << 9; 1638 else 1639 U |= ARMII::IndexModePost << 9; 1640 1641 // On stores, the writeback operand precedes Rt. 1642 switch (Inst.getOpcode()) { 1643 case ARM::STRD: 1644 case ARM::STRD_PRE: 1645 case ARM::STRD_POST: 1646 case ARM::STRH: 1647 case ARM::STRH_PRE: 1648 case ARM::STRH_POST: 1649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1650 return MCDisassembler::Fail; 1651 break; 1652 default: 1653 break; 1654 } 1655 } 1656 1657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1658 return MCDisassembler::Fail; 1659 switch (Inst.getOpcode()) { 1660 case ARM::STRD: 1661 case ARM::STRD_PRE: 1662 case ARM::STRD_POST: 1663 case ARM::LDRD: 1664 case ARM::LDRD_PRE: 1665 case ARM::LDRD_POST: 1666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1667 return MCDisassembler::Fail; 1668 break; 1669 default: 1670 break; 1671 } 1672 1673 if (writeback) { 1674 // On loads, the writeback operand comes after Rt. 1675 switch (Inst.getOpcode()) { 1676 case ARM::LDRD: 1677 case ARM::LDRD_PRE: 1678 case ARM::LDRD_POST: 1679 case ARM::LDRH: 1680 case ARM::LDRH_PRE: 1681 case ARM::LDRH_POST: 1682 case ARM::LDRSH: 1683 case ARM::LDRSH_PRE: 1684 case ARM::LDRSH_POST: 1685 case ARM::LDRSB: 1686 case ARM::LDRSB_PRE: 1687 case ARM::LDRSB_POST: 1688 case ARM::LDRHTr: 1689 case ARM::LDRSBTr: 1690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1691 return MCDisassembler::Fail; 1692 break; 1693 default: 1694 break; 1695 } 1696 } 1697 1698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1699 return MCDisassembler::Fail; 1700 1701 if (type) { 1702 Inst.addOperand(MCOperand::CreateReg(0)); 1703 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1704 } else { 1705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1706 return MCDisassembler::Fail; 1707 Inst.addOperand(MCOperand::CreateImm(U)); 1708 } 1709 1710 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1711 return MCDisassembler::Fail; 1712 1713 return S; 1714 } 1715 1716 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1717 uint64_t Address, const void *Decoder) { 1718 DecodeStatus S = MCDisassembler::Success; 1719 1720 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1721 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1722 1723 switch (mode) { 1724 case 0: 1725 mode = ARM_AM::da; 1726 break; 1727 case 1: 1728 mode = ARM_AM::ia; 1729 break; 1730 case 2: 1731 mode = ARM_AM::db; 1732 break; 1733 case 3: 1734 mode = ARM_AM::ib; 1735 break; 1736 } 1737 1738 Inst.addOperand(MCOperand::CreateImm(mode)); 1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 1742 return S; 1743 } 1744 1745 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1746 unsigned Insn, 1747 uint64_t Address, const void *Decoder) { 1748 DecodeStatus S = MCDisassembler::Success; 1749 1750 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1751 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1752 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1753 1754 if (pred == 0xF) { 1755 switch (Inst.getOpcode()) { 1756 case ARM::LDMDA: 1757 Inst.setOpcode(ARM::RFEDA); 1758 break; 1759 case ARM::LDMDA_UPD: 1760 Inst.setOpcode(ARM::RFEDA_UPD); 1761 break; 1762 case ARM::LDMDB: 1763 Inst.setOpcode(ARM::RFEDB); 1764 break; 1765 case ARM::LDMDB_UPD: 1766 Inst.setOpcode(ARM::RFEDB_UPD); 1767 break; 1768 case ARM::LDMIA: 1769 Inst.setOpcode(ARM::RFEIA); 1770 break; 1771 case ARM::LDMIA_UPD: 1772 Inst.setOpcode(ARM::RFEIA_UPD); 1773 break; 1774 case ARM::LDMIB: 1775 Inst.setOpcode(ARM::RFEIB); 1776 break; 1777 case ARM::LDMIB_UPD: 1778 Inst.setOpcode(ARM::RFEIB_UPD); 1779 break; 1780 case ARM::STMDA: 1781 Inst.setOpcode(ARM::SRSDA); 1782 break; 1783 case ARM::STMDA_UPD: 1784 Inst.setOpcode(ARM::SRSDA_UPD); 1785 break; 1786 case ARM::STMDB: 1787 Inst.setOpcode(ARM::SRSDB); 1788 break; 1789 case ARM::STMDB_UPD: 1790 Inst.setOpcode(ARM::SRSDB_UPD); 1791 break; 1792 case ARM::STMIA: 1793 Inst.setOpcode(ARM::SRSIA); 1794 break; 1795 case ARM::STMIA_UPD: 1796 Inst.setOpcode(ARM::SRSIA_UPD); 1797 break; 1798 case ARM::STMIB: 1799 Inst.setOpcode(ARM::SRSIB); 1800 break; 1801 case ARM::STMIB_UPD: 1802 Inst.setOpcode(ARM::SRSIB_UPD); 1803 break; 1804 default: 1805 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1806 } 1807 1808 // For stores (which become SRS's, the only operand is the mode. 1809 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1810 Inst.addOperand( 1811 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1812 return S; 1813 } 1814 1815 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1816 } 1817 1818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1821 return MCDisassembler::Fail; // Tied 1822 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 return S; 1828 } 1829 1830 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1831 uint64_t Address, const void *Decoder) { 1832 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1833 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1834 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1835 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1836 1837 DecodeStatus S = MCDisassembler::Success; 1838 1839 // imod == '01' --> UNPREDICTABLE 1840 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1841 // return failure here. The '01' imod value is unprintable, so there's 1842 // nothing useful we could do even if we returned UNPREDICTABLE. 1843 1844 if (imod == 1) return MCDisassembler::Fail; 1845 1846 if (imod && M) { 1847 Inst.setOpcode(ARM::CPS3p); 1848 Inst.addOperand(MCOperand::CreateImm(imod)); 1849 Inst.addOperand(MCOperand::CreateImm(iflags)); 1850 Inst.addOperand(MCOperand::CreateImm(mode)); 1851 } else if (imod && !M) { 1852 Inst.setOpcode(ARM::CPS2p); 1853 Inst.addOperand(MCOperand::CreateImm(imod)); 1854 Inst.addOperand(MCOperand::CreateImm(iflags)); 1855 if (mode) S = MCDisassembler::SoftFail; 1856 } else if (!imod && M) { 1857 Inst.setOpcode(ARM::CPS1p); 1858 Inst.addOperand(MCOperand::CreateImm(mode)); 1859 if (iflags) S = MCDisassembler::SoftFail; 1860 } else { 1861 // imod == '00' && M == '0' --> UNPREDICTABLE 1862 Inst.setOpcode(ARM::CPS1p); 1863 Inst.addOperand(MCOperand::CreateImm(mode)); 1864 S = MCDisassembler::SoftFail; 1865 } 1866 1867 return S; 1868 } 1869 1870 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1871 uint64_t Address, const void *Decoder) { 1872 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1873 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1874 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1875 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1876 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 // imod == '01' --> UNPREDICTABLE 1880 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1881 // return failure here. The '01' imod value is unprintable, so there's 1882 // nothing useful we could do even if we returned UNPREDICTABLE. 1883 1884 if (imod == 1) return MCDisassembler::Fail; 1885 1886 if (imod && M) { 1887 Inst.setOpcode(ARM::t2CPS3p); 1888 Inst.addOperand(MCOperand::CreateImm(imod)); 1889 Inst.addOperand(MCOperand::CreateImm(iflags)); 1890 Inst.addOperand(MCOperand::CreateImm(mode)); 1891 } else if (imod && !M) { 1892 Inst.setOpcode(ARM::t2CPS2p); 1893 Inst.addOperand(MCOperand::CreateImm(imod)); 1894 Inst.addOperand(MCOperand::CreateImm(iflags)); 1895 if (mode) S = MCDisassembler::SoftFail; 1896 } else if (!imod && M) { 1897 Inst.setOpcode(ARM::t2CPS1p); 1898 Inst.addOperand(MCOperand::CreateImm(mode)); 1899 if (iflags) S = MCDisassembler::SoftFail; 1900 } else { 1901 // imod == '00' && M == '0' --> UNPREDICTABLE 1902 Inst.setOpcode(ARM::t2CPS1p); 1903 Inst.addOperand(MCOperand::CreateImm(mode)); 1904 S = MCDisassembler::SoftFail; 1905 } 1906 1907 return S; 1908 } 1909 1910 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1911 uint64_t Address, const void *Decoder) { 1912 DecodeStatus S = MCDisassembler::Success; 1913 1914 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1915 unsigned imm = 0; 1916 1917 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1918 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1919 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1920 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1921 1922 if (Inst.getOpcode() == ARM::t2MOVTi16) 1923 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1924 return MCDisassembler::Fail; 1925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1926 return MCDisassembler::Fail; 1927 1928 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1929 Inst.addOperand(MCOperand::CreateImm(imm)); 1930 1931 return S; 1932 } 1933 1934 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1935 uint64_t Address, const void *Decoder) { 1936 DecodeStatus S = MCDisassembler::Success; 1937 1938 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1939 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1940 unsigned imm = 0; 1941 1942 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1943 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1944 1945 if (Inst.getOpcode() == ARM::MOVTi16) 1946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1952 Inst.addOperand(MCOperand::CreateImm(imm)); 1953 1954 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1955 return MCDisassembler::Fail; 1956 1957 return S; 1958 } 1959 1960 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1961 uint64_t Address, const void *Decoder) { 1962 DecodeStatus S = MCDisassembler::Success; 1963 1964 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1965 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1966 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1967 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1968 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1969 1970 if (pred == 0xF) 1971 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1972 1973 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1976 return MCDisassembler::Fail; 1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1978 return MCDisassembler::Fail; 1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1980 return MCDisassembler::Fail; 1981 1982 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1983 return MCDisassembler::Fail; 1984 1985 return S; 1986 } 1987 1988 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 1989 uint64_t Address, const void *Decoder) { 1990 DecodeStatus S = MCDisassembler::Success; 1991 1992 unsigned add = fieldFromInstruction32(Val, 12, 1); 1993 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1994 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1995 1996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1997 return MCDisassembler::Fail; 1998 1999 if (!add) imm *= -1; 2000 if (imm == 0 && !add) imm = INT32_MIN; 2001 Inst.addOperand(MCOperand::CreateImm(imm)); 2002 if (Rn == 15) 2003 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2004 2005 return S; 2006 } 2007 2008 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2009 uint64_t Address, const void *Decoder) { 2010 DecodeStatus S = MCDisassembler::Success; 2011 2012 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2013 unsigned U = fieldFromInstruction32(Val, 8, 1); 2014 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2015 2016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2017 return MCDisassembler::Fail; 2018 2019 if (U) 2020 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2021 else 2022 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2023 2024 return S; 2025 } 2026 2027 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2028 uint64_t Address, const void *Decoder) { 2029 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2030 } 2031 2032 static DecodeStatus 2033 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2034 uint64_t Address, const void *Decoder) { 2035 DecodeStatus S = MCDisassembler::Success; 2036 2037 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2038 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2039 2040 if (pred == 0xF) { 2041 Inst.setOpcode(ARM::BLXi); 2042 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2043 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2044 true, 4, Inst, Decoder)) 2045 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2046 return S; 2047 } 2048 2049 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2050 true, 4, Inst, Decoder)) 2051 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2052 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2053 return MCDisassembler::Fail; 2054 2055 return S; 2056 } 2057 2058 2059 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2060 uint64_t Address, const void *Decoder) { 2061 DecodeStatus S = MCDisassembler::Success; 2062 2063 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2064 unsigned align = fieldFromInstruction32(Val, 4, 2); 2065 2066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2067 return MCDisassembler::Fail; 2068 if (!align) 2069 Inst.addOperand(MCOperand::CreateImm(0)); 2070 else 2071 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2072 2073 return S; 2074 } 2075 2076 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2077 uint64_t Address, const void *Decoder) { 2078 DecodeStatus S = MCDisassembler::Success; 2079 2080 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2081 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2082 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2083 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2084 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2085 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2086 2087 // First output register 2088 switch (Inst.getOpcode()) { 2089 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2090 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2091 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2092 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2093 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2094 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2095 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2096 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2097 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2098 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2099 return MCDisassembler::Fail; 2100 break; 2101 case ARM::VLD2b16: 2102 case ARM::VLD2b32: 2103 case ARM::VLD2b8: 2104 case ARM::VLD2b16wb_fixed: 2105 case ARM::VLD2b16wb_register: 2106 case ARM::VLD2b32wb_fixed: 2107 case ARM::VLD2b32wb_register: 2108 case ARM::VLD2b8wb_fixed: 2109 case ARM::VLD2b8wb_register: 2110 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2111 return MCDisassembler::Fail; 2112 break; 2113 default: 2114 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2115 return MCDisassembler::Fail; 2116 } 2117 2118 // Second output register 2119 switch (Inst.getOpcode()) { 2120 case ARM::VLD3d8: 2121 case ARM::VLD3d16: 2122 case ARM::VLD3d32: 2123 case ARM::VLD3d8_UPD: 2124 case ARM::VLD3d16_UPD: 2125 case ARM::VLD3d32_UPD: 2126 case ARM::VLD4d8: 2127 case ARM::VLD4d16: 2128 case ARM::VLD4d32: 2129 case ARM::VLD4d8_UPD: 2130 case ARM::VLD4d16_UPD: 2131 case ARM::VLD4d32_UPD: 2132 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2133 return MCDisassembler::Fail; 2134 break; 2135 case ARM::VLD3q8: 2136 case ARM::VLD3q16: 2137 case ARM::VLD3q32: 2138 case ARM::VLD3q8_UPD: 2139 case ARM::VLD3q16_UPD: 2140 case ARM::VLD3q32_UPD: 2141 case ARM::VLD4q8: 2142 case ARM::VLD4q16: 2143 case ARM::VLD4q32: 2144 case ARM::VLD4q8_UPD: 2145 case ARM::VLD4q16_UPD: 2146 case ARM::VLD4q32_UPD: 2147 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2148 return MCDisassembler::Fail; 2149 default: 2150 break; 2151 } 2152 2153 // Third output register 2154 switch(Inst.getOpcode()) { 2155 case ARM::VLD3d8: 2156 case ARM::VLD3d16: 2157 case ARM::VLD3d32: 2158 case ARM::VLD3d8_UPD: 2159 case ARM::VLD3d16_UPD: 2160 case ARM::VLD3d32_UPD: 2161 case ARM::VLD4d8: 2162 case ARM::VLD4d16: 2163 case ARM::VLD4d32: 2164 case ARM::VLD4d8_UPD: 2165 case ARM::VLD4d16_UPD: 2166 case ARM::VLD4d32_UPD: 2167 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2168 return MCDisassembler::Fail; 2169 break; 2170 case ARM::VLD3q8: 2171 case ARM::VLD3q16: 2172 case ARM::VLD3q32: 2173 case ARM::VLD3q8_UPD: 2174 case ARM::VLD3q16_UPD: 2175 case ARM::VLD3q32_UPD: 2176 case ARM::VLD4q8: 2177 case ARM::VLD4q16: 2178 case ARM::VLD4q32: 2179 case ARM::VLD4q8_UPD: 2180 case ARM::VLD4q16_UPD: 2181 case ARM::VLD4q32_UPD: 2182 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2183 return MCDisassembler::Fail; 2184 break; 2185 default: 2186 break; 2187 } 2188 2189 // Fourth output register 2190 switch (Inst.getOpcode()) { 2191 case ARM::VLD4d8: 2192 case ARM::VLD4d16: 2193 case ARM::VLD4d32: 2194 case ARM::VLD4d8_UPD: 2195 case ARM::VLD4d16_UPD: 2196 case ARM::VLD4d32_UPD: 2197 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 break; 2200 case ARM::VLD4q8: 2201 case ARM::VLD4q16: 2202 case ARM::VLD4q32: 2203 case ARM::VLD4q8_UPD: 2204 case ARM::VLD4q16_UPD: 2205 case ARM::VLD4q32_UPD: 2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 break; 2209 default: 2210 break; 2211 } 2212 2213 // Writeback operand 2214 switch (Inst.getOpcode()) { 2215 case ARM::VLD1d8wb_fixed: 2216 case ARM::VLD1d16wb_fixed: 2217 case ARM::VLD1d32wb_fixed: 2218 case ARM::VLD1d64wb_fixed: 2219 case ARM::VLD1d8wb_register: 2220 case ARM::VLD1d16wb_register: 2221 case ARM::VLD1d32wb_register: 2222 case ARM::VLD1d64wb_register: 2223 case ARM::VLD1q8wb_fixed: 2224 case ARM::VLD1q16wb_fixed: 2225 case ARM::VLD1q32wb_fixed: 2226 case ARM::VLD1q64wb_fixed: 2227 case ARM::VLD1q8wb_register: 2228 case ARM::VLD1q16wb_register: 2229 case ARM::VLD1q32wb_register: 2230 case ARM::VLD1q64wb_register: 2231 case ARM::VLD1d8Twb_fixed: 2232 case ARM::VLD1d8Twb_register: 2233 case ARM::VLD1d16Twb_fixed: 2234 case ARM::VLD1d16Twb_register: 2235 case ARM::VLD1d32Twb_fixed: 2236 case ARM::VLD1d32Twb_register: 2237 case ARM::VLD1d64Twb_fixed: 2238 case ARM::VLD1d64Twb_register: 2239 case ARM::VLD1d8Qwb_fixed: 2240 case ARM::VLD1d8Qwb_register: 2241 case ARM::VLD1d16Qwb_fixed: 2242 case ARM::VLD1d16Qwb_register: 2243 case ARM::VLD1d32Qwb_fixed: 2244 case ARM::VLD1d32Qwb_register: 2245 case ARM::VLD1d64Qwb_fixed: 2246 case ARM::VLD1d64Qwb_register: 2247 case ARM::VLD2d8wb_fixed: 2248 case ARM::VLD2d16wb_fixed: 2249 case ARM::VLD2d32wb_fixed: 2250 case ARM::VLD2q8wb_fixed: 2251 case ARM::VLD2q16wb_fixed: 2252 case ARM::VLD2q32wb_fixed: 2253 case ARM::VLD2d8wb_register: 2254 case ARM::VLD2d16wb_register: 2255 case ARM::VLD2d32wb_register: 2256 case ARM::VLD2q8wb_register: 2257 case ARM::VLD2q16wb_register: 2258 case ARM::VLD2q32wb_register: 2259 case ARM::VLD2b8wb_fixed: 2260 case ARM::VLD2b16wb_fixed: 2261 case ARM::VLD2b32wb_fixed: 2262 case ARM::VLD2b8wb_register: 2263 case ARM::VLD2b16wb_register: 2264 case ARM::VLD2b32wb_register: 2265 case ARM::VLD3d8_UPD: 2266 case ARM::VLD3d16_UPD: 2267 case ARM::VLD3d32_UPD: 2268 case ARM::VLD3q8_UPD: 2269 case ARM::VLD3q16_UPD: 2270 case ARM::VLD3q32_UPD: 2271 case ARM::VLD4d8_UPD: 2272 case ARM::VLD4d16_UPD: 2273 case ARM::VLD4d32_UPD: 2274 case ARM::VLD4q8_UPD: 2275 case ARM::VLD4q16_UPD: 2276 case ARM::VLD4q32_UPD: 2277 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2278 return MCDisassembler::Fail; 2279 break; 2280 default: 2281 break; 2282 } 2283 2284 // AddrMode6 Base (register+alignment) 2285 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2286 return MCDisassembler::Fail; 2287 2288 // AddrMode6 Offset (register) 2289 switch (Inst.getOpcode()) { 2290 default: 2291 // The below have been updated to have explicit am6offset split 2292 // between fixed and register offset. For those instructions not 2293 // yet updated, we need to add an additional reg0 operand for the 2294 // fixed variant. 2295 // 2296 // The fixed offset encodes as Rm == 0xd, so we check for that. 2297 if (Rm == 0xd) { 2298 Inst.addOperand(MCOperand::CreateReg(0)); 2299 break; 2300 } 2301 // Fall through to handle the register offset variant. 2302 case ARM::VLD1d8wb_fixed: 2303 case ARM::VLD1d16wb_fixed: 2304 case ARM::VLD1d32wb_fixed: 2305 case ARM::VLD1d64wb_fixed: 2306 case ARM::VLD1d8Twb_fixed: 2307 case ARM::VLD1d16Twb_fixed: 2308 case ARM::VLD1d32Twb_fixed: 2309 case ARM::VLD1d64Twb_fixed: 2310 case ARM::VLD1d8Qwb_fixed: 2311 case ARM::VLD1d16Qwb_fixed: 2312 case ARM::VLD1d32Qwb_fixed: 2313 case ARM::VLD1d64Qwb_fixed: 2314 case ARM::VLD1d8wb_register: 2315 case ARM::VLD1d16wb_register: 2316 case ARM::VLD1d32wb_register: 2317 case ARM::VLD1d64wb_register: 2318 case ARM::VLD1q8wb_fixed: 2319 case ARM::VLD1q16wb_fixed: 2320 case ARM::VLD1q32wb_fixed: 2321 case ARM::VLD1q64wb_fixed: 2322 case ARM::VLD1q8wb_register: 2323 case ARM::VLD1q16wb_register: 2324 case ARM::VLD1q32wb_register: 2325 case ARM::VLD1q64wb_register: 2326 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2327 // variant encodes Rm == 0xf. Anything else is a register offset post- 2328 // increment and we need to add the register operand to the instruction. 2329 if (Rm != 0xD && Rm != 0xF && 2330 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2331 return MCDisassembler::Fail; 2332 break; 2333 } 2334 2335 return S; 2336 } 2337 2338 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2339 uint64_t Address, const void *Decoder) { 2340 DecodeStatus S = MCDisassembler::Success; 2341 2342 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2343 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2344 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2345 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2346 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2347 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2348 2349 // Writeback Operand 2350 switch (Inst.getOpcode()) { 2351 case ARM::VST1d8wb_fixed: 2352 case ARM::VST1d16wb_fixed: 2353 case ARM::VST1d32wb_fixed: 2354 case ARM::VST1d64wb_fixed: 2355 case ARM::VST1d8wb_register: 2356 case ARM::VST1d16wb_register: 2357 case ARM::VST1d32wb_register: 2358 case ARM::VST1d64wb_register: 2359 case ARM::VST1q8wb_fixed: 2360 case ARM::VST1q16wb_fixed: 2361 case ARM::VST1q32wb_fixed: 2362 case ARM::VST1q64wb_fixed: 2363 case ARM::VST1q8wb_register: 2364 case ARM::VST1q16wb_register: 2365 case ARM::VST1q32wb_register: 2366 case ARM::VST1q64wb_register: 2367 case ARM::VST1d8Twb_fixed: 2368 case ARM::VST1d16Twb_fixed: 2369 case ARM::VST1d32Twb_fixed: 2370 case ARM::VST1d64Twb_fixed: 2371 case ARM::VST1d8Twb_register: 2372 case ARM::VST1d16Twb_register: 2373 case ARM::VST1d32Twb_register: 2374 case ARM::VST1d64Twb_register: 2375 case ARM::VST1d8Qwb_fixed: 2376 case ARM::VST1d16Qwb_fixed: 2377 case ARM::VST1d32Qwb_fixed: 2378 case ARM::VST1d64Qwb_fixed: 2379 case ARM::VST1d8Qwb_register: 2380 case ARM::VST1d16Qwb_register: 2381 case ARM::VST1d32Qwb_register: 2382 case ARM::VST1d64Qwb_register: 2383 case ARM::VST2d8wb_fixed: 2384 case ARM::VST2d16wb_fixed: 2385 case ARM::VST2d32wb_fixed: 2386 case ARM::VST2d8wb_register: 2387 case ARM::VST2d16wb_register: 2388 case ARM::VST2d32wb_register: 2389 case ARM::VST2q8wb_fixed: 2390 case ARM::VST2q16wb_fixed: 2391 case ARM::VST2q32wb_fixed: 2392 case ARM::VST2q8wb_register: 2393 case ARM::VST2q16wb_register: 2394 case ARM::VST2q32wb_register: 2395 case ARM::VST2b8wb_fixed: 2396 case ARM::VST2b16wb_fixed: 2397 case ARM::VST2b32wb_fixed: 2398 case ARM::VST2b8wb_register: 2399 case ARM::VST2b16wb_register: 2400 case ARM::VST2b32wb_register: 2401 Inst.addOperand(MCOperand::CreateImm(0)); 2402 break; 2403 case ARM::VST3d8_UPD: 2404 case ARM::VST3d16_UPD: 2405 case ARM::VST3d32_UPD: 2406 case ARM::VST3q8_UPD: 2407 case ARM::VST3q16_UPD: 2408 case ARM::VST3q32_UPD: 2409 case ARM::VST4d8_UPD: 2410 case ARM::VST4d16_UPD: 2411 case ARM::VST4d32_UPD: 2412 case ARM::VST4q8_UPD: 2413 case ARM::VST4q16_UPD: 2414 case ARM::VST4q32_UPD: 2415 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 break; 2418 default: 2419 break; 2420 } 2421 2422 // AddrMode6 Base (register+alignment) 2423 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2424 return MCDisassembler::Fail; 2425 2426 // AddrMode6 Offset (register) 2427 switch (Inst.getOpcode()) { 2428 default: 2429 if (Rm == 0xD) 2430 Inst.addOperand(MCOperand::CreateReg(0)); 2431 else if (Rm != 0xF) { 2432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2433 return MCDisassembler::Fail; 2434 } 2435 break; 2436 case ARM::VST1d8wb_fixed: 2437 case ARM::VST1d16wb_fixed: 2438 case ARM::VST1d32wb_fixed: 2439 case ARM::VST1d64wb_fixed: 2440 case ARM::VST1q8wb_fixed: 2441 case ARM::VST1q16wb_fixed: 2442 case ARM::VST1q32wb_fixed: 2443 case ARM::VST1q64wb_fixed: 2444 case ARM::VST1d8Twb_fixed: 2445 case ARM::VST1d16Twb_fixed: 2446 case ARM::VST1d32Twb_fixed: 2447 case ARM::VST1d64Twb_fixed: 2448 case ARM::VST1d8Qwb_fixed: 2449 case ARM::VST1d16Qwb_fixed: 2450 case ARM::VST1d32Qwb_fixed: 2451 case ARM::VST1d64Qwb_fixed: 2452 case ARM::VST2d8wb_fixed: 2453 case ARM::VST2d16wb_fixed: 2454 case ARM::VST2d32wb_fixed: 2455 case ARM::VST2q8wb_fixed: 2456 case ARM::VST2q16wb_fixed: 2457 case ARM::VST2q32wb_fixed: 2458 case ARM::VST2b8wb_fixed: 2459 case ARM::VST2b16wb_fixed: 2460 case ARM::VST2b32wb_fixed: 2461 break; 2462 } 2463 2464 2465 // First input register 2466 switch (Inst.getOpcode()) { 2467 case ARM::VST1q16: 2468 case ARM::VST1q32: 2469 case ARM::VST1q64: 2470 case ARM::VST1q8: 2471 case ARM::VST1q16wb_fixed: 2472 case ARM::VST1q16wb_register: 2473 case ARM::VST1q32wb_fixed: 2474 case ARM::VST1q32wb_register: 2475 case ARM::VST1q64wb_fixed: 2476 case ARM::VST1q64wb_register: 2477 case ARM::VST1q8wb_fixed: 2478 case ARM::VST1q8wb_register: 2479 case ARM::VST2d16: 2480 case ARM::VST2d32: 2481 case ARM::VST2d8: 2482 case ARM::VST2d16wb_fixed: 2483 case ARM::VST2d16wb_register: 2484 case ARM::VST2d32wb_fixed: 2485 case ARM::VST2d32wb_register: 2486 case ARM::VST2d8wb_fixed: 2487 case ARM::VST2d8wb_register: 2488 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 break; 2491 case ARM::VST2b16: 2492 case ARM::VST2b32: 2493 case ARM::VST2b8: 2494 case ARM::VST2b16wb_fixed: 2495 case ARM::VST2b16wb_register: 2496 case ARM::VST2b32wb_fixed: 2497 case ARM::VST2b32wb_register: 2498 case ARM::VST2b8wb_fixed: 2499 case ARM::VST2b8wb_register: 2500 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2501 return MCDisassembler::Fail; 2502 break; 2503 default: 2504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 } 2507 2508 // Second input register 2509 switch (Inst.getOpcode()) { 2510 case ARM::VST3d8: 2511 case ARM::VST3d16: 2512 case ARM::VST3d32: 2513 case ARM::VST3d8_UPD: 2514 case ARM::VST3d16_UPD: 2515 case ARM::VST3d32_UPD: 2516 case ARM::VST4d8: 2517 case ARM::VST4d16: 2518 case ARM::VST4d32: 2519 case ARM::VST4d8_UPD: 2520 case ARM::VST4d16_UPD: 2521 case ARM::VST4d32_UPD: 2522 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2523 return MCDisassembler::Fail; 2524 break; 2525 case ARM::VST3q8: 2526 case ARM::VST3q16: 2527 case ARM::VST3q32: 2528 case ARM::VST3q8_UPD: 2529 case ARM::VST3q16_UPD: 2530 case ARM::VST3q32_UPD: 2531 case ARM::VST4q8: 2532 case ARM::VST4q16: 2533 case ARM::VST4q32: 2534 case ARM::VST4q8_UPD: 2535 case ARM::VST4q16_UPD: 2536 case ARM::VST4q32_UPD: 2537 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 break; 2540 default: 2541 break; 2542 } 2543 2544 // Third input register 2545 switch (Inst.getOpcode()) { 2546 case ARM::VST3d8: 2547 case ARM::VST3d16: 2548 case ARM::VST3d32: 2549 case ARM::VST3d8_UPD: 2550 case ARM::VST3d16_UPD: 2551 case ARM::VST3d32_UPD: 2552 case ARM::VST4d8: 2553 case ARM::VST4d16: 2554 case ARM::VST4d32: 2555 case ARM::VST4d8_UPD: 2556 case ARM::VST4d16_UPD: 2557 case ARM::VST4d32_UPD: 2558 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2559 return MCDisassembler::Fail; 2560 break; 2561 case ARM::VST3q8: 2562 case ARM::VST3q16: 2563 case ARM::VST3q32: 2564 case ARM::VST3q8_UPD: 2565 case ARM::VST3q16_UPD: 2566 case ARM::VST3q32_UPD: 2567 case ARM::VST4q8: 2568 case ARM::VST4q16: 2569 case ARM::VST4q32: 2570 case ARM::VST4q8_UPD: 2571 case ARM::VST4q16_UPD: 2572 case ARM::VST4q32_UPD: 2573 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2574 return MCDisassembler::Fail; 2575 break; 2576 default: 2577 break; 2578 } 2579 2580 // Fourth input register 2581 switch (Inst.getOpcode()) { 2582 case ARM::VST4d8: 2583 case ARM::VST4d16: 2584 case ARM::VST4d32: 2585 case ARM::VST4d8_UPD: 2586 case ARM::VST4d16_UPD: 2587 case ARM::VST4d32_UPD: 2588 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2589 return MCDisassembler::Fail; 2590 break; 2591 case ARM::VST4q8: 2592 case ARM::VST4q16: 2593 case ARM::VST4q32: 2594 case ARM::VST4q8_UPD: 2595 case ARM::VST4q16_UPD: 2596 case ARM::VST4q32_UPD: 2597 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 break; 2600 default: 2601 break; 2602 } 2603 2604 return S; 2605 } 2606 2607 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2608 uint64_t Address, const void *Decoder) { 2609 DecodeStatus S = MCDisassembler::Success; 2610 2611 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2612 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2613 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2614 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2615 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2616 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2617 2618 align *= (1 << size); 2619 2620 switch (Inst.getOpcode()) { 2621 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2622 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2623 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2624 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2625 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2626 return MCDisassembler::Fail; 2627 break; 2628 default: 2629 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2630 return MCDisassembler::Fail; 2631 break; 2632 } 2633 if (Rm != 0xF) { 2634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2635 return MCDisassembler::Fail; 2636 } 2637 2638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2639 return MCDisassembler::Fail; 2640 Inst.addOperand(MCOperand::CreateImm(align)); 2641 2642 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2643 // variant encodes Rm == 0xf. Anything else is a register offset post- 2644 // increment and we need to add the register operand to the instruction. 2645 if (Rm != 0xD && Rm != 0xF && 2646 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2647 return MCDisassembler::Fail; 2648 2649 return S; 2650 } 2651 2652 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2653 uint64_t Address, const void *Decoder) { 2654 DecodeStatus S = MCDisassembler::Success; 2655 2656 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2657 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2658 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2659 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2660 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2661 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2662 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2663 align *= 2*size; 2664 2665 switch (Inst.getOpcode()) { 2666 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2667 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2668 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2669 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2670 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 break; 2673 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2674 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2675 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2676 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2677 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 break; 2680 default: 2681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 break; 2684 } 2685 2686 if (Rm != 0xF) 2687 Inst.addOperand(MCOperand::CreateImm(0)); 2688 2689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 Inst.addOperand(MCOperand::CreateImm(align)); 2692 2693 if (Rm == 0xD) 2694 Inst.addOperand(MCOperand::CreateReg(0)); 2695 else if (Rm != 0xF) { 2696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 } 2699 2700 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 2703 return S; 2704 } 2705 2706 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2707 uint64_t Address, const void *Decoder) { 2708 DecodeStatus S = MCDisassembler::Success; 2709 2710 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2711 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2712 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2713 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2714 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2715 2716 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2717 return MCDisassembler::Fail; 2718 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2721 return MCDisassembler::Fail; 2722 if (Rm != 0xF) { 2723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 } 2726 2727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2728 return MCDisassembler::Fail; 2729 Inst.addOperand(MCOperand::CreateImm(0)); 2730 2731 if (Rm == 0xD) 2732 Inst.addOperand(MCOperand::CreateReg(0)); 2733 else if (Rm != 0xF) { 2734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2735 return MCDisassembler::Fail; 2736 } 2737 2738 return S; 2739 } 2740 2741 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2742 uint64_t Address, const void *Decoder) { 2743 DecodeStatus S = MCDisassembler::Success; 2744 2745 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2746 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2747 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2748 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2749 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2750 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2751 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2752 2753 if (size == 0x3) { 2754 size = 4; 2755 align = 16; 2756 } else { 2757 if (size == 2) { 2758 size = 1 << size; 2759 align *= 8; 2760 } else { 2761 size = 1 << size; 2762 align *= 4*size; 2763 } 2764 } 2765 2766 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2767 return MCDisassembler::Fail; 2768 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2769 return MCDisassembler::Fail; 2770 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2771 return MCDisassembler::Fail; 2772 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2773 return MCDisassembler::Fail; 2774 if (Rm != 0xF) { 2775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2776 return MCDisassembler::Fail; 2777 } 2778 2779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 Inst.addOperand(MCOperand::CreateImm(align)); 2782 2783 if (Rm == 0xD) 2784 Inst.addOperand(MCOperand::CreateReg(0)); 2785 else if (Rm != 0xF) { 2786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 } 2789 2790 return S; 2791 } 2792 2793 static DecodeStatus 2794 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2795 uint64_t Address, const void *Decoder) { 2796 DecodeStatus S = MCDisassembler::Success; 2797 2798 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2799 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2800 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2801 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2802 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2803 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2804 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2805 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2806 2807 if (Q) { 2808 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 } else { 2811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 } 2814 2815 Inst.addOperand(MCOperand::CreateImm(imm)); 2816 2817 switch (Inst.getOpcode()) { 2818 case ARM::VORRiv4i16: 2819 case ARM::VORRiv2i32: 2820 case ARM::VBICiv4i16: 2821 case ARM::VBICiv2i32: 2822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 break; 2825 case ARM::VORRiv8i16: 2826 case ARM::VORRiv4i32: 2827 case ARM::VBICiv8i16: 2828 case ARM::VBICiv4i32: 2829 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2830 return MCDisassembler::Fail; 2831 break; 2832 default: 2833 break; 2834 } 2835 2836 return S; 2837 } 2838 2839 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2840 uint64_t Address, const void *Decoder) { 2841 DecodeStatus S = MCDisassembler::Success; 2842 2843 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2844 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2845 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2846 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2847 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2848 2849 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2850 return MCDisassembler::Fail; 2851 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2852 return MCDisassembler::Fail; 2853 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2854 2855 return S; 2856 } 2857 2858 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2859 uint64_t Address, const void *Decoder) { 2860 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2861 return MCDisassembler::Success; 2862 } 2863 2864 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2865 uint64_t Address, const void *Decoder) { 2866 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2867 return MCDisassembler::Success; 2868 } 2869 2870 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2871 uint64_t Address, const void *Decoder) { 2872 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2873 return MCDisassembler::Success; 2874 } 2875 2876 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2877 uint64_t Address, const void *Decoder) { 2878 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2879 return MCDisassembler::Success; 2880 } 2881 2882 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2883 uint64_t Address, const void *Decoder) { 2884 DecodeStatus S = MCDisassembler::Success; 2885 2886 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2887 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2888 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2889 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2890 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2891 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2892 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2893 2894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 if (op) { 2897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2898 return MCDisassembler::Fail; // Writeback 2899 } 2900 2901 switch (Inst.getOpcode()) { 2902 case ARM::VTBL2: 2903 case ARM::VTBX2: 2904 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2905 return MCDisassembler::Fail; 2906 break; 2907 default: 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 } 2911 2912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2913 return MCDisassembler::Fail; 2914 2915 return S; 2916 } 2917 2918 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2919 uint64_t Address, const void *Decoder) { 2920 DecodeStatus S = MCDisassembler::Success; 2921 2922 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2923 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2924 2925 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 2928 switch(Inst.getOpcode()) { 2929 default: 2930 return MCDisassembler::Fail; 2931 case ARM::tADR: 2932 break; // tADR does not explicitly represent the PC as an operand. 2933 case ARM::tADDrSPi: 2934 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2935 break; 2936 } 2937 2938 Inst.addOperand(MCOperand::CreateImm(imm)); 2939 return S; 2940 } 2941 2942 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 2943 uint64_t Address, const void *Decoder) { 2944 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2945 return MCDisassembler::Success; 2946 } 2947 2948 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 2949 uint64_t Address, const void *Decoder) { 2950 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2951 return MCDisassembler::Success; 2952 } 2953 2954 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 2955 uint64_t Address, const void *Decoder) { 2956 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2957 return MCDisassembler::Success; 2958 } 2959 2960 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 2961 uint64_t Address, const void *Decoder) { 2962 DecodeStatus S = MCDisassembler::Success; 2963 2964 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2965 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2966 2967 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2968 return MCDisassembler::Fail; 2969 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2970 return MCDisassembler::Fail; 2971 2972 return S; 2973 } 2974 2975 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 2976 uint64_t Address, const void *Decoder) { 2977 DecodeStatus S = MCDisassembler::Success; 2978 2979 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2980 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2981 2982 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 Inst.addOperand(MCOperand::CreateImm(imm)); 2985 2986 return S; 2987 } 2988 2989 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 2990 uint64_t Address, const void *Decoder) { 2991 unsigned imm = Val << 2; 2992 2993 Inst.addOperand(MCOperand::CreateImm(imm)); 2994 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2995 2996 return MCDisassembler::Success; 2997 } 2998 2999 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3000 uint64_t Address, const void *Decoder) { 3001 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3002 Inst.addOperand(MCOperand::CreateImm(Val)); 3003 3004 return MCDisassembler::Success; 3005 } 3006 3007 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3008 uint64_t Address, const void *Decoder) { 3009 DecodeStatus S = MCDisassembler::Success; 3010 3011 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3012 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3013 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3014 3015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3018 return MCDisassembler::Fail; 3019 Inst.addOperand(MCOperand::CreateImm(imm)); 3020 3021 return S; 3022 } 3023 3024 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3025 uint64_t Address, const void *Decoder) { 3026 DecodeStatus S = MCDisassembler::Success; 3027 3028 switch (Inst.getOpcode()) { 3029 case ARM::t2PLDs: 3030 case ARM::t2PLDWs: 3031 case ARM::t2PLIs: 3032 break; 3033 default: { 3034 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3035 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 } 3038 } 3039 3040 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3041 if (Rn == 0xF) { 3042 switch (Inst.getOpcode()) { 3043 case ARM::t2LDRBs: 3044 Inst.setOpcode(ARM::t2LDRBpci); 3045 break; 3046 case ARM::t2LDRHs: 3047 Inst.setOpcode(ARM::t2LDRHpci); 3048 break; 3049 case ARM::t2LDRSHs: 3050 Inst.setOpcode(ARM::t2LDRSHpci); 3051 break; 3052 case ARM::t2LDRSBs: 3053 Inst.setOpcode(ARM::t2LDRSBpci); 3054 break; 3055 case ARM::t2PLDs: 3056 Inst.setOpcode(ARM::t2PLDi12); 3057 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3058 break; 3059 default: 3060 return MCDisassembler::Fail; 3061 } 3062 3063 int imm = fieldFromInstruction32(Insn, 0, 12); 3064 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3065 Inst.addOperand(MCOperand::CreateImm(imm)); 3066 3067 return S; 3068 } 3069 3070 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3071 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3072 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3073 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 3076 return S; 3077 } 3078 3079 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3080 uint64_t Address, const void *Decoder) { 3081 int imm = Val & 0xFF; 3082 if (!(Val & 0x100)) imm *= -1; 3083 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3084 3085 return MCDisassembler::Success; 3086 } 3087 3088 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3089 uint64_t Address, const void *Decoder) { 3090 DecodeStatus S = MCDisassembler::Success; 3091 3092 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3093 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3094 3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3098 return MCDisassembler::Fail; 3099 3100 return S; 3101 } 3102 3103 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3104 uint64_t Address, const void *Decoder) { 3105 DecodeStatus S = MCDisassembler::Success; 3106 3107 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3108 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3109 3110 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3111 return MCDisassembler::Fail; 3112 3113 Inst.addOperand(MCOperand::CreateImm(imm)); 3114 3115 return S; 3116 } 3117 3118 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3119 uint64_t Address, const void *Decoder) { 3120 int imm = Val & 0xFF; 3121 if (Val == 0) 3122 imm = INT32_MIN; 3123 else if (!(Val & 0x100)) 3124 imm *= -1; 3125 Inst.addOperand(MCOperand::CreateImm(imm)); 3126 3127 return MCDisassembler::Success; 3128 } 3129 3130 3131 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3132 uint64_t Address, const void *Decoder) { 3133 DecodeStatus S = MCDisassembler::Success; 3134 3135 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3136 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3137 3138 // Some instructions always use an additive offset. 3139 switch (Inst.getOpcode()) { 3140 case ARM::t2LDRT: 3141 case ARM::t2LDRBT: 3142 case ARM::t2LDRHT: 3143 case ARM::t2LDRSBT: 3144 case ARM::t2LDRSHT: 3145 case ARM::t2STRT: 3146 case ARM::t2STRBT: 3147 case ARM::t2STRHT: 3148 imm |= 0x100; 3149 break; 3150 default: 3151 break; 3152 } 3153 3154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3155 return MCDisassembler::Fail; 3156 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3157 return MCDisassembler::Fail; 3158 3159 return S; 3160 } 3161 3162 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3163 uint64_t Address, const void *Decoder) { 3164 DecodeStatus S = MCDisassembler::Success; 3165 3166 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3167 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3168 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3169 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3170 addr |= Rn << 9; 3171 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3172 3173 if (!load) { 3174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3175 return MCDisassembler::Fail; 3176 } 3177 3178 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3179 return MCDisassembler::Fail; 3180 3181 if (load) { 3182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3183 return MCDisassembler::Fail; 3184 } 3185 3186 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 3189 return S; 3190 } 3191 3192 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3193 uint64_t Address, const void *Decoder) { 3194 DecodeStatus S = MCDisassembler::Success; 3195 3196 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3197 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3198 3199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3200 return MCDisassembler::Fail; 3201 Inst.addOperand(MCOperand::CreateImm(imm)); 3202 3203 return S; 3204 } 3205 3206 3207 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3208 uint64_t Address, const void *Decoder) { 3209 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3210 3211 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3212 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3213 Inst.addOperand(MCOperand::CreateImm(imm)); 3214 3215 return MCDisassembler::Success; 3216 } 3217 3218 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3219 uint64_t Address, const void *Decoder) { 3220 DecodeStatus S = MCDisassembler::Success; 3221 3222 if (Inst.getOpcode() == ARM::tADDrSP) { 3223 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3224 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3225 3226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3231 } else if (Inst.getOpcode() == ARM::tADDspr) { 3232 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3233 3234 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3235 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3237 return MCDisassembler::Fail; 3238 } 3239 3240 return S; 3241 } 3242 3243 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3244 uint64_t Address, const void *Decoder) { 3245 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3246 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3247 3248 Inst.addOperand(MCOperand::CreateImm(imod)); 3249 Inst.addOperand(MCOperand::CreateImm(flags)); 3250 3251 return MCDisassembler::Success; 3252 } 3253 3254 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3255 uint64_t Address, const void *Decoder) { 3256 DecodeStatus S = MCDisassembler::Success; 3257 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3258 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3259 3260 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 Inst.addOperand(MCOperand::CreateImm(add)); 3263 3264 return S; 3265 } 3266 3267 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3268 uint64_t Address, const void *Decoder) { 3269 if (!tryAddingSymbolicOperand(Address, 3270 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3271 true, 4, Inst, Decoder)) 3272 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3273 return MCDisassembler::Success; 3274 } 3275 3276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3277 uint64_t Address, const void *Decoder) { 3278 if (Val == 0xA || Val == 0xB) 3279 return MCDisassembler::Fail; 3280 3281 Inst.addOperand(MCOperand::CreateImm(Val)); 3282 return MCDisassembler::Success; 3283 } 3284 3285 static DecodeStatus 3286 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3287 uint64_t Address, const void *Decoder) { 3288 DecodeStatus S = MCDisassembler::Success; 3289 3290 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3291 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3292 3293 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3297 return MCDisassembler::Fail; 3298 return S; 3299 } 3300 3301 static DecodeStatus 3302 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3303 uint64_t Address, const void *Decoder) { 3304 DecodeStatus S = MCDisassembler::Success; 3305 3306 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3307 if (pred == 0xE || pred == 0xF) { 3308 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3309 switch (opc) { 3310 default: 3311 return MCDisassembler::Fail; 3312 case 0xf3bf8f4: 3313 Inst.setOpcode(ARM::t2DSB); 3314 break; 3315 case 0xf3bf8f5: 3316 Inst.setOpcode(ARM::t2DMB); 3317 break; 3318 case 0xf3bf8f6: 3319 Inst.setOpcode(ARM::t2ISB); 3320 break; 3321 } 3322 3323 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3324 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3325 } 3326 3327 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3328 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3329 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3330 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3331 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3332 3333 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 3338 return S; 3339 } 3340 3341 // Decode a shifted immediate operand. These basically consist 3342 // of an 8-bit value, and a 4-bit directive that specifies either 3343 // a splat operation or a rotation. 3344 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3345 uint64_t Address, const void *Decoder) { 3346 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3347 if (ctrl == 0) { 3348 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3349 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3350 switch (byte) { 3351 case 0: 3352 Inst.addOperand(MCOperand::CreateImm(imm)); 3353 break; 3354 case 1: 3355 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3356 break; 3357 case 2: 3358 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3359 break; 3360 case 3: 3361 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3362 (imm << 8) | imm)); 3363 break; 3364 } 3365 } else { 3366 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3367 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3368 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3369 Inst.addOperand(MCOperand::CreateImm(imm)); 3370 } 3371 3372 return MCDisassembler::Success; 3373 } 3374 3375 static DecodeStatus 3376 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3377 uint64_t Address, const void *Decoder){ 3378 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3379 return MCDisassembler::Success; 3380 } 3381 3382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3383 uint64_t Address, const void *Decoder){ 3384 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3385 true, 4, Inst, Decoder)) 3386 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3387 return MCDisassembler::Success; 3388 } 3389 3390 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3391 uint64_t Address, const void *Decoder) { 3392 switch (Val) { 3393 default: 3394 return MCDisassembler::Fail; 3395 case 0xF: // SY 3396 case 0xE: // ST 3397 case 0xB: // ISH 3398 case 0xA: // ISHST 3399 case 0x7: // NSH 3400 case 0x6: // NSHST 3401 case 0x3: // OSH 3402 case 0x2: // OSHST 3403 break; 3404 } 3405 3406 Inst.addOperand(MCOperand::CreateImm(Val)); 3407 return MCDisassembler::Success; 3408 } 3409 3410 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3411 uint64_t Address, const void *Decoder) { 3412 if (!Val) return MCDisassembler::Fail; 3413 Inst.addOperand(MCOperand::CreateImm(Val)); 3414 return MCDisassembler::Success; 3415 } 3416 3417 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3418 uint64_t Address, const void *Decoder) { 3419 DecodeStatus S = MCDisassembler::Success; 3420 3421 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3422 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3423 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3424 3425 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3426 3427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3428 return MCDisassembler::Fail; 3429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3430 return MCDisassembler::Fail; 3431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 3436 return S; 3437 } 3438 3439 3440 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3441 uint64_t Address, const void *Decoder){ 3442 DecodeStatus S = MCDisassembler::Success; 3443 3444 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3445 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3446 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3447 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3448 3449 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3450 return MCDisassembler::Fail; 3451 3452 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3453 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3454 3455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 3464 return S; 3465 } 3466 3467 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3468 uint64_t Address, const void *Decoder) { 3469 DecodeStatus S = MCDisassembler::Success; 3470 3471 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3472 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3473 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3474 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3475 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3476 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3477 3478 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3479 3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3481 return MCDisassembler::Fail; 3482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3483 return MCDisassembler::Fail; 3484 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 3489 return S; 3490 } 3491 3492 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3493 uint64_t Address, const void *Decoder) { 3494 DecodeStatus S = MCDisassembler::Success; 3495 3496 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3497 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3498 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3499 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3500 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3501 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3502 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3503 3504 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3505 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3506 3507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3510 return MCDisassembler::Fail; 3511 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 3516 return S; 3517 } 3518 3519 3520 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3521 uint64_t Address, const void *Decoder) { 3522 DecodeStatus S = MCDisassembler::Success; 3523 3524 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3525 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3526 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3527 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3528 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3529 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3530 3531 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3532 3533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3534 return MCDisassembler::Fail; 3535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3536 return MCDisassembler::Fail; 3537 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3538 return MCDisassembler::Fail; 3539 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3540 return MCDisassembler::Fail; 3541 3542 return S; 3543 } 3544 3545 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3546 uint64_t Address, const void *Decoder) { 3547 DecodeStatus S = MCDisassembler::Success; 3548 3549 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3550 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3551 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3552 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3553 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3554 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3555 3556 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3557 3558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3565 return MCDisassembler::Fail; 3566 3567 return S; 3568 } 3569 3570 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3571 uint64_t Address, const void *Decoder) { 3572 DecodeStatus S = MCDisassembler::Success; 3573 3574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3576 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3577 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3578 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3579 3580 unsigned align = 0; 3581 unsigned index = 0; 3582 switch (size) { 3583 default: 3584 return MCDisassembler::Fail; 3585 case 0: 3586 if (fieldFromInstruction32(Insn, 4, 1)) 3587 return MCDisassembler::Fail; // UNDEFINED 3588 index = fieldFromInstruction32(Insn, 5, 3); 3589 break; 3590 case 1: 3591 if (fieldFromInstruction32(Insn, 5, 1)) 3592 return MCDisassembler::Fail; // UNDEFINED 3593 index = fieldFromInstruction32(Insn, 6, 2); 3594 if (fieldFromInstruction32(Insn, 4, 1)) 3595 align = 2; 3596 break; 3597 case 2: 3598 if (fieldFromInstruction32(Insn, 6, 1)) 3599 return MCDisassembler::Fail; // UNDEFINED 3600 index = fieldFromInstruction32(Insn, 7, 1); 3601 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3602 align = 4; 3603 } 3604 3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 if (Rm != 0xF) { // Writeback 3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 } 3611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 Inst.addOperand(MCOperand::CreateImm(align)); 3614 if (Rm != 0xF) { 3615 if (Rm != 0xD) { 3616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3617 return MCDisassembler::Fail; 3618 } else 3619 Inst.addOperand(MCOperand::CreateReg(0)); 3620 } 3621 3622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 Inst.addOperand(MCOperand::CreateImm(index)); 3625 3626 return S; 3627 } 3628 3629 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3630 uint64_t Address, const void *Decoder) { 3631 DecodeStatus S = MCDisassembler::Success; 3632 3633 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3634 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3635 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3636 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3637 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3638 3639 unsigned align = 0; 3640 unsigned index = 0; 3641 switch (size) { 3642 default: 3643 return MCDisassembler::Fail; 3644 case 0: 3645 if (fieldFromInstruction32(Insn, 4, 1)) 3646 return MCDisassembler::Fail; // UNDEFINED 3647 index = fieldFromInstruction32(Insn, 5, 3); 3648 break; 3649 case 1: 3650 if (fieldFromInstruction32(Insn, 5, 1)) 3651 return MCDisassembler::Fail; // UNDEFINED 3652 index = fieldFromInstruction32(Insn, 6, 2); 3653 if (fieldFromInstruction32(Insn, 4, 1)) 3654 align = 2; 3655 break; 3656 case 2: 3657 if (fieldFromInstruction32(Insn, 6, 1)) 3658 return MCDisassembler::Fail; // UNDEFINED 3659 index = fieldFromInstruction32(Insn, 7, 1); 3660 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3661 align = 4; 3662 } 3663 3664 if (Rm != 0xF) { // Writeback 3665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3666 return MCDisassembler::Fail; 3667 } 3668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 Inst.addOperand(MCOperand::CreateImm(align)); 3671 if (Rm != 0xF) { 3672 if (Rm != 0xD) { 3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 } else 3676 Inst.addOperand(MCOperand::CreateReg(0)); 3677 } 3678 3679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 Inst.addOperand(MCOperand::CreateImm(index)); 3682 3683 return S; 3684 } 3685 3686 3687 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3688 uint64_t Address, const void *Decoder) { 3689 DecodeStatus S = MCDisassembler::Success; 3690 3691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3692 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3693 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3694 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3695 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3696 3697 unsigned align = 0; 3698 unsigned index = 0; 3699 unsigned inc = 1; 3700 switch (size) { 3701 default: 3702 return MCDisassembler::Fail; 3703 case 0: 3704 index = fieldFromInstruction32(Insn, 5, 3); 3705 if (fieldFromInstruction32(Insn, 4, 1)) 3706 align = 2; 3707 break; 3708 case 1: 3709 index = fieldFromInstruction32(Insn, 6, 2); 3710 if (fieldFromInstruction32(Insn, 4, 1)) 3711 align = 4; 3712 if (fieldFromInstruction32(Insn, 5, 1)) 3713 inc = 2; 3714 break; 3715 case 2: 3716 if (fieldFromInstruction32(Insn, 5, 1)) 3717 return MCDisassembler::Fail; // UNDEFINED 3718 index = fieldFromInstruction32(Insn, 7, 1); 3719 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3720 align = 8; 3721 if (fieldFromInstruction32(Insn, 6, 1)) 3722 inc = 2; 3723 break; 3724 } 3725 3726 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 if (Rm != 0xF) { // Writeback 3731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 } 3734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 Inst.addOperand(MCOperand::CreateImm(align)); 3737 if (Rm != 0xF) { 3738 if (Rm != 0xD) { 3739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 } else 3742 Inst.addOperand(MCOperand::CreateReg(0)); 3743 } 3744 3745 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 Inst.addOperand(MCOperand::CreateImm(index)); 3750 3751 return S; 3752 } 3753 3754 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3755 uint64_t Address, const void *Decoder) { 3756 DecodeStatus S = MCDisassembler::Success; 3757 3758 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3759 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3760 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3761 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3762 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3763 3764 unsigned align = 0; 3765 unsigned index = 0; 3766 unsigned inc = 1; 3767 switch (size) { 3768 default: 3769 return MCDisassembler::Fail; 3770 case 0: 3771 index = fieldFromInstruction32(Insn, 5, 3); 3772 if (fieldFromInstruction32(Insn, 4, 1)) 3773 align = 2; 3774 break; 3775 case 1: 3776 index = fieldFromInstruction32(Insn, 6, 2); 3777 if (fieldFromInstruction32(Insn, 4, 1)) 3778 align = 4; 3779 if (fieldFromInstruction32(Insn, 5, 1)) 3780 inc = 2; 3781 break; 3782 case 2: 3783 if (fieldFromInstruction32(Insn, 5, 1)) 3784 return MCDisassembler::Fail; // UNDEFINED 3785 index = fieldFromInstruction32(Insn, 7, 1); 3786 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3787 align = 8; 3788 if (fieldFromInstruction32(Insn, 6, 1)) 3789 inc = 2; 3790 break; 3791 } 3792 3793 if (Rm != 0xF) { // Writeback 3794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3795 return MCDisassembler::Fail; 3796 } 3797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3798 return MCDisassembler::Fail; 3799 Inst.addOperand(MCOperand::CreateImm(align)); 3800 if (Rm != 0xF) { 3801 if (Rm != 0xD) { 3802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3803 return MCDisassembler::Fail; 3804 } else 3805 Inst.addOperand(MCOperand::CreateReg(0)); 3806 } 3807 3808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 Inst.addOperand(MCOperand::CreateImm(index)); 3813 3814 return S; 3815 } 3816 3817 3818 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3819 uint64_t Address, const void *Decoder) { 3820 DecodeStatus S = MCDisassembler::Success; 3821 3822 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3823 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3824 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3825 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3826 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3827 3828 unsigned align = 0; 3829 unsigned index = 0; 3830 unsigned inc = 1; 3831 switch (size) { 3832 default: 3833 return MCDisassembler::Fail; 3834 case 0: 3835 if (fieldFromInstruction32(Insn, 4, 1)) 3836 return MCDisassembler::Fail; // UNDEFINED 3837 index = fieldFromInstruction32(Insn, 5, 3); 3838 break; 3839 case 1: 3840 if (fieldFromInstruction32(Insn, 4, 1)) 3841 return MCDisassembler::Fail; // UNDEFINED 3842 index = fieldFromInstruction32(Insn, 6, 2); 3843 if (fieldFromInstruction32(Insn, 5, 1)) 3844 inc = 2; 3845 break; 3846 case 2: 3847 if (fieldFromInstruction32(Insn, 4, 2)) 3848 return MCDisassembler::Fail; // UNDEFINED 3849 index = fieldFromInstruction32(Insn, 7, 1); 3850 if (fieldFromInstruction32(Insn, 6, 1)) 3851 inc = 2; 3852 break; 3853 } 3854 3855 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3858 return MCDisassembler::Fail; 3859 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3860 return MCDisassembler::Fail; 3861 3862 if (Rm != 0xF) { // Writeback 3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 } 3866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3867 return MCDisassembler::Fail; 3868 Inst.addOperand(MCOperand::CreateImm(align)); 3869 if (Rm != 0xF) { 3870 if (Rm != 0xD) { 3871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 } else 3874 Inst.addOperand(MCOperand::CreateReg(0)); 3875 } 3876 3877 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3880 return MCDisassembler::Fail; 3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 Inst.addOperand(MCOperand::CreateImm(index)); 3884 3885 return S; 3886 } 3887 3888 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 3889 uint64_t Address, const void *Decoder) { 3890 DecodeStatus S = MCDisassembler::Success; 3891 3892 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3893 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3894 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3895 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3896 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3897 3898 unsigned align = 0; 3899 unsigned index = 0; 3900 unsigned inc = 1; 3901 switch (size) { 3902 default: 3903 return MCDisassembler::Fail; 3904 case 0: 3905 if (fieldFromInstruction32(Insn, 4, 1)) 3906 return MCDisassembler::Fail; // UNDEFINED 3907 index = fieldFromInstruction32(Insn, 5, 3); 3908 break; 3909 case 1: 3910 if (fieldFromInstruction32(Insn, 4, 1)) 3911 return MCDisassembler::Fail; // UNDEFINED 3912 index = fieldFromInstruction32(Insn, 6, 2); 3913 if (fieldFromInstruction32(Insn, 5, 1)) 3914 inc = 2; 3915 break; 3916 case 2: 3917 if (fieldFromInstruction32(Insn, 4, 2)) 3918 return MCDisassembler::Fail; // UNDEFINED 3919 index = fieldFromInstruction32(Insn, 7, 1); 3920 if (fieldFromInstruction32(Insn, 6, 1)) 3921 inc = 2; 3922 break; 3923 } 3924 3925 if (Rm != 0xF) { // Writeback 3926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3927 return MCDisassembler::Fail; 3928 } 3929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3930 return MCDisassembler::Fail; 3931 Inst.addOperand(MCOperand::CreateImm(align)); 3932 if (Rm != 0xF) { 3933 if (Rm != 0xD) { 3934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3935 return MCDisassembler::Fail; 3936 } else 3937 Inst.addOperand(MCOperand::CreateReg(0)); 3938 } 3939 3940 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3941 return MCDisassembler::Fail; 3942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3943 return MCDisassembler::Fail; 3944 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 Inst.addOperand(MCOperand::CreateImm(index)); 3947 3948 return S; 3949 } 3950 3951 3952 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 3953 uint64_t Address, const void *Decoder) { 3954 DecodeStatus S = MCDisassembler::Success; 3955 3956 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3957 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3958 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3959 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3960 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3961 3962 unsigned align = 0; 3963 unsigned index = 0; 3964 unsigned inc = 1; 3965 switch (size) { 3966 default: 3967 return MCDisassembler::Fail; 3968 case 0: 3969 if (fieldFromInstruction32(Insn, 4, 1)) 3970 align = 4; 3971 index = fieldFromInstruction32(Insn, 5, 3); 3972 break; 3973 case 1: 3974 if (fieldFromInstruction32(Insn, 4, 1)) 3975 align = 8; 3976 index = fieldFromInstruction32(Insn, 6, 2); 3977 if (fieldFromInstruction32(Insn, 5, 1)) 3978 inc = 2; 3979 break; 3980 case 2: 3981 if (fieldFromInstruction32(Insn, 4, 2)) 3982 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3983 index = fieldFromInstruction32(Insn, 7, 1); 3984 if (fieldFromInstruction32(Insn, 6, 1)) 3985 inc = 2; 3986 break; 3987 } 3988 3989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3990 return MCDisassembler::Fail; 3991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3992 return MCDisassembler::Fail; 3993 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 3998 if (Rm != 0xF) { // Writeback 3999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 } 4002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 Inst.addOperand(MCOperand::CreateImm(align)); 4005 if (Rm != 0xF) { 4006 if (Rm != 0xD) { 4007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 } else 4010 Inst.addOperand(MCOperand::CreateReg(0)); 4011 } 4012 4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 Inst.addOperand(MCOperand::CreateImm(index)); 4022 4023 return S; 4024 } 4025 4026 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4027 uint64_t Address, const void *Decoder) { 4028 DecodeStatus S = MCDisassembler::Success; 4029 4030 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4031 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4032 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4033 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4034 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4035 4036 unsigned align = 0; 4037 unsigned index = 0; 4038 unsigned inc = 1; 4039 switch (size) { 4040 default: 4041 return MCDisassembler::Fail; 4042 case 0: 4043 if (fieldFromInstruction32(Insn, 4, 1)) 4044 align = 4; 4045 index = fieldFromInstruction32(Insn, 5, 3); 4046 break; 4047 case 1: 4048 if (fieldFromInstruction32(Insn, 4, 1)) 4049 align = 8; 4050 index = fieldFromInstruction32(Insn, 6, 2); 4051 if (fieldFromInstruction32(Insn, 5, 1)) 4052 inc = 2; 4053 break; 4054 case 2: 4055 if (fieldFromInstruction32(Insn, 4, 2)) 4056 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4057 index = fieldFromInstruction32(Insn, 7, 1); 4058 if (fieldFromInstruction32(Insn, 6, 1)) 4059 inc = 2; 4060 break; 4061 } 4062 4063 if (Rm != 0xF) { // Writeback 4064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4065 return MCDisassembler::Fail; 4066 } 4067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4068 return MCDisassembler::Fail; 4069 Inst.addOperand(MCOperand::CreateImm(align)); 4070 if (Rm != 0xF) { 4071 if (Rm != 0xD) { 4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4073 return MCDisassembler::Fail; 4074 } else 4075 Inst.addOperand(MCOperand::CreateReg(0)); 4076 } 4077 4078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4079 return MCDisassembler::Fail; 4080 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4081 return MCDisassembler::Fail; 4082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4085 return MCDisassembler::Fail; 4086 Inst.addOperand(MCOperand::CreateImm(index)); 4087 4088 return S; 4089 } 4090 4091 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4092 uint64_t Address, const void *Decoder) { 4093 DecodeStatus S = MCDisassembler::Success; 4094 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4095 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4096 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4097 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4098 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4099 4100 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4101 S = MCDisassembler::SoftFail; 4102 4103 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4104 return MCDisassembler::Fail; 4105 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4110 return MCDisassembler::Fail; 4111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4112 return MCDisassembler::Fail; 4113 4114 return S; 4115 } 4116 4117 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4118 uint64_t Address, const void *Decoder) { 4119 DecodeStatus S = MCDisassembler::Success; 4120 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4121 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4122 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4123 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4124 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4125 4126 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4127 S = MCDisassembler::SoftFail; 4128 4129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4130 return MCDisassembler::Fail; 4131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4132 return MCDisassembler::Fail; 4133 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4134 return MCDisassembler::Fail; 4135 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4136 return MCDisassembler::Fail; 4137 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4138 return MCDisassembler::Fail; 4139 4140 return S; 4141 } 4142 4143 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4144 uint64_t Address, const void *Decoder) { 4145 DecodeStatus S = MCDisassembler::Success; 4146 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4147 // The InstPrinter needs to have the low bit of the predicate in 4148 // the mask operand to be able to print it properly. 4149 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4150 4151 if (pred == 0xF) { 4152 pred = 0xE; 4153 S = MCDisassembler::SoftFail; 4154 } 4155 4156 if ((mask & 0xF) == 0) { 4157 // Preserve the high bit of the mask, which is the low bit of 4158 // the predicate. 4159 mask &= 0x10; 4160 mask |= 0x8; 4161 S = MCDisassembler::SoftFail; 4162 } 4163 4164 Inst.addOperand(MCOperand::CreateImm(pred)); 4165 Inst.addOperand(MCOperand::CreateImm(mask)); 4166 return S; 4167 } 4168 4169 static DecodeStatus 4170 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4171 uint64_t Address, const void *Decoder) { 4172 DecodeStatus S = MCDisassembler::Success; 4173 4174 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4175 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4176 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4177 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4178 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4179 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4180 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4181 bool writeback = (W == 1) | (P == 0); 4182 4183 addr |= (U << 8) | (Rn << 9); 4184 4185 if (writeback && (Rn == Rt || Rn == Rt2)) 4186 Check(S, MCDisassembler::SoftFail); 4187 if (Rt == Rt2) 4188 Check(S, MCDisassembler::SoftFail); 4189 4190 // Rt 4191 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4192 return MCDisassembler::Fail; 4193 // Rt2 4194 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4195 return MCDisassembler::Fail; 4196 // Writeback operand 4197 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4198 return MCDisassembler::Fail; 4199 // addr 4200 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4201 return MCDisassembler::Fail; 4202 4203 return S; 4204 } 4205 4206 static DecodeStatus 4207 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4208 uint64_t Address, const void *Decoder) { 4209 DecodeStatus S = MCDisassembler::Success; 4210 4211 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4212 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4213 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4214 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4215 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4216 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4217 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4218 bool writeback = (W == 1) | (P == 0); 4219 4220 addr |= (U << 8) | (Rn << 9); 4221 4222 if (writeback && (Rn == Rt || Rn == Rt2)) 4223 Check(S, MCDisassembler::SoftFail); 4224 4225 // Writeback operand 4226 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 // Rt 4229 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 // Rt2 4232 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4233 return MCDisassembler::Fail; 4234 // addr 4235 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4236 return MCDisassembler::Fail; 4237 4238 return S; 4239 } 4240 4241 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4242 uint64_t Address, const void *Decoder) { 4243 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4244 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4245 if (sign1 != sign2) return MCDisassembler::Fail; 4246 4247 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4248 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4249 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4250 Val |= sign1 << 12; 4251 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4252 4253 return MCDisassembler::Success; 4254 } 4255 4256 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4257 uint64_t Address, 4258 const void *Decoder) { 4259 DecodeStatus S = MCDisassembler::Success; 4260 4261 // Shift of "asr #32" is not allowed in Thumb2 mode. 4262 if (Val == 0x20) S = MCDisassembler::SoftFail; 4263 Inst.addOperand(MCOperand::CreateImm(Val)); 4264 return S; 4265 } 4266 4267 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4268 uint64_t Address, const void *Decoder) { 4269 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4270 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4271 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4272 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4273 4274 if (pred == 0xF) 4275 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4276 4277 DecodeStatus S = MCDisassembler::Success; 4278 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4279 return MCDisassembler::Fail; 4280 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4283 return MCDisassembler::Fail; 4284 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4285 return MCDisassembler::Fail; 4286 4287 return S; 4288 } 4289 4290 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4291 uint64_t Address, const void *Decoder) { 4292 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4293 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4294 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4295 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4296 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4297 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4298 4299 DecodeStatus S = MCDisassembler::Success; 4300 4301 // VMOVv2f32 is ambiguous with these decodings. 4302 if (!(imm & 0x38) && cmode == 0xF) { 4303 Inst.setOpcode(ARM::VMOVv2f32); 4304 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4305 } 4306 4307 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4308 4309 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4310 return MCDisassembler::Fail; 4311 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4312 return MCDisassembler::Fail; 4313 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4314 4315 return S; 4316 } 4317 4318 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4319 uint64_t Address, const void *Decoder) { 4320 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4321 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4322 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4323 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4324 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4325 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4326 4327 DecodeStatus S = MCDisassembler::Success; 4328 4329 // VMOVv4f32 is ambiguous with these decodings. 4330 if (!(imm & 0x38) && cmode == 0xF) { 4331 Inst.setOpcode(ARM::VMOVv4f32); 4332 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4333 } 4334 4335 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4336 4337 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4338 return MCDisassembler::Fail; 4339 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4340 return MCDisassembler::Fail; 4341 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4342 4343 return S; 4344 } 4345 4346 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4347 uint64_t Address, const void *Decoder) { 4348 DecodeStatus S = MCDisassembler::Success; 4349 4350 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4351 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4352 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4353 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4354 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4355 4356 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4357 S = MCDisassembler::SoftFail; 4358 4359 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4362 return MCDisassembler::Fail; 4363 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4364 return MCDisassembler::Fail; 4365 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 4370 return S; 4371 } 4372 4373