1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 const EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 const EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 llvm_unreachable("Invalid DecodeStatus!"); 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 132 unsigned RegNo, uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 146 uint64_t Address, const void *Decoder); 147 148 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 153 unsigned Insn, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 165 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 166 unsigned Insn, 167 uint64_t Adddress, 168 const void *Decoder); 169 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 262 263 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 326 327 328 #include "ARMGenDisassemblerTables.inc" 329 #include "ARMGenInstrInfo.inc" 330 #include "ARMGenEDInfo.inc" 331 332 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 333 return new ARMDisassembler(STI); 334 } 335 336 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 337 return new ThumbDisassembler(STI); 338 } 339 340 const EDInstInfo *ARMDisassembler::getEDInfo() const { 341 return instInfoARM; 342 } 343 344 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 345 return instInfoARM; 346 } 347 348 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 349 const MemoryObject &Region, 350 uint64_t Address, 351 raw_ostream &os, 352 raw_ostream &cs) const { 353 CommentStream = &cs; 354 355 uint8_t bytes[4]; 356 357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 359 360 // We want to read exactly 4 bytes of data. 361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 362 Size = 0; 363 return MCDisassembler::Fail; 364 } 365 366 // Encoded as a small-endian 32-bit word in the stream. 367 uint32_t insn = (bytes[3] << 24) | 368 (bytes[2] << 16) | 369 (bytes[1] << 8) | 370 (bytes[0] << 0); 371 372 // Calling the auto-generated decoder function. 373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 374 if (result != MCDisassembler::Fail) { 375 Size = 4; 376 return result; 377 } 378 379 // VFP and NEON instructions, similarly, are shared between ARM 380 // and Thumb modes. 381 MI.clear(); 382 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 return result; 386 } 387 388 MI.clear(); 389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 390 if (result != MCDisassembler::Fail) { 391 Size = 4; 392 // Add a fake predicate operand, because we share these instruction 393 // definitions with Thumb2 where these instructions are predicable. 394 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 395 return MCDisassembler::Fail; 396 return result; 397 } 398 399 MI.clear(); 400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 401 if (result != MCDisassembler::Fail) { 402 Size = 4; 403 // Add a fake predicate operand, because we share these instruction 404 // definitions with Thumb2 where these instructions are predicable. 405 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 406 return MCDisassembler::Fail; 407 return result; 408 } 409 410 MI.clear(); 411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 412 if (result != MCDisassembler::Fail) { 413 Size = 4; 414 // Add a fake predicate operand, because we share these instruction 415 // definitions with Thumb2 where these instructions are predicable. 416 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 417 return MCDisassembler::Fail; 418 return result; 419 } 420 421 MI.clear(); 422 423 Size = 0; 424 return MCDisassembler::Fail; 425 } 426 427 namespace llvm { 428 extern const MCInstrDesc ARMInsts[]; 429 } 430 431 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 432 /// immediate Value in the MCInst. The immediate Value has had any PC 433 /// adjustment made by the caller. If the instruction is a branch instruction 434 /// then isBranch is true, else false. If the getOpInfo() function was set as 435 /// part of the setupForSymbolicDisassembly() call then that function is called 436 /// to get any symbolic information at the Address for this instruction. If 437 /// that returns non-zero then the symbolic information it returns is used to 438 /// create an MCExpr and that is added as an operand to the MCInst. If 439 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 440 /// Value is done and if a symbol is found an MCExpr is created with that, else 441 /// an MCExpr with Value is created. This function returns true if it adds an 442 /// operand to the MCInst and false otherwise. 443 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 444 bool isBranch, uint64_t InstSize, 445 MCInst &MI, const void *Decoder) { 446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 448 struct LLVMOpInfo1 SymbolicOp; 449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 450 SymbolicOp.Value = Value; 451 void *DisInfo = Dis->getDisInfoBlock(); 452 453 if (!getOpInfo || 454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 455 // Clear SymbolicOp.Value from above and also all other fields. 456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 458 if (!SymbolLookUp) 459 return false; 460 uint64_t ReferenceType; 461 if (isBranch) 462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 463 else 464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 465 const char *ReferenceName; 466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 467 &ReferenceName); 468 if (Name) { 469 SymbolicOp.AddSymbol.Name = Name; 470 SymbolicOp.AddSymbol.Present = true; 471 } 472 // For branches always create an MCExpr so it gets printed as hex address. 473 else if (isBranch) { 474 SymbolicOp.Value = Value; 475 } 476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 478 if (!Name && !isBranch) 479 return false; 480 } 481 482 MCContext *Ctx = Dis->getMCContext(); 483 const MCExpr *Add = NULL; 484 if (SymbolicOp.AddSymbol.Present) { 485 if (SymbolicOp.AddSymbol.Name) { 486 StringRef Name(SymbolicOp.AddSymbol.Name); 487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 488 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 489 } else { 490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 491 } 492 } 493 494 const MCExpr *Sub = NULL; 495 if (SymbolicOp.SubtractSymbol.Present) { 496 if (SymbolicOp.SubtractSymbol.Name) { 497 StringRef Name(SymbolicOp.SubtractSymbol.Name); 498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 500 } else { 501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 502 } 503 } 504 505 const MCExpr *Off = NULL; 506 if (SymbolicOp.Value != 0) 507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 508 509 const MCExpr *Expr; 510 if (Sub) { 511 const MCExpr *LHS; 512 if (Add) 513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 514 else 515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 516 if (Off != 0) 517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 518 else 519 Expr = LHS; 520 } else if (Add) { 521 if (Off != 0) 522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 523 else 524 Expr = Add; 525 } else { 526 if (Off != 0) 527 Expr = Off; 528 else 529 Expr = MCConstantExpr::Create(0, *Ctx); 530 } 531 532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 537 MI.addOperand(MCOperand::CreateExpr(Expr)); 538 else 539 llvm_unreachable("bad SymbolicOp.VariantKind"); 540 541 return true; 542 } 543 544 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 545 /// referenced by a load instruction with the base register that is the Pc. 546 /// These can often be values in a literal pool near the Address of the 547 /// instruction. The Address of the instruction and its immediate Value are 548 /// used as a possible literal pool entry. The SymbolLookUp call back will 549 /// return the name of a symbol referenced by the the literal pool's entry if 550 /// the referenced address is that of a symbol. Or it will return a pointer to 551 /// a literal 'C' string if the referenced address of the literal pool's entry 552 /// is an address into a section with 'C' string literals. 553 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 554 const void *Decoder) { 555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 557 if (SymbolLookUp) { 558 void *DisInfo = Dis->getDisInfoBlock(); 559 uint64_t ReferenceType; 560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 561 const char *ReferenceName; 562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 566 } 567 } 568 569 // Thumb1 instructions don't have explicit S bits. Rather, they 570 // implicitly set CPSR. Since it's not represented in the encoding, the 571 // auto-generated decoder won't inject the CPSR operand. We need to fix 572 // that as a post-pass. 573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 576 MCInst::iterator I = MI.begin(); 577 for (unsigned i = 0; i < NumOps; ++i, ++I) { 578 if (I == MI.end()) break; 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 580 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 582 return; 583 } 584 } 585 586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 587 } 588 589 // Most Thumb instructions don't have explicit predicates in the 590 // encoding, but rather get their predicates from IT context. We need 591 // to fix up the predicate operands using this context information as a 592 // post-pass. 593 MCDisassembler::DecodeStatus 594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 595 MCDisassembler::DecodeStatus S = Success; 596 597 // A few instructions actually have predicates encoded in them. Don't 598 // try to overwrite it if we're seeing one of those. 599 switch (MI.getOpcode()) { 600 case ARM::tBcc: 601 case ARM::t2Bcc: 602 case ARM::tCBZ: 603 case ARM::tCBNZ: 604 case ARM::tCPS: 605 case ARM::t2CPS3p: 606 case ARM::t2CPS2p: 607 case ARM::t2CPS1p: 608 case ARM::tMOVSr: 609 case ARM::tSETEND: 610 // Some instructions (mostly conditional branches) are not 611 // allowed in IT blocks. 612 if (!ITBlock.empty()) 613 S = SoftFail; 614 else 615 return Success; 616 break; 617 case ARM::tB: 618 case ARM::t2B: 619 case ARM::t2TBB: 620 case ARM::t2TBH: 621 // Some instructions (mostly unconditional branches) can 622 // only appears at the end of, or outside of, an IT. 623 if (ITBlock.size() > 1) 624 S = SoftFail; 625 break; 626 default: 627 break; 628 } 629 630 // If we're in an IT block, base the predicate on that. Otherwise, 631 // assume a predicate of AL. 632 unsigned CC; 633 if (!ITBlock.empty()) { 634 CC = ITBlock.back(); 635 if (CC == 0xF) 636 CC = ARMCC::AL; 637 ITBlock.pop_back(); 638 } else 639 CC = ARMCC::AL; 640 641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 643 MCInst::iterator I = MI.begin(); 644 for (unsigned i = 0; i < NumOps; ++i, ++I) { 645 if (I == MI.end()) break; 646 if (OpInfo[i].isPredicate()) { 647 I = MI.insert(I, MCOperand::CreateImm(CC)); 648 ++I; 649 if (CC == ARMCC::AL) 650 MI.insert(I, MCOperand::CreateReg(0)); 651 else 652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 653 return S; 654 } 655 } 656 657 I = MI.insert(I, MCOperand::CreateImm(CC)); 658 ++I; 659 if (CC == ARMCC::AL) 660 MI.insert(I, MCOperand::CreateReg(0)); 661 else 662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 663 664 return S; 665 } 666 667 // Thumb VFP instructions are a special case. Because we share their 668 // encodings between ARM and Thumb modes, and they are predicable in ARM 669 // mode, the auto-generated decoder will give them an (incorrect) 670 // predicate operand. We need to rewrite these operands based on the IT 671 // context as a post-pass. 672 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 673 unsigned CC; 674 if (!ITBlock.empty()) { 675 CC = ITBlock.back(); 676 ITBlock.pop_back(); 677 } else 678 CC = ARMCC::AL; 679 680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 681 MCInst::iterator I = MI.begin(); 682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 683 for (unsigned i = 0; i < NumOps; ++i, ++I) { 684 if (OpInfo[i].isPredicate() ) { 685 I->setImm(CC); 686 ++I; 687 if (CC == ARMCC::AL) 688 I->setReg(0); 689 else 690 I->setReg(ARM::CPSR); 691 return; 692 } 693 } 694 } 695 696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 697 const MemoryObject &Region, 698 uint64_t Address, 699 raw_ostream &os, 700 raw_ostream &cs) const { 701 CommentStream = &cs; 702 703 uint8_t bytes[4]; 704 705 assert((STI.getFeatureBits() & ARM::ModeThumb) && 706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 707 708 // We want to read exactly 2 bytes of data. 709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 710 Size = 0; 711 return MCDisassembler::Fail; 712 } 713 714 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 716 if (result != MCDisassembler::Fail) { 717 Size = 2; 718 Check(result, AddThumbPredicate(MI)); 719 return result; 720 } 721 722 MI.clear(); 723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 724 if (result) { 725 Size = 2; 726 bool InITBlock = !ITBlock.empty(); 727 Check(result, AddThumbPredicate(MI)); 728 AddThumb1SBit(MI, InITBlock); 729 return result; 730 } 731 732 MI.clear(); 733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 734 if (result != MCDisassembler::Fail) { 735 Size = 2; 736 737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 738 // the Thumb predicate. 739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 740 result = MCDisassembler::SoftFail; 741 742 Check(result, AddThumbPredicate(MI)); 743 744 // If we find an IT instruction, we need to parse its condition 745 // code and mask operands so that we can apply them correctly 746 // to the subsequent instructions. 747 if (MI.getOpcode() == ARM::t2IT) { 748 749 // (3 - the number of trailing zeros) is the number of then / else. 750 unsigned firstcond = MI.getOperand(0).getImm(); 751 unsigned Mask = MI.getOperand(1).getImm(); 752 unsigned CondBit0 = Mask >> 4 & 1; 753 unsigned NumTZ = CountTrailingZeros_32(Mask); 754 assert(NumTZ <= 3 && "Invalid IT mask!"); 755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 756 bool T = ((Mask >> Pos) & 1) == CondBit0; 757 if (T) 758 ITBlock.insert(ITBlock.begin(), firstcond); 759 else 760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 761 } 762 763 ITBlock.push_back(firstcond); 764 } 765 766 return result; 767 } 768 769 // We want to read exactly 4 bytes of data. 770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 771 Size = 0; 772 return MCDisassembler::Fail; 773 } 774 775 uint32_t insn32 = (bytes[3] << 8) | 776 (bytes[2] << 0) | 777 (bytes[1] << 24) | 778 (bytes[0] << 16); 779 MI.clear(); 780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 781 if (result != MCDisassembler::Fail) { 782 Size = 4; 783 bool InITBlock = ITBlock.size(); 784 Check(result, AddThumbPredicate(MI)); 785 AddThumb1SBit(MI, InITBlock); 786 return result; 787 } 788 789 MI.clear(); 790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 791 if (result != MCDisassembler::Fail) { 792 Size = 4; 793 Check(result, AddThumbPredicate(MI)); 794 return result; 795 } 796 797 MI.clear(); 798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 799 if (result != MCDisassembler::Fail) { 800 Size = 4; 801 UpdateThumbVFPPredicate(MI); 802 return result; 803 } 804 805 MI.clear(); 806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 807 if (result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(result, AddThumbPredicate(MI)); 810 return result; 811 } 812 813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 814 MI.clear(); 815 uint32_t NEONLdStInsn = insn32; 816 NEONLdStInsn &= 0xF0FFFFFF; 817 NEONLdStInsn |= 0x04000000; 818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 819 if (result != MCDisassembler::Fail) { 820 Size = 4; 821 Check(result, AddThumbPredicate(MI)); 822 return result; 823 } 824 } 825 826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 827 MI.clear(); 828 uint32_t NEONDataInsn = insn32; 829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 833 if (result != MCDisassembler::Fail) { 834 Size = 4; 835 Check(result, AddThumbPredicate(MI)); 836 return result; 837 } 838 } 839 840 Size = 0; 841 return MCDisassembler::Fail; 842 } 843 844 845 extern "C" void LLVMInitializeARMDisassembler() { 846 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 847 createARMDisassembler); 848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 849 createThumbDisassembler); 850 } 851 852 static const unsigned GPRDecoderTable[] = { 853 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 854 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 855 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 856 ARM::R12, ARM::SP, ARM::LR, ARM::PC 857 }; 858 859 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 860 uint64_t Address, const void *Decoder) { 861 if (RegNo > 15) 862 return MCDisassembler::Fail; 863 864 unsigned Register = GPRDecoderTable[RegNo]; 865 Inst.addOperand(MCOperand::CreateReg(Register)); 866 return MCDisassembler::Success; 867 } 868 869 static DecodeStatus 870 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 871 uint64_t Address, const void *Decoder) { 872 if (RegNo == 15) return MCDisassembler::Fail; 873 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 874 } 875 876 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 877 uint64_t Address, const void *Decoder) { 878 if (RegNo > 7) 879 return MCDisassembler::Fail; 880 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 881 } 882 883 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 unsigned Register = 0; 886 switch (RegNo) { 887 case 0: 888 Register = ARM::R0; 889 break; 890 case 1: 891 Register = ARM::R1; 892 break; 893 case 2: 894 Register = ARM::R2; 895 break; 896 case 3: 897 Register = ARM::R3; 898 break; 899 case 9: 900 Register = ARM::R9; 901 break; 902 case 12: 903 Register = ARM::R12; 904 break; 905 default: 906 return MCDisassembler::Fail; 907 } 908 909 Inst.addOperand(MCOperand::CreateReg(Register)); 910 return MCDisassembler::Success; 911 } 912 913 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 914 uint64_t Address, const void *Decoder) { 915 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 916 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 917 } 918 919 static const unsigned SPRDecoderTable[] = { 920 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 921 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 922 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 923 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 924 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 925 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 926 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 927 ARM::S28, ARM::S29, ARM::S30, ARM::S31 928 }; 929 930 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 if (RegNo > 31) 933 return MCDisassembler::Fail; 934 935 unsigned Register = SPRDecoderTable[RegNo]; 936 Inst.addOperand(MCOperand::CreateReg(Register)); 937 return MCDisassembler::Success; 938 } 939 940 static const unsigned DPRDecoderTable[] = { 941 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 942 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 943 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 944 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 945 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 946 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 947 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 948 ARM::D28, ARM::D29, ARM::D30, ARM::D31 949 }; 950 951 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 952 uint64_t Address, const void *Decoder) { 953 if (RegNo > 31) 954 return MCDisassembler::Fail; 955 956 unsigned Register = DPRDecoderTable[RegNo]; 957 Inst.addOperand(MCOperand::CreateReg(Register)); 958 return MCDisassembler::Success; 959 } 960 961 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 962 uint64_t Address, const void *Decoder) { 963 if (RegNo > 7) 964 return MCDisassembler::Fail; 965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 966 } 967 968 static DecodeStatus 969 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 970 uint64_t Address, const void *Decoder) { 971 if (RegNo > 15) 972 return MCDisassembler::Fail; 973 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 974 } 975 976 static const unsigned QPRDecoderTable[] = { 977 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 978 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 979 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 980 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 981 }; 982 983 984 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 985 uint64_t Address, const void *Decoder) { 986 if (RegNo > 31) 987 return MCDisassembler::Fail; 988 RegNo >>= 1; 989 990 unsigned Register = QPRDecoderTable[RegNo]; 991 Inst.addOperand(MCOperand::CreateReg(Register)); 992 return MCDisassembler::Success; 993 } 994 995 static const unsigned DPairDecoderTable[] = { 996 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 997 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 998 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 999 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1000 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1001 ARM::Q15 1002 }; 1003 1004 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 if (RegNo > 30) 1007 return MCDisassembler::Fail; 1008 1009 unsigned Register = DPairDecoderTable[RegNo]; 1010 Inst.addOperand(MCOperand::CreateReg(Register)); 1011 return MCDisassembler::Success; 1012 } 1013 1014 static const unsigned DPairSpacedDecoderTable[] = { 1015 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1016 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1017 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1018 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1019 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1020 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1021 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1022 ARM::D28_D30, ARM::D29_D31 1023 }; 1024 1025 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 1026 unsigned RegNo, 1027 uint64_t Address, 1028 const void *Decoder) { 1029 if (RegNo > 29) 1030 return MCDisassembler::Fail; 1031 1032 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1033 Inst.addOperand(MCOperand::CreateReg(Register)); 1034 return MCDisassembler::Success; 1035 } 1036 1037 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 1038 uint64_t Address, const void *Decoder) { 1039 if (Val == 0xF) return MCDisassembler::Fail; 1040 // AL predicate is not allowed on Thumb1 branches. 1041 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1042 return MCDisassembler::Fail; 1043 Inst.addOperand(MCOperand::CreateImm(Val)); 1044 if (Val == ARMCC::AL) { 1045 Inst.addOperand(MCOperand::CreateReg(0)); 1046 } else 1047 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1048 return MCDisassembler::Success; 1049 } 1050 1051 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1052 uint64_t Address, const void *Decoder) { 1053 if (Val) 1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1055 else 1056 Inst.addOperand(MCOperand::CreateReg(0)); 1057 return MCDisassembler::Success; 1058 } 1059 1060 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1061 uint64_t Address, const void *Decoder) { 1062 uint32_t imm = Val & 0xFF; 1063 uint32_t rot = (Val & 0xF00) >> 7; 1064 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1065 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1066 return MCDisassembler::Success; 1067 } 1068 1069 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1070 uint64_t Address, const void *Decoder) { 1071 DecodeStatus S = MCDisassembler::Success; 1072 1073 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1074 unsigned type = fieldFromInstruction32(Val, 5, 2); 1075 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1076 1077 // Register-immediate 1078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1079 return MCDisassembler::Fail; 1080 1081 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1082 switch (type) { 1083 case 0: 1084 Shift = ARM_AM::lsl; 1085 break; 1086 case 1: 1087 Shift = ARM_AM::lsr; 1088 break; 1089 case 2: 1090 Shift = ARM_AM::asr; 1091 break; 1092 case 3: 1093 Shift = ARM_AM::ror; 1094 break; 1095 } 1096 1097 if (Shift == ARM_AM::ror && imm == 0) 1098 Shift = ARM_AM::rrx; 1099 1100 unsigned Op = Shift | (imm << 3); 1101 Inst.addOperand(MCOperand::CreateImm(Op)); 1102 1103 return S; 1104 } 1105 1106 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1107 uint64_t Address, const void *Decoder) { 1108 DecodeStatus S = MCDisassembler::Success; 1109 1110 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1111 unsigned type = fieldFromInstruction32(Val, 5, 2); 1112 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1113 1114 // Register-register 1115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1116 return MCDisassembler::Fail; 1117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1118 return MCDisassembler::Fail; 1119 1120 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1121 switch (type) { 1122 case 0: 1123 Shift = ARM_AM::lsl; 1124 break; 1125 case 1: 1126 Shift = ARM_AM::lsr; 1127 break; 1128 case 2: 1129 Shift = ARM_AM::asr; 1130 break; 1131 case 3: 1132 Shift = ARM_AM::ror; 1133 break; 1134 } 1135 1136 Inst.addOperand(MCOperand::CreateImm(Shift)); 1137 1138 return S; 1139 } 1140 1141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1142 uint64_t Address, const void *Decoder) { 1143 DecodeStatus S = MCDisassembler::Success; 1144 1145 bool writebackLoad = false; 1146 unsigned writebackReg = 0; 1147 switch (Inst.getOpcode()) { 1148 default: 1149 break; 1150 case ARM::LDMIA_UPD: 1151 case ARM::LDMDB_UPD: 1152 case ARM::LDMIB_UPD: 1153 case ARM::LDMDA_UPD: 1154 case ARM::t2LDMIA_UPD: 1155 case ARM::t2LDMDB_UPD: 1156 writebackLoad = true; 1157 writebackReg = Inst.getOperand(0).getReg(); 1158 break; 1159 } 1160 1161 // Empty register lists are not allowed. 1162 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1163 for (unsigned i = 0; i < 16; ++i) { 1164 if (Val & (1 << i)) { 1165 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1166 return MCDisassembler::Fail; 1167 // Writeback not allowed if Rn is in the target list. 1168 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1169 Check(S, MCDisassembler::SoftFail); 1170 } 1171 } 1172 1173 return S; 1174 } 1175 1176 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1177 uint64_t Address, const void *Decoder) { 1178 DecodeStatus S = MCDisassembler::Success; 1179 1180 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1181 unsigned regs = Val & 0xFF; 1182 1183 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1184 return MCDisassembler::Fail; 1185 for (unsigned i = 0; i < (regs - 1); ++i) { 1186 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1187 return MCDisassembler::Fail; 1188 } 1189 1190 return S; 1191 } 1192 1193 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1194 uint64_t Address, const void *Decoder) { 1195 DecodeStatus S = MCDisassembler::Success; 1196 1197 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1198 unsigned regs = (Val & 0xFF) / 2; 1199 1200 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1201 return MCDisassembler::Fail; 1202 for (unsigned i = 0; i < (regs - 1); ++i) { 1203 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1204 return MCDisassembler::Fail; 1205 } 1206 1207 return S; 1208 } 1209 1210 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1211 uint64_t Address, const void *Decoder) { 1212 // This operand encodes a mask of contiguous zeros between a specified MSB 1213 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1214 // the mask of all bits LSB-and-lower, and then xor them to create 1215 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1216 // create the final mask. 1217 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1218 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1219 1220 DecodeStatus S = MCDisassembler::Success; 1221 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1222 1223 uint32_t msb_mask = 0xFFFFFFFF; 1224 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1225 uint32_t lsb_mask = (1U << lsb) - 1; 1226 1227 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1228 return S; 1229 } 1230 1231 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1232 uint64_t Address, const void *Decoder) { 1233 DecodeStatus S = MCDisassembler::Success; 1234 1235 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1236 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1237 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1238 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1239 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1240 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1241 1242 switch (Inst.getOpcode()) { 1243 case ARM::LDC_OFFSET: 1244 case ARM::LDC_PRE: 1245 case ARM::LDC_POST: 1246 case ARM::LDC_OPTION: 1247 case ARM::LDCL_OFFSET: 1248 case ARM::LDCL_PRE: 1249 case ARM::LDCL_POST: 1250 case ARM::LDCL_OPTION: 1251 case ARM::STC_OFFSET: 1252 case ARM::STC_PRE: 1253 case ARM::STC_POST: 1254 case ARM::STC_OPTION: 1255 case ARM::STCL_OFFSET: 1256 case ARM::STCL_PRE: 1257 case ARM::STCL_POST: 1258 case ARM::STCL_OPTION: 1259 case ARM::t2LDC_OFFSET: 1260 case ARM::t2LDC_PRE: 1261 case ARM::t2LDC_POST: 1262 case ARM::t2LDC_OPTION: 1263 case ARM::t2LDCL_OFFSET: 1264 case ARM::t2LDCL_PRE: 1265 case ARM::t2LDCL_POST: 1266 case ARM::t2LDCL_OPTION: 1267 case ARM::t2STC_OFFSET: 1268 case ARM::t2STC_PRE: 1269 case ARM::t2STC_POST: 1270 case ARM::t2STC_OPTION: 1271 case ARM::t2STCL_OFFSET: 1272 case ARM::t2STCL_PRE: 1273 case ARM::t2STCL_POST: 1274 case ARM::t2STCL_OPTION: 1275 if (coproc == 0xA || coproc == 0xB) 1276 return MCDisassembler::Fail; 1277 break; 1278 default: 1279 break; 1280 } 1281 1282 Inst.addOperand(MCOperand::CreateImm(coproc)); 1283 Inst.addOperand(MCOperand::CreateImm(CRd)); 1284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 1287 switch (Inst.getOpcode()) { 1288 case ARM::t2LDC2_OFFSET: 1289 case ARM::t2LDC2L_OFFSET: 1290 case ARM::t2LDC2_PRE: 1291 case ARM::t2LDC2L_PRE: 1292 case ARM::t2STC2_OFFSET: 1293 case ARM::t2STC2L_OFFSET: 1294 case ARM::t2STC2_PRE: 1295 case ARM::t2STC2L_PRE: 1296 case ARM::LDC2_OFFSET: 1297 case ARM::LDC2L_OFFSET: 1298 case ARM::LDC2_PRE: 1299 case ARM::LDC2L_PRE: 1300 case ARM::STC2_OFFSET: 1301 case ARM::STC2L_OFFSET: 1302 case ARM::STC2_PRE: 1303 case ARM::STC2L_PRE: 1304 case ARM::t2LDC_OFFSET: 1305 case ARM::t2LDCL_OFFSET: 1306 case ARM::t2LDC_PRE: 1307 case ARM::t2LDCL_PRE: 1308 case ARM::t2STC_OFFSET: 1309 case ARM::t2STCL_OFFSET: 1310 case ARM::t2STC_PRE: 1311 case ARM::t2STCL_PRE: 1312 case ARM::LDC_OFFSET: 1313 case ARM::LDCL_OFFSET: 1314 case ARM::LDC_PRE: 1315 case ARM::LDCL_PRE: 1316 case ARM::STC_OFFSET: 1317 case ARM::STCL_OFFSET: 1318 case ARM::STC_PRE: 1319 case ARM::STCL_PRE: 1320 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1321 Inst.addOperand(MCOperand::CreateImm(imm)); 1322 break; 1323 case ARM::t2LDC2_POST: 1324 case ARM::t2LDC2L_POST: 1325 case ARM::t2STC2_POST: 1326 case ARM::t2STC2L_POST: 1327 case ARM::LDC2_POST: 1328 case ARM::LDC2L_POST: 1329 case ARM::STC2_POST: 1330 case ARM::STC2L_POST: 1331 case ARM::t2LDC_POST: 1332 case ARM::t2LDCL_POST: 1333 case ARM::t2STC_POST: 1334 case ARM::t2STCL_POST: 1335 case ARM::LDC_POST: 1336 case ARM::LDCL_POST: 1337 case ARM::STC_POST: 1338 case ARM::STCL_POST: 1339 imm |= U << 8; 1340 // fall through. 1341 default: 1342 // The 'option' variant doesn't encode 'U' in the immediate since 1343 // the immediate is unsigned [0,255]. 1344 Inst.addOperand(MCOperand::CreateImm(imm)); 1345 break; 1346 } 1347 1348 switch (Inst.getOpcode()) { 1349 case ARM::LDC_OFFSET: 1350 case ARM::LDC_PRE: 1351 case ARM::LDC_POST: 1352 case ARM::LDC_OPTION: 1353 case ARM::LDCL_OFFSET: 1354 case ARM::LDCL_PRE: 1355 case ARM::LDCL_POST: 1356 case ARM::LDCL_OPTION: 1357 case ARM::STC_OFFSET: 1358 case ARM::STC_PRE: 1359 case ARM::STC_POST: 1360 case ARM::STC_OPTION: 1361 case ARM::STCL_OFFSET: 1362 case ARM::STCL_PRE: 1363 case ARM::STCL_POST: 1364 case ARM::STCL_OPTION: 1365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 return S; 1373 } 1374 1375 static DecodeStatus 1376 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1377 uint64_t Address, const void *Decoder) { 1378 DecodeStatus S = MCDisassembler::Success; 1379 1380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1381 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1382 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1383 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1384 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1385 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1386 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1387 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1388 1389 // On stores, the writeback operand precedes Rt. 1390 switch (Inst.getOpcode()) { 1391 case ARM::STR_POST_IMM: 1392 case ARM::STR_POST_REG: 1393 case ARM::STRB_POST_IMM: 1394 case ARM::STRB_POST_REG: 1395 case ARM::STRT_POST_REG: 1396 case ARM::STRT_POST_IMM: 1397 case ARM::STRBT_POST_REG: 1398 case ARM::STRBT_POST_IMM: 1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 1409 // On loads, the writeback operand comes after Rt. 1410 switch (Inst.getOpcode()) { 1411 case ARM::LDR_POST_IMM: 1412 case ARM::LDR_POST_REG: 1413 case ARM::LDRB_POST_IMM: 1414 case ARM::LDRB_POST_REG: 1415 case ARM::LDRBT_POST_REG: 1416 case ARM::LDRBT_POST_IMM: 1417 case ARM::LDRT_POST_REG: 1418 case ARM::LDRT_POST_IMM: 1419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1420 return MCDisassembler::Fail; 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1427 return MCDisassembler::Fail; 1428 1429 ARM_AM::AddrOpc Op = ARM_AM::add; 1430 if (!fieldFromInstruction32(Insn, 23, 1)) 1431 Op = ARM_AM::sub; 1432 1433 bool writeback = (P == 0) || (W == 1); 1434 unsigned idx_mode = 0; 1435 if (P && writeback) 1436 idx_mode = ARMII::IndexModePre; 1437 else if (!P && writeback) 1438 idx_mode = ARMII::IndexModePost; 1439 1440 if (writeback && (Rn == 15 || Rn == Rt)) 1441 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1442 1443 if (reg) { 1444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1445 return MCDisassembler::Fail; 1446 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1447 switch( fieldFromInstruction32(Insn, 5, 2)) { 1448 case 0: 1449 Opc = ARM_AM::lsl; 1450 break; 1451 case 1: 1452 Opc = ARM_AM::lsr; 1453 break; 1454 case 2: 1455 Opc = ARM_AM::asr; 1456 break; 1457 case 3: 1458 Opc = ARM_AM::ror; 1459 break; 1460 default: 1461 return MCDisassembler::Fail; 1462 } 1463 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1464 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1465 1466 Inst.addOperand(MCOperand::CreateImm(imm)); 1467 } else { 1468 Inst.addOperand(MCOperand::CreateReg(0)); 1469 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1470 Inst.addOperand(MCOperand::CreateImm(tmp)); 1471 } 1472 1473 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1474 return MCDisassembler::Fail; 1475 1476 return S; 1477 } 1478 1479 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1480 uint64_t Address, const void *Decoder) { 1481 DecodeStatus S = MCDisassembler::Success; 1482 1483 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1484 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1485 unsigned type = fieldFromInstruction32(Val, 5, 2); 1486 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1487 unsigned U = fieldFromInstruction32(Val, 12, 1); 1488 1489 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1490 switch (type) { 1491 case 0: 1492 ShOp = ARM_AM::lsl; 1493 break; 1494 case 1: 1495 ShOp = ARM_AM::lsr; 1496 break; 1497 case 2: 1498 ShOp = ARM_AM::asr; 1499 break; 1500 case 3: 1501 ShOp = ARM_AM::ror; 1502 break; 1503 } 1504 1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1508 return MCDisassembler::Fail; 1509 unsigned shift; 1510 if (U) 1511 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1512 else 1513 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1514 Inst.addOperand(MCOperand::CreateImm(shift)); 1515 1516 return S; 1517 } 1518 1519 static DecodeStatus 1520 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1521 uint64_t Address, const void *Decoder) { 1522 DecodeStatus S = MCDisassembler::Success; 1523 1524 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1525 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1526 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1527 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1528 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1529 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1530 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1531 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1532 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1533 1534 bool writeback = (W == 1) | (P == 0); 1535 1536 // For {LD,ST}RD, Rt must be even, else undefined. 1537 switch (Inst.getOpcode()) { 1538 case ARM::STRD: 1539 case ARM::STRD_PRE: 1540 case ARM::STRD_POST: 1541 case ARM::LDRD: 1542 case ARM::LDRD_PRE: 1543 case ARM::LDRD_POST: 1544 if (Rt & 0x1) return MCDisassembler::Fail; 1545 break; 1546 default: 1547 break; 1548 } 1549 1550 if (writeback) { // Writeback 1551 if (P) 1552 U |= ARMII::IndexModePre << 9; 1553 else 1554 U |= ARMII::IndexModePost << 9; 1555 1556 // On stores, the writeback operand precedes Rt. 1557 switch (Inst.getOpcode()) { 1558 case ARM::STRD: 1559 case ARM::STRD_PRE: 1560 case ARM::STRD_POST: 1561 case ARM::STRH: 1562 case ARM::STRH_PRE: 1563 case ARM::STRH_POST: 1564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1565 return MCDisassembler::Fail; 1566 break; 1567 default: 1568 break; 1569 } 1570 } 1571 1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1573 return MCDisassembler::Fail; 1574 switch (Inst.getOpcode()) { 1575 case ARM::STRD: 1576 case ARM::STRD_PRE: 1577 case ARM::STRD_POST: 1578 case ARM::LDRD: 1579 case ARM::LDRD_PRE: 1580 case ARM::LDRD_POST: 1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 if (writeback) { 1589 // On loads, the writeback operand comes after Rt. 1590 switch (Inst.getOpcode()) { 1591 case ARM::LDRD: 1592 case ARM::LDRD_PRE: 1593 case ARM::LDRD_POST: 1594 case ARM::LDRH: 1595 case ARM::LDRH_PRE: 1596 case ARM::LDRH_POST: 1597 case ARM::LDRSH: 1598 case ARM::LDRSH_PRE: 1599 case ARM::LDRSH_POST: 1600 case ARM::LDRSB: 1601 case ARM::LDRSB_PRE: 1602 case ARM::LDRSB_POST: 1603 case ARM::LDRHTr: 1604 case ARM::LDRSBTr: 1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1614 return MCDisassembler::Fail; 1615 1616 if (type) { 1617 Inst.addOperand(MCOperand::CreateReg(0)); 1618 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1619 } else { 1620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1621 return MCDisassembler::Fail; 1622 Inst.addOperand(MCOperand::CreateImm(U)); 1623 } 1624 1625 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1626 return MCDisassembler::Fail; 1627 1628 return S; 1629 } 1630 1631 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1632 uint64_t Address, const void *Decoder) { 1633 DecodeStatus S = MCDisassembler::Success; 1634 1635 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1636 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1637 1638 switch (mode) { 1639 case 0: 1640 mode = ARM_AM::da; 1641 break; 1642 case 1: 1643 mode = ARM_AM::ia; 1644 break; 1645 case 2: 1646 mode = ARM_AM::db; 1647 break; 1648 case 3: 1649 mode = ARM_AM::ib; 1650 break; 1651 } 1652 1653 Inst.addOperand(MCOperand::CreateImm(mode)); 1654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1655 return MCDisassembler::Fail; 1656 1657 return S; 1658 } 1659 1660 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1661 unsigned Insn, 1662 uint64_t Address, const void *Decoder) { 1663 DecodeStatus S = MCDisassembler::Success; 1664 1665 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1666 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1667 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1668 1669 if (pred == 0xF) { 1670 switch (Inst.getOpcode()) { 1671 case ARM::LDMDA: 1672 Inst.setOpcode(ARM::RFEDA); 1673 break; 1674 case ARM::LDMDA_UPD: 1675 Inst.setOpcode(ARM::RFEDA_UPD); 1676 break; 1677 case ARM::LDMDB: 1678 Inst.setOpcode(ARM::RFEDB); 1679 break; 1680 case ARM::LDMDB_UPD: 1681 Inst.setOpcode(ARM::RFEDB_UPD); 1682 break; 1683 case ARM::LDMIA: 1684 Inst.setOpcode(ARM::RFEIA); 1685 break; 1686 case ARM::LDMIA_UPD: 1687 Inst.setOpcode(ARM::RFEIA_UPD); 1688 break; 1689 case ARM::LDMIB: 1690 Inst.setOpcode(ARM::RFEIB); 1691 break; 1692 case ARM::LDMIB_UPD: 1693 Inst.setOpcode(ARM::RFEIB_UPD); 1694 break; 1695 case ARM::STMDA: 1696 Inst.setOpcode(ARM::SRSDA); 1697 break; 1698 case ARM::STMDA_UPD: 1699 Inst.setOpcode(ARM::SRSDA_UPD); 1700 break; 1701 case ARM::STMDB: 1702 Inst.setOpcode(ARM::SRSDB); 1703 break; 1704 case ARM::STMDB_UPD: 1705 Inst.setOpcode(ARM::SRSDB_UPD); 1706 break; 1707 case ARM::STMIA: 1708 Inst.setOpcode(ARM::SRSIA); 1709 break; 1710 case ARM::STMIA_UPD: 1711 Inst.setOpcode(ARM::SRSIA_UPD); 1712 break; 1713 case ARM::STMIB: 1714 Inst.setOpcode(ARM::SRSIB); 1715 break; 1716 case ARM::STMIB_UPD: 1717 Inst.setOpcode(ARM::SRSIB_UPD); 1718 break; 1719 default: 1720 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1721 } 1722 1723 // For stores (which become SRS's, the only operand is the mode. 1724 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1725 Inst.addOperand( 1726 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1727 return S; 1728 } 1729 1730 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1731 } 1732 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1736 return MCDisassembler::Fail; // Tied 1737 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1738 return MCDisassembler::Fail; 1739 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 1742 return S; 1743 } 1744 1745 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1746 uint64_t Address, const void *Decoder) { 1747 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1748 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1749 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1750 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1751 1752 DecodeStatus S = MCDisassembler::Success; 1753 1754 // imod == '01' --> UNPREDICTABLE 1755 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1756 // return failure here. The '01' imod value is unprintable, so there's 1757 // nothing useful we could do even if we returned UNPREDICTABLE. 1758 1759 if (imod == 1) return MCDisassembler::Fail; 1760 1761 if (imod && M) { 1762 Inst.setOpcode(ARM::CPS3p); 1763 Inst.addOperand(MCOperand::CreateImm(imod)); 1764 Inst.addOperand(MCOperand::CreateImm(iflags)); 1765 Inst.addOperand(MCOperand::CreateImm(mode)); 1766 } else if (imod && !M) { 1767 Inst.setOpcode(ARM::CPS2p); 1768 Inst.addOperand(MCOperand::CreateImm(imod)); 1769 Inst.addOperand(MCOperand::CreateImm(iflags)); 1770 if (mode) S = MCDisassembler::SoftFail; 1771 } else if (!imod && M) { 1772 Inst.setOpcode(ARM::CPS1p); 1773 Inst.addOperand(MCOperand::CreateImm(mode)); 1774 if (iflags) S = MCDisassembler::SoftFail; 1775 } else { 1776 // imod == '00' && M == '0' --> UNPREDICTABLE 1777 Inst.setOpcode(ARM::CPS1p); 1778 Inst.addOperand(MCOperand::CreateImm(mode)); 1779 S = MCDisassembler::SoftFail; 1780 } 1781 1782 return S; 1783 } 1784 1785 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1786 uint64_t Address, const void *Decoder) { 1787 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1788 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1789 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1790 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1791 1792 DecodeStatus S = MCDisassembler::Success; 1793 1794 // imod == '01' --> UNPREDICTABLE 1795 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1796 // return failure here. The '01' imod value is unprintable, so there's 1797 // nothing useful we could do even if we returned UNPREDICTABLE. 1798 1799 if (imod == 1) return MCDisassembler::Fail; 1800 1801 if (imod && M) { 1802 Inst.setOpcode(ARM::t2CPS3p); 1803 Inst.addOperand(MCOperand::CreateImm(imod)); 1804 Inst.addOperand(MCOperand::CreateImm(iflags)); 1805 Inst.addOperand(MCOperand::CreateImm(mode)); 1806 } else if (imod && !M) { 1807 Inst.setOpcode(ARM::t2CPS2p); 1808 Inst.addOperand(MCOperand::CreateImm(imod)); 1809 Inst.addOperand(MCOperand::CreateImm(iflags)); 1810 if (mode) S = MCDisassembler::SoftFail; 1811 } else if (!imod && M) { 1812 Inst.setOpcode(ARM::t2CPS1p); 1813 Inst.addOperand(MCOperand::CreateImm(mode)); 1814 if (iflags) S = MCDisassembler::SoftFail; 1815 } else { 1816 // imod == '00' && M == '0' --> UNPREDICTABLE 1817 Inst.setOpcode(ARM::t2CPS1p); 1818 Inst.addOperand(MCOperand::CreateImm(mode)); 1819 S = MCDisassembler::SoftFail; 1820 } 1821 1822 return S; 1823 } 1824 1825 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1826 uint64_t Address, const void *Decoder) { 1827 DecodeStatus S = MCDisassembler::Success; 1828 1829 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1830 unsigned imm = 0; 1831 1832 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1833 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1834 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1835 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1836 1837 if (Inst.getOpcode() == ARM::t2MOVTi16) 1838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 1843 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1844 Inst.addOperand(MCOperand::CreateImm(imm)); 1845 1846 return S; 1847 } 1848 1849 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1850 uint64_t Address, const void *Decoder) { 1851 DecodeStatus S = MCDisassembler::Success; 1852 1853 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1854 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1855 unsigned imm = 0; 1856 1857 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1858 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1859 1860 if (Inst.getOpcode() == ARM::MOVTi16) 1861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1862 return MCDisassembler::Fail; 1863 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1864 return MCDisassembler::Fail; 1865 1866 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1867 Inst.addOperand(MCOperand::CreateImm(imm)); 1868 1869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 1872 return S; 1873 } 1874 1875 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1876 uint64_t Address, const void *Decoder) { 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1880 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1881 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1882 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1883 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1884 1885 if (pred == 0xF) 1886 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1887 1888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1889 return MCDisassembler::Fail; 1890 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1891 return MCDisassembler::Fail; 1892 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1893 return MCDisassembler::Fail; 1894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1895 return MCDisassembler::Fail; 1896 1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 1900 return S; 1901 } 1902 1903 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned add = fieldFromInstruction32(Val, 12, 1); 1908 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1909 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1910 1911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 1914 if (!add) imm *= -1; 1915 if (imm == 0 && !add) imm = INT32_MIN; 1916 Inst.addOperand(MCOperand::CreateImm(imm)); 1917 if (Rn == 15) 1918 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1919 1920 return S; 1921 } 1922 1923 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1924 uint64_t Address, const void *Decoder) { 1925 DecodeStatus S = MCDisassembler::Success; 1926 1927 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1928 unsigned U = fieldFromInstruction32(Val, 8, 1); 1929 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1930 1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1932 return MCDisassembler::Fail; 1933 1934 if (U) 1935 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1936 else 1937 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1938 1939 return S; 1940 } 1941 1942 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1943 uint64_t Address, const void *Decoder) { 1944 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1945 } 1946 1947 static DecodeStatus 1948 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1949 uint64_t Address, const void *Decoder) { 1950 DecodeStatus S = MCDisassembler::Success; 1951 1952 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1953 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1954 1955 if (pred == 0xF) { 1956 Inst.setOpcode(ARM::BLXi); 1957 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1958 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1959 true, 4, Inst, Decoder)) 1960 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1961 return S; 1962 } 1963 1964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1965 true, 4, Inst, Decoder)) 1966 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1967 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 1970 return S; 1971 } 1972 1973 1974 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1975 uint64_t Address, const void *Decoder) { 1976 DecodeStatus S = MCDisassembler::Success; 1977 1978 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1979 unsigned align = fieldFromInstruction32(Val, 4, 2); 1980 1981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 if (!align) 1984 Inst.addOperand(MCOperand::CreateImm(0)); 1985 else 1986 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1987 1988 return S; 1989 } 1990 1991 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1992 uint64_t Address, const void *Decoder) { 1993 DecodeStatus S = MCDisassembler::Success; 1994 1995 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1996 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1997 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1999 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2001 2002 // First output register 2003 switch (Inst.getOpcode()) { 2004 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2005 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2006 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2007 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2008 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2009 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2010 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2011 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2012 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2013 2014 // FIXME: These go in the VLDnDup* functions, not here. 2015 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2016 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2017 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2018 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2019 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2020 return MCDisassembler::Fail; 2021 break; 2022 case ARM::VLD2b16: 2023 case ARM::VLD2b32: 2024 case ARM::VLD2b8: 2025 case ARM::VLD2b16wb_fixed: 2026 case ARM::VLD2b16wb_register: 2027 case ARM::VLD2b32wb_fixed: 2028 case ARM::VLD2b32wb_register: 2029 case ARM::VLD2b8wb_fixed: 2030 case ARM::VLD2b8wb_register: 2031 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2032 return MCDisassembler::Fail; 2033 break; 2034 default: 2035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2036 return MCDisassembler::Fail; 2037 } 2038 2039 // Second output register 2040 switch (Inst.getOpcode()) { 2041 case ARM::VLD3d8: 2042 case ARM::VLD3d16: 2043 case ARM::VLD3d32: 2044 case ARM::VLD3d8_UPD: 2045 case ARM::VLD3d16_UPD: 2046 case ARM::VLD3d32_UPD: 2047 case ARM::VLD4d8: 2048 case ARM::VLD4d16: 2049 case ARM::VLD4d32: 2050 case ARM::VLD4d8_UPD: 2051 case ARM::VLD4d16_UPD: 2052 case ARM::VLD4d32_UPD: 2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 break; 2056 case ARM::VLD3q8: 2057 case ARM::VLD3q16: 2058 case ARM::VLD3q32: 2059 case ARM::VLD3q8_UPD: 2060 case ARM::VLD3q16_UPD: 2061 case ARM::VLD3q32_UPD: 2062 case ARM::VLD4q8: 2063 case ARM::VLD4q16: 2064 case ARM::VLD4q32: 2065 case ARM::VLD4q8_UPD: 2066 case ARM::VLD4q16_UPD: 2067 case ARM::VLD4q32_UPD: 2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2069 return MCDisassembler::Fail; 2070 default: 2071 break; 2072 } 2073 2074 // Third output register 2075 switch(Inst.getOpcode()) { 2076 case ARM::VLD3d8: 2077 case ARM::VLD3d16: 2078 case ARM::VLD3d32: 2079 case ARM::VLD3d8_UPD: 2080 case ARM::VLD3d16_UPD: 2081 case ARM::VLD3d32_UPD: 2082 case ARM::VLD4d8: 2083 case ARM::VLD4d16: 2084 case ARM::VLD4d32: 2085 case ARM::VLD4d8_UPD: 2086 case ARM::VLD4d16_UPD: 2087 case ARM::VLD4d32_UPD: 2088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2089 return MCDisassembler::Fail; 2090 break; 2091 case ARM::VLD3q8: 2092 case ARM::VLD3q16: 2093 case ARM::VLD3q32: 2094 case ARM::VLD3q8_UPD: 2095 case ARM::VLD3q16_UPD: 2096 case ARM::VLD3q32_UPD: 2097 case ARM::VLD4q8: 2098 case ARM::VLD4q16: 2099 case ARM::VLD4q32: 2100 case ARM::VLD4q8_UPD: 2101 case ARM::VLD4q16_UPD: 2102 case ARM::VLD4q32_UPD: 2103 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 break; 2106 default: 2107 break; 2108 } 2109 2110 // Fourth output register 2111 switch (Inst.getOpcode()) { 2112 case ARM::VLD4d8: 2113 case ARM::VLD4d16: 2114 case ARM::VLD4d32: 2115 case ARM::VLD4d8_UPD: 2116 case ARM::VLD4d16_UPD: 2117 case ARM::VLD4d32_UPD: 2118 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 break; 2121 case ARM::VLD4q8: 2122 case ARM::VLD4q16: 2123 case ARM::VLD4q32: 2124 case ARM::VLD4q8_UPD: 2125 case ARM::VLD4q16_UPD: 2126 case ARM::VLD4q32_UPD: 2127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 break; 2130 default: 2131 break; 2132 } 2133 2134 // Writeback operand 2135 switch (Inst.getOpcode()) { 2136 case ARM::VLD1d8wb_fixed: 2137 case ARM::VLD1d16wb_fixed: 2138 case ARM::VLD1d32wb_fixed: 2139 case ARM::VLD1d64wb_fixed: 2140 case ARM::VLD1d8wb_register: 2141 case ARM::VLD1d16wb_register: 2142 case ARM::VLD1d32wb_register: 2143 case ARM::VLD1d64wb_register: 2144 case ARM::VLD1q8wb_fixed: 2145 case ARM::VLD1q16wb_fixed: 2146 case ARM::VLD1q32wb_fixed: 2147 case ARM::VLD1q64wb_fixed: 2148 case ARM::VLD1q8wb_register: 2149 case ARM::VLD1q16wb_register: 2150 case ARM::VLD1q32wb_register: 2151 case ARM::VLD1q64wb_register: 2152 case ARM::VLD1d8Twb_fixed: 2153 case ARM::VLD1d8Twb_register: 2154 case ARM::VLD1d16Twb_fixed: 2155 case ARM::VLD1d16Twb_register: 2156 case ARM::VLD1d32Twb_fixed: 2157 case ARM::VLD1d32Twb_register: 2158 case ARM::VLD1d64Twb_fixed: 2159 case ARM::VLD1d64Twb_register: 2160 case ARM::VLD1d8Qwb_fixed: 2161 case ARM::VLD1d8Qwb_register: 2162 case ARM::VLD1d16Qwb_fixed: 2163 case ARM::VLD1d16Qwb_register: 2164 case ARM::VLD1d32Qwb_fixed: 2165 case ARM::VLD1d32Qwb_register: 2166 case ARM::VLD1d64Qwb_fixed: 2167 case ARM::VLD1d64Qwb_register: 2168 case ARM::VLD2d8wb_fixed: 2169 case ARM::VLD2d16wb_fixed: 2170 case ARM::VLD2d32wb_fixed: 2171 case ARM::VLD2q8wb_fixed: 2172 case ARM::VLD2q16wb_fixed: 2173 case ARM::VLD2q32wb_fixed: 2174 case ARM::VLD2d8wb_register: 2175 case ARM::VLD2d16wb_register: 2176 case ARM::VLD2d32wb_register: 2177 case ARM::VLD2q8wb_register: 2178 case ARM::VLD2q16wb_register: 2179 case ARM::VLD2q32wb_register: 2180 case ARM::VLD2b8wb_fixed: 2181 case ARM::VLD2b16wb_fixed: 2182 case ARM::VLD2b32wb_fixed: 2183 case ARM::VLD2b8wb_register: 2184 case ARM::VLD2b16wb_register: 2185 case ARM::VLD2b32wb_register: 2186 case ARM::VLD3d8_UPD: 2187 case ARM::VLD3d16_UPD: 2188 case ARM::VLD3d32_UPD: 2189 case ARM::VLD3q8_UPD: 2190 case ARM::VLD3q16_UPD: 2191 case ARM::VLD3q32_UPD: 2192 case ARM::VLD4d8_UPD: 2193 case ARM::VLD4d16_UPD: 2194 case ARM::VLD4d32_UPD: 2195 case ARM::VLD4q8_UPD: 2196 case ARM::VLD4q16_UPD: 2197 case ARM::VLD4q32_UPD: 2198 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2199 return MCDisassembler::Fail; 2200 break; 2201 default: 2202 break; 2203 } 2204 2205 // AddrMode6 Base (register+alignment) 2206 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 2209 // AddrMode6 Offset (register) 2210 switch (Inst.getOpcode()) { 2211 default: 2212 // The below have been updated to have explicit am6offset split 2213 // between fixed and register offset. For those instructions not 2214 // yet updated, we need to add an additional reg0 operand for the 2215 // fixed variant. 2216 // 2217 // The fixed offset encodes as Rm == 0xd, so we check for that. 2218 if (Rm == 0xd) { 2219 Inst.addOperand(MCOperand::CreateReg(0)); 2220 break; 2221 } 2222 // Fall through to handle the register offset variant. 2223 case ARM::VLD1d8wb_fixed: 2224 case ARM::VLD1d16wb_fixed: 2225 case ARM::VLD1d32wb_fixed: 2226 case ARM::VLD1d64wb_fixed: 2227 case ARM::VLD1d8Twb_fixed: 2228 case ARM::VLD1d16Twb_fixed: 2229 case ARM::VLD1d32Twb_fixed: 2230 case ARM::VLD1d64Twb_fixed: 2231 case ARM::VLD1d8Qwb_fixed: 2232 case ARM::VLD1d16Qwb_fixed: 2233 case ARM::VLD1d32Qwb_fixed: 2234 case ARM::VLD1d64Qwb_fixed: 2235 case ARM::VLD1d8wb_register: 2236 case ARM::VLD1d16wb_register: 2237 case ARM::VLD1d32wb_register: 2238 case ARM::VLD1d64wb_register: 2239 case ARM::VLD1q8wb_fixed: 2240 case ARM::VLD1q16wb_fixed: 2241 case ARM::VLD1q32wb_fixed: 2242 case ARM::VLD1q64wb_fixed: 2243 case ARM::VLD1q8wb_register: 2244 case ARM::VLD1q16wb_register: 2245 case ARM::VLD1q32wb_register: 2246 case ARM::VLD1q64wb_register: 2247 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2248 // variant encodes Rm == 0xf. Anything else is a register offset post- 2249 // increment and we need to add the register operand to the instruction. 2250 if (Rm != 0xD && Rm != 0xF && 2251 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2252 return MCDisassembler::Fail; 2253 break; 2254 } 2255 2256 return S; 2257 } 2258 2259 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2260 uint64_t Address, const void *Decoder) { 2261 DecodeStatus S = MCDisassembler::Success; 2262 2263 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2264 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2265 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2266 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2267 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2268 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2269 2270 // Writeback Operand 2271 switch (Inst.getOpcode()) { 2272 case ARM::VST1d8wb_fixed: 2273 case ARM::VST1d16wb_fixed: 2274 case ARM::VST1d32wb_fixed: 2275 case ARM::VST1d64wb_fixed: 2276 case ARM::VST1d8wb_register: 2277 case ARM::VST1d16wb_register: 2278 case ARM::VST1d32wb_register: 2279 case ARM::VST1d64wb_register: 2280 case ARM::VST1q8wb_fixed: 2281 case ARM::VST1q16wb_fixed: 2282 case ARM::VST1q32wb_fixed: 2283 case ARM::VST1q64wb_fixed: 2284 case ARM::VST1q8wb_register: 2285 case ARM::VST1q16wb_register: 2286 case ARM::VST1q32wb_register: 2287 case ARM::VST1q64wb_register: 2288 case ARM::VST1d8Twb_fixed: 2289 case ARM::VST1d16Twb_fixed: 2290 case ARM::VST1d32Twb_fixed: 2291 case ARM::VST1d64Twb_fixed: 2292 case ARM::VST1d8Twb_register: 2293 case ARM::VST1d16Twb_register: 2294 case ARM::VST1d32Twb_register: 2295 case ARM::VST1d64Twb_register: 2296 case ARM::VST1d8Qwb_fixed: 2297 case ARM::VST1d16Qwb_fixed: 2298 case ARM::VST1d32Qwb_fixed: 2299 case ARM::VST1d64Qwb_fixed: 2300 case ARM::VST1d8Qwb_register: 2301 case ARM::VST1d16Qwb_register: 2302 case ARM::VST1d32Qwb_register: 2303 case ARM::VST1d64Qwb_register: 2304 case ARM::VST2d8wb_fixed: 2305 case ARM::VST2d16wb_fixed: 2306 case ARM::VST2d32wb_fixed: 2307 case ARM::VST2d8wb_register: 2308 case ARM::VST2d16wb_register: 2309 case ARM::VST2d32wb_register: 2310 case ARM::VST2q8wb_fixed: 2311 case ARM::VST2q16wb_fixed: 2312 case ARM::VST2q32wb_fixed: 2313 case ARM::VST2q8wb_register: 2314 case ARM::VST2q16wb_register: 2315 case ARM::VST2q32wb_register: 2316 case ARM::VST2b8wb_fixed: 2317 case ARM::VST2b16wb_fixed: 2318 case ARM::VST2b32wb_fixed: 2319 case ARM::VST2b8wb_register: 2320 case ARM::VST2b16wb_register: 2321 case ARM::VST2b32wb_register: 2322 case ARM::VST3d8_UPD: 2323 case ARM::VST3d16_UPD: 2324 case ARM::VST3d32_UPD: 2325 case ARM::VST3q8_UPD: 2326 case ARM::VST3q16_UPD: 2327 case ARM::VST3q32_UPD: 2328 case ARM::VST4d8_UPD: 2329 case ARM::VST4d16_UPD: 2330 case ARM::VST4d32_UPD: 2331 case ARM::VST4q8_UPD: 2332 case ARM::VST4q16_UPD: 2333 case ARM::VST4q32_UPD: 2334 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2335 return MCDisassembler::Fail; 2336 break; 2337 default: 2338 break; 2339 } 2340 2341 // AddrMode6 Base (register+alignment) 2342 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2343 return MCDisassembler::Fail; 2344 2345 // AddrMode6 Offset (register) 2346 switch (Inst.getOpcode()) { 2347 default: 2348 if (Rm == 0xD) 2349 Inst.addOperand(MCOperand::CreateReg(0)); 2350 else if (Rm != 0xF) { 2351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2352 return MCDisassembler::Fail; 2353 } 2354 break; 2355 case ARM::VST1d8wb_fixed: 2356 case ARM::VST1d16wb_fixed: 2357 case ARM::VST1d32wb_fixed: 2358 case ARM::VST1d64wb_fixed: 2359 case ARM::VST1q8wb_fixed: 2360 case ARM::VST1q16wb_fixed: 2361 case ARM::VST1q32wb_fixed: 2362 case ARM::VST1q64wb_fixed: 2363 break; 2364 } 2365 2366 2367 // First input register 2368 switch (Inst.getOpcode()) { 2369 case ARM::VST1q16: 2370 case ARM::VST1q32: 2371 case ARM::VST1q64: 2372 case ARM::VST1q8: 2373 case ARM::VST1q16wb_fixed: 2374 case ARM::VST1q16wb_register: 2375 case ARM::VST1q32wb_fixed: 2376 case ARM::VST1q32wb_register: 2377 case ARM::VST1q64wb_fixed: 2378 case ARM::VST1q64wb_register: 2379 case ARM::VST1q8wb_fixed: 2380 case ARM::VST1q8wb_register: 2381 case ARM::VST2d16: 2382 case ARM::VST2d32: 2383 case ARM::VST2d8: 2384 case ARM::VST2d16wb_fixed: 2385 case ARM::VST2d16wb_register: 2386 case ARM::VST2d32wb_fixed: 2387 case ARM::VST2d32wb_register: 2388 case ARM::VST2d8wb_fixed: 2389 case ARM::VST2d8wb_register: 2390 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2391 return MCDisassembler::Fail; 2392 break; 2393 case ARM::VST2b16: 2394 case ARM::VST2b32: 2395 case ARM::VST2b8: 2396 case ARM::VST2b16wb_fixed: 2397 case ARM::VST2b16wb_register: 2398 case ARM::VST2b32wb_fixed: 2399 case ARM::VST2b32wb_register: 2400 case ARM::VST2b8wb_fixed: 2401 case ARM::VST2b8wb_register: 2402 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2403 return MCDisassembler::Fail; 2404 break; 2405 default: 2406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 } 2409 2410 // Second input register 2411 switch (Inst.getOpcode()) { 2412 case ARM::VST3d8: 2413 case ARM::VST3d16: 2414 case ARM::VST3d32: 2415 case ARM::VST3d8_UPD: 2416 case ARM::VST3d16_UPD: 2417 case ARM::VST3d32_UPD: 2418 case ARM::VST4d8: 2419 case ARM::VST4d16: 2420 case ARM::VST4d32: 2421 case ARM::VST4d8_UPD: 2422 case ARM::VST4d16_UPD: 2423 case ARM::VST4d32_UPD: 2424 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2425 return MCDisassembler::Fail; 2426 break; 2427 case ARM::VST3q8: 2428 case ARM::VST3q16: 2429 case ARM::VST3q32: 2430 case ARM::VST3q8_UPD: 2431 case ARM::VST3q16_UPD: 2432 case ARM::VST3q32_UPD: 2433 case ARM::VST4q8: 2434 case ARM::VST4q16: 2435 case ARM::VST4q32: 2436 case ARM::VST4q8_UPD: 2437 case ARM::VST4q16_UPD: 2438 case ARM::VST4q32_UPD: 2439 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 break; 2442 default: 2443 break; 2444 } 2445 2446 // Third input register 2447 switch (Inst.getOpcode()) { 2448 case ARM::VST3d8: 2449 case ARM::VST3d16: 2450 case ARM::VST3d32: 2451 case ARM::VST3d8_UPD: 2452 case ARM::VST3d16_UPD: 2453 case ARM::VST3d32_UPD: 2454 case ARM::VST4d8: 2455 case ARM::VST4d16: 2456 case ARM::VST4d32: 2457 case ARM::VST4d8_UPD: 2458 case ARM::VST4d16_UPD: 2459 case ARM::VST4d32_UPD: 2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 break; 2463 case ARM::VST3q8: 2464 case ARM::VST3q16: 2465 case ARM::VST3q32: 2466 case ARM::VST3q8_UPD: 2467 case ARM::VST3q16_UPD: 2468 case ARM::VST3q32_UPD: 2469 case ARM::VST4q8: 2470 case ARM::VST4q16: 2471 case ARM::VST4q32: 2472 case ARM::VST4q8_UPD: 2473 case ARM::VST4q16_UPD: 2474 case ARM::VST4q32_UPD: 2475 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 break; 2478 default: 2479 break; 2480 } 2481 2482 // Fourth input register 2483 switch (Inst.getOpcode()) { 2484 case ARM::VST4d8: 2485 case ARM::VST4d16: 2486 case ARM::VST4d32: 2487 case ARM::VST4d8_UPD: 2488 case ARM::VST4d16_UPD: 2489 case ARM::VST4d32_UPD: 2490 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2491 return MCDisassembler::Fail; 2492 break; 2493 case ARM::VST4q8: 2494 case ARM::VST4q16: 2495 case ARM::VST4q32: 2496 case ARM::VST4q8_UPD: 2497 case ARM::VST4q16_UPD: 2498 case ARM::VST4q32_UPD: 2499 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2500 return MCDisassembler::Fail; 2501 break; 2502 default: 2503 break; 2504 } 2505 2506 return S; 2507 } 2508 2509 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2510 uint64_t Address, const void *Decoder) { 2511 DecodeStatus S = MCDisassembler::Success; 2512 2513 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2514 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2515 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2517 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2518 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2519 2520 align *= (1 << size); 2521 2522 switch (Inst.getOpcode()) { 2523 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2524 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2525 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2526 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2527 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2528 return MCDisassembler::Fail; 2529 break; 2530 default: 2531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 break; 2534 } 2535 if (Rm != 0xF) { 2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2537 return MCDisassembler::Fail; 2538 } 2539 2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2541 return MCDisassembler::Fail; 2542 Inst.addOperand(MCOperand::CreateImm(align)); 2543 2544 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2545 // variant encodes Rm == 0xf. Anything else is a register offset post- 2546 // increment and we need to add the register operand to the instruction. 2547 if (Rm != 0xD && Rm != 0xF && 2548 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2549 return MCDisassembler::Fail; 2550 2551 return S; 2552 } 2553 2554 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2555 uint64_t Address, const void *Decoder) { 2556 DecodeStatus S = MCDisassembler::Success; 2557 2558 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2559 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2560 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2561 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2562 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2563 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2564 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2565 align *= 2*size; 2566 2567 switch (Inst.getOpcode()) { 2568 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2569 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2570 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2571 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2572 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 break; 2575 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2576 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2577 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2578 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2579 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2580 return MCDisassembler::Fail; 2581 break; 2582 default: 2583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2584 return MCDisassembler::Fail; 2585 break; 2586 } 2587 2588 if (Rm != 0xF) 2589 Inst.addOperand(MCOperand::CreateImm(0)); 2590 2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 Inst.addOperand(MCOperand::CreateImm(align)); 2594 2595 if (Rm == 0xD) 2596 Inst.addOperand(MCOperand::CreateReg(0)); 2597 else if (Rm != 0xF) { 2598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2599 return MCDisassembler::Fail; 2600 } 2601 2602 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2603 return MCDisassembler::Fail; 2604 2605 return S; 2606 } 2607 2608 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2609 uint64_t Address, const void *Decoder) { 2610 DecodeStatus S = MCDisassembler::Success; 2611 2612 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2613 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2614 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2615 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2616 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2617 2618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2621 return MCDisassembler::Fail; 2622 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2623 return MCDisassembler::Fail; 2624 if (Rm != 0xF) { 2625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2626 return MCDisassembler::Fail; 2627 } 2628 2629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2630 return MCDisassembler::Fail; 2631 Inst.addOperand(MCOperand::CreateImm(0)); 2632 2633 if (Rm == 0xD) 2634 Inst.addOperand(MCOperand::CreateReg(0)); 2635 else if (Rm != 0xF) { 2636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2637 return MCDisassembler::Fail; 2638 } 2639 2640 return S; 2641 } 2642 2643 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2644 uint64_t Address, const void *Decoder) { 2645 DecodeStatus S = MCDisassembler::Success; 2646 2647 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2648 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2649 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2650 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2651 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2652 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2653 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2654 2655 if (size == 0x3) { 2656 size = 4; 2657 align = 16; 2658 } else { 2659 if (size == 2) { 2660 size = 1 << size; 2661 align *= 8; 2662 } else { 2663 size = 1 << size; 2664 align *= 4*size; 2665 } 2666 } 2667 2668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2669 return MCDisassembler::Fail; 2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2673 return MCDisassembler::Fail; 2674 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2675 return MCDisassembler::Fail; 2676 if (Rm != 0xF) { 2677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 } 2680 2681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 Inst.addOperand(MCOperand::CreateImm(align)); 2684 2685 if (Rm == 0xD) 2686 Inst.addOperand(MCOperand::CreateReg(0)); 2687 else if (Rm != 0xF) { 2688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2689 return MCDisassembler::Fail; 2690 } 2691 2692 return S; 2693 } 2694 2695 static DecodeStatus 2696 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2697 uint64_t Address, const void *Decoder) { 2698 DecodeStatus S = MCDisassembler::Success; 2699 2700 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2701 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2702 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2703 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2704 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2705 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2706 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2707 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2708 2709 if (Q) { 2710 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2711 return MCDisassembler::Fail; 2712 } else { 2713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 } 2716 2717 Inst.addOperand(MCOperand::CreateImm(imm)); 2718 2719 switch (Inst.getOpcode()) { 2720 case ARM::VORRiv4i16: 2721 case ARM::VORRiv2i32: 2722 case ARM::VBICiv4i16: 2723 case ARM::VBICiv2i32: 2724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 break; 2727 case ARM::VORRiv8i16: 2728 case ARM::VORRiv4i32: 2729 case ARM::VBICiv8i16: 2730 case ARM::VBICiv4i32: 2731 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2732 return MCDisassembler::Fail; 2733 break; 2734 default: 2735 break; 2736 } 2737 2738 return S; 2739 } 2740 2741 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2742 uint64_t Address, const void *Decoder) { 2743 DecodeStatus S = MCDisassembler::Success; 2744 2745 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2746 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2747 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2748 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2749 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2750 2751 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2756 2757 return S; 2758 } 2759 2760 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2761 uint64_t Address, const void *Decoder) { 2762 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2763 return MCDisassembler::Success; 2764 } 2765 2766 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2767 uint64_t Address, const void *Decoder) { 2768 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2769 return MCDisassembler::Success; 2770 } 2771 2772 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2773 uint64_t Address, const void *Decoder) { 2774 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2775 return MCDisassembler::Success; 2776 } 2777 2778 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2779 uint64_t Address, const void *Decoder) { 2780 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2781 return MCDisassembler::Success; 2782 } 2783 2784 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2785 uint64_t Address, const void *Decoder) { 2786 DecodeStatus S = MCDisassembler::Success; 2787 2788 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2789 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2790 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2791 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2792 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2793 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2794 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2795 2796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2797 return MCDisassembler::Fail; 2798 if (op) { 2799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2800 return MCDisassembler::Fail; // Writeback 2801 } 2802 2803 switch (Inst.getOpcode()) { 2804 case ARM::VTBL2: 2805 case ARM::VTBX2: 2806 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2807 return MCDisassembler::Fail; 2808 break; 2809 default: 2810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2811 return MCDisassembler::Fail; 2812 } 2813 2814 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2815 return MCDisassembler::Fail; 2816 2817 return S; 2818 } 2819 2820 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2821 uint64_t Address, const void *Decoder) { 2822 DecodeStatus S = MCDisassembler::Success; 2823 2824 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2825 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2826 2827 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2828 return MCDisassembler::Fail; 2829 2830 switch(Inst.getOpcode()) { 2831 default: 2832 return MCDisassembler::Fail; 2833 case ARM::tADR: 2834 break; // tADR does not explicitly represent the PC as an operand. 2835 case ARM::tADDrSPi: 2836 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2837 break; 2838 } 2839 2840 Inst.addOperand(MCOperand::CreateImm(imm)); 2841 return S; 2842 } 2843 2844 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2845 uint64_t Address, const void *Decoder) { 2846 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2847 return MCDisassembler::Success; 2848 } 2849 2850 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2851 uint64_t Address, const void *Decoder) { 2852 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2853 return MCDisassembler::Success; 2854 } 2855 2856 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2857 uint64_t Address, const void *Decoder) { 2858 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2859 return MCDisassembler::Success; 2860 } 2861 2862 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2863 uint64_t Address, const void *Decoder) { 2864 DecodeStatus S = MCDisassembler::Success; 2865 2866 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2867 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2868 2869 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2870 return MCDisassembler::Fail; 2871 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2872 return MCDisassembler::Fail; 2873 2874 return S; 2875 } 2876 2877 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2878 uint64_t Address, const void *Decoder) { 2879 DecodeStatus S = MCDisassembler::Success; 2880 2881 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2882 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2883 2884 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2885 return MCDisassembler::Fail; 2886 Inst.addOperand(MCOperand::CreateImm(imm)); 2887 2888 return S; 2889 } 2890 2891 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2892 uint64_t Address, const void *Decoder) { 2893 unsigned imm = Val << 2; 2894 2895 Inst.addOperand(MCOperand::CreateImm(imm)); 2896 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2897 2898 return MCDisassembler::Success; 2899 } 2900 2901 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2902 uint64_t Address, const void *Decoder) { 2903 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2904 Inst.addOperand(MCOperand::CreateImm(Val)); 2905 2906 return MCDisassembler::Success; 2907 } 2908 2909 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2910 uint64_t Address, const void *Decoder) { 2911 DecodeStatus S = MCDisassembler::Success; 2912 2913 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2914 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2915 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2916 2917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 Inst.addOperand(MCOperand::CreateImm(imm)); 2922 2923 return S; 2924 } 2925 2926 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2927 uint64_t Address, const void *Decoder) { 2928 DecodeStatus S = MCDisassembler::Success; 2929 2930 switch (Inst.getOpcode()) { 2931 case ARM::t2PLDs: 2932 case ARM::t2PLDWs: 2933 case ARM::t2PLIs: 2934 break; 2935 default: { 2936 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2937 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 } 2940 } 2941 2942 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2943 if (Rn == 0xF) { 2944 switch (Inst.getOpcode()) { 2945 case ARM::t2LDRBs: 2946 Inst.setOpcode(ARM::t2LDRBpci); 2947 break; 2948 case ARM::t2LDRHs: 2949 Inst.setOpcode(ARM::t2LDRHpci); 2950 break; 2951 case ARM::t2LDRSHs: 2952 Inst.setOpcode(ARM::t2LDRSHpci); 2953 break; 2954 case ARM::t2LDRSBs: 2955 Inst.setOpcode(ARM::t2LDRSBpci); 2956 break; 2957 case ARM::t2PLDs: 2958 Inst.setOpcode(ARM::t2PLDi12); 2959 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2960 break; 2961 default: 2962 return MCDisassembler::Fail; 2963 } 2964 2965 int imm = fieldFromInstruction32(Insn, 0, 12); 2966 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2967 Inst.addOperand(MCOperand::CreateImm(imm)); 2968 2969 return S; 2970 } 2971 2972 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2973 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2974 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2975 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2976 return MCDisassembler::Fail; 2977 2978 return S; 2979 } 2980 2981 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2982 uint64_t Address, const void *Decoder) { 2983 int imm = Val & 0xFF; 2984 if (!(Val & 0x100)) imm *= -1; 2985 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2986 2987 return MCDisassembler::Success; 2988 } 2989 2990 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2991 uint64_t Address, const void *Decoder) { 2992 DecodeStatus S = MCDisassembler::Success; 2993 2994 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2995 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2996 2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 3002 return S; 3003 } 3004 3005 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 3006 uint64_t Address, const void *Decoder) { 3007 DecodeStatus S = MCDisassembler::Success; 3008 3009 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3010 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3011 3012 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 3015 Inst.addOperand(MCOperand::CreateImm(imm)); 3016 3017 return S; 3018 } 3019 3020 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 3021 uint64_t Address, const void *Decoder) { 3022 int imm = Val & 0xFF; 3023 if (Val == 0) 3024 imm = INT32_MIN; 3025 else if (!(Val & 0x100)) 3026 imm *= -1; 3027 Inst.addOperand(MCOperand::CreateImm(imm)); 3028 3029 return MCDisassembler::Success; 3030 } 3031 3032 3033 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 3034 uint64_t Address, const void *Decoder) { 3035 DecodeStatus S = MCDisassembler::Success; 3036 3037 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3038 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3039 3040 // Some instructions always use an additive offset. 3041 switch (Inst.getOpcode()) { 3042 case ARM::t2LDRT: 3043 case ARM::t2LDRBT: 3044 case ARM::t2LDRHT: 3045 case ARM::t2LDRSBT: 3046 case ARM::t2LDRSHT: 3047 case ARM::t2STRT: 3048 case ARM::t2STRBT: 3049 case ARM::t2STRHT: 3050 imm |= 0x100; 3051 break; 3052 default: 3053 break; 3054 } 3055 3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3057 return MCDisassembler::Fail; 3058 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 3061 return S; 3062 } 3063 3064 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 3065 uint64_t Address, const void *Decoder) { 3066 DecodeStatus S = MCDisassembler::Success; 3067 3068 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3070 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3071 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3072 addr |= Rn << 9; 3073 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3074 3075 if (!load) { 3076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3077 return MCDisassembler::Fail; 3078 } 3079 3080 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3081 return MCDisassembler::Fail; 3082 3083 if (load) { 3084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 } 3087 3088 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 3091 return S; 3092 } 3093 3094 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 3095 uint64_t Address, const void *Decoder) { 3096 DecodeStatus S = MCDisassembler::Success; 3097 3098 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3099 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3100 3101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3102 return MCDisassembler::Fail; 3103 Inst.addOperand(MCOperand::CreateImm(imm)); 3104 3105 return S; 3106 } 3107 3108 3109 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 3110 uint64_t Address, const void *Decoder) { 3111 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3112 3113 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3114 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3115 Inst.addOperand(MCOperand::CreateImm(imm)); 3116 3117 return MCDisassembler::Success; 3118 } 3119 3120 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3121 uint64_t Address, const void *Decoder) { 3122 DecodeStatus S = MCDisassembler::Success; 3123 3124 if (Inst.getOpcode() == ARM::tADDrSP) { 3125 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3126 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3127 3128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3129 return MCDisassembler::Fail; 3130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3131 return MCDisassembler::Fail; 3132 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3133 } else if (Inst.getOpcode() == ARM::tADDspr) { 3134 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3135 3136 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3137 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 } 3141 3142 return S; 3143 } 3144 3145 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3146 uint64_t Address, const void *Decoder) { 3147 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3148 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3149 3150 Inst.addOperand(MCOperand::CreateImm(imod)); 3151 Inst.addOperand(MCOperand::CreateImm(flags)); 3152 3153 return MCDisassembler::Success; 3154 } 3155 3156 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3157 uint64_t Address, const void *Decoder) { 3158 DecodeStatus S = MCDisassembler::Success; 3159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3160 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3161 3162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3163 return MCDisassembler::Fail; 3164 Inst.addOperand(MCOperand::CreateImm(add)); 3165 3166 return S; 3167 } 3168 3169 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3170 uint64_t Address, const void *Decoder) { 3171 if (!tryAddingSymbolicOperand(Address, 3172 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3173 true, 4, Inst, Decoder)) 3174 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3175 return MCDisassembler::Success; 3176 } 3177 3178 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3179 uint64_t Address, const void *Decoder) { 3180 if (Val == 0xA || Val == 0xB) 3181 return MCDisassembler::Fail; 3182 3183 Inst.addOperand(MCOperand::CreateImm(Val)); 3184 return MCDisassembler::Success; 3185 } 3186 3187 static DecodeStatus 3188 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3189 uint64_t Address, const void *Decoder) { 3190 DecodeStatus S = MCDisassembler::Success; 3191 3192 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3193 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3194 3195 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3197 return MCDisassembler::Fail; 3198 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3199 return MCDisassembler::Fail; 3200 return S; 3201 } 3202 3203 static DecodeStatus 3204 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3205 uint64_t Address, const void *Decoder) { 3206 DecodeStatus S = MCDisassembler::Success; 3207 3208 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3209 if (pred == 0xE || pred == 0xF) { 3210 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3211 switch (opc) { 3212 default: 3213 return MCDisassembler::Fail; 3214 case 0xf3bf8f4: 3215 Inst.setOpcode(ARM::t2DSB); 3216 break; 3217 case 0xf3bf8f5: 3218 Inst.setOpcode(ARM::t2DMB); 3219 break; 3220 case 0xf3bf8f6: 3221 Inst.setOpcode(ARM::t2ISB); 3222 break; 3223 } 3224 3225 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3226 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3227 } 3228 3229 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3230 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3231 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3232 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3233 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3234 3235 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3238 return MCDisassembler::Fail; 3239 3240 return S; 3241 } 3242 3243 // Decode a shifted immediate operand. These basically consist 3244 // of an 8-bit value, and a 4-bit directive that specifies either 3245 // a splat operation or a rotation. 3246 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3247 uint64_t Address, const void *Decoder) { 3248 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3249 if (ctrl == 0) { 3250 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3251 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3252 switch (byte) { 3253 case 0: 3254 Inst.addOperand(MCOperand::CreateImm(imm)); 3255 break; 3256 case 1: 3257 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3258 break; 3259 case 2: 3260 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3261 break; 3262 case 3: 3263 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3264 (imm << 8) | imm)); 3265 break; 3266 } 3267 } else { 3268 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3269 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3270 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3271 Inst.addOperand(MCOperand::CreateImm(imm)); 3272 } 3273 3274 return MCDisassembler::Success; 3275 } 3276 3277 static DecodeStatus 3278 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3279 uint64_t Address, const void *Decoder){ 3280 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3281 return MCDisassembler::Success; 3282 } 3283 3284 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3285 uint64_t Address, const void *Decoder){ 3286 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3287 true, 4, Inst, Decoder)) 3288 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3289 return MCDisassembler::Success; 3290 } 3291 3292 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3293 uint64_t Address, const void *Decoder) { 3294 switch (Val) { 3295 default: 3296 return MCDisassembler::Fail; 3297 case 0xF: // SY 3298 case 0xE: // ST 3299 case 0xB: // ISH 3300 case 0xA: // ISHST 3301 case 0x7: // NSH 3302 case 0x6: // NSHST 3303 case 0x3: // OSH 3304 case 0x2: // OSHST 3305 break; 3306 } 3307 3308 Inst.addOperand(MCOperand::CreateImm(Val)); 3309 return MCDisassembler::Success; 3310 } 3311 3312 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3313 uint64_t Address, const void *Decoder) { 3314 if (!Val) return MCDisassembler::Fail; 3315 Inst.addOperand(MCOperand::CreateImm(Val)); 3316 return MCDisassembler::Success; 3317 } 3318 3319 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3320 uint64_t Address, const void *Decoder) { 3321 DecodeStatus S = MCDisassembler::Success; 3322 3323 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3324 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3325 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3326 3327 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3328 3329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 3338 return S; 3339 } 3340 3341 3342 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3343 uint64_t Address, const void *Decoder){ 3344 DecodeStatus S = MCDisassembler::Success; 3345 3346 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3347 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3348 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3349 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3350 3351 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 3354 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3355 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3356 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3360 return MCDisassembler::Fail; 3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 3366 return S; 3367 } 3368 3369 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3370 uint64_t Address, const void *Decoder) { 3371 DecodeStatus S = MCDisassembler::Success; 3372 3373 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3374 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3375 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3376 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3377 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3378 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3379 3380 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3381 3382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3383 return MCDisassembler::Fail; 3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3389 return MCDisassembler::Fail; 3390 3391 return S; 3392 } 3393 3394 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3395 uint64_t Address, const void *Decoder) { 3396 DecodeStatus S = MCDisassembler::Success; 3397 3398 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3399 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3400 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3401 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3402 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3403 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3404 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3405 3406 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3407 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3408 3409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3410 return MCDisassembler::Fail; 3411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3412 return MCDisassembler::Fail; 3413 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3414 return MCDisassembler::Fail; 3415 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 3418 return S; 3419 } 3420 3421 3422 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3423 uint64_t Address, const void *Decoder) { 3424 DecodeStatus S = MCDisassembler::Success; 3425 3426 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3427 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3428 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3429 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3430 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3431 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3432 3433 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3434 3435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 3444 return S; 3445 } 3446 3447 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3448 uint64_t Address, const void *Decoder) { 3449 DecodeStatus S = MCDisassembler::Success; 3450 3451 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3452 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3453 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3454 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3455 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3456 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3457 3458 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3459 3460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 3469 return S; 3470 } 3471 3472 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3473 uint64_t Address, const void *Decoder) { 3474 DecodeStatus S = MCDisassembler::Success; 3475 3476 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3477 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3478 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3479 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3480 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3481 3482 unsigned align = 0; 3483 unsigned index = 0; 3484 switch (size) { 3485 default: 3486 return MCDisassembler::Fail; 3487 case 0: 3488 if (fieldFromInstruction32(Insn, 4, 1)) 3489 return MCDisassembler::Fail; // UNDEFINED 3490 index = fieldFromInstruction32(Insn, 5, 3); 3491 break; 3492 case 1: 3493 if (fieldFromInstruction32(Insn, 5, 1)) 3494 return MCDisassembler::Fail; // UNDEFINED 3495 index = fieldFromInstruction32(Insn, 6, 2); 3496 if (fieldFromInstruction32(Insn, 4, 1)) 3497 align = 2; 3498 break; 3499 case 2: 3500 if (fieldFromInstruction32(Insn, 6, 1)) 3501 return MCDisassembler::Fail; // UNDEFINED 3502 index = fieldFromInstruction32(Insn, 7, 1); 3503 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3504 align = 4; 3505 } 3506 3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 if (Rm != 0xF) { // Writeback 3510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3511 return MCDisassembler::Fail; 3512 } 3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 Inst.addOperand(MCOperand::CreateImm(align)); 3516 if (Rm != 0xF) { 3517 if (Rm != 0xD) { 3518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3519 return MCDisassembler::Fail; 3520 } else 3521 Inst.addOperand(MCOperand::CreateReg(0)); 3522 } 3523 3524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 Inst.addOperand(MCOperand::CreateImm(index)); 3527 3528 return S; 3529 } 3530 3531 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3532 uint64_t Address, const void *Decoder) { 3533 DecodeStatus S = MCDisassembler::Success; 3534 3535 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3536 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3537 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3538 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3539 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3540 3541 unsigned align = 0; 3542 unsigned index = 0; 3543 switch (size) { 3544 default: 3545 return MCDisassembler::Fail; 3546 case 0: 3547 if (fieldFromInstruction32(Insn, 4, 1)) 3548 return MCDisassembler::Fail; // UNDEFINED 3549 index = fieldFromInstruction32(Insn, 5, 3); 3550 break; 3551 case 1: 3552 if (fieldFromInstruction32(Insn, 5, 1)) 3553 return MCDisassembler::Fail; // UNDEFINED 3554 index = fieldFromInstruction32(Insn, 6, 2); 3555 if (fieldFromInstruction32(Insn, 4, 1)) 3556 align = 2; 3557 break; 3558 case 2: 3559 if (fieldFromInstruction32(Insn, 6, 1)) 3560 return MCDisassembler::Fail; // UNDEFINED 3561 index = fieldFromInstruction32(Insn, 7, 1); 3562 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3563 align = 4; 3564 } 3565 3566 if (Rm != 0xF) { // Writeback 3567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 } 3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 Inst.addOperand(MCOperand::CreateImm(align)); 3573 if (Rm != 0xF) { 3574 if (Rm != 0xD) { 3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 } else 3578 Inst.addOperand(MCOperand::CreateReg(0)); 3579 } 3580 3581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 Inst.addOperand(MCOperand::CreateImm(index)); 3584 3585 return S; 3586 } 3587 3588 3589 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3590 uint64_t Address, const void *Decoder) { 3591 DecodeStatus S = MCDisassembler::Success; 3592 3593 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3594 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3595 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3596 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3597 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3598 3599 unsigned align = 0; 3600 unsigned index = 0; 3601 unsigned inc = 1; 3602 switch (size) { 3603 default: 3604 return MCDisassembler::Fail; 3605 case 0: 3606 index = fieldFromInstruction32(Insn, 5, 3); 3607 if (fieldFromInstruction32(Insn, 4, 1)) 3608 align = 2; 3609 break; 3610 case 1: 3611 index = fieldFromInstruction32(Insn, 6, 2); 3612 if (fieldFromInstruction32(Insn, 4, 1)) 3613 align = 4; 3614 if (fieldFromInstruction32(Insn, 5, 1)) 3615 inc = 2; 3616 break; 3617 case 2: 3618 if (fieldFromInstruction32(Insn, 5, 1)) 3619 return MCDisassembler::Fail; // UNDEFINED 3620 index = fieldFromInstruction32(Insn, 7, 1); 3621 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3622 align = 8; 3623 if (fieldFromInstruction32(Insn, 6, 1)) 3624 inc = 2; 3625 break; 3626 } 3627 3628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3629 return MCDisassembler::Fail; 3630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 if (Rm != 0xF) { // Writeback 3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 } 3636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 Inst.addOperand(MCOperand::CreateImm(align)); 3639 if (Rm != 0xF) { 3640 if (Rm != 0xD) { 3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 } else 3644 Inst.addOperand(MCOperand::CreateReg(0)); 3645 } 3646 3647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 Inst.addOperand(MCOperand::CreateImm(index)); 3652 3653 return S; 3654 } 3655 3656 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3657 uint64_t Address, const void *Decoder) { 3658 DecodeStatus S = MCDisassembler::Success; 3659 3660 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3661 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3662 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3663 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3664 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3665 3666 unsigned align = 0; 3667 unsigned index = 0; 3668 unsigned inc = 1; 3669 switch (size) { 3670 default: 3671 return MCDisassembler::Fail; 3672 case 0: 3673 index = fieldFromInstruction32(Insn, 5, 3); 3674 if (fieldFromInstruction32(Insn, 4, 1)) 3675 align = 2; 3676 break; 3677 case 1: 3678 index = fieldFromInstruction32(Insn, 6, 2); 3679 if (fieldFromInstruction32(Insn, 4, 1)) 3680 align = 4; 3681 if (fieldFromInstruction32(Insn, 5, 1)) 3682 inc = 2; 3683 break; 3684 case 2: 3685 if (fieldFromInstruction32(Insn, 5, 1)) 3686 return MCDisassembler::Fail; // UNDEFINED 3687 index = fieldFromInstruction32(Insn, 7, 1); 3688 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3689 align = 8; 3690 if (fieldFromInstruction32(Insn, 6, 1)) 3691 inc = 2; 3692 break; 3693 } 3694 3695 if (Rm != 0xF) { // Writeback 3696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 } 3699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3700 return MCDisassembler::Fail; 3701 Inst.addOperand(MCOperand::CreateImm(align)); 3702 if (Rm != 0xF) { 3703 if (Rm != 0xD) { 3704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 } else 3707 Inst.addOperand(MCOperand::CreateReg(0)); 3708 } 3709 3710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 Inst.addOperand(MCOperand::CreateImm(index)); 3715 3716 return S; 3717 } 3718 3719 3720 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3721 uint64_t Address, const void *Decoder) { 3722 DecodeStatus S = MCDisassembler::Success; 3723 3724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3725 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3726 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3727 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3728 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3729 3730 unsigned align = 0; 3731 unsigned index = 0; 3732 unsigned inc = 1; 3733 switch (size) { 3734 default: 3735 return MCDisassembler::Fail; 3736 case 0: 3737 if (fieldFromInstruction32(Insn, 4, 1)) 3738 return MCDisassembler::Fail; // UNDEFINED 3739 index = fieldFromInstruction32(Insn, 5, 3); 3740 break; 3741 case 1: 3742 if (fieldFromInstruction32(Insn, 4, 1)) 3743 return MCDisassembler::Fail; // UNDEFINED 3744 index = fieldFromInstruction32(Insn, 6, 2); 3745 if (fieldFromInstruction32(Insn, 5, 1)) 3746 inc = 2; 3747 break; 3748 case 2: 3749 if (fieldFromInstruction32(Insn, 4, 2)) 3750 return MCDisassembler::Fail; // UNDEFINED 3751 index = fieldFromInstruction32(Insn, 7, 1); 3752 if (fieldFromInstruction32(Insn, 6, 1)) 3753 inc = 2; 3754 break; 3755 } 3756 3757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 3764 if (Rm != 0xF) { // Writeback 3765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3766 return MCDisassembler::Fail; 3767 } 3768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3769 return MCDisassembler::Fail; 3770 Inst.addOperand(MCOperand::CreateImm(align)); 3771 if (Rm != 0xF) { 3772 if (Rm != 0xD) { 3773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3774 return MCDisassembler::Fail; 3775 } else 3776 Inst.addOperand(MCOperand::CreateReg(0)); 3777 } 3778 3779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3784 return MCDisassembler::Fail; 3785 Inst.addOperand(MCOperand::CreateImm(index)); 3786 3787 return S; 3788 } 3789 3790 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3791 uint64_t Address, const void *Decoder) { 3792 DecodeStatus S = MCDisassembler::Success; 3793 3794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3795 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3796 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3797 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3798 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3799 3800 unsigned align = 0; 3801 unsigned index = 0; 3802 unsigned inc = 1; 3803 switch (size) { 3804 default: 3805 return MCDisassembler::Fail; 3806 case 0: 3807 if (fieldFromInstruction32(Insn, 4, 1)) 3808 return MCDisassembler::Fail; // UNDEFINED 3809 index = fieldFromInstruction32(Insn, 5, 3); 3810 break; 3811 case 1: 3812 if (fieldFromInstruction32(Insn, 4, 1)) 3813 return MCDisassembler::Fail; // UNDEFINED 3814 index = fieldFromInstruction32(Insn, 6, 2); 3815 if (fieldFromInstruction32(Insn, 5, 1)) 3816 inc = 2; 3817 break; 3818 case 2: 3819 if (fieldFromInstruction32(Insn, 4, 2)) 3820 return MCDisassembler::Fail; // UNDEFINED 3821 index = fieldFromInstruction32(Insn, 7, 1); 3822 if (fieldFromInstruction32(Insn, 6, 1)) 3823 inc = 2; 3824 break; 3825 } 3826 3827 if (Rm != 0xF) { // Writeback 3828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 } 3831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3832 return MCDisassembler::Fail; 3833 Inst.addOperand(MCOperand::CreateImm(align)); 3834 if (Rm != 0xF) { 3835 if (Rm != 0xD) { 3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3837 return MCDisassembler::Fail; 3838 } else 3839 Inst.addOperand(MCOperand::CreateReg(0)); 3840 } 3841 3842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3843 return MCDisassembler::Fail; 3844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3845 return MCDisassembler::Fail; 3846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3847 return MCDisassembler::Fail; 3848 Inst.addOperand(MCOperand::CreateImm(index)); 3849 3850 return S; 3851 } 3852 3853 3854 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3855 uint64_t Address, const void *Decoder) { 3856 DecodeStatus S = MCDisassembler::Success; 3857 3858 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3859 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3860 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3861 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3862 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3863 3864 unsigned align = 0; 3865 unsigned index = 0; 3866 unsigned inc = 1; 3867 switch (size) { 3868 default: 3869 return MCDisassembler::Fail; 3870 case 0: 3871 if (fieldFromInstruction32(Insn, 4, 1)) 3872 align = 4; 3873 index = fieldFromInstruction32(Insn, 5, 3); 3874 break; 3875 case 1: 3876 if (fieldFromInstruction32(Insn, 4, 1)) 3877 align = 8; 3878 index = fieldFromInstruction32(Insn, 6, 2); 3879 if (fieldFromInstruction32(Insn, 5, 1)) 3880 inc = 2; 3881 break; 3882 case 2: 3883 if (fieldFromInstruction32(Insn, 4, 2)) 3884 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3885 index = fieldFromInstruction32(Insn, 7, 1); 3886 if (fieldFromInstruction32(Insn, 6, 1)) 3887 inc = 2; 3888 break; 3889 } 3890 3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3894 return MCDisassembler::Fail; 3895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3896 return MCDisassembler::Fail; 3897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 3900 if (Rm != 0xF) { // Writeback 3901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 } 3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 Inst.addOperand(MCOperand::CreateImm(align)); 3907 if (Rm != 0xF) { 3908 if (Rm != 0xD) { 3909 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3910 return MCDisassembler::Fail; 3911 } else 3912 Inst.addOperand(MCOperand::CreateReg(0)); 3913 } 3914 3915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3916 return MCDisassembler::Fail; 3917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3918 return MCDisassembler::Fail; 3919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3920 return MCDisassembler::Fail; 3921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 Inst.addOperand(MCOperand::CreateImm(index)); 3924 3925 return S; 3926 } 3927 3928 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3929 uint64_t Address, const void *Decoder) { 3930 DecodeStatus S = MCDisassembler::Success; 3931 3932 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3933 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3934 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3935 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3936 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3937 3938 unsigned align = 0; 3939 unsigned index = 0; 3940 unsigned inc = 1; 3941 switch (size) { 3942 default: 3943 return MCDisassembler::Fail; 3944 case 0: 3945 if (fieldFromInstruction32(Insn, 4, 1)) 3946 align = 4; 3947 index = fieldFromInstruction32(Insn, 5, 3); 3948 break; 3949 case 1: 3950 if (fieldFromInstruction32(Insn, 4, 1)) 3951 align = 8; 3952 index = fieldFromInstruction32(Insn, 6, 2); 3953 if (fieldFromInstruction32(Insn, 5, 1)) 3954 inc = 2; 3955 break; 3956 case 2: 3957 if (fieldFromInstruction32(Insn, 4, 2)) 3958 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3959 index = fieldFromInstruction32(Insn, 7, 1); 3960 if (fieldFromInstruction32(Insn, 6, 1)) 3961 inc = 2; 3962 break; 3963 } 3964 3965 if (Rm != 0xF) { // Writeback 3966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3967 return MCDisassembler::Fail; 3968 } 3969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3970 return MCDisassembler::Fail; 3971 Inst.addOperand(MCOperand::CreateImm(align)); 3972 if (Rm != 0xF) { 3973 if (Rm != 0xD) { 3974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3975 return MCDisassembler::Fail; 3976 } else 3977 Inst.addOperand(MCOperand::CreateReg(0)); 3978 } 3979 3980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3981 return MCDisassembler::Fail; 3982 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3983 return MCDisassembler::Fail; 3984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3985 return MCDisassembler::Fail; 3986 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3987 return MCDisassembler::Fail; 3988 Inst.addOperand(MCOperand::CreateImm(index)); 3989 3990 return S; 3991 } 3992 3993 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3994 uint64_t Address, const void *Decoder) { 3995 DecodeStatus S = MCDisassembler::Success; 3996 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3997 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3998 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3999 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4000 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4001 4002 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4003 S = MCDisassembler::SoftFail; 4004 4005 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 4016 return S; 4017 } 4018 4019 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 4020 uint64_t Address, const void *Decoder) { 4021 DecodeStatus S = MCDisassembler::Success; 4022 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4023 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4024 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4025 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4026 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4027 4028 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4029 S = MCDisassembler::SoftFail; 4030 4031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4038 return MCDisassembler::Fail; 4039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4040 return MCDisassembler::Fail; 4041 4042 return S; 4043 } 4044 4045 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 4046 uint64_t Address, const void *Decoder) { 4047 DecodeStatus S = MCDisassembler::Success; 4048 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4049 // The InstPrinter needs to have the low bit of the predicate in 4050 // the mask operand to be able to print it properly. 4051 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4052 4053 if (pred == 0xF) { 4054 pred = 0xE; 4055 S = MCDisassembler::SoftFail; 4056 } 4057 4058 if ((mask & 0xF) == 0) { 4059 // Preserve the high bit of the mask, which is the low bit of 4060 // the predicate. 4061 mask &= 0x10; 4062 mask |= 0x8; 4063 S = MCDisassembler::SoftFail; 4064 } 4065 4066 Inst.addOperand(MCOperand::CreateImm(pred)); 4067 Inst.addOperand(MCOperand::CreateImm(mask)); 4068 return S; 4069 } 4070 4071 static DecodeStatus 4072 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4073 uint64_t Address, const void *Decoder) { 4074 DecodeStatus S = MCDisassembler::Success; 4075 4076 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4077 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4078 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4079 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4080 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4081 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4082 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4083 bool writeback = (W == 1) | (P == 0); 4084 4085 addr |= (U << 8) | (Rn << 9); 4086 4087 if (writeback && (Rn == Rt || Rn == Rt2)) 4088 Check(S, MCDisassembler::SoftFail); 4089 if (Rt == Rt2) 4090 Check(S, MCDisassembler::SoftFail); 4091 4092 // Rt 4093 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4094 return MCDisassembler::Fail; 4095 // Rt2 4096 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4097 return MCDisassembler::Fail; 4098 // Writeback operand 4099 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4100 return MCDisassembler::Fail; 4101 // addr 4102 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4103 return MCDisassembler::Fail; 4104 4105 return S; 4106 } 4107 4108 static DecodeStatus 4109 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4110 uint64_t Address, const void *Decoder) { 4111 DecodeStatus S = MCDisassembler::Success; 4112 4113 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4114 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4115 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4116 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4117 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4118 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4119 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4120 bool writeback = (W == 1) | (P == 0); 4121 4122 addr |= (U << 8) | (Rn << 9); 4123 4124 if (writeback && (Rn == Rt || Rn == Rt2)) 4125 Check(S, MCDisassembler::SoftFail); 4126 4127 // Writeback operand 4128 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4129 return MCDisassembler::Fail; 4130 // Rt 4131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4132 return MCDisassembler::Fail; 4133 // Rt2 4134 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4135 return MCDisassembler::Fail; 4136 // addr 4137 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4138 return MCDisassembler::Fail; 4139 4140 return S; 4141 } 4142 4143 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4144 uint64_t Address, const void *Decoder) { 4145 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4146 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4147 if (sign1 != sign2) return MCDisassembler::Fail; 4148 4149 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4150 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4151 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4152 Val |= sign1 << 12; 4153 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4154 4155 return MCDisassembler::Success; 4156 } 4157 4158 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4159 uint64_t Address, 4160 const void *Decoder) { 4161 DecodeStatus S = MCDisassembler::Success; 4162 4163 // Shift of "asr #32" is not allowed in Thumb2 mode. 4164 if (Val == 0x20) S = MCDisassembler::SoftFail; 4165 Inst.addOperand(MCOperand::CreateImm(Val)); 4166 return S; 4167 } 4168 4169 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4170 uint64_t Address, const void *Decoder) { 4171 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4172 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4173 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4174 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4175 4176 if (pred == 0xF) 4177 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4178 4179 DecodeStatus S = MCDisassembler::Success; 4180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 4189 return S; 4190 } 4191 4192 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4193 uint64_t Address, const void *Decoder) { 4194 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4195 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4196 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4197 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4198 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4199 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4200 4201 DecodeStatus S = MCDisassembler::Success; 4202 4203 // VMOVv2f32 is ambiguous with these decodings. 4204 if (!(imm & 0x38) && cmode == 0xF) { 4205 Inst.setOpcode(ARM::VMOVv2f32); 4206 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4207 } 4208 4209 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4210 4211 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4214 return MCDisassembler::Fail; 4215 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4216 4217 return S; 4218 } 4219 4220 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4221 uint64_t Address, const void *Decoder) { 4222 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4223 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4224 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4225 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4226 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4227 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4228 4229 DecodeStatus S = MCDisassembler::Success; 4230 4231 // VMOVv4f32 is ambiguous with these decodings. 4232 if (!(imm & 0x38) && cmode == 0xF) { 4233 Inst.setOpcode(ARM::VMOVv4f32); 4234 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4235 } 4236 4237 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4238 4239 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4244 4245 return S; 4246 } 4247