1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "llvm/MC/EDInstInfo.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 /// ARMDisassembler - ARM disassembler for all ARM platforms. 34 class ARMDisassembler : public MCDisassembler { 35 public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 const EDInstInfo *getEDInfo() const; 55 private: 56 }; 57 58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59 class ThumbDisassembler : public MCDisassembler { 60 public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 const EDInstInfo *getEDInfo() const; 80 private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84 }; 85 } 86 87 static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 llvm_unreachable("Invalid DecodeStatus!"); 100 } 101 102 103 // Forward declare these because the autogenerated code will reference them. 104 // Definitions are further down. 105 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 131 unsigned RegNo, uint64_t Address, 132 const void *Decoder); 133 134 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 147 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 148 uint64_t Address, const void *Decoder); 149 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 152 unsigned Insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 164 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 165 unsigned Insn, 166 uint64_t Adddress, 167 const void *Decoder); 168 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 263 264 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 327 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 #include "ARMGenDisassemblerTables.inc" 330 #include "ARMGenInstrInfo.inc" 331 #include "ARMGenEDInfo.inc" 332 333 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 334 return new ARMDisassembler(STI); 335 } 336 337 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 338 return new ThumbDisassembler(STI); 339 } 340 341 const EDInstInfo *ARMDisassembler::getEDInfo() const { 342 return instInfoARM; 343 } 344 345 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 346 return instInfoARM; 347 } 348 349 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 350 const MemoryObject &Region, 351 uint64_t Address, 352 raw_ostream &os, 353 raw_ostream &cs) const { 354 CommentStream = &cs; 355 356 uint8_t bytes[4]; 357 358 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 359 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 360 361 // We want to read exactly 4 bytes of data. 362 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 363 Size = 0; 364 return MCDisassembler::Fail; 365 } 366 367 // Encoded as a small-endian 32-bit word in the stream. 368 uint32_t insn = (bytes[3] << 24) | 369 (bytes[2] << 16) | 370 (bytes[1] << 8) | 371 (bytes[0] << 0); 372 373 // Calling the auto-generated decoder function. 374 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 375 if (result != MCDisassembler::Fail) { 376 Size = 4; 377 return result; 378 } 379 380 // VFP and NEON instructions, similarly, are shared between ARM 381 // and Thumb modes. 382 MI.clear(); 383 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 384 if (result != MCDisassembler::Fail) { 385 Size = 4; 386 return result; 387 } 388 389 MI.clear(); 390 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 391 if (result != MCDisassembler::Fail) { 392 Size = 4; 393 // Add a fake predicate operand, because we share these instruction 394 // definitions with Thumb2 where these instructions are predicable. 395 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 396 return MCDisassembler::Fail; 397 return result; 398 } 399 400 MI.clear(); 401 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 402 if (result != MCDisassembler::Fail) { 403 Size = 4; 404 // Add a fake predicate operand, because we share these instruction 405 // definitions with Thumb2 where these instructions are predicable. 406 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 407 return MCDisassembler::Fail; 408 return result; 409 } 410 411 MI.clear(); 412 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 413 if (result != MCDisassembler::Fail) { 414 Size = 4; 415 // Add a fake predicate operand, because we share these instruction 416 // definitions with Thumb2 where these instructions are predicable. 417 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 418 return MCDisassembler::Fail; 419 return result; 420 } 421 422 MI.clear(); 423 424 Size = 0; 425 return MCDisassembler::Fail; 426 } 427 428 namespace llvm { 429 extern const MCInstrDesc ARMInsts[]; 430 } 431 432 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 433 /// immediate Value in the MCInst. The immediate Value has had any PC 434 /// adjustment made by the caller. If the instruction is a branch instruction 435 /// then isBranch is true, else false. If the getOpInfo() function was set as 436 /// part of the setupForSymbolicDisassembly() call then that function is called 437 /// to get any symbolic information at the Address for this instruction. If 438 /// that returns non-zero then the symbolic information it returns is used to 439 /// create an MCExpr and that is added as an operand to the MCInst. If 440 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 441 /// Value is done and if a symbol is found an MCExpr is created with that, else 442 /// an MCExpr with Value is created. This function returns true if it adds an 443 /// operand to the MCInst and false otherwise. 444 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 445 bool isBranch, uint64_t InstSize, 446 MCInst &MI, const void *Decoder) { 447 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 448 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 449 struct LLVMOpInfo1 SymbolicOp; 450 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 451 SymbolicOp.Value = Value; 452 void *DisInfo = Dis->getDisInfoBlock(); 453 454 if (!getOpInfo || 455 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 456 // Clear SymbolicOp.Value from above and also all other fields. 457 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 458 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 459 if (!SymbolLookUp) 460 return false; 461 uint64_t ReferenceType; 462 if (isBranch) 463 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 464 else 465 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 466 const char *ReferenceName; 467 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 468 &ReferenceName); 469 if (Name) { 470 SymbolicOp.AddSymbol.Name = Name; 471 SymbolicOp.AddSymbol.Present = true; 472 } 473 // For branches always create an MCExpr so it gets printed as hex address. 474 else if (isBranch) { 475 SymbolicOp.Value = Value; 476 } 477 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 478 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 479 if (!Name && !isBranch) 480 return false; 481 } 482 483 MCContext *Ctx = Dis->getMCContext(); 484 const MCExpr *Add = NULL; 485 if (SymbolicOp.AddSymbol.Present) { 486 if (SymbolicOp.AddSymbol.Name) { 487 StringRef Name(SymbolicOp.AddSymbol.Name); 488 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 489 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 490 } else { 491 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 492 } 493 } 494 495 const MCExpr *Sub = NULL; 496 if (SymbolicOp.SubtractSymbol.Present) { 497 if (SymbolicOp.SubtractSymbol.Name) { 498 StringRef Name(SymbolicOp.SubtractSymbol.Name); 499 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 500 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 501 } else { 502 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 503 } 504 } 505 506 const MCExpr *Off = NULL; 507 if (SymbolicOp.Value != 0) 508 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 509 510 const MCExpr *Expr; 511 if (Sub) { 512 const MCExpr *LHS; 513 if (Add) 514 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 515 else 516 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 517 if (Off != 0) 518 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 519 else 520 Expr = LHS; 521 } else if (Add) { 522 if (Off != 0) 523 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 524 else 525 Expr = Add; 526 } else { 527 if (Off != 0) 528 Expr = Off; 529 else 530 Expr = MCConstantExpr::Create(0, *Ctx); 531 } 532 533 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 534 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 535 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 536 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 537 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 538 MI.addOperand(MCOperand::CreateExpr(Expr)); 539 else 540 llvm_unreachable("bad SymbolicOp.VariantKind"); 541 542 return true; 543 } 544 545 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 546 /// referenced by a load instruction with the base register that is the Pc. 547 /// These can often be values in a literal pool near the Address of the 548 /// instruction. The Address of the instruction and its immediate Value are 549 /// used as a possible literal pool entry. The SymbolLookUp call back will 550 /// return the name of a symbol referenced by the the literal pool's entry if 551 /// the referenced address is that of a symbol. Or it will return a pointer to 552 /// a literal 'C' string if the referenced address of the literal pool's entry 553 /// is an address into a section with 'C' string literals. 554 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 555 const void *Decoder) { 556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 557 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 558 if (SymbolLookUp) { 559 void *DisInfo = Dis->getDisInfoBlock(); 560 uint64_t ReferenceType; 561 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 562 const char *ReferenceName; 563 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 564 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 565 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 566 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 567 } 568 } 569 570 // Thumb1 instructions don't have explicit S bits. Rather, they 571 // implicitly set CPSR. Since it's not represented in the encoding, the 572 // auto-generated decoder won't inject the CPSR operand. We need to fix 573 // that as a post-pass. 574 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 575 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 576 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 577 MCInst::iterator I = MI.begin(); 578 for (unsigned i = 0; i < NumOps; ++i, ++I) { 579 if (I == MI.end()) break; 580 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 581 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 582 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 583 return; 584 } 585 } 586 587 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 588 } 589 590 // Most Thumb instructions don't have explicit predicates in the 591 // encoding, but rather get their predicates from IT context. We need 592 // to fix up the predicate operands using this context information as a 593 // post-pass. 594 MCDisassembler::DecodeStatus 595 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 596 MCDisassembler::DecodeStatus S = Success; 597 598 // A few instructions actually have predicates encoded in them. Don't 599 // try to overwrite it if we're seeing one of those. 600 switch (MI.getOpcode()) { 601 case ARM::tBcc: 602 case ARM::t2Bcc: 603 case ARM::tCBZ: 604 case ARM::tCBNZ: 605 case ARM::tCPS: 606 case ARM::t2CPS3p: 607 case ARM::t2CPS2p: 608 case ARM::t2CPS1p: 609 case ARM::tMOVSr: 610 case ARM::tSETEND: 611 // Some instructions (mostly conditional branches) are not 612 // allowed in IT blocks. 613 if (!ITBlock.empty()) 614 S = SoftFail; 615 else 616 return Success; 617 break; 618 case ARM::tB: 619 case ARM::t2B: 620 case ARM::t2TBB: 621 case ARM::t2TBH: 622 // Some instructions (mostly unconditional branches) can 623 // only appears at the end of, or outside of, an IT. 624 if (ITBlock.size() > 1) 625 S = SoftFail; 626 break; 627 default: 628 break; 629 } 630 631 // If we're in an IT block, base the predicate on that. Otherwise, 632 // assume a predicate of AL. 633 unsigned CC; 634 if (!ITBlock.empty()) { 635 CC = ITBlock.back(); 636 if (CC == 0xF) 637 CC = ARMCC::AL; 638 ITBlock.pop_back(); 639 } else 640 CC = ARMCC::AL; 641 642 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 643 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 644 MCInst::iterator I = MI.begin(); 645 for (unsigned i = 0; i < NumOps; ++i, ++I) { 646 if (I == MI.end()) break; 647 if (OpInfo[i].isPredicate()) { 648 I = MI.insert(I, MCOperand::CreateImm(CC)); 649 ++I; 650 if (CC == ARMCC::AL) 651 MI.insert(I, MCOperand::CreateReg(0)); 652 else 653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 654 return S; 655 } 656 } 657 658 I = MI.insert(I, MCOperand::CreateImm(CC)); 659 ++I; 660 if (CC == ARMCC::AL) 661 MI.insert(I, MCOperand::CreateReg(0)); 662 else 663 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 664 665 return S; 666 } 667 668 // Thumb VFP instructions are a special case. Because we share their 669 // encodings between ARM and Thumb modes, and they are predicable in ARM 670 // mode, the auto-generated decoder will give them an (incorrect) 671 // predicate operand. We need to rewrite these operands based on the IT 672 // context as a post-pass. 673 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 674 unsigned CC; 675 if (!ITBlock.empty()) { 676 CC = ITBlock.back(); 677 ITBlock.pop_back(); 678 } else 679 CC = ARMCC::AL; 680 681 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 682 MCInst::iterator I = MI.begin(); 683 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 684 for (unsigned i = 0; i < NumOps; ++i, ++I) { 685 if (OpInfo[i].isPredicate() ) { 686 I->setImm(CC); 687 ++I; 688 if (CC == ARMCC::AL) 689 I->setReg(0); 690 else 691 I->setReg(ARM::CPSR); 692 return; 693 } 694 } 695 } 696 697 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 698 const MemoryObject &Region, 699 uint64_t Address, 700 raw_ostream &os, 701 raw_ostream &cs) const { 702 CommentStream = &cs; 703 704 uint8_t bytes[4]; 705 706 assert((STI.getFeatureBits() & ARM::ModeThumb) && 707 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 708 709 // We want to read exactly 2 bytes of data. 710 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 711 Size = 0; 712 return MCDisassembler::Fail; 713 } 714 715 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 716 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 717 if (result != MCDisassembler::Fail) { 718 Size = 2; 719 Check(result, AddThumbPredicate(MI)); 720 return result; 721 } 722 723 MI.clear(); 724 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 725 if (result) { 726 Size = 2; 727 bool InITBlock = !ITBlock.empty(); 728 Check(result, AddThumbPredicate(MI)); 729 AddThumb1SBit(MI, InITBlock); 730 return result; 731 } 732 733 MI.clear(); 734 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 735 if (result != MCDisassembler::Fail) { 736 Size = 2; 737 738 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 739 // the Thumb predicate. 740 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 741 result = MCDisassembler::SoftFail; 742 743 Check(result, AddThumbPredicate(MI)); 744 745 // If we find an IT instruction, we need to parse its condition 746 // code and mask operands so that we can apply them correctly 747 // to the subsequent instructions. 748 if (MI.getOpcode() == ARM::t2IT) { 749 750 // (3 - the number of trailing zeros) is the number of then / else. 751 unsigned firstcond = MI.getOperand(0).getImm(); 752 unsigned Mask = MI.getOperand(1).getImm(); 753 unsigned CondBit0 = Mask >> 4 & 1; 754 unsigned NumTZ = CountTrailingZeros_32(Mask); 755 assert(NumTZ <= 3 && "Invalid IT mask!"); 756 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 757 bool T = ((Mask >> Pos) & 1) == CondBit0; 758 if (T) 759 ITBlock.insert(ITBlock.begin(), firstcond); 760 else 761 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 762 } 763 764 ITBlock.push_back(firstcond); 765 } 766 767 return result; 768 } 769 770 // We want to read exactly 4 bytes of data. 771 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 772 Size = 0; 773 return MCDisassembler::Fail; 774 } 775 776 uint32_t insn32 = (bytes[3] << 8) | 777 (bytes[2] << 0) | 778 (bytes[1] << 24) | 779 (bytes[0] << 16); 780 MI.clear(); 781 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 4; 784 bool InITBlock = ITBlock.size(); 785 Check(result, AddThumbPredicate(MI)); 786 AddThumb1SBit(MI, InITBlock); 787 return result; 788 } 789 790 MI.clear(); 791 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 792 if (result != MCDisassembler::Fail) { 793 Size = 4; 794 Check(result, AddThumbPredicate(MI)); 795 return result; 796 } 797 798 MI.clear(); 799 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 800 if (result != MCDisassembler::Fail) { 801 Size = 4; 802 UpdateThumbVFPPredicate(MI); 803 return result; 804 } 805 806 MI.clear(); 807 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 808 if (result != MCDisassembler::Fail) { 809 Size = 4; 810 Check(result, AddThumbPredicate(MI)); 811 return result; 812 } 813 814 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 815 MI.clear(); 816 uint32_t NEONLdStInsn = insn32; 817 NEONLdStInsn &= 0xF0FFFFFF; 818 NEONLdStInsn |= 0x04000000; 819 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 820 if (result != MCDisassembler::Fail) { 821 Size = 4; 822 Check(result, AddThumbPredicate(MI)); 823 return result; 824 } 825 } 826 827 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 828 MI.clear(); 829 uint32_t NEONDataInsn = insn32; 830 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 831 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 832 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 833 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 834 if (result != MCDisassembler::Fail) { 835 Size = 4; 836 Check(result, AddThumbPredicate(MI)); 837 return result; 838 } 839 } 840 841 Size = 0; 842 return MCDisassembler::Fail; 843 } 844 845 846 extern "C" void LLVMInitializeARMDisassembler() { 847 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 848 createARMDisassembler); 849 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 850 createThumbDisassembler); 851 } 852 853 static const uint16_t GPRDecoderTable[] = { 854 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 855 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 856 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 857 ARM::R12, ARM::SP, ARM::LR, ARM::PC 858 }; 859 860 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 861 uint64_t Address, const void *Decoder) { 862 if (RegNo > 15) 863 return MCDisassembler::Fail; 864 865 unsigned Register = GPRDecoderTable[RegNo]; 866 Inst.addOperand(MCOperand::CreateReg(Register)); 867 return MCDisassembler::Success; 868 } 869 870 static DecodeStatus 871 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 872 uint64_t Address, const void *Decoder) { 873 DecodeStatus S = MCDisassembler::Success; 874 875 if (RegNo == 15) 876 S = MCDisassembler::SoftFail; 877 878 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 879 880 return S; 881 } 882 883 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 if (RegNo > 7) 886 return MCDisassembler::Fail; 887 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 888 } 889 890 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 891 uint64_t Address, const void *Decoder) { 892 unsigned Register = 0; 893 switch (RegNo) { 894 case 0: 895 Register = ARM::R0; 896 break; 897 case 1: 898 Register = ARM::R1; 899 break; 900 case 2: 901 Register = ARM::R2; 902 break; 903 case 3: 904 Register = ARM::R3; 905 break; 906 case 9: 907 Register = ARM::R9; 908 break; 909 case 12: 910 Register = ARM::R12; 911 break; 912 default: 913 return MCDisassembler::Fail; 914 } 915 916 Inst.addOperand(MCOperand::CreateReg(Register)); 917 return MCDisassembler::Success; 918 } 919 920 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 921 uint64_t Address, const void *Decoder) { 922 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 923 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 924 } 925 926 static const uint16_t SPRDecoderTable[] = { 927 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 928 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 929 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 930 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 931 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 932 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 933 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 934 ARM::S28, ARM::S29, ARM::S30, ARM::S31 935 }; 936 937 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 938 uint64_t Address, const void *Decoder) { 939 if (RegNo > 31) 940 return MCDisassembler::Fail; 941 942 unsigned Register = SPRDecoderTable[RegNo]; 943 Inst.addOperand(MCOperand::CreateReg(Register)); 944 return MCDisassembler::Success; 945 } 946 947 static const uint16_t DPRDecoderTable[] = { 948 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 949 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 950 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 951 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 952 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 953 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 954 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 955 ARM::D28, ARM::D29, ARM::D30, ARM::D31 956 }; 957 958 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 if (RegNo > 31) 961 return MCDisassembler::Fail; 962 963 unsigned Register = DPRDecoderTable[RegNo]; 964 Inst.addOperand(MCOperand::CreateReg(Register)); 965 return MCDisassembler::Success; 966 } 967 968 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 969 uint64_t Address, const void *Decoder) { 970 if (RegNo > 7) 971 return MCDisassembler::Fail; 972 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 973 } 974 975 static DecodeStatus 976 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 if (RegNo > 15) 979 return MCDisassembler::Fail; 980 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 981 } 982 983 static const uint16_t QPRDecoderTable[] = { 984 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 985 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 986 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 987 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 988 }; 989 990 991 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 992 uint64_t Address, const void *Decoder) { 993 if (RegNo > 31) 994 return MCDisassembler::Fail; 995 RegNo >>= 1; 996 997 unsigned Register = QPRDecoderTable[RegNo]; 998 Inst.addOperand(MCOperand::CreateReg(Register)); 999 return MCDisassembler::Success; 1000 } 1001 1002 static const uint16_t DPairDecoderTable[] = { 1003 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1004 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1005 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1006 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1007 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1008 ARM::Q15 1009 }; 1010 1011 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1012 uint64_t Address, const void *Decoder) { 1013 if (RegNo > 30) 1014 return MCDisassembler::Fail; 1015 1016 unsigned Register = DPairDecoderTable[RegNo]; 1017 Inst.addOperand(MCOperand::CreateReg(Register)); 1018 return MCDisassembler::Success; 1019 } 1020 1021 static const uint16_t DPairSpacedDecoderTable[] = { 1022 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1023 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1024 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1025 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1026 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1027 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1028 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1029 ARM::D28_D30, ARM::D29_D31 1030 }; 1031 1032 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1033 unsigned RegNo, 1034 uint64_t Address, 1035 const void *Decoder) { 1036 if (RegNo > 29) 1037 return MCDisassembler::Fail; 1038 1039 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1040 Inst.addOperand(MCOperand::CreateReg(Register)); 1041 return MCDisassembler::Success; 1042 } 1043 1044 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1045 uint64_t Address, const void *Decoder) { 1046 if (Val == 0xF) return MCDisassembler::Fail; 1047 // AL predicate is not allowed on Thumb1 branches. 1048 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1049 return MCDisassembler::Fail; 1050 Inst.addOperand(MCOperand::CreateImm(Val)); 1051 if (Val == ARMCC::AL) { 1052 Inst.addOperand(MCOperand::CreateReg(0)); 1053 } else 1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1055 return MCDisassembler::Success; 1056 } 1057 1058 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1059 uint64_t Address, const void *Decoder) { 1060 if (Val) 1061 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1062 else 1063 Inst.addOperand(MCOperand::CreateReg(0)); 1064 return MCDisassembler::Success; 1065 } 1066 1067 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1068 uint64_t Address, const void *Decoder) { 1069 uint32_t imm = Val & 0xFF; 1070 uint32_t rot = (Val & 0xF00) >> 7; 1071 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1072 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1073 return MCDisassembler::Success; 1074 } 1075 1076 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1077 uint64_t Address, const void *Decoder) { 1078 DecodeStatus S = MCDisassembler::Success; 1079 1080 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1081 unsigned type = fieldFromInstruction32(Val, 5, 2); 1082 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1083 1084 // Register-immediate 1085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1086 return MCDisassembler::Fail; 1087 1088 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1089 switch (type) { 1090 case 0: 1091 Shift = ARM_AM::lsl; 1092 break; 1093 case 1: 1094 Shift = ARM_AM::lsr; 1095 break; 1096 case 2: 1097 Shift = ARM_AM::asr; 1098 break; 1099 case 3: 1100 Shift = ARM_AM::ror; 1101 break; 1102 } 1103 1104 if (Shift == ARM_AM::ror && imm == 0) 1105 Shift = ARM_AM::rrx; 1106 1107 unsigned Op = Shift | (imm << 3); 1108 Inst.addOperand(MCOperand::CreateImm(Op)); 1109 1110 return S; 1111 } 1112 1113 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1114 uint64_t Address, const void *Decoder) { 1115 DecodeStatus S = MCDisassembler::Success; 1116 1117 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1118 unsigned type = fieldFromInstruction32(Val, 5, 2); 1119 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1120 1121 // Register-register 1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1123 return MCDisassembler::Fail; 1124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1125 return MCDisassembler::Fail; 1126 1127 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1128 switch (type) { 1129 case 0: 1130 Shift = ARM_AM::lsl; 1131 break; 1132 case 1: 1133 Shift = ARM_AM::lsr; 1134 break; 1135 case 2: 1136 Shift = ARM_AM::asr; 1137 break; 1138 case 3: 1139 Shift = ARM_AM::ror; 1140 break; 1141 } 1142 1143 Inst.addOperand(MCOperand::CreateImm(Shift)); 1144 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 bool writebackLoad = false; 1153 unsigned writebackReg = 0; 1154 switch (Inst.getOpcode()) { 1155 default: 1156 break; 1157 case ARM::LDMIA_UPD: 1158 case ARM::LDMDB_UPD: 1159 case ARM::LDMIB_UPD: 1160 case ARM::LDMDA_UPD: 1161 case ARM::t2LDMIA_UPD: 1162 case ARM::t2LDMDB_UPD: 1163 writebackLoad = true; 1164 writebackReg = Inst.getOperand(0).getReg(); 1165 break; 1166 } 1167 1168 // Empty register lists are not allowed. 1169 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1170 for (unsigned i = 0; i < 16; ++i) { 1171 if (Val & (1 << i)) { 1172 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1173 return MCDisassembler::Fail; 1174 // Writeback not allowed if Rn is in the target list. 1175 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1176 Check(S, MCDisassembler::SoftFail); 1177 } 1178 } 1179 1180 return S; 1181 } 1182 1183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1184 uint64_t Address, const void *Decoder) { 1185 DecodeStatus S = MCDisassembler::Success; 1186 1187 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1188 unsigned regs = Val & 0xFF; 1189 1190 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1191 return MCDisassembler::Fail; 1192 for (unsigned i = 0; i < (regs - 1); ++i) { 1193 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1194 return MCDisassembler::Fail; 1195 } 1196 1197 return S; 1198 } 1199 1200 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1201 uint64_t Address, const void *Decoder) { 1202 DecodeStatus S = MCDisassembler::Success; 1203 1204 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1205 unsigned regs = (Val & 0xFF) / 2; 1206 1207 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1208 return MCDisassembler::Fail; 1209 for (unsigned i = 0; i < (regs - 1); ++i) { 1210 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1211 return MCDisassembler::Fail; 1212 } 1213 1214 return S; 1215 } 1216 1217 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1218 uint64_t Address, const void *Decoder) { 1219 // This operand encodes a mask of contiguous zeros between a specified MSB 1220 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1221 // the mask of all bits LSB-and-lower, and then xor them to create 1222 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1223 // create the final mask. 1224 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1225 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1226 1227 DecodeStatus S = MCDisassembler::Success; 1228 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1229 1230 uint32_t msb_mask = 0xFFFFFFFF; 1231 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1232 uint32_t lsb_mask = (1U << lsb) - 1; 1233 1234 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1235 return S; 1236 } 1237 1238 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1239 uint64_t Address, const void *Decoder) { 1240 DecodeStatus S = MCDisassembler::Success; 1241 1242 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1243 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1244 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1245 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1247 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1248 1249 switch (Inst.getOpcode()) { 1250 case ARM::LDC_OFFSET: 1251 case ARM::LDC_PRE: 1252 case ARM::LDC_POST: 1253 case ARM::LDC_OPTION: 1254 case ARM::LDCL_OFFSET: 1255 case ARM::LDCL_PRE: 1256 case ARM::LDCL_POST: 1257 case ARM::LDCL_OPTION: 1258 case ARM::STC_OFFSET: 1259 case ARM::STC_PRE: 1260 case ARM::STC_POST: 1261 case ARM::STC_OPTION: 1262 case ARM::STCL_OFFSET: 1263 case ARM::STCL_PRE: 1264 case ARM::STCL_POST: 1265 case ARM::STCL_OPTION: 1266 case ARM::t2LDC_OFFSET: 1267 case ARM::t2LDC_PRE: 1268 case ARM::t2LDC_POST: 1269 case ARM::t2LDC_OPTION: 1270 case ARM::t2LDCL_OFFSET: 1271 case ARM::t2LDCL_PRE: 1272 case ARM::t2LDCL_POST: 1273 case ARM::t2LDCL_OPTION: 1274 case ARM::t2STC_OFFSET: 1275 case ARM::t2STC_PRE: 1276 case ARM::t2STC_POST: 1277 case ARM::t2STC_OPTION: 1278 case ARM::t2STCL_OFFSET: 1279 case ARM::t2STCL_PRE: 1280 case ARM::t2STCL_POST: 1281 case ARM::t2STCL_OPTION: 1282 if (coproc == 0xA || coproc == 0xB) 1283 return MCDisassembler::Fail; 1284 break; 1285 default: 1286 break; 1287 } 1288 1289 Inst.addOperand(MCOperand::CreateImm(coproc)); 1290 Inst.addOperand(MCOperand::CreateImm(CRd)); 1291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1292 return MCDisassembler::Fail; 1293 1294 switch (Inst.getOpcode()) { 1295 case ARM::t2LDC2_OFFSET: 1296 case ARM::t2LDC2L_OFFSET: 1297 case ARM::t2LDC2_PRE: 1298 case ARM::t2LDC2L_PRE: 1299 case ARM::t2STC2_OFFSET: 1300 case ARM::t2STC2L_OFFSET: 1301 case ARM::t2STC2_PRE: 1302 case ARM::t2STC2L_PRE: 1303 case ARM::LDC2_OFFSET: 1304 case ARM::LDC2L_OFFSET: 1305 case ARM::LDC2_PRE: 1306 case ARM::LDC2L_PRE: 1307 case ARM::STC2_OFFSET: 1308 case ARM::STC2L_OFFSET: 1309 case ARM::STC2_PRE: 1310 case ARM::STC2L_PRE: 1311 case ARM::t2LDC_OFFSET: 1312 case ARM::t2LDCL_OFFSET: 1313 case ARM::t2LDC_PRE: 1314 case ARM::t2LDCL_PRE: 1315 case ARM::t2STC_OFFSET: 1316 case ARM::t2STCL_OFFSET: 1317 case ARM::t2STC_PRE: 1318 case ARM::t2STCL_PRE: 1319 case ARM::LDC_OFFSET: 1320 case ARM::LDCL_OFFSET: 1321 case ARM::LDC_PRE: 1322 case ARM::LDCL_PRE: 1323 case ARM::STC_OFFSET: 1324 case ARM::STCL_OFFSET: 1325 case ARM::STC_PRE: 1326 case ARM::STCL_PRE: 1327 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1328 Inst.addOperand(MCOperand::CreateImm(imm)); 1329 break; 1330 case ARM::t2LDC2_POST: 1331 case ARM::t2LDC2L_POST: 1332 case ARM::t2STC2_POST: 1333 case ARM::t2STC2L_POST: 1334 case ARM::LDC2_POST: 1335 case ARM::LDC2L_POST: 1336 case ARM::STC2_POST: 1337 case ARM::STC2L_POST: 1338 case ARM::t2LDC_POST: 1339 case ARM::t2LDCL_POST: 1340 case ARM::t2STC_POST: 1341 case ARM::t2STCL_POST: 1342 case ARM::LDC_POST: 1343 case ARM::LDCL_POST: 1344 case ARM::STC_POST: 1345 case ARM::STCL_POST: 1346 imm |= U << 8; 1347 // fall through. 1348 default: 1349 // The 'option' variant doesn't encode 'U' in the immediate since 1350 // the immediate is unsigned [0,255]. 1351 Inst.addOperand(MCOperand::CreateImm(imm)); 1352 break; 1353 } 1354 1355 switch (Inst.getOpcode()) { 1356 case ARM::LDC_OFFSET: 1357 case ARM::LDC_PRE: 1358 case ARM::LDC_POST: 1359 case ARM::LDC_OPTION: 1360 case ARM::LDCL_OFFSET: 1361 case ARM::LDCL_PRE: 1362 case ARM::LDCL_POST: 1363 case ARM::LDCL_OPTION: 1364 case ARM::STC_OFFSET: 1365 case ARM::STC_PRE: 1366 case ARM::STC_POST: 1367 case ARM::STC_OPTION: 1368 case ARM::STCL_OFFSET: 1369 case ARM::STCL_PRE: 1370 case ARM::STCL_POST: 1371 case ARM::STCL_OPTION: 1372 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1373 return MCDisassembler::Fail; 1374 break; 1375 default: 1376 break; 1377 } 1378 1379 return S; 1380 } 1381 1382 static DecodeStatus 1383 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1384 uint64_t Address, const void *Decoder) { 1385 DecodeStatus S = MCDisassembler::Success; 1386 1387 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1388 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1389 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1390 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1391 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1392 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1393 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1394 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1395 1396 // On stores, the writeback operand precedes Rt. 1397 switch (Inst.getOpcode()) { 1398 case ARM::STR_POST_IMM: 1399 case ARM::STR_POST_REG: 1400 case ARM::STRB_POST_IMM: 1401 case ARM::STRB_POST_REG: 1402 case ARM::STRT_POST_REG: 1403 case ARM::STRT_POST_IMM: 1404 case ARM::STRBT_POST_REG: 1405 case ARM::STRBT_POST_IMM: 1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 break; 1409 default: 1410 break; 1411 } 1412 1413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1414 return MCDisassembler::Fail; 1415 1416 // On loads, the writeback operand comes after Rt. 1417 switch (Inst.getOpcode()) { 1418 case ARM::LDR_POST_IMM: 1419 case ARM::LDR_POST_REG: 1420 case ARM::LDRB_POST_IMM: 1421 case ARM::LDRB_POST_REG: 1422 case ARM::LDRBT_POST_REG: 1423 case ARM::LDRBT_POST_IMM: 1424 case ARM::LDRT_POST_REG: 1425 case ARM::LDRT_POST_IMM: 1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1427 return MCDisassembler::Fail; 1428 break; 1429 default: 1430 break; 1431 } 1432 1433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1434 return MCDisassembler::Fail; 1435 1436 ARM_AM::AddrOpc Op = ARM_AM::add; 1437 if (!fieldFromInstruction32(Insn, 23, 1)) 1438 Op = ARM_AM::sub; 1439 1440 bool writeback = (P == 0) || (W == 1); 1441 unsigned idx_mode = 0; 1442 if (P && writeback) 1443 idx_mode = ARMII::IndexModePre; 1444 else if (!P && writeback) 1445 idx_mode = ARMII::IndexModePost; 1446 1447 if (writeback && (Rn == 15 || Rn == Rt)) 1448 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1449 1450 if (reg) { 1451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1452 return MCDisassembler::Fail; 1453 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1454 switch( fieldFromInstruction32(Insn, 5, 2)) { 1455 case 0: 1456 Opc = ARM_AM::lsl; 1457 break; 1458 case 1: 1459 Opc = ARM_AM::lsr; 1460 break; 1461 case 2: 1462 Opc = ARM_AM::asr; 1463 break; 1464 case 3: 1465 Opc = ARM_AM::ror; 1466 break; 1467 default: 1468 return MCDisassembler::Fail; 1469 } 1470 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1471 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1472 1473 Inst.addOperand(MCOperand::CreateImm(imm)); 1474 } else { 1475 Inst.addOperand(MCOperand::CreateReg(0)); 1476 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1477 Inst.addOperand(MCOperand::CreateImm(tmp)); 1478 } 1479 1480 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1481 return MCDisassembler::Fail; 1482 1483 return S; 1484 } 1485 1486 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1487 uint64_t Address, const void *Decoder) { 1488 DecodeStatus S = MCDisassembler::Success; 1489 1490 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1491 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1492 unsigned type = fieldFromInstruction32(Val, 5, 2); 1493 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1494 unsigned U = fieldFromInstruction32(Val, 12, 1); 1495 1496 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1497 switch (type) { 1498 case 0: 1499 ShOp = ARM_AM::lsl; 1500 break; 1501 case 1: 1502 ShOp = ARM_AM::lsr; 1503 break; 1504 case 2: 1505 ShOp = ARM_AM::asr; 1506 break; 1507 case 3: 1508 ShOp = ARM_AM::ror; 1509 break; 1510 } 1511 1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1513 return MCDisassembler::Fail; 1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1515 return MCDisassembler::Fail; 1516 unsigned shift; 1517 if (U) 1518 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1519 else 1520 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1521 Inst.addOperand(MCOperand::CreateImm(shift)); 1522 1523 return S; 1524 } 1525 1526 static DecodeStatus 1527 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1528 uint64_t Address, const void *Decoder) { 1529 DecodeStatus S = MCDisassembler::Success; 1530 1531 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1532 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1533 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1534 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1535 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1536 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1537 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1538 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1539 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1540 unsigned Rt2 = Rt + 1; 1541 1542 bool writeback = (W == 1) | (P == 0); 1543 1544 // For {LD,ST}RD, Rt must be even, else undefined. 1545 switch (Inst.getOpcode()) { 1546 case ARM::STRD: 1547 case ARM::STRD_PRE: 1548 case ARM::STRD_POST: 1549 case ARM::LDRD: 1550 case ARM::LDRD_PRE: 1551 case ARM::LDRD_POST: 1552 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1553 break; 1554 default: 1555 break; 1556 } 1557 switch (Inst.getOpcode()) { 1558 case ARM::STRD: 1559 case ARM::STRD_PRE: 1560 case ARM::STRD_POST: 1561 if (P == 0 && W == 1) 1562 S = MCDisassembler::SoftFail; 1563 1564 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1565 S = MCDisassembler::SoftFail; 1566 if (type && Rm == 15) 1567 S = MCDisassembler::SoftFail; 1568 if (Rt2 == 15) 1569 S = MCDisassembler::SoftFail; 1570 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1571 S = MCDisassembler::SoftFail; 1572 break; 1573 case ARM::STRH: 1574 case ARM::STRH_PRE: 1575 case ARM::STRH_POST: 1576 if (Rt == 15) 1577 S = MCDisassembler::SoftFail; 1578 if (writeback && (Rn == 15 || Rn == Rt)) 1579 S = MCDisassembler::SoftFail; 1580 if (!type && Rm == 15) 1581 S = MCDisassembler::SoftFail; 1582 break; 1583 case ARM::LDRD: 1584 case ARM::LDRD_PRE: 1585 case ARM::LDRD_POST: 1586 if (type && Rn == 15){ 1587 if (Rt2 == 15) 1588 S = MCDisassembler::SoftFail; 1589 break; 1590 } 1591 if (P == 0 && W == 1) 1592 S = MCDisassembler::SoftFail; 1593 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1594 S = MCDisassembler::SoftFail; 1595 if (!type && writeback && Rn == 15) 1596 S = MCDisassembler::SoftFail; 1597 if (writeback && (Rn == Rt || Rn == Rt2)) 1598 S = MCDisassembler::SoftFail; 1599 break; 1600 case ARM::LDRH: 1601 case ARM::LDRH_PRE: 1602 case ARM::LDRH_POST: 1603 if (type && Rn == 15){ 1604 if (Rt == 15) 1605 S = MCDisassembler::SoftFail; 1606 break; 1607 } 1608 if (Rt == 15) 1609 S = MCDisassembler::SoftFail; 1610 if (!type && Rm == 15) 1611 S = MCDisassembler::SoftFail; 1612 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1613 S = MCDisassembler::SoftFail; 1614 break; 1615 case ARM::LDRSH: 1616 case ARM::LDRSH_PRE: 1617 case ARM::LDRSH_POST: 1618 case ARM::LDRSB: 1619 case ARM::LDRSB_PRE: 1620 case ARM::LDRSB_POST: 1621 if (type && Rn == 15){ 1622 if (Rt == 15) 1623 S = MCDisassembler::SoftFail; 1624 break; 1625 } 1626 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1627 S = MCDisassembler::SoftFail; 1628 if (!type && (Rt == 15 || Rm == 15)) 1629 S = MCDisassembler::SoftFail; 1630 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1631 S = MCDisassembler::SoftFail; 1632 break; 1633 default: 1634 break; 1635 } 1636 1637 if (writeback) { // Writeback 1638 if (P) 1639 U |= ARMII::IndexModePre << 9; 1640 else 1641 U |= ARMII::IndexModePost << 9; 1642 1643 // On stores, the writeback operand precedes Rt. 1644 switch (Inst.getOpcode()) { 1645 case ARM::STRD: 1646 case ARM::STRD_PRE: 1647 case ARM::STRD_POST: 1648 case ARM::STRH: 1649 case ARM::STRH_PRE: 1650 case ARM::STRH_POST: 1651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1652 return MCDisassembler::Fail; 1653 break; 1654 default: 1655 break; 1656 } 1657 } 1658 1659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1660 return MCDisassembler::Fail; 1661 switch (Inst.getOpcode()) { 1662 case ARM::STRD: 1663 case ARM::STRD_PRE: 1664 case ARM::STRD_POST: 1665 case ARM::LDRD: 1666 case ARM::LDRD_PRE: 1667 case ARM::LDRD_POST: 1668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1669 return MCDisassembler::Fail; 1670 break; 1671 default: 1672 break; 1673 } 1674 1675 if (writeback) { 1676 // On loads, the writeback operand comes after Rt. 1677 switch (Inst.getOpcode()) { 1678 case ARM::LDRD: 1679 case ARM::LDRD_PRE: 1680 case ARM::LDRD_POST: 1681 case ARM::LDRH: 1682 case ARM::LDRH_PRE: 1683 case ARM::LDRH_POST: 1684 case ARM::LDRSH: 1685 case ARM::LDRSH_PRE: 1686 case ARM::LDRSH_POST: 1687 case ARM::LDRSB: 1688 case ARM::LDRSB_PRE: 1689 case ARM::LDRSB_POST: 1690 case ARM::LDRHTr: 1691 case ARM::LDRSBTr: 1692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1693 return MCDisassembler::Fail; 1694 break; 1695 default: 1696 break; 1697 } 1698 } 1699 1700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1701 return MCDisassembler::Fail; 1702 1703 if (type) { 1704 Inst.addOperand(MCOperand::CreateReg(0)); 1705 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1706 } else { 1707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1708 return MCDisassembler::Fail; 1709 Inst.addOperand(MCOperand::CreateImm(U)); 1710 } 1711 1712 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 1715 return S; 1716 } 1717 1718 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1719 uint64_t Address, const void *Decoder) { 1720 DecodeStatus S = MCDisassembler::Success; 1721 1722 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1723 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1724 1725 switch (mode) { 1726 case 0: 1727 mode = ARM_AM::da; 1728 break; 1729 case 1: 1730 mode = ARM_AM::ia; 1731 break; 1732 case 2: 1733 mode = ARM_AM::db; 1734 break; 1735 case 3: 1736 mode = ARM_AM::ib; 1737 break; 1738 } 1739 1740 Inst.addOperand(MCOperand::CreateImm(mode)); 1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1742 return MCDisassembler::Fail; 1743 1744 return S; 1745 } 1746 1747 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1748 unsigned Insn, 1749 uint64_t Address, const void *Decoder) { 1750 DecodeStatus S = MCDisassembler::Success; 1751 1752 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1753 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1754 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1755 1756 if (pred == 0xF) { 1757 switch (Inst.getOpcode()) { 1758 case ARM::LDMDA: 1759 Inst.setOpcode(ARM::RFEDA); 1760 break; 1761 case ARM::LDMDA_UPD: 1762 Inst.setOpcode(ARM::RFEDA_UPD); 1763 break; 1764 case ARM::LDMDB: 1765 Inst.setOpcode(ARM::RFEDB); 1766 break; 1767 case ARM::LDMDB_UPD: 1768 Inst.setOpcode(ARM::RFEDB_UPD); 1769 break; 1770 case ARM::LDMIA: 1771 Inst.setOpcode(ARM::RFEIA); 1772 break; 1773 case ARM::LDMIA_UPD: 1774 Inst.setOpcode(ARM::RFEIA_UPD); 1775 break; 1776 case ARM::LDMIB: 1777 Inst.setOpcode(ARM::RFEIB); 1778 break; 1779 case ARM::LDMIB_UPD: 1780 Inst.setOpcode(ARM::RFEIB_UPD); 1781 break; 1782 case ARM::STMDA: 1783 Inst.setOpcode(ARM::SRSDA); 1784 break; 1785 case ARM::STMDA_UPD: 1786 Inst.setOpcode(ARM::SRSDA_UPD); 1787 break; 1788 case ARM::STMDB: 1789 Inst.setOpcode(ARM::SRSDB); 1790 break; 1791 case ARM::STMDB_UPD: 1792 Inst.setOpcode(ARM::SRSDB_UPD); 1793 break; 1794 case ARM::STMIA: 1795 Inst.setOpcode(ARM::SRSIA); 1796 break; 1797 case ARM::STMIA_UPD: 1798 Inst.setOpcode(ARM::SRSIA_UPD); 1799 break; 1800 case ARM::STMIB: 1801 Inst.setOpcode(ARM::SRSIB); 1802 break; 1803 case ARM::STMIB_UPD: 1804 Inst.setOpcode(ARM::SRSIB_UPD); 1805 break; 1806 default: 1807 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1808 } 1809 1810 // For stores (which become SRS's, the only operand is the mode. 1811 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1812 Inst.addOperand( 1813 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1814 return S; 1815 } 1816 1817 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1818 } 1819 1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1821 return MCDisassembler::Fail; 1822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1823 return MCDisassembler::Fail; // Tied 1824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1827 return MCDisassembler::Fail; 1828 1829 return S; 1830 } 1831 1832 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1833 uint64_t Address, const void *Decoder) { 1834 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1835 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1836 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1837 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1838 1839 DecodeStatus S = MCDisassembler::Success; 1840 1841 // imod == '01' --> UNPREDICTABLE 1842 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1843 // return failure here. The '01' imod value is unprintable, so there's 1844 // nothing useful we could do even if we returned UNPREDICTABLE. 1845 1846 if (imod == 1) return MCDisassembler::Fail; 1847 1848 if (imod && M) { 1849 Inst.setOpcode(ARM::CPS3p); 1850 Inst.addOperand(MCOperand::CreateImm(imod)); 1851 Inst.addOperand(MCOperand::CreateImm(iflags)); 1852 Inst.addOperand(MCOperand::CreateImm(mode)); 1853 } else if (imod && !M) { 1854 Inst.setOpcode(ARM::CPS2p); 1855 Inst.addOperand(MCOperand::CreateImm(imod)); 1856 Inst.addOperand(MCOperand::CreateImm(iflags)); 1857 if (mode) S = MCDisassembler::SoftFail; 1858 } else if (!imod && M) { 1859 Inst.setOpcode(ARM::CPS1p); 1860 Inst.addOperand(MCOperand::CreateImm(mode)); 1861 if (iflags) S = MCDisassembler::SoftFail; 1862 } else { 1863 // imod == '00' && M == '0' --> UNPREDICTABLE 1864 Inst.setOpcode(ARM::CPS1p); 1865 Inst.addOperand(MCOperand::CreateImm(mode)); 1866 S = MCDisassembler::SoftFail; 1867 } 1868 1869 return S; 1870 } 1871 1872 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1873 uint64_t Address, const void *Decoder) { 1874 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1875 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1876 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1877 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1878 1879 DecodeStatus S = MCDisassembler::Success; 1880 1881 // imod == '01' --> UNPREDICTABLE 1882 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1883 // return failure here. The '01' imod value is unprintable, so there's 1884 // nothing useful we could do even if we returned UNPREDICTABLE. 1885 1886 if (imod == 1) return MCDisassembler::Fail; 1887 1888 if (imod && M) { 1889 Inst.setOpcode(ARM::t2CPS3p); 1890 Inst.addOperand(MCOperand::CreateImm(imod)); 1891 Inst.addOperand(MCOperand::CreateImm(iflags)); 1892 Inst.addOperand(MCOperand::CreateImm(mode)); 1893 } else if (imod && !M) { 1894 Inst.setOpcode(ARM::t2CPS2p); 1895 Inst.addOperand(MCOperand::CreateImm(imod)); 1896 Inst.addOperand(MCOperand::CreateImm(iflags)); 1897 if (mode) S = MCDisassembler::SoftFail; 1898 } else if (!imod && M) { 1899 Inst.setOpcode(ARM::t2CPS1p); 1900 Inst.addOperand(MCOperand::CreateImm(mode)); 1901 if (iflags) S = MCDisassembler::SoftFail; 1902 } else { 1903 // imod == '00' && M == '0' --> UNPREDICTABLE 1904 Inst.setOpcode(ARM::t2CPS1p); 1905 Inst.addOperand(MCOperand::CreateImm(mode)); 1906 S = MCDisassembler::SoftFail; 1907 } 1908 1909 return S; 1910 } 1911 1912 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1913 uint64_t Address, const void *Decoder) { 1914 DecodeStatus S = MCDisassembler::Success; 1915 1916 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1917 unsigned imm = 0; 1918 1919 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1920 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1921 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1922 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1923 1924 if (Inst.getOpcode() == ARM::t2MOVTi16) 1925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1926 return MCDisassembler::Fail; 1927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1928 return MCDisassembler::Fail; 1929 1930 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1931 Inst.addOperand(MCOperand::CreateImm(imm)); 1932 1933 return S; 1934 } 1935 1936 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1937 uint64_t Address, const void *Decoder) { 1938 DecodeStatus S = MCDisassembler::Success; 1939 1940 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1941 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1942 unsigned imm = 0; 1943 1944 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1945 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1946 1947 if (Inst.getOpcode() == ARM::MOVTi16) 1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1951 return MCDisassembler::Fail; 1952 1953 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1954 Inst.addOperand(MCOperand::CreateImm(imm)); 1955 1956 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1957 return MCDisassembler::Fail; 1958 1959 return S; 1960 } 1961 1962 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1963 uint64_t Address, const void *Decoder) { 1964 DecodeStatus S = MCDisassembler::Success; 1965 1966 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1967 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1968 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1969 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1970 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1971 1972 if (pred == 0xF) 1973 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1974 1975 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1976 return MCDisassembler::Fail; 1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1978 return MCDisassembler::Fail; 1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1980 return MCDisassembler::Fail; 1981 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 1984 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1985 return MCDisassembler::Fail; 1986 1987 return S; 1988 } 1989 1990 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 1991 uint64_t Address, const void *Decoder) { 1992 DecodeStatus S = MCDisassembler::Success; 1993 1994 unsigned add = fieldFromInstruction32(Val, 12, 1); 1995 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1996 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1997 1998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1999 return MCDisassembler::Fail; 2000 2001 if (!add) imm *= -1; 2002 if (imm == 0 && !add) imm = INT32_MIN; 2003 Inst.addOperand(MCOperand::CreateImm(imm)); 2004 if (Rn == 15) 2005 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2006 2007 return S; 2008 } 2009 2010 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2011 uint64_t Address, const void *Decoder) { 2012 DecodeStatus S = MCDisassembler::Success; 2013 2014 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2015 unsigned U = fieldFromInstruction32(Val, 8, 1); 2016 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2017 2018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2019 return MCDisassembler::Fail; 2020 2021 if (U) 2022 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2023 else 2024 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2025 2026 return S; 2027 } 2028 2029 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2030 uint64_t Address, const void *Decoder) { 2031 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2032 } 2033 2034 static DecodeStatus 2035 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2036 uint64_t Address, const void *Decoder) { 2037 DecodeStatus S = MCDisassembler::Success; 2038 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) | 2039 (fieldFromInstruction32(Insn, 11, 1) << 18) | 2040 (fieldFromInstruction32(Insn, 13, 1) << 17) | 2041 (fieldFromInstruction32(Insn, 16, 6) << 11) | 2042 (fieldFromInstruction32(Insn, 26, 1) << 19); 2043 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4, 2044 true, 4, Inst, Decoder)) 2045 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1))); 2046 return S; 2047 } 2048 2049 static DecodeStatus 2050 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2051 uint64_t Address, const void *Decoder) { 2052 DecodeStatus S = MCDisassembler::Success; 2053 2054 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2055 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2056 2057 if (pred == 0xF) { 2058 Inst.setOpcode(ARM::BLXi); 2059 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2061 true, 4, Inst, Decoder)) 2062 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2063 return S; 2064 } 2065 2066 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2067 true, 4, Inst, Decoder)) 2068 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2069 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2070 return MCDisassembler::Fail; 2071 2072 return S; 2073 } 2074 2075 2076 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2077 uint64_t Address, const void *Decoder) { 2078 DecodeStatus S = MCDisassembler::Success; 2079 2080 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2081 unsigned align = fieldFromInstruction32(Val, 4, 2); 2082 2083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2084 return MCDisassembler::Fail; 2085 if (!align) 2086 Inst.addOperand(MCOperand::CreateImm(0)); 2087 else 2088 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2089 2090 return S; 2091 } 2092 2093 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2094 uint64_t Address, const void *Decoder) { 2095 DecodeStatus S = MCDisassembler::Success; 2096 2097 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2098 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2099 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2100 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2101 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2102 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2103 2104 // First output register 2105 switch (Inst.getOpcode()) { 2106 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2107 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2108 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2109 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2110 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2111 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2112 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2113 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2114 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2115 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2116 return MCDisassembler::Fail; 2117 break; 2118 case ARM::VLD2b16: 2119 case ARM::VLD2b32: 2120 case ARM::VLD2b8: 2121 case ARM::VLD2b16wb_fixed: 2122 case ARM::VLD2b16wb_register: 2123 case ARM::VLD2b32wb_fixed: 2124 case ARM::VLD2b32wb_register: 2125 case ARM::VLD2b8wb_fixed: 2126 case ARM::VLD2b8wb_register: 2127 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 break; 2130 default: 2131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 } 2134 2135 // Second output register 2136 switch (Inst.getOpcode()) { 2137 case ARM::VLD3d8: 2138 case ARM::VLD3d16: 2139 case ARM::VLD3d32: 2140 case ARM::VLD3d8_UPD: 2141 case ARM::VLD3d16_UPD: 2142 case ARM::VLD3d32_UPD: 2143 case ARM::VLD4d8: 2144 case ARM::VLD4d16: 2145 case ARM::VLD4d32: 2146 case ARM::VLD4d8_UPD: 2147 case ARM::VLD4d16_UPD: 2148 case ARM::VLD4d32_UPD: 2149 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2150 return MCDisassembler::Fail; 2151 break; 2152 case ARM::VLD3q8: 2153 case ARM::VLD3q16: 2154 case ARM::VLD3q32: 2155 case ARM::VLD3q8_UPD: 2156 case ARM::VLD3q16_UPD: 2157 case ARM::VLD3q32_UPD: 2158 case ARM::VLD4q8: 2159 case ARM::VLD4q16: 2160 case ARM::VLD4q32: 2161 case ARM::VLD4q8_UPD: 2162 case ARM::VLD4q16_UPD: 2163 case ARM::VLD4q32_UPD: 2164 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 default: 2167 break; 2168 } 2169 2170 // Third output register 2171 switch(Inst.getOpcode()) { 2172 case ARM::VLD3d8: 2173 case ARM::VLD3d16: 2174 case ARM::VLD3d32: 2175 case ARM::VLD3d8_UPD: 2176 case ARM::VLD3d16_UPD: 2177 case ARM::VLD3d32_UPD: 2178 case ARM::VLD4d8: 2179 case ARM::VLD4d16: 2180 case ARM::VLD4d32: 2181 case ARM::VLD4d8_UPD: 2182 case ARM::VLD4d16_UPD: 2183 case ARM::VLD4d32_UPD: 2184 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2185 return MCDisassembler::Fail; 2186 break; 2187 case ARM::VLD3q8: 2188 case ARM::VLD3q16: 2189 case ARM::VLD3q32: 2190 case ARM::VLD3q8_UPD: 2191 case ARM::VLD3q16_UPD: 2192 case ARM::VLD3q32_UPD: 2193 case ARM::VLD4q8: 2194 case ARM::VLD4q16: 2195 case ARM::VLD4q32: 2196 case ARM::VLD4q8_UPD: 2197 case ARM::VLD4q16_UPD: 2198 case ARM::VLD4q32_UPD: 2199 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 break; 2202 default: 2203 break; 2204 } 2205 2206 // Fourth output register 2207 switch (Inst.getOpcode()) { 2208 case ARM::VLD4d8: 2209 case ARM::VLD4d16: 2210 case ARM::VLD4d32: 2211 case ARM::VLD4d8_UPD: 2212 case ARM::VLD4d16_UPD: 2213 case ARM::VLD4d32_UPD: 2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 break; 2217 case ARM::VLD4q8: 2218 case ARM::VLD4q16: 2219 case ARM::VLD4q32: 2220 case ARM::VLD4q8_UPD: 2221 case ARM::VLD4q16_UPD: 2222 case ARM::VLD4q32_UPD: 2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2224 return MCDisassembler::Fail; 2225 break; 2226 default: 2227 break; 2228 } 2229 2230 // Writeback operand 2231 switch (Inst.getOpcode()) { 2232 case ARM::VLD1d8wb_fixed: 2233 case ARM::VLD1d16wb_fixed: 2234 case ARM::VLD1d32wb_fixed: 2235 case ARM::VLD1d64wb_fixed: 2236 case ARM::VLD1d8wb_register: 2237 case ARM::VLD1d16wb_register: 2238 case ARM::VLD1d32wb_register: 2239 case ARM::VLD1d64wb_register: 2240 case ARM::VLD1q8wb_fixed: 2241 case ARM::VLD1q16wb_fixed: 2242 case ARM::VLD1q32wb_fixed: 2243 case ARM::VLD1q64wb_fixed: 2244 case ARM::VLD1q8wb_register: 2245 case ARM::VLD1q16wb_register: 2246 case ARM::VLD1q32wb_register: 2247 case ARM::VLD1q64wb_register: 2248 case ARM::VLD1d8Twb_fixed: 2249 case ARM::VLD1d8Twb_register: 2250 case ARM::VLD1d16Twb_fixed: 2251 case ARM::VLD1d16Twb_register: 2252 case ARM::VLD1d32Twb_fixed: 2253 case ARM::VLD1d32Twb_register: 2254 case ARM::VLD1d64Twb_fixed: 2255 case ARM::VLD1d64Twb_register: 2256 case ARM::VLD1d8Qwb_fixed: 2257 case ARM::VLD1d8Qwb_register: 2258 case ARM::VLD1d16Qwb_fixed: 2259 case ARM::VLD1d16Qwb_register: 2260 case ARM::VLD1d32Qwb_fixed: 2261 case ARM::VLD1d32Qwb_register: 2262 case ARM::VLD1d64Qwb_fixed: 2263 case ARM::VLD1d64Qwb_register: 2264 case ARM::VLD2d8wb_fixed: 2265 case ARM::VLD2d16wb_fixed: 2266 case ARM::VLD2d32wb_fixed: 2267 case ARM::VLD2q8wb_fixed: 2268 case ARM::VLD2q16wb_fixed: 2269 case ARM::VLD2q32wb_fixed: 2270 case ARM::VLD2d8wb_register: 2271 case ARM::VLD2d16wb_register: 2272 case ARM::VLD2d32wb_register: 2273 case ARM::VLD2q8wb_register: 2274 case ARM::VLD2q16wb_register: 2275 case ARM::VLD2q32wb_register: 2276 case ARM::VLD2b8wb_fixed: 2277 case ARM::VLD2b16wb_fixed: 2278 case ARM::VLD2b32wb_fixed: 2279 case ARM::VLD2b8wb_register: 2280 case ARM::VLD2b16wb_register: 2281 case ARM::VLD2b32wb_register: 2282 Inst.addOperand(MCOperand::CreateImm(0)); 2283 break; 2284 case ARM::VLD3d8_UPD: 2285 case ARM::VLD3d16_UPD: 2286 case ARM::VLD3d32_UPD: 2287 case ARM::VLD3q8_UPD: 2288 case ARM::VLD3q16_UPD: 2289 case ARM::VLD3q32_UPD: 2290 case ARM::VLD4d8_UPD: 2291 case ARM::VLD4d16_UPD: 2292 case ARM::VLD4d32_UPD: 2293 case ARM::VLD4q8_UPD: 2294 case ARM::VLD4q16_UPD: 2295 case ARM::VLD4q32_UPD: 2296 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2297 return MCDisassembler::Fail; 2298 break; 2299 default: 2300 break; 2301 } 2302 2303 // AddrMode6 Base (register+alignment) 2304 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2305 return MCDisassembler::Fail; 2306 2307 // AddrMode6 Offset (register) 2308 switch (Inst.getOpcode()) { 2309 default: 2310 // The below have been updated to have explicit am6offset split 2311 // between fixed and register offset. For those instructions not 2312 // yet updated, we need to add an additional reg0 operand for the 2313 // fixed variant. 2314 // 2315 // The fixed offset encodes as Rm == 0xd, so we check for that. 2316 if (Rm == 0xd) { 2317 Inst.addOperand(MCOperand::CreateReg(0)); 2318 break; 2319 } 2320 // Fall through to handle the register offset variant. 2321 case ARM::VLD1d8wb_fixed: 2322 case ARM::VLD1d16wb_fixed: 2323 case ARM::VLD1d32wb_fixed: 2324 case ARM::VLD1d64wb_fixed: 2325 case ARM::VLD1d8Twb_fixed: 2326 case ARM::VLD1d16Twb_fixed: 2327 case ARM::VLD1d32Twb_fixed: 2328 case ARM::VLD1d64Twb_fixed: 2329 case ARM::VLD1d8Qwb_fixed: 2330 case ARM::VLD1d16Qwb_fixed: 2331 case ARM::VLD1d32Qwb_fixed: 2332 case ARM::VLD1d64Qwb_fixed: 2333 case ARM::VLD1d8wb_register: 2334 case ARM::VLD1d16wb_register: 2335 case ARM::VLD1d32wb_register: 2336 case ARM::VLD1d64wb_register: 2337 case ARM::VLD1q8wb_fixed: 2338 case ARM::VLD1q16wb_fixed: 2339 case ARM::VLD1q32wb_fixed: 2340 case ARM::VLD1q64wb_fixed: 2341 case ARM::VLD1q8wb_register: 2342 case ARM::VLD1q16wb_register: 2343 case ARM::VLD1q32wb_register: 2344 case ARM::VLD1q64wb_register: 2345 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2346 // variant encodes Rm == 0xf. Anything else is a register offset post- 2347 // increment and we need to add the register operand to the instruction. 2348 if (Rm != 0xD && Rm != 0xF && 2349 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2350 return MCDisassembler::Fail; 2351 break; 2352 case ARM::VLD2d8wb_fixed: 2353 case ARM::VLD2d16wb_fixed: 2354 case ARM::VLD2d32wb_fixed: 2355 case ARM::VLD2b8wb_fixed: 2356 case ARM::VLD2b16wb_fixed: 2357 case ARM::VLD2b32wb_fixed: 2358 case ARM::VLD2q8wb_fixed: 2359 case ARM::VLD2q16wb_fixed: 2360 case ARM::VLD2q32wb_fixed: 2361 break; 2362 } 2363 2364 return S; 2365 } 2366 2367 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2368 uint64_t Address, const void *Decoder) { 2369 DecodeStatus S = MCDisassembler::Success; 2370 2371 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2372 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2373 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2374 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2375 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2376 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2377 2378 // Writeback Operand 2379 switch (Inst.getOpcode()) { 2380 case ARM::VST1d8wb_fixed: 2381 case ARM::VST1d16wb_fixed: 2382 case ARM::VST1d32wb_fixed: 2383 case ARM::VST1d64wb_fixed: 2384 case ARM::VST1d8wb_register: 2385 case ARM::VST1d16wb_register: 2386 case ARM::VST1d32wb_register: 2387 case ARM::VST1d64wb_register: 2388 case ARM::VST1q8wb_fixed: 2389 case ARM::VST1q16wb_fixed: 2390 case ARM::VST1q32wb_fixed: 2391 case ARM::VST1q64wb_fixed: 2392 case ARM::VST1q8wb_register: 2393 case ARM::VST1q16wb_register: 2394 case ARM::VST1q32wb_register: 2395 case ARM::VST1q64wb_register: 2396 case ARM::VST1d8Twb_fixed: 2397 case ARM::VST1d16Twb_fixed: 2398 case ARM::VST1d32Twb_fixed: 2399 case ARM::VST1d64Twb_fixed: 2400 case ARM::VST1d8Twb_register: 2401 case ARM::VST1d16Twb_register: 2402 case ARM::VST1d32Twb_register: 2403 case ARM::VST1d64Twb_register: 2404 case ARM::VST1d8Qwb_fixed: 2405 case ARM::VST1d16Qwb_fixed: 2406 case ARM::VST1d32Qwb_fixed: 2407 case ARM::VST1d64Qwb_fixed: 2408 case ARM::VST1d8Qwb_register: 2409 case ARM::VST1d16Qwb_register: 2410 case ARM::VST1d32Qwb_register: 2411 case ARM::VST1d64Qwb_register: 2412 case ARM::VST2d8wb_fixed: 2413 case ARM::VST2d16wb_fixed: 2414 case ARM::VST2d32wb_fixed: 2415 case ARM::VST2d8wb_register: 2416 case ARM::VST2d16wb_register: 2417 case ARM::VST2d32wb_register: 2418 case ARM::VST2q8wb_fixed: 2419 case ARM::VST2q16wb_fixed: 2420 case ARM::VST2q32wb_fixed: 2421 case ARM::VST2q8wb_register: 2422 case ARM::VST2q16wb_register: 2423 case ARM::VST2q32wb_register: 2424 case ARM::VST2b8wb_fixed: 2425 case ARM::VST2b16wb_fixed: 2426 case ARM::VST2b32wb_fixed: 2427 case ARM::VST2b8wb_register: 2428 case ARM::VST2b16wb_register: 2429 case ARM::VST2b32wb_register: 2430 if (Rm == 0xF) 2431 return MCDisassembler::Fail; 2432 Inst.addOperand(MCOperand::CreateImm(0)); 2433 break; 2434 case ARM::VST3d8_UPD: 2435 case ARM::VST3d16_UPD: 2436 case ARM::VST3d32_UPD: 2437 case ARM::VST3q8_UPD: 2438 case ARM::VST3q16_UPD: 2439 case ARM::VST3q32_UPD: 2440 case ARM::VST4d8_UPD: 2441 case ARM::VST4d16_UPD: 2442 case ARM::VST4d32_UPD: 2443 case ARM::VST4q8_UPD: 2444 case ARM::VST4q16_UPD: 2445 case ARM::VST4q32_UPD: 2446 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 break; 2449 default: 2450 break; 2451 } 2452 2453 // AddrMode6 Base (register+alignment) 2454 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 2457 // AddrMode6 Offset (register) 2458 switch (Inst.getOpcode()) { 2459 default: 2460 if (Rm == 0xD) 2461 Inst.addOperand(MCOperand::CreateReg(0)); 2462 else if (Rm != 0xF) { 2463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 } 2466 break; 2467 case ARM::VST1d8wb_fixed: 2468 case ARM::VST1d16wb_fixed: 2469 case ARM::VST1d32wb_fixed: 2470 case ARM::VST1d64wb_fixed: 2471 case ARM::VST1q8wb_fixed: 2472 case ARM::VST1q16wb_fixed: 2473 case ARM::VST1q32wb_fixed: 2474 case ARM::VST1q64wb_fixed: 2475 case ARM::VST1d8Twb_fixed: 2476 case ARM::VST1d16Twb_fixed: 2477 case ARM::VST1d32Twb_fixed: 2478 case ARM::VST1d64Twb_fixed: 2479 case ARM::VST1d8Qwb_fixed: 2480 case ARM::VST1d16Qwb_fixed: 2481 case ARM::VST1d32Qwb_fixed: 2482 case ARM::VST1d64Qwb_fixed: 2483 case ARM::VST2d8wb_fixed: 2484 case ARM::VST2d16wb_fixed: 2485 case ARM::VST2d32wb_fixed: 2486 case ARM::VST2q8wb_fixed: 2487 case ARM::VST2q16wb_fixed: 2488 case ARM::VST2q32wb_fixed: 2489 case ARM::VST2b8wb_fixed: 2490 case ARM::VST2b16wb_fixed: 2491 case ARM::VST2b32wb_fixed: 2492 break; 2493 } 2494 2495 2496 // First input register 2497 switch (Inst.getOpcode()) { 2498 case ARM::VST1q16: 2499 case ARM::VST1q32: 2500 case ARM::VST1q64: 2501 case ARM::VST1q8: 2502 case ARM::VST1q16wb_fixed: 2503 case ARM::VST1q16wb_register: 2504 case ARM::VST1q32wb_fixed: 2505 case ARM::VST1q32wb_register: 2506 case ARM::VST1q64wb_fixed: 2507 case ARM::VST1q64wb_register: 2508 case ARM::VST1q8wb_fixed: 2509 case ARM::VST1q8wb_register: 2510 case ARM::VST2d16: 2511 case ARM::VST2d32: 2512 case ARM::VST2d8: 2513 case ARM::VST2d16wb_fixed: 2514 case ARM::VST2d16wb_register: 2515 case ARM::VST2d32wb_fixed: 2516 case ARM::VST2d32wb_register: 2517 case ARM::VST2d8wb_fixed: 2518 case ARM::VST2d8wb_register: 2519 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2520 return MCDisassembler::Fail; 2521 break; 2522 case ARM::VST2b16: 2523 case ARM::VST2b32: 2524 case ARM::VST2b8: 2525 case ARM::VST2b16wb_fixed: 2526 case ARM::VST2b16wb_register: 2527 case ARM::VST2b32wb_fixed: 2528 case ARM::VST2b32wb_register: 2529 case ARM::VST2b8wb_fixed: 2530 case ARM::VST2b8wb_register: 2531 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 break; 2534 default: 2535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 } 2538 2539 // Second input register 2540 switch (Inst.getOpcode()) { 2541 case ARM::VST3d8: 2542 case ARM::VST3d16: 2543 case ARM::VST3d32: 2544 case ARM::VST3d8_UPD: 2545 case ARM::VST3d16_UPD: 2546 case ARM::VST3d32_UPD: 2547 case ARM::VST4d8: 2548 case ARM::VST4d16: 2549 case ARM::VST4d32: 2550 case ARM::VST4d8_UPD: 2551 case ARM::VST4d16_UPD: 2552 case ARM::VST4d32_UPD: 2553 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2554 return MCDisassembler::Fail; 2555 break; 2556 case ARM::VST3q8: 2557 case ARM::VST3q16: 2558 case ARM::VST3q32: 2559 case ARM::VST3q8_UPD: 2560 case ARM::VST3q16_UPD: 2561 case ARM::VST3q32_UPD: 2562 case ARM::VST4q8: 2563 case ARM::VST4q16: 2564 case ARM::VST4q32: 2565 case ARM::VST4q8_UPD: 2566 case ARM::VST4q16_UPD: 2567 case ARM::VST4q32_UPD: 2568 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2569 return MCDisassembler::Fail; 2570 break; 2571 default: 2572 break; 2573 } 2574 2575 // Third input register 2576 switch (Inst.getOpcode()) { 2577 case ARM::VST3d8: 2578 case ARM::VST3d16: 2579 case ARM::VST3d32: 2580 case ARM::VST3d8_UPD: 2581 case ARM::VST3d16_UPD: 2582 case ARM::VST3d32_UPD: 2583 case ARM::VST4d8: 2584 case ARM::VST4d16: 2585 case ARM::VST4d32: 2586 case ARM::VST4d8_UPD: 2587 case ARM::VST4d16_UPD: 2588 case ARM::VST4d32_UPD: 2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2590 return MCDisassembler::Fail; 2591 break; 2592 case ARM::VST3q8: 2593 case ARM::VST3q16: 2594 case ARM::VST3q32: 2595 case ARM::VST3q8_UPD: 2596 case ARM::VST3q16_UPD: 2597 case ARM::VST3q32_UPD: 2598 case ARM::VST4q8: 2599 case ARM::VST4q16: 2600 case ARM::VST4q32: 2601 case ARM::VST4q8_UPD: 2602 case ARM::VST4q16_UPD: 2603 case ARM::VST4q32_UPD: 2604 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 break; 2607 default: 2608 break; 2609 } 2610 2611 // Fourth input register 2612 switch (Inst.getOpcode()) { 2613 case ARM::VST4d8: 2614 case ARM::VST4d16: 2615 case ARM::VST4d32: 2616 case ARM::VST4d8_UPD: 2617 case ARM::VST4d16_UPD: 2618 case ARM::VST4d32_UPD: 2619 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2620 return MCDisassembler::Fail; 2621 break; 2622 case ARM::VST4q8: 2623 case ARM::VST4q16: 2624 case ARM::VST4q32: 2625 case ARM::VST4q8_UPD: 2626 case ARM::VST4q16_UPD: 2627 case ARM::VST4q32_UPD: 2628 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2629 return MCDisassembler::Fail; 2630 break; 2631 default: 2632 break; 2633 } 2634 2635 return S; 2636 } 2637 2638 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2639 uint64_t Address, const void *Decoder) { 2640 DecodeStatus S = MCDisassembler::Success; 2641 2642 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2643 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2644 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2645 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2646 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2647 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2648 2649 align *= (1 << size); 2650 2651 switch (Inst.getOpcode()) { 2652 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2653 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2654 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2655 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2656 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2657 return MCDisassembler::Fail; 2658 break; 2659 default: 2660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2661 return MCDisassembler::Fail; 2662 break; 2663 } 2664 if (Rm != 0xF) { 2665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2666 return MCDisassembler::Fail; 2667 } 2668 2669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2670 return MCDisassembler::Fail; 2671 Inst.addOperand(MCOperand::CreateImm(align)); 2672 2673 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2674 // variant encodes Rm == 0xf. Anything else is a register offset post- 2675 // increment and we need to add the register operand to the instruction. 2676 if (Rm != 0xD && Rm != 0xF && 2677 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 2680 return S; 2681 } 2682 2683 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2684 uint64_t Address, const void *Decoder) { 2685 DecodeStatus S = MCDisassembler::Success; 2686 2687 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2688 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2689 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2690 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2691 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2692 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2693 align *= 2*size; 2694 2695 switch (Inst.getOpcode()) { 2696 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2697 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2698 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2699 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2700 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 break; 2703 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2704 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2705 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2706 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2707 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2708 return MCDisassembler::Fail; 2709 break; 2710 default: 2711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2712 return MCDisassembler::Fail; 2713 break; 2714 } 2715 2716 if (Rm != 0xF) 2717 Inst.addOperand(MCOperand::CreateImm(0)); 2718 2719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 Inst.addOperand(MCOperand::CreateImm(align)); 2722 2723 if (Rm != 0xD && Rm != 0xF) { 2724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 } 2727 2728 return S; 2729 } 2730 2731 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2732 uint64_t Address, const void *Decoder) { 2733 DecodeStatus S = MCDisassembler::Success; 2734 2735 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2736 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2737 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2738 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2739 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2740 2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2746 return MCDisassembler::Fail; 2747 if (Rm != 0xF) { 2748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 } 2751 2752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 Inst.addOperand(MCOperand::CreateImm(0)); 2755 2756 if (Rm == 0xD) 2757 Inst.addOperand(MCOperand::CreateReg(0)); 2758 else if (Rm != 0xF) { 2759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2760 return MCDisassembler::Fail; 2761 } 2762 2763 return S; 2764 } 2765 2766 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2767 uint64_t Address, const void *Decoder) { 2768 DecodeStatus S = MCDisassembler::Success; 2769 2770 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2771 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2772 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2773 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2774 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2775 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2776 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2777 2778 if (size == 0x3) { 2779 size = 4; 2780 align = 16; 2781 } else { 2782 if (size == 2) { 2783 size = 1 << size; 2784 align *= 8; 2785 } else { 2786 size = 1 << size; 2787 align *= 4*size; 2788 } 2789 } 2790 2791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2792 return MCDisassembler::Fail; 2793 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2794 return MCDisassembler::Fail; 2795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2796 return MCDisassembler::Fail; 2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2798 return MCDisassembler::Fail; 2799 if (Rm != 0xF) { 2800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2801 return MCDisassembler::Fail; 2802 } 2803 2804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 Inst.addOperand(MCOperand::CreateImm(align)); 2807 2808 if (Rm == 0xD) 2809 Inst.addOperand(MCOperand::CreateReg(0)); 2810 else if (Rm != 0xF) { 2811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 } 2814 2815 return S; 2816 } 2817 2818 static DecodeStatus 2819 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2820 uint64_t Address, const void *Decoder) { 2821 DecodeStatus S = MCDisassembler::Success; 2822 2823 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2824 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2825 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2826 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2827 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2828 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2829 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2830 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2831 2832 if (Q) { 2833 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 } else { 2836 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2837 return MCDisassembler::Fail; 2838 } 2839 2840 Inst.addOperand(MCOperand::CreateImm(imm)); 2841 2842 switch (Inst.getOpcode()) { 2843 case ARM::VORRiv4i16: 2844 case ARM::VORRiv2i32: 2845 case ARM::VBICiv4i16: 2846 case ARM::VBICiv2i32: 2847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2848 return MCDisassembler::Fail; 2849 break; 2850 case ARM::VORRiv8i16: 2851 case ARM::VORRiv4i32: 2852 case ARM::VBICiv8i16: 2853 case ARM::VBICiv4i32: 2854 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2855 return MCDisassembler::Fail; 2856 break; 2857 default: 2858 break; 2859 } 2860 2861 return S; 2862 } 2863 2864 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2865 uint64_t Address, const void *Decoder) { 2866 DecodeStatus S = MCDisassembler::Success; 2867 2868 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2869 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2870 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2871 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2872 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2873 2874 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2879 2880 return S; 2881 } 2882 2883 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2884 uint64_t Address, const void *Decoder) { 2885 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2886 return MCDisassembler::Success; 2887 } 2888 2889 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2890 uint64_t Address, const void *Decoder) { 2891 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2892 return MCDisassembler::Success; 2893 } 2894 2895 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2896 uint64_t Address, const void *Decoder) { 2897 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2898 return MCDisassembler::Success; 2899 } 2900 2901 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2902 uint64_t Address, const void *Decoder) { 2903 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2904 return MCDisassembler::Success; 2905 } 2906 2907 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2908 uint64_t Address, const void *Decoder) { 2909 DecodeStatus S = MCDisassembler::Success; 2910 2911 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2912 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2913 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2914 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2915 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2916 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2917 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2918 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 if (op) { 2922 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2923 return MCDisassembler::Fail; // Writeback 2924 } 2925 2926 switch (Inst.getOpcode()) { 2927 case ARM::VTBL2: 2928 case ARM::VTBX2: 2929 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 break; 2932 default: 2933 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2934 return MCDisassembler::Fail; 2935 } 2936 2937 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 2940 return S; 2941 } 2942 2943 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2944 uint64_t Address, const void *Decoder) { 2945 DecodeStatus S = MCDisassembler::Success; 2946 2947 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2948 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2949 2950 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 2953 switch(Inst.getOpcode()) { 2954 default: 2955 return MCDisassembler::Fail; 2956 case ARM::tADR: 2957 break; // tADR does not explicitly represent the PC as an operand. 2958 case ARM::tADDrSPi: 2959 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2960 break; 2961 } 2962 2963 Inst.addOperand(MCOperand::CreateImm(imm)); 2964 return S; 2965 } 2966 2967 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 2968 uint64_t Address, const void *Decoder) { 2969 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 2970 true, 2, Inst, Decoder)) 2971 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2972 return MCDisassembler::Success; 2973 } 2974 2975 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 2976 uint64_t Address, const void *Decoder) { 2977 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 2978 true, 4, Inst, Decoder)) 2979 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2980 return MCDisassembler::Success; 2981 } 2982 2983 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 2984 uint64_t Address, const void *Decoder) { 2985 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 2986 true, 2, Inst, Decoder)) 2987 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2988 return MCDisassembler::Success; 2989 } 2990 2991 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 2992 uint64_t Address, const void *Decoder) { 2993 DecodeStatus S = MCDisassembler::Success; 2994 2995 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2996 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2997 2998 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3001 return MCDisassembler::Fail; 3002 3003 return S; 3004 } 3005 3006 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3007 uint64_t Address, const void *Decoder) { 3008 DecodeStatus S = MCDisassembler::Success; 3009 3010 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 3011 unsigned imm = fieldFromInstruction32(Val, 3, 5); 3012 3013 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3014 return MCDisassembler::Fail; 3015 Inst.addOperand(MCOperand::CreateImm(imm)); 3016 3017 return S; 3018 } 3019 3020 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3021 uint64_t Address, const void *Decoder) { 3022 unsigned imm = Val << 2; 3023 3024 Inst.addOperand(MCOperand::CreateImm(imm)); 3025 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3026 3027 return MCDisassembler::Success; 3028 } 3029 3030 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3031 uint64_t Address, const void *Decoder) { 3032 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3033 Inst.addOperand(MCOperand::CreateImm(Val)); 3034 3035 return MCDisassembler::Success; 3036 } 3037 3038 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3039 uint64_t Address, const void *Decoder) { 3040 DecodeStatus S = MCDisassembler::Success; 3041 3042 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3043 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3044 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3045 3046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3047 return MCDisassembler::Fail; 3048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 Inst.addOperand(MCOperand::CreateImm(imm)); 3051 3052 return S; 3053 } 3054 3055 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3056 uint64_t Address, const void *Decoder) { 3057 DecodeStatus S = MCDisassembler::Success; 3058 3059 switch (Inst.getOpcode()) { 3060 case ARM::t2PLDs: 3061 case ARM::t2PLDWs: 3062 case ARM::t2PLIs: 3063 break; 3064 default: { 3065 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3066 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3067 return MCDisassembler::Fail; 3068 } 3069 } 3070 3071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3072 if (Rn == 0xF) { 3073 switch (Inst.getOpcode()) { 3074 case ARM::t2LDRBs: 3075 Inst.setOpcode(ARM::t2LDRBpci); 3076 break; 3077 case ARM::t2LDRHs: 3078 Inst.setOpcode(ARM::t2LDRHpci); 3079 break; 3080 case ARM::t2LDRSHs: 3081 Inst.setOpcode(ARM::t2LDRSHpci); 3082 break; 3083 case ARM::t2LDRSBs: 3084 Inst.setOpcode(ARM::t2LDRSBpci); 3085 break; 3086 case ARM::t2PLDs: 3087 Inst.setOpcode(ARM::t2PLDi12); 3088 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3089 break; 3090 default: 3091 return MCDisassembler::Fail; 3092 } 3093 3094 int imm = fieldFromInstruction32(Insn, 0, 12); 3095 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3096 Inst.addOperand(MCOperand::CreateImm(imm)); 3097 3098 return S; 3099 } 3100 3101 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3102 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3103 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3104 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3105 return MCDisassembler::Fail; 3106 3107 return S; 3108 } 3109 3110 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3111 uint64_t Address, const void *Decoder) { 3112 int imm = Val & 0xFF; 3113 if (!(Val & 0x100)) imm *= -1; 3114 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3115 3116 return MCDisassembler::Success; 3117 } 3118 3119 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3120 uint64_t Address, const void *Decoder) { 3121 DecodeStatus S = MCDisassembler::Success; 3122 3123 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3124 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3125 3126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3127 return MCDisassembler::Fail; 3128 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3129 return MCDisassembler::Fail; 3130 3131 return S; 3132 } 3133 3134 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3135 uint64_t Address, const void *Decoder) { 3136 DecodeStatus S = MCDisassembler::Success; 3137 3138 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3139 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3140 3141 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3142 return MCDisassembler::Fail; 3143 3144 Inst.addOperand(MCOperand::CreateImm(imm)); 3145 3146 return S; 3147 } 3148 3149 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3150 uint64_t Address, const void *Decoder) { 3151 int imm = Val & 0xFF; 3152 if (Val == 0) 3153 imm = INT32_MIN; 3154 else if (!(Val & 0x100)) 3155 imm *= -1; 3156 Inst.addOperand(MCOperand::CreateImm(imm)); 3157 3158 return MCDisassembler::Success; 3159 } 3160 3161 3162 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3163 uint64_t Address, const void *Decoder) { 3164 DecodeStatus S = MCDisassembler::Success; 3165 3166 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3167 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3168 3169 // Some instructions always use an additive offset. 3170 switch (Inst.getOpcode()) { 3171 case ARM::t2LDRT: 3172 case ARM::t2LDRBT: 3173 case ARM::t2LDRHT: 3174 case ARM::t2LDRSBT: 3175 case ARM::t2LDRSHT: 3176 case ARM::t2STRT: 3177 case ARM::t2STRBT: 3178 case ARM::t2STRHT: 3179 imm |= 0x100; 3180 break; 3181 default: 3182 break; 3183 } 3184 3185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3186 return MCDisassembler::Fail; 3187 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 3190 return S; 3191 } 3192 3193 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3194 uint64_t Address, const void *Decoder) { 3195 DecodeStatus S = MCDisassembler::Success; 3196 3197 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3198 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3199 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3200 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3201 addr |= Rn << 9; 3202 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3203 3204 if (!load) { 3205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3206 return MCDisassembler::Fail; 3207 } 3208 3209 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3210 return MCDisassembler::Fail; 3211 3212 if (load) { 3213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3214 return MCDisassembler::Fail; 3215 } 3216 3217 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 3220 return S; 3221 } 3222 3223 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3224 uint64_t Address, const void *Decoder) { 3225 DecodeStatus S = MCDisassembler::Success; 3226 3227 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3228 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3229 3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3231 return MCDisassembler::Fail; 3232 Inst.addOperand(MCOperand::CreateImm(imm)); 3233 3234 return S; 3235 } 3236 3237 3238 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3239 uint64_t Address, const void *Decoder) { 3240 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3241 3242 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3243 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3244 Inst.addOperand(MCOperand::CreateImm(imm)); 3245 3246 return MCDisassembler::Success; 3247 } 3248 3249 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3250 uint64_t Address, const void *Decoder) { 3251 DecodeStatus S = MCDisassembler::Success; 3252 3253 if (Inst.getOpcode() == ARM::tADDrSP) { 3254 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3255 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3256 3257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3262 } else if (Inst.getOpcode() == ARM::tADDspr) { 3263 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3264 3265 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3266 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 } 3270 3271 return S; 3272 } 3273 3274 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3275 uint64_t Address, const void *Decoder) { 3276 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3277 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3278 3279 Inst.addOperand(MCOperand::CreateImm(imod)); 3280 Inst.addOperand(MCOperand::CreateImm(flags)); 3281 3282 return MCDisassembler::Success; 3283 } 3284 3285 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3286 uint64_t Address, const void *Decoder) { 3287 DecodeStatus S = MCDisassembler::Success; 3288 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3289 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3290 3291 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 Inst.addOperand(MCOperand::CreateImm(add)); 3294 3295 return S; 3296 } 3297 3298 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3299 uint64_t Address, const void *Decoder) { 3300 if (!tryAddingSymbolicOperand(Address, 3301 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3302 true, 4, Inst, Decoder)) 3303 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3304 return MCDisassembler::Success; 3305 } 3306 3307 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3308 uint64_t Address, const void *Decoder) { 3309 if (Val == 0xA || Val == 0xB) 3310 return MCDisassembler::Fail; 3311 3312 Inst.addOperand(MCOperand::CreateImm(Val)); 3313 return MCDisassembler::Success; 3314 } 3315 3316 static DecodeStatus 3317 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3318 uint64_t Address, const void *Decoder) { 3319 DecodeStatus S = MCDisassembler::Success; 3320 3321 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3322 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3323 3324 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 return S; 3330 } 3331 3332 static DecodeStatus 3333 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3334 uint64_t Address, const void *Decoder) { 3335 DecodeStatus S = MCDisassembler::Success; 3336 3337 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3338 if (pred == 0xE || pred == 0xF) { 3339 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3340 switch (opc) { 3341 default: 3342 return MCDisassembler::Fail; 3343 case 0xf3bf8f4: 3344 Inst.setOpcode(ARM::t2DSB); 3345 break; 3346 case 0xf3bf8f5: 3347 Inst.setOpcode(ARM::t2DMB); 3348 break; 3349 case 0xf3bf8f6: 3350 Inst.setOpcode(ARM::t2ISB); 3351 break; 3352 } 3353 3354 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3355 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3356 } 3357 3358 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3359 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3360 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3361 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3362 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3363 3364 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3365 return MCDisassembler::Fail; 3366 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 3369 return S; 3370 } 3371 3372 // Decode a shifted immediate operand. These basically consist 3373 // of an 8-bit value, and a 4-bit directive that specifies either 3374 // a splat operation or a rotation. 3375 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3376 uint64_t Address, const void *Decoder) { 3377 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3378 if (ctrl == 0) { 3379 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3380 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3381 switch (byte) { 3382 case 0: 3383 Inst.addOperand(MCOperand::CreateImm(imm)); 3384 break; 3385 case 1: 3386 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3387 break; 3388 case 2: 3389 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3390 break; 3391 case 3: 3392 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3393 (imm << 8) | imm)); 3394 break; 3395 } 3396 } else { 3397 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3398 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3399 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3400 Inst.addOperand(MCOperand::CreateImm(imm)); 3401 } 3402 3403 return MCDisassembler::Success; 3404 } 3405 3406 static DecodeStatus 3407 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3408 uint64_t Address, const void *Decoder){ 3409 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4, 3410 true, 2, Inst, Decoder)) 3411 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1))); 3412 return MCDisassembler::Success; 3413 } 3414 3415 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3416 uint64_t Address, const void *Decoder){ 3417 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3418 true, 4, Inst, Decoder)) 3419 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3420 return MCDisassembler::Success; 3421 } 3422 3423 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3424 uint64_t Address, const void *Decoder) { 3425 switch (Val) { 3426 default: 3427 return MCDisassembler::Fail; 3428 case 0xF: // SY 3429 case 0xE: // ST 3430 case 0xB: // ISH 3431 case 0xA: // ISHST 3432 case 0x7: // NSH 3433 case 0x6: // NSHST 3434 case 0x3: // OSH 3435 case 0x2: // OSHST 3436 break; 3437 } 3438 3439 Inst.addOperand(MCOperand::CreateImm(Val)); 3440 return MCDisassembler::Success; 3441 } 3442 3443 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3444 uint64_t Address, const void *Decoder) { 3445 if (!Val) return MCDisassembler::Fail; 3446 Inst.addOperand(MCOperand::CreateImm(Val)); 3447 return MCDisassembler::Success; 3448 } 3449 3450 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3451 uint64_t Address, const void *Decoder) { 3452 DecodeStatus S = MCDisassembler::Success; 3453 3454 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3455 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3456 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3457 3458 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3459 3460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 3469 return S; 3470 } 3471 3472 3473 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3474 uint64_t Address, const void *Decoder){ 3475 DecodeStatus S = MCDisassembler::Success; 3476 3477 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3478 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3479 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3480 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3481 3482 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3483 return MCDisassembler::Fail; 3484 3485 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3486 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3487 3488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3489 return MCDisassembler::Fail; 3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 3497 return S; 3498 } 3499 3500 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3501 uint64_t Address, const void *Decoder) { 3502 DecodeStatus S = MCDisassembler::Success; 3503 3504 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3505 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3506 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3507 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3508 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3509 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3510 3511 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3512 3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3516 return MCDisassembler::Fail; 3517 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3520 return MCDisassembler::Fail; 3521 3522 return S; 3523 } 3524 3525 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3526 uint64_t Address, const void *Decoder) { 3527 DecodeStatus S = MCDisassembler::Success; 3528 3529 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3530 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3531 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3532 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3533 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3534 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3536 3537 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3538 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3539 3540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3541 return MCDisassembler::Fail; 3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3547 return MCDisassembler::Fail; 3548 3549 return S; 3550 } 3551 3552 3553 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3554 uint64_t Address, const void *Decoder) { 3555 DecodeStatus S = MCDisassembler::Success; 3556 3557 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3558 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3559 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3560 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3561 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3562 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3563 3564 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3565 3566 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 3575 return S; 3576 } 3577 3578 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3579 uint64_t Address, const void *Decoder) { 3580 DecodeStatus S = MCDisassembler::Success; 3581 3582 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3583 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3584 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3585 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3586 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3587 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3588 3589 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3590 3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 3600 return S; 3601 } 3602 3603 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3604 uint64_t Address, const void *Decoder) { 3605 DecodeStatus S = MCDisassembler::Success; 3606 3607 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3608 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3609 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3610 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3611 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3612 3613 unsigned align = 0; 3614 unsigned index = 0; 3615 switch (size) { 3616 default: 3617 return MCDisassembler::Fail; 3618 case 0: 3619 if (fieldFromInstruction32(Insn, 4, 1)) 3620 return MCDisassembler::Fail; // UNDEFINED 3621 index = fieldFromInstruction32(Insn, 5, 3); 3622 break; 3623 case 1: 3624 if (fieldFromInstruction32(Insn, 5, 1)) 3625 return MCDisassembler::Fail; // UNDEFINED 3626 index = fieldFromInstruction32(Insn, 6, 2); 3627 if (fieldFromInstruction32(Insn, 4, 1)) 3628 align = 2; 3629 break; 3630 case 2: 3631 if (fieldFromInstruction32(Insn, 6, 1)) 3632 return MCDisassembler::Fail; // UNDEFINED 3633 index = fieldFromInstruction32(Insn, 7, 1); 3634 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3635 align = 4; 3636 } 3637 3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 if (Rm != 0xF) { // Writeback 3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 } 3644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 Inst.addOperand(MCOperand::CreateImm(align)); 3647 if (Rm != 0xF) { 3648 if (Rm != 0xD) { 3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 } else 3652 Inst.addOperand(MCOperand::CreateReg(0)); 3653 } 3654 3655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3656 return MCDisassembler::Fail; 3657 Inst.addOperand(MCOperand::CreateImm(index)); 3658 3659 return S; 3660 } 3661 3662 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3663 uint64_t Address, const void *Decoder) { 3664 DecodeStatus S = MCDisassembler::Success; 3665 3666 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3667 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3668 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3669 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3670 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3671 3672 unsigned align = 0; 3673 unsigned index = 0; 3674 switch (size) { 3675 default: 3676 return MCDisassembler::Fail; 3677 case 0: 3678 if (fieldFromInstruction32(Insn, 4, 1)) 3679 return MCDisassembler::Fail; // UNDEFINED 3680 index = fieldFromInstruction32(Insn, 5, 3); 3681 break; 3682 case 1: 3683 if (fieldFromInstruction32(Insn, 5, 1)) 3684 return MCDisassembler::Fail; // UNDEFINED 3685 index = fieldFromInstruction32(Insn, 6, 2); 3686 if (fieldFromInstruction32(Insn, 4, 1)) 3687 align = 2; 3688 break; 3689 case 2: 3690 if (fieldFromInstruction32(Insn, 6, 1)) 3691 return MCDisassembler::Fail; // UNDEFINED 3692 index = fieldFromInstruction32(Insn, 7, 1); 3693 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3694 align = 4; 3695 } 3696 3697 if (Rm != 0xF) { // Writeback 3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 } 3701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3702 return MCDisassembler::Fail; 3703 Inst.addOperand(MCOperand::CreateImm(align)); 3704 if (Rm != 0xF) { 3705 if (Rm != 0xD) { 3706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3707 return MCDisassembler::Fail; 3708 } else 3709 Inst.addOperand(MCOperand::CreateReg(0)); 3710 } 3711 3712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 Inst.addOperand(MCOperand::CreateImm(index)); 3715 3716 return S; 3717 } 3718 3719 3720 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3721 uint64_t Address, const void *Decoder) { 3722 DecodeStatus S = MCDisassembler::Success; 3723 3724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3725 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3726 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3727 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3728 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3729 3730 unsigned align = 0; 3731 unsigned index = 0; 3732 unsigned inc = 1; 3733 switch (size) { 3734 default: 3735 return MCDisassembler::Fail; 3736 case 0: 3737 index = fieldFromInstruction32(Insn, 5, 3); 3738 if (fieldFromInstruction32(Insn, 4, 1)) 3739 align = 2; 3740 break; 3741 case 1: 3742 index = fieldFromInstruction32(Insn, 6, 2); 3743 if (fieldFromInstruction32(Insn, 4, 1)) 3744 align = 4; 3745 if (fieldFromInstruction32(Insn, 5, 1)) 3746 inc = 2; 3747 break; 3748 case 2: 3749 if (fieldFromInstruction32(Insn, 5, 1)) 3750 return MCDisassembler::Fail; // UNDEFINED 3751 index = fieldFromInstruction32(Insn, 7, 1); 3752 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3753 align = 8; 3754 if (fieldFromInstruction32(Insn, 6, 1)) 3755 inc = 2; 3756 break; 3757 } 3758 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 if (Rm != 0xF) { // Writeback 3764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3765 return MCDisassembler::Fail; 3766 } 3767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3768 return MCDisassembler::Fail; 3769 Inst.addOperand(MCOperand::CreateImm(align)); 3770 if (Rm != 0xF) { 3771 if (Rm != 0xD) { 3772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 } else 3775 Inst.addOperand(MCOperand::CreateReg(0)); 3776 } 3777 3778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3779 return MCDisassembler::Fail; 3780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3781 return MCDisassembler::Fail; 3782 Inst.addOperand(MCOperand::CreateImm(index)); 3783 3784 return S; 3785 } 3786 3787 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3788 uint64_t Address, const void *Decoder) { 3789 DecodeStatus S = MCDisassembler::Success; 3790 3791 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3792 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3793 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3794 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3795 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3796 3797 unsigned align = 0; 3798 unsigned index = 0; 3799 unsigned inc = 1; 3800 switch (size) { 3801 default: 3802 return MCDisassembler::Fail; 3803 case 0: 3804 index = fieldFromInstruction32(Insn, 5, 3); 3805 if (fieldFromInstruction32(Insn, 4, 1)) 3806 align = 2; 3807 break; 3808 case 1: 3809 index = fieldFromInstruction32(Insn, 6, 2); 3810 if (fieldFromInstruction32(Insn, 4, 1)) 3811 align = 4; 3812 if (fieldFromInstruction32(Insn, 5, 1)) 3813 inc = 2; 3814 break; 3815 case 2: 3816 if (fieldFromInstruction32(Insn, 5, 1)) 3817 return MCDisassembler::Fail; // UNDEFINED 3818 index = fieldFromInstruction32(Insn, 7, 1); 3819 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3820 align = 8; 3821 if (fieldFromInstruction32(Insn, 6, 1)) 3822 inc = 2; 3823 break; 3824 } 3825 3826 if (Rm != 0xF) { // Writeback 3827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3828 return MCDisassembler::Fail; 3829 } 3830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 Inst.addOperand(MCOperand::CreateImm(align)); 3833 if (Rm != 0xF) { 3834 if (Rm != 0xD) { 3835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 } else 3838 Inst.addOperand(MCOperand::CreateReg(0)); 3839 } 3840 3841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3842 return MCDisassembler::Fail; 3843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3844 return MCDisassembler::Fail; 3845 Inst.addOperand(MCOperand::CreateImm(index)); 3846 3847 return S; 3848 } 3849 3850 3851 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3852 uint64_t Address, const void *Decoder) { 3853 DecodeStatus S = MCDisassembler::Success; 3854 3855 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3857 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3858 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3859 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3860 3861 unsigned align = 0; 3862 unsigned index = 0; 3863 unsigned inc = 1; 3864 switch (size) { 3865 default: 3866 return MCDisassembler::Fail; 3867 case 0: 3868 if (fieldFromInstruction32(Insn, 4, 1)) 3869 return MCDisassembler::Fail; // UNDEFINED 3870 index = fieldFromInstruction32(Insn, 5, 3); 3871 break; 3872 case 1: 3873 if (fieldFromInstruction32(Insn, 4, 1)) 3874 return MCDisassembler::Fail; // UNDEFINED 3875 index = fieldFromInstruction32(Insn, 6, 2); 3876 if (fieldFromInstruction32(Insn, 5, 1)) 3877 inc = 2; 3878 break; 3879 case 2: 3880 if (fieldFromInstruction32(Insn, 4, 2)) 3881 return MCDisassembler::Fail; // UNDEFINED 3882 index = fieldFromInstruction32(Insn, 7, 1); 3883 if (fieldFromInstruction32(Insn, 6, 1)) 3884 inc = 2; 3885 break; 3886 } 3887 3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3893 return MCDisassembler::Fail; 3894 3895 if (Rm != 0xF) { // Writeback 3896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 } 3899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3900 return MCDisassembler::Fail; 3901 Inst.addOperand(MCOperand::CreateImm(align)); 3902 if (Rm != 0xF) { 3903 if (Rm != 0xD) { 3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 } else 3907 Inst.addOperand(MCOperand::CreateReg(0)); 3908 } 3909 3910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3913 return MCDisassembler::Fail; 3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3915 return MCDisassembler::Fail; 3916 Inst.addOperand(MCOperand::CreateImm(index)); 3917 3918 return S; 3919 } 3920 3921 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 3922 uint64_t Address, const void *Decoder) { 3923 DecodeStatus S = MCDisassembler::Success; 3924 3925 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3926 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3927 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3928 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3929 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3930 3931 unsigned align = 0; 3932 unsigned index = 0; 3933 unsigned inc = 1; 3934 switch (size) { 3935 default: 3936 return MCDisassembler::Fail; 3937 case 0: 3938 if (fieldFromInstruction32(Insn, 4, 1)) 3939 return MCDisassembler::Fail; // UNDEFINED 3940 index = fieldFromInstruction32(Insn, 5, 3); 3941 break; 3942 case 1: 3943 if (fieldFromInstruction32(Insn, 4, 1)) 3944 return MCDisassembler::Fail; // UNDEFINED 3945 index = fieldFromInstruction32(Insn, 6, 2); 3946 if (fieldFromInstruction32(Insn, 5, 1)) 3947 inc = 2; 3948 break; 3949 case 2: 3950 if (fieldFromInstruction32(Insn, 4, 2)) 3951 return MCDisassembler::Fail; // UNDEFINED 3952 index = fieldFromInstruction32(Insn, 7, 1); 3953 if (fieldFromInstruction32(Insn, 6, 1)) 3954 inc = 2; 3955 break; 3956 } 3957 3958 if (Rm != 0xF) { // Writeback 3959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 } 3962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3963 return MCDisassembler::Fail; 3964 Inst.addOperand(MCOperand::CreateImm(align)); 3965 if (Rm != 0xF) { 3966 if (Rm != 0xD) { 3967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3968 return MCDisassembler::Fail; 3969 } else 3970 Inst.addOperand(MCOperand::CreateReg(0)); 3971 } 3972 3973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3974 return MCDisassembler::Fail; 3975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3976 return MCDisassembler::Fail; 3977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3978 return MCDisassembler::Fail; 3979 Inst.addOperand(MCOperand::CreateImm(index)); 3980 3981 return S; 3982 } 3983 3984 3985 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 3986 uint64_t Address, const void *Decoder) { 3987 DecodeStatus S = MCDisassembler::Success; 3988 3989 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3990 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3991 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3992 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3993 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3994 3995 unsigned align = 0; 3996 unsigned index = 0; 3997 unsigned inc = 1; 3998 switch (size) { 3999 default: 4000 return MCDisassembler::Fail; 4001 case 0: 4002 if (fieldFromInstruction32(Insn, 4, 1)) 4003 align = 4; 4004 index = fieldFromInstruction32(Insn, 5, 3); 4005 break; 4006 case 1: 4007 if (fieldFromInstruction32(Insn, 4, 1)) 4008 align = 8; 4009 index = fieldFromInstruction32(Insn, 6, 2); 4010 if (fieldFromInstruction32(Insn, 5, 1)) 4011 inc = 2; 4012 break; 4013 case 2: 4014 if (fieldFromInstruction32(Insn, 4, 2)) 4015 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4016 index = fieldFromInstruction32(Insn, 7, 1); 4017 if (fieldFromInstruction32(Insn, 6, 1)) 4018 inc = 2; 4019 break; 4020 } 4021 4022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 4031 if (Rm != 0xF) { // Writeback 4032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4033 return MCDisassembler::Fail; 4034 } 4035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 Inst.addOperand(MCOperand::CreateImm(align)); 4038 if (Rm != 0xF) { 4039 if (Rm != 0xD) { 4040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 } else 4043 Inst.addOperand(MCOperand::CreateReg(0)); 4044 } 4045 4046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4047 return MCDisassembler::Fail; 4048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4049 return MCDisassembler::Fail; 4050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4053 return MCDisassembler::Fail; 4054 Inst.addOperand(MCOperand::CreateImm(index)); 4055 4056 return S; 4057 } 4058 4059 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4060 uint64_t Address, const void *Decoder) { 4061 DecodeStatus S = MCDisassembler::Success; 4062 4063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4064 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4065 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4066 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4067 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4068 4069 unsigned align = 0; 4070 unsigned index = 0; 4071 unsigned inc = 1; 4072 switch (size) { 4073 default: 4074 return MCDisassembler::Fail; 4075 case 0: 4076 if (fieldFromInstruction32(Insn, 4, 1)) 4077 align = 4; 4078 index = fieldFromInstruction32(Insn, 5, 3); 4079 break; 4080 case 1: 4081 if (fieldFromInstruction32(Insn, 4, 1)) 4082 align = 8; 4083 index = fieldFromInstruction32(Insn, 6, 2); 4084 if (fieldFromInstruction32(Insn, 5, 1)) 4085 inc = 2; 4086 break; 4087 case 2: 4088 if (fieldFromInstruction32(Insn, 4, 2)) 4089 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4090 index = fieldFromInstruction32(Insn, 7, 1); 4091 if (fieldFromInstruction32(Insn, 6, 1)) 4092 inc = 2; 4093 break; 4094 } 4095 4096 if (Rm != 0xF) { // Writeback 4097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4098 return MCDisassembler::Fail; 4099 } 4100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4101 return MCDisassembler::Fail; 4102 Inst.addOperand(MCOperand::CreateImm(align)); 4103 if (Rm != 0xF) { 4104 if (Rm != 0xD) { 4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 } else 4108 Inst.addOperand(MCOperand::CreateReg(0)); 4109 } 4110 4111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4112 return MCDisassembler::Fail; 4113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4116 return MCDisassembler::Fail; 4117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 Inst.addOperand(MCOperand::CreateImm(index)); 4120 4121 return S; 4122 } 4123 4124 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4125 uint64_t Address, const void *Decoder) { 4126 DecodeStatus S = MCDisassembler::Success; 4127 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4128 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4129 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4130 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4131 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4132 4133 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4134 S = MCDisassembler::SoftFail; 4135 4136 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4137 return MCDisassembler::Fail; 4138 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4139 return MCDisassembler::Fail; 4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4143 return MCDisassembler::Fail; 4144 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 4147 return S; 4148 } 4149 4150 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4151 uint64_t Address, const void *Decoder) { 4152 DecodeStatus S = MCDisassembler::Success; 4153 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4154 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4155 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4156 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4157 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4158 4159 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4160 S = MCDisassembler::SoftFail; 4161 4162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4163 return MCDisassembler::Fail; 4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4165 return MCDisassembler::Fail; 4166 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4167 return MCDisassembler::Fail; 4168 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4169 return MCDisassembler::Fail; 4170 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 4173 return S; 4174 } 4175 4176 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4177 uint64_t Address, const void *Decoder) { 4178 DecodeStatus S = MCDisassembler::Success; 4179 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4180 // The InstPrinter needs to have the low bit of the predicate in 4181 // the mask operand to be able to print it properly. 4182 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4183 4184 if (pred == 0xF) { 4185 pred = 0xE; 4186 S = MCDisassembler::SoftFail; 4187 } 4188 4189 if ((mask & 0xF) == 0) { 4190 // Preserve the high bit of the mask, which is the low bit of 4191 // the predicate. 4192 mask &= 0x10; 4193 mask |= 0x8; 4194 S = MCDisassembler::SoftFail; 4195 } 4196 4197 Inst.addOperand(MCOperand::CreateImm(pred)); 4198 Inst.addOperand(MCOperand::CreateImm(mask)); 4199 return S; 4200 } 4201 4202 static DecodeStatus 4203 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4204 uint64_t Address, const void *Decoder) { 4205 DecodeStatus S = MCDisassembler::Success; 4206 4207 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4208 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4209 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4210 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4211 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4212 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4213 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4214 bool writeback = (W == 1) | (P == 0); 4215 4216 addr |= (U << 8) | (Rn << 9); 4217 4218 if (writeback && (Rn == Rt || Rn == Rt2)) 4219 Check(S, MCDisassembler::SoftFail); 4220 if (Rt == Rt2) 4221 Check(S, MCDisassembler::SoftFail); 4222 4223 // Rt 4224 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4225 return MCDisassembler::Fail; 4226 // Rt2 4227 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4228 return MCDisassembler::Fail; 4229 // Writeback operand 4230 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 // addr 4233 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 4236 return S; 4237 } 4238 4239 static DecodeStatus 4240 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4241 uint64_t Address, const void *Decoder) { 4242 DecodeStatus S = MCDisassembler::Success; 4243 4244 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4245 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4247 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4248 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4249 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4250 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4251 bool writeback = (W == 1) | (P == 0); 4252 4253 addr |= (U << 8) | (Rn << 9); 4254 4255 if (writeback && (Rn == Rt || Rn == Rt2)) 4256 Check(S, MCDisassembler::SoftFail); 4257 4258 // Writeback operand 4259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 // Rt 4262 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 // Rt2 4265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 // addr 4268 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 4271 return S; 4272 } 4273 4274 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4275 uint64_t Address, const void *Decoder) { 4276 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4277 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4278 if (sign1 != sign2) return MCDisassembler::Fail; 4279 4280 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4281 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4282 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4283 Val |= sign1 << 12; 4284 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4285 4286 return MCDisassembler::Success; 4287 } 4288 4289 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4290 uint64_t Address, 4291 const void *Decoder) { 4292 DecodeStatus S = MCDisassembler::Success; 4293 4294 // Shift of "asr #32" is not allowed in Thumb2 mode. 4295 if (Val == 0x20) S = MCDisassembler::SoftFail; 4296 Inst.addOperand(MCOperand::CreateImm(Val)); 4297 return S; 4298 } 4299 4300 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4301 uint64_t Address, const void *Decoder) { 4302 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4303 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4304 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4305 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4306 4307 if (pred == 0xF) 4308 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4309 4310 DecodeStatus S = MCDisassembler::Success; 4311 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4312 return MCDisassembler::Fail; 4313 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 4320 return S; 4321 } 4322 4323 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4324 uint64_t Address, const void *Decoder) { 4325 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4326 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4327 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4328 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4329 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4330 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4331 4332 DecodeStatus S = MCDisassembler::Success; 4333 4334 // VMOVv2f32 is ambiguous with these decodings. 4335 if (!(imm & 0x38) && cmode == 0xF) { 4336 Inst.setOpcode(ARM::VMOVv2f32); 4337 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4338 } 4339 4340 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4341 4342 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4347 4348 return S; 4349 } 4350 4351 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4352 uint64_t Address, const void *Decoder) { 4353 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4354 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4355 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4356 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4357 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4358 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4359 4360 DecodeStatus S = MCDisassembler::Success; 4361 4362 // VMOVv4f32 is ambiguous with these decodings. 4363 if (!(imm & 0x38) && cmode == 0xF) { 4364 Inst.setOpcode(ARM::VMOVv4f32); 4365 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4366 } 4367 4368 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4369 4370 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4371 return MCDisassembler::Fail; 4372 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4373 return MCDisassembler::Fail; 4374 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4375 4376 return S; 4377 } 4378 4379 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4380 uint64_t Address, const void *Decoder) { 4381 DecodeStatus S = MCDisassembler::Success; 4382 4383 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4384 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4385 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4386 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4387 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4388 4389 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4390 S = MCDisassembler::SoftFail; 4391 4392 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4393 return MCDisassembler::Fail; 4394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4397 return MCDisassembler::Fail; 4398 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 4403 return S; 4404 } 4405 4406