[ARMv8] Add support for the v8 cryptography extensions.

llvm-svn: 190996

This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)

llvm-svn: 187804

[ARMv8] Add support for the NEON instructions vmaxnm/vminnm.

This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.

llvm-svn: 186504

Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.

llvm-svn: 185651

Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.

This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while ot

Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.

This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.

llvm-svn: 185642

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ARM: check predicate bits for thumb instructions

When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

llvm-svn: 184707

ARM: rGPR is meant to be unpredictable, not undefined

llvm-svn: 184706

ARM: fix IT decoding

mask == 0 -> UNPRED

llvm-svn: 184702

ARM: enable decoding of pc-relative PLD/PLI

llvm-svn: 184701

ARM: fix thumb literal loads decoding

This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

llvm-svn: 184180

ARM: thumb stores cannot use PC as dest register

llvm-svn: 184179

ARM: fix B decoding

llvm-svn: 183914

ARM: Enforce decoding rules for VLDn instructions

llvm-svn: 183731

ARM: Fix STREX/LDREX reecoding

The decoded MCInst wasn't reencoded as the same instruction

llvm-svn: 183729

ARM: ISB cannot be passed the same options as DMB

ISB should only accepts full system sync, other options are reserved

llvm-svn: 183656

ARM: fix VMOVvnf32 decoding when ambiguous with VCVT

Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

llvm-svn: 183612

ARM: enforce SRS decoding constraints

llvm-svn: 183611

ARM: fix CPS decoding when ambiguous with QADD

Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS de

ARM: fix CPS decoding when ambiguous with QADD

Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

llvm-svn: 183610

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ARM: fix VCVT decoding

UNPRED was reported instead of UNDEF

llvm-svn: 183608

ARM: add fstmx and fldmx instructions for assembly

These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.

Pat

ARM: add fstmx and fldmx instructions for assembly

These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.

Patch by Amaury de la Vieuville.

llvm-svn: 183011

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Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.

llvm-svn: 182680

Remove the Copied parameter from MemoryObject::readBytes.

There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's to

Remove the Copied parameter from MemoryObject::readBytes.

There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.

Defines away PR16132.

llvm-svn: 182636

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Add MCSymbolizer for symbolic/annotated disassembly.

This is a basic first step towards symbolization of disassembled
instructions. This used to be done using externally provided (C API)
callbacks.

Add MCSymbolizer for symbolic/annotated disassembly.

This is a basic first step towards symbolization of disassembled
instructions. This used to be done using externally provided (C API)
callbacks. This patch introduces:
- the MCSymbolizer class, that mimics the same functions that were used
in the X86 and ARM disassemblers to symbolize immediate operands and
to annotate loads based off PC (for things like c string literals).
- the MCExternalSymbolizer class, which implements the old C API.
- the MCRelocationInfo class, which provides a way for targets to
translate relocations (either object::RelocationRef, or disassembler
C API VariantKinds) to MCExprs.
- the MCObjectSymbolizer class, which does symbolization using what it
finds in an object::ObjectFile. This makes simple symbolization (with
no fancy relocation stuff) work for all object formats!
- x86-64 Mach-O and ELF MCRelocationInfos.
- A basic ARM Mach-O MCRelocationInfo, that provides just enough to
support the C API VariantKinds.

Most of what works in otool (the only user of the old symbolization API
that I know of) for x86-64 symbolic disassembly (-tvV) works, namely:
- symbol references: call _foo; jmp 15 <_foo+50>
- relocations: call _foo-_bar; call _foo-4
- __cf?string: leaq 193(%rip), %rax ## literal pool for "hello"
Stub support is the main missing part (because libObject doesn't know,
among other things, about mach-o indirect symbols).

As for the MCSymbolizer API, instead of relying on the disassemblers
to call the tryAdding* methods, maybe this could be done automagically
using InstrInfo? For instance, even though PC-relative LEAs are used
to get the address of string literals in a typical Mach-O file, a MOV
would be used in an ELF file. And right now, the explicit symbolization
only recognizes PC-relative LEAs. InstrInfo should have already have
most of what is needed to know what to symbolize, so this can
definitely be improved.

I'd also like to remove object::RelocationRef::getValueString (it seems
only used by relocation printing in objdump), as simply printing the
created MCExpr is definitely enough (and cleaner than string concats).

llvm-svn: 182625

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VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly wr

VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

llvm-svn: 182281

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Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so sh

Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

llvm-svn: 182279

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