1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 327 const void *Decoder); 328 329 330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 395 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 #include "ARMGenDisassemblerTables.inc" 400 401 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 402 return new ARMDisassembler(STI); 403 } 404 405 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 406 return new ThumbDisassembler(STI); 407 } 408 409 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 410 const MemoryObject &Region, 411 uint64_t Address, 412 raw_ostream &os, 413 raw_ostream &cs) const { 414 CommentStream = &cs; 415 416 uint8_t bytes[4]; 417 418 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 419 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 420 421 // We want to read exactly 4 bytes of data. 422 if (Region.readBytes(Address, 4, bytes) == -1) { 423 Size = 0; 424 return MCDisassembler::Fail; 425 } 426 427 // Encoded as a small-endian 32-bit word in the stream. 428 uint32_t insn = (bytes[3] << 24) | 429 (bytes[2] << 16) | 430 (bytes[1] << 8) | 431 (bytes[0] << 0); 432 433 // Calling the auto-generated decoder function. 434 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 435 Address, this, STI); 436 if (result != MCDisassembler::Fail) { 437 Size = 4; 438 return result; 439 } 440 441 // VFP and NEON instructions, similarly, are shared between ARM 442 // and Thumb modes. 443 MI.clear(); 444 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 445 if (result != MCDisassembler::Fail) { 446 Size = 4; 447 return result; 448 } 449 450 MI.clear(); 451 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 452 this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 // Add a fake predicate operand, because we share these instruction 456 // definitions with Thumb2 where these instructions are predicable. 457 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 458 return MCDisassembler::Fail; 459 return result; 460 } 461 462 MI.clear(); 463 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 464 this, STI); 465 if (result != MCDisassembler::Fail) { 466 Size = 4; 467 // Add a fake predicate operand, because we share these instruction 468 // definitions with Thumb2 where these instructions are predicable. 469 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 470 return MCDisassembler::Fail; 471 return result; 472 } 473 474 MI.clear(); 475 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 476 this, STI); 477 if (result != MCDisassembler::Fail) { 478 Size = 4; 479 // Add a fake predicate operand, because we share these instruction 480 // definitions with Thumb2 where these instructions are predicable. 481 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 482 return MCDisassembler::Fail; 483 return result; 484 } 485 486 MI.clear(); 487 488 Size = 0; 489 return MCDisassembler::Fail; 490 } 491 492 namespace llvm { 493 extern const MCInstrDesc ARMInsts[]; 494 } 495 496 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 497 /// immediate Value in the MCInst. The immediate Value has had any PC 498 /// adjustment made by the caller. If the instruction is a branch instruction 499 /// then isBranch is true, else false. If the getOpInfo() function was set as 500 /// part of the setupForSymbolicDisassembly() call then that function is called 501 /// to get any symbolic information at the Address for this instruction. If 502 /// that returns non-zero then the symbolic information it returns is used to 503 /// create an MCExpr and that is added as an operand to the MCInst. If 504 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 505 /// Value is done and if a symbol is found an MCExpr is created with that, else 506 /// an MCExpr with Value is created. This function returns true if it adds an 507 /// operand to the MCInst and false otherwise. 508 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 509 bool isBranch, uint64_t InstSize, 510 MCInst &MI, const void *Decoder) { 511 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 512 // FIXME: Does it make sense for value to be negative? 513 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 514 /* Offset */ 0, InstSize); 515 } 516 517 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 518 /// referenced by a load instruction with the base register that is the Pc. 519 /// These can often be values in a literal pool near the Address of the 520 /// instruction. The Address of the instruction and its immediate Value are 521 /// used as a possible literal pool entry. The SymbolLookUp call back will 522 /// return the name of a symbol referenced by the literal pool's entry if 523 /// the referenced address is that of a symbol. Or it will return a pointer to 524 /// a literal 'C' string if the referenced address of the literal pool's entry 525 /// is an address into a section with 'C' string literals. 526 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 527 const void *Decoder) { 528 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 529 Dis->tryAddingPcLoadReferenceComment(Value, Address); 530 } 531 532 // Thumb1 instructions don't have explicit S bits. Rather, they 533 // implicitly set CPSR. Since it's not represented in the encoding, the 534 // auto-generated decoder won't inject the CPSR operand. We need to fix 535 // that as a post-pass. 536 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 537 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 538 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 539 MCInst::iterator I = MI.begin(); 540 for (unsigned i = 0; i < NumOps; ++i, ++I) { 541 if (I == MI.end()) break; 542 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 543 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 544 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 545 return; 546 } 547 } 548 549 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 550 } 551 552 // Most Thumb instructions don't have explicit predicates in the 553 // encoding, but rather get their predicates from IT context. We need 554 // to fix up the predicate operands using this context information as a 555 // post-pass. 556 MCDisassembler::DecodeStatus 557 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 558 MCDisassembler::DecodeStatus S = Success; 559 560 // A few instructions actually have predicates encoded in them. Don't 561 // try to overwrite it if we're seeing one of those. 562 switch (MI.getOpcode()) { 563 case ARM::tBcc: 564 case ARM::t2Bcc: 565 case ARM::tCBZ: 566 case ARM::tCBNZ: 567 case ARM::tCPS: 568 case ARM::t2CPS3p: 569 case ARM::t2CPS2p: 570 case ARM::t2CPS1p: 571 case ARM::tMOVSr: 572 case ARM::tSETEND: 573 // Some instructions (mostly conditional branches) are not 574 // allowed in IT blocks. 575 if (ITBlock.instrInITBlock()) 576 S = SoftFail; 577 else 578 return Success; 579 break; 580 case ARM::tB: 581 case ARM::t2B: 582 case ARM::t2TBB: 583 case ARM::t2TBH: 584 // Some instructions (mostly unconditional branches) can 585 // only appears at the end of, or outside of, an IT. 586 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 587 S = SoftFail; 588 break; 589 default: 590 break; 591 } 592 593 // If we're in an IT block, base the predicate on that. Otherwise, 594 // assume a predicate of AL. 595 unsigned CC; 596 CC = ITBlock.getITCC(); 597 if (CC == 0xF) 598 CC = ARMCC::AL; 599 if (ITBlock.instrInITBlock()) 600 ITBlock.advanceITState(); 601 602 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 603 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 604 MCInst::iterator I = MI.begin(); 605 for (unsigned i = 0; i < NumOps; ++i, ++I) { 606 if (I == MI.end()) break; 607 if (OpInfo[i].isPredicate()) { 608 I = MI.insert(I, MCOperand::CreateImm(CC)); 609 ++I; 610 if (CC == ARMCC::AL) 611 MI.insert(I, MCOperand::CreateReg(0)); 612 else 613 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 614 return S; 615 } 616 } 617 618 I = MI.insert(I, MCOperand::CreateImm(CC)); 619 ++I; 620 if (CC == ARMCC::AL) 621 MI.insert(I, MCOperand::CreateReg(0)); 622 else 623 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 624 625 return S; 626 } 627 628 // Thumb VFP instructions are a special case. Because we share their 629 // encodings between ARM and Thumb modes, and they are predicable in ARM 630 // mode, the auto-generated decoder will give them an (incorrect) 631 // predicate operand. We need to rewrite these operands based on the IT 632 // context as a post-pass. 633 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 634 unsigned CC; 635 CC = ITBlock.getITCC(); 636 if (ITBlock.instrInITBlock()) 637 ITBlock.advanceITState(); 638 639 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 640 MCInst::iterator I = MI.begin(); 641 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 642 for (unsigned i = 0; i < NumOps; ++i, ++I) { 643 if (OpInfo[i].isPredicate() ) { 644 I->setImm(CC); 645 ++I; 646 if (CC == ARMCC::AL) 647 I->setReg(0); 648 else 649 I->setReg(ARM::CPSR); 650 return; 651 } 652 } 653 } 654 655 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 656 const MemoryObject &Region, 657 uint64_t Address, 658 raw_ostream &os, 659 raw_ostream &cs) const { 660 CommentStream = &cs; 661 662 uint8_t bytes[4]; 663 664 assert((STI.getFeatureBits() & ARM::ModeThumb) && 665 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 666 667 // We want to read exactly 2 bytes of data. 668 if (Region.readBytes(Address, 2, bytes) == -1) { 669 Size = 0; 670 return MCDisassembler::Fail; 671 } 672 673 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 674 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 675 Address, this, STI); 676 if (result != MCDisassembler::Fail) { 677 Size = 2; 678 Check(result, AddThumbPredicate(MI)); 679 return result; 680 } 681 682 MI.clear(); 683 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 684 Address, this, STI); 685 if (result) { 686 Size = 2; 687 bool InITBlock = ITBlock.instrInITBlock(); 688 Check(result, AddThumbPredicate(MI)); 689 AddThumb1SBit(MI, InITBlock); 690 return result; 691 } 692 693 MI.clear(); 694 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 695 Address, this, STI); 696 if (result != MCDisassembler::Fail) { 697 Size = 2; 698 699 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 700 // the Thumb predicate. 701 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 702 result = MCDisassembler::SoftFail; 703 704 Check(result, AddThumbPredicate(MI)); 705 706 // If we find an IT instruction, we need to parse its condition 707 // code and mask operands so that we can apply them correctly 708 // to the subsequent instructions. 709 if (MI.getOpcode() == ARM::t2IT) { 710 711 unsigned Firstcond = MI.getOperand(0).getImm(); 712 unsigned Mask = MI.getOperand(1).getImm(); 713 ITBlock.setITState(Firstcond, Mask); 714 } 715 716 return result; 717 } 718 719 // We want to read exactly 4 bytes of data. 720 if (Region.readBytes(Address, 4, bytes) == -1) { 721 Size = 0; 722 return MCDisassembler::Fail; 723 } 724 725 uint32_t insn32 = (bytes[3] << 8) | 726 (bytes[2] << 0) | 727 (bytes[1] << 24) | 728 (bytes[0] << 16); 729 MI.clear(); 730 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 731 this, STI); 732 if (result != MCDisassembler::Fail) { 733 Size = 4; 734 bool InITBlock = ITBlock.instrInITBlock(); 735 Check(result, AddThumbPredicate(MI)); 736 AddThumb1SBit(MI, InITBlock); 737 return result; 738 } 739 740 MI.clear(); 741 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 742 this, STI); 743 if (result != MCDisassembler::Fail) { 744 Size = 4; 745 Check(result, AddThumbPredicate(MI)); 746 return result; 747 } 748 749 MI.clear(); 750 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 751 if (result != MCDisassembler::Fail) { 752 Size = 4; 753 UpdateThumbVFPPredicate(MI); 754 return result; 755 } 756 757 MI.clear(); 758 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 759 this, STI); 760 if (result != MCDisassembler::Fail) { 761 Size = 4; 762 Check(result, AddThumbPredicate(MI)); 763 return result; 764 } 765 766 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 767 MI.clear(); 768 uint32_t NEONLdStInsn = insn32; 769 NEONLdStInsn &= 0xF0FFFFFF; 770 NEONLdStInsn |= 0x04000000; 771 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 772 Address, this, STI); 773 if (result != MCDisassembler::Fail) { 774 Size = 4; 775 Check(result, AddThumbPredicate(MI)); 776 return result; 777 } 778 } 779 780 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 781 MI.clear(); 782 uint32_t NEONDataInsn = insn32; 783 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 784 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 785 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 786 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 787 Address, this, STI); 788 if (result != MCDisassembler::Fail) { 789 Size = 4; 790 Check(result, AddThumbPredicate(MI)); 791 return result; 792 } 793 } 794 795 Size = 0; 796 return MCDisassembler::Fail; 797 } 798 799 800 extern "C" void LLVMInitializeARMDisassembler() { 801 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 802 createARMDisassembler); 803 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 804 createThumbDisassembler); 805 } 806 807 static const uint16_t GPRDecoderTable[] = { 808 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 809 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 810 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 811 ARM::R12, ARM::SP, ARM::LR, ARM::PC 812 }; 813 814 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 815 uint64_t Address, const void *Decoder) { 816 if (RegNo > 15) 817 return MCDisassembler::Fail; 818 819 unsigned Register = GPRDecoderTable[RegNo]; 820 Inst.addOperand(MCOperand::CreateReg(Register)); 821 return MCDisassembler::Success; 822 } 823 824 static DecodeStatus 825 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 826 uint64_t Address, const void *Decoder) { 827 DecodeStatus S = MCDisassembler::Success; 828 829 if (RegNo == 15) 830 S = MCDisassembler::SoftFail; 831 832 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 833 834 return S; 835 } 836 837 static DecodeStatus 838 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 839 uint64_t Address, const void *Decoder) { 840 DecodeStatus S = MCDisassembler::Success; 841 842 if (RegNo == 15) 843 { 844 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 845 return MCDisassembler::Success; 846 } 847 848 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 849 return S; 850 } 851 852 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 853 uint64_t Address, const void *Decoder) { 854 if (RegNo > 7) 855 return MCDisassembler::Fail; 856 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 857 } 858 859 static const uint16_t GPRPairDecoderTable[] = { 860 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 861 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 862 }; 863 864 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 865 uint64_t Address, const void *Decoder) { 866 DecodeStatus S = MCDisassembler::Success; 867 868 if (RegNo > 13) 869 return MCDisassembler::Fail; 870 871 if ((RegNo & 1) || RegNo == 0xe) 872 S = MCDisassembler::SoftFail; 873 874 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 875 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 876 return S; 877 } 878 879 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 880 uint64_t Address, const void *Decoder) { 881 unsigned Register = 0; 882 switch (RegNo) { 883 case 0: 884 Register = ARM::R0; 885 break; 886 case 1: 887 Register = ARM::R1; 888 break; 889 case 2: 890 Register = ARM::R2; 891 break; 892 case 3: 893 Register = ARM::R3; 894 break; 895 case 9: 896 Register = ARM::R9; 897 break; 898 case 12: 899 Register = ARM::R12; 900 break; 901 default: 902 return MCDisassembler::Fail; 903 } 904 905 Inst.addOperand(MCOperand::CreateReg(Register)); 906 return MCDisassembler::Success; 907 } 908 909 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 910 uint64_t Address, const void *Decoder) { 911 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 912 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 913 } 914 915 static const uint16_t SPRDecoderTable[] = { 916 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 917 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 918 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 919 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 920 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 921 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 922 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 923 ARM::S28, ARM::S29, ARM::S30, ARM::S31 924 }; 925 926 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 927 uint64_t Address, const void *Decoder) { 928 if (RegNo > 31) 929 return MCDisassembler::Fail; 930 931 unsigned Register = SPRDecoderTable[RegNo]; 932 Inst.addOperand(MCOperand::CreateReg(Register)); 933 return MCDisassembler::Success; 934 } 935 936 static const uint16_t DPRDecoderTable[] = { 937 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 938 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 939 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 940 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 941 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 942 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 943 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 944 ARM::D28, ARM::D29, ARM::D30, ARM::D31 945 }; 946 947 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 948 uint64_t Address, const void *Decoder) { 949 if (RegNo > 31) 950 return MCDisassembler::Fail; 951 952 unsigned Register = DPRDecoderTable[RegNo]; 953 Inst.addOperand(MCOperand::CreateReg(Register)); 954 return MCDisassembler::Success; 955 } 956 957 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 958 uint64_t Address, const void *Decoder) { 959 if (RegNo > 7) 960 return MCDisassembler::Fail; 961 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 962 } 963 964 static DecodeStatus 965 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 966 uint64_t Address, const void *Decoder) { 967 if (RegNo > 15) 968 return MCDisassembler::Fail; 969 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 970 } 971 972 static const uint16_t QPRDecoderTable[] = { 973 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 974 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 975 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 976 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 977 }; 978 979 980 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 981 uint64_t Address, const void *Decoder) { 982 if (RegNo > 31 || (RegNo & 1) != 0) 983 return MCDisassembler::Fail; 984 RegNo >>= 1; 985 986 unsigned Register = QPRDecoderTable[RegNo]; 987 Inst.addOperand(MCOperand::CreateReg(Register)); 988 return MCDisassembler::Success; 989 } 990 991 static const uint16_t DPairDecoderTable[] = { 992 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 993 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 994 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 995 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 996 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 997 ARM::Q15 998 }; 999 1000 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1001 uint64_t Address, const void *Decoder) { 1002 if (RegNo > 30) 1003 return MCDisassembler::Fail; 1004 1005 unsigned Register = DPairDecoderTable[RegNo]; 1006 Inst.addOperand(MCOperand::CreateReg(Register)); 1007 return MCDisassembler::Success; 1008 } 1009 1010 static const uint16_t DPairSpacedDecoderTable[] = { 1011 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1012 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1013 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1014 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1015 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1016 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1017 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1018 ARM::D28_D30, ARM::D29_D31 1019 }; 1020 1021 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1022 unsigned RegNo, 1023 uint64_t Address, 1024 const void *Decoder) { 1025 if (RegNo > 29) 1026 return MCDisassembler::Fail; 1027 1028 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1029 Inst.addOperand(MCOperand::CreateReg(Register)); 1030 return MCDisassembler::Success; 1031 } 1032 1033 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1034 uint64_t Address, const void *Decoder) { 1035 if (Val == 0xF) return MCDisassembler::Fail; 1036 // AL predicate is not allowed on Thumb1 branches. 1037 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1038 return MCDisassembler::Fail; 1039 Inst.addOperand(MCOperand::CreateImm(Val)); 1040 if (Val == ARMCC::AL) { 1041 Inst.addOperand(MCOperand::CreateReg(0)); 1042 } else 1043 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1044 return MCDisassembler::Success; 1045 } 1046 1047 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1048 uint64_t Address, const void *Decoder) { 1049 if (Val) 1050 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1051 else 1052 Inst.addOperand(MCOperand::CreateReg(0)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1057 uint64_t Address, const void *Decoder) { 1058 uint32_t imm = Val & 0xFF; 1059 uint32_t rot = (Val & 0xF00) >> 7; 1060 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1061 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1062 return MCDisassembler::Success; 1063 } 1064 1065 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1066 uint64_t Address, const void *Decoder) { 1067 DecodeStatus S = MCDisassembler::Success; 1068 1069 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1070 unsigned type = fieldFromInstruction(Val, 5, 2); 1071 unsigned imm = fieldFromInstruction(Val, 7, 5); 1072 1073 // Register-immediate 1074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1075 return MCDisassembler::Fail; 1076 1077 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1078 switch (type) { 1079 case 0: 1080 Shift = ARM_AM::lsl; 1081 break; 1082 case 1: 1083 Shift = ARM_AM::lsr; 1084 break; 1085 case 2: 1086 Shift = ARM_AM::asr; 1087 break; 1088 case 3: 1089 Shift = ARM_AM::ror; 1090 break; 1091 } 1092 1093 if (Shift == ARM_AM::ror && imm == 0) 1094 Shift = ARM_AM::rrx; 1095 1096 unsigned Op = Shift | (imm << 3); 1097 Inst.addOperand(MCOperand::CreateImm(Op)); 1098 1099 return S; 1100 } 1101 1102 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1103 uint64_t Address, const void *Decoder) { 1104 DecodeStatus S = MCDisassembler::Success; 1105 1106 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1107 unsigned type = fieldFromInstruction(Val, 5, 2); 1108 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1109 1110 // Register-register 1111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1112 return MCDisassembler::Fail; 1113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1114 return MCDisassembler::Fail; 1115 1116 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1117 switch (type) { 1118 case 0: 1119 Shift = ARM_AM::lsl; 1120 break; 1121 case 1: 1122 Shift = ARM_AM::lsr; 1123 break; 1124 case 2: 1125 Shift = ARM_AM::asr; 1126 break; 1127 case 3: 1128 Shift = ARM_AM::ror; 1129 break; 1130 } 1131 1132 Inst.addOperand(MCOperand::CreateImm(Shift)); 1133 1134 return S; 1135 } 1136 1137 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1138 uint64_t Address, const void *Decoder) { 1139 DecodeStatus S = MCDisassembler::Success; 1140 1141 bool writebackLoad = false; 1142 unsigned writebackReg = 0; 1143 switch (Inst.getOpcode()) { 1144 default: 1145 break; 1146 case ARM::LDMIA_UPD: 1147 case ARM::LDMDB_UPD: 1148 case ARM::LDMIB_UPD: 1149 case ARM::LDMDA_UPD: 1150 case ARM::t2LDMIA_UPD: 1151 case ARM::t2LDMDB_UPD: 1152 writebackLoad = true; 1153 writebackReg = Inst.getOperand(0).getReg(); 1154 break; 1155 } 1156 1157 // Empty register lists are not allowed. 1158 if (Val == 0) return MCDisassembler::Fail; 1159 for (unsigned i = 0; i < 16; ++i) { 1160 if (Val & (1 << i)) { 1161 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1162 return MCDisassembler::Fail; 1163 // Writeback not allowed if Rn is in the target list. 1164 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1165 Check(S, MCDisassembler::SoftFail); 1166 } 1167 } 1168 1169 return S; 1170 } 1171 1172 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1173 uint64_t Address, const void *Decoder) { 1174 DecodeStatus S = MCDisassembler::Success; 1175 1176 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1177 unsigned regs = fieldFromInstruction(Val, 0, 8); 1178 1179 // In case of unpredictable encoding, tweak the operands. 1180 if (regs == 0 || (Vd + regs) > 32) { 1181 regs = Vd + regs > 32 ? 32 - Vd : regs; 1182 regs = std::max( 1u, regs); 1183 S = MCDisassembler::SoftFail; 1184 } 1185 1186 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1187 return MCDisassembler::Fail; 1188 for (unsigned i = 0; i < (regs - 1); ++i) { 1189 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1190 return MCDisassembler::Fail; 1191 } 1192 1193 return S; 1194 } 1195 1196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1197 uint64_t Address, const void *Decoder) { 1198 DecodeStatus S = MCDisassembler::Success; 1199 1200 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1201 unsigned regs = fieldFromInstruction(Val, 1, 7); 1202 1203 // In case of unpredictable encoding, tweak the operands. 1204 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1205 regs = Vd + regs > 32 ? 32 - Vd : regs; 1206 regs = std::max( 1u, regs); 1207 regs = std::min(16u, regs); 1208 S = MCDisassembler::SoftFail; 1209 } 1210 1211 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1212 return MCDisassembler::Fail; 1213 for (unsigned i = 0; i < (regs - 1); ++i) { 1214 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1215 return MCDisassembler::Fail; 1216 } 1217 1218 return S; 1219 } 1220 1221 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1222 uint64_t Address, const void *Decoder) { 1223 // This operand encodes a mask of contiguous zeros between a specified MSB 1224 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1225 // the mask of all bits LSB-and-lower, and then xor them to create 1226 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1227 // create the final mask. 1228 unsigned msb = fieldFromInstruction(Val, 5, 5); 1229 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1230 1231 DecodeStatus S = MCDisassembler::Success; 1232 if (lsb > msb) { 1233 Check(S, MCDisassembler::SoftFail); 1234 // The check above will cause the warning for the "potentially undefined 1235 // instruction encoding" but we can't build a bad MCOperand value here 1236 // with a lsb > msb or else printing the MCInst will cause a crash. 1237 lsb = msb; 1238 } 1239 1240 uint32_t msb_mask = 0xFFFFFFFF; 1241 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1242 uint32_t lsb_mask = (1U << lsb) - 1; 1243 1244 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1245 return S; 1246 } 1247 1248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1249 uint64_t Address, const void *Decoder) { 1250 DecodeStatus S = MCDisassembler::Success; 1251 1252 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1253 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1254 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1255 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1256 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1257 unsigned U = fieldFromInstruction(Insn, 23, 1); 1258 1259 switch (Inst.getOpcode()) { 1260 case ARM::LDC_OFFSET: 1261 case ARM::LDC_PRE: 1262 case ARM::LDC_POST: 1263 case ARM::LDC_OPTION: 1264 case ARM::LDCL_OFFSET: 1265 case ARM::LDCL_PRE: 1266 case ARM::LDCL_POST: 1267 case ARM::LDCL_OPTION: 1268 case ARM::STC_OFFSET: 1269 case ARM::STC_PRE: 1270 case ARM::STC_POST: 1271 case ARM::STC_OPTION: 1272 case ARM::STCL_OFFSET: 1273 case ARM::STCL_PRE: 1274 case ARM::STCL_POST: 1275 case ARM::STCL_OPTION: 1276 case ARM::t2LDC_OFFSET: 1277 case ARM::t2LDC_PRE: 1278 case ARM::t2LDC_POST: 1279 case ARM::t2LDC_OPTION: 1280 case ARM::t2LDCL_OFFSET: 1281 case ARM::t2LDCL_PRE: 1282 case ARM::t2LDCL_POST: 1283 case ARM::t2LDCL_OPTION: 1284 case ARM::t2STC_OFFSET: 1285 case ARM::t2STC_PRE: 1286 case ARM::t2STC_POST: 1287 case ARM::t2STC_OPTION: 1288 case ARM::t2STCL_OFFSET: 1289 case ARM::t2STCL_PRE: 1290 case ARM::t2STCL_POST: 1291 case ARM::t2STCL_OPTION: 1292 if (coproc == 0xA || coproc == 0xB) 1293 return MCDisassembler::Fail; 1294 break; 1295 default: 1296 break; 1297 } 1298 1299 Inst.addOperand(MCOperand::CreateImm(coproc)); 1300 Inst.addOperand(MCOperand::CreateImm(CRd)); 1301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1302 return MCDisassembler::Fail; 1303 1304 switch (Inst.getOpcode()) { 1305 case ARM::t2LDC2_OFFSET: 1306 case ARM::t2LDC2L_OFFSET: 1307 case ARM::t2LDC2_PRE: 1308 case ARM::t2LDC2L_PRE: 1309 case ARM::t2STC2_OFFSET: 1310 case ARM::t2STC2L_OFFSET: 1311 case ARM::t2STC2_PRE: 1312 case ARM::t2STC2L_PRE: 1313 case ARM::LDC2_OFFSET: 1314 case ARM::LDC2L_OFFSET: 1315 case ARM::LDC2_PRE: 1316 case ARM::LDC2L_PRE: 1317 case ARM::STC2_OFFSET: 1318 case ARM::STC2L_OFFSET: 1319 case ARM::STC2_PRE: 1320 case ARM::STC2L_PRE: 1321 case ARM::t2LDC_OFFSET: 1322 case ARM::t2LDCL_OFFSET: 1323 case ARM::t2LDC_PRE: 1324 case ARM::t2LDCL_PRE: 1325 case ARM::t2STC_OFFSET: 1326 case ARM::t2STCL_OFFSET: 1327 case ARM::t2STC_PRE: 1328 case ARM::t2STCL_PRE: 1329 case ARM::LDC_OFFSET: 1330 case ARM::LDCL_OFFSET: 1331 case ARM::LDC_PRE: 1332 case ARM::LDCL_PRE: 1333 case ARM::STC_OFFSET: 1334 case ARM::STCL_OFFSET: 1335 case ARM::STC_PRE: 1336 case ARM::STCL_PRE: 1337 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1338 Inst.addOperand(MCOperand::CreateImm(imm)); 1339 break; 1340 case ARM::t2LDC2_POST: 1341 case ARM::t2LDC2L_POST: 1342 case ARM::t2STC2_POST: 1343 case ARM::t2STC2L_POST: 1344 case ARM::LDC2_POST: 1345 case ARM::LDC2L_POST: 1346 case ARM::STC2_POST: 1347 case ARM::STC2L_POST: 1348 case ARM::t2LDC_POST: 1349 case ARM::t2LDCL_POST: 1350 case ARM::t2STC_POST: 1351 case ARM::t2STCL_POST: 1352 case ARM::LDC_POST: 1353 case ARM::LDCL_POST: 1354 case ARM::STC_POST: 1355 case ARM::STCL_POST: 1356 imm |= U << 8; 1357 // fall through. 1358 default: 1359 // The 'option' variant doesn't encode 'U' in the immediate since 1360 // the immediate is unsigned [0,255]. 1361 Inst.addOperand(MCOperand::CreateImm(imm)); 1362 break; 1363 } 1364 1365 switch (Inst.getOpcode()) { 1366 case ARM::LDC_OFFSET: 1367 case ARM::LDC_PRE: 1368 case ARM::LDC_POST: 1369 case ARM::LDC_OPTION: 1370 case ARM::LDCL_OFFSET: 1371 case ARM::LDCL_PRE: 1372 case ARM::LDCL_POST: 1373 case ARM::LDCL_OPTION: 1374 case ARM::STC_OFFSET: 1375 case ARM::STC_PRE: 1376 case ARM::STC_POST: 1377 case ARM::STC_OPTION: 1378 case ARM::STCL_OFFSET: 1379 case ARM::STCL_PRE: 1380 case ARM::STCL_POST: 1381 case ARM::STCL_OPTION: 1382 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1383 return MCDisassembler::Fail; 1384 break; 1385 default: 1386 break; 1387 } 1388 1389 return S; 1390 } 1391 1392 static DecodeStatus 1393 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1394 uint64_t Address, const void *Decoder) { 1395 DecodeStatus S = MCDisassembler::Success; 1396 1397 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1398 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1399 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1400 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1401 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1402 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1403 unsigned P = fieldFromInstruction(Insn, 24, 1); 1404 unsigned W = fieldFromInstruction(Insn, 21, 1); 1405 1406 // On stores, the writeback operand precedes Rt. 1407 switch (Inst.getOpcode()) { 1408 case ARM::STR_POST_IMM: 1409 case ARM::STR_POST_REG: 1410 case ARM::STRB_POST_IMM: 1411 case ARM::STRB_POST_REG: 1412 case ARM::STRT_POST_REG: 1413 case ARM::STRT_POST_IMM: 1414 case ARM::STRBT_POST_REG: 1415 case ARM::STRBT_POST_IMM: 1416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1417 return MCDisassembler::Fail; 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1424 return MCDisassembler::Fail; 1425 1426 // On loads, the writeback operand comes after Rt. 1427 switch (Inst.getOpcode()) { 1428 case ARM::LDR_POST_IMM: 1429 case ARM::LDR_POST_REG: 1430 case ARM::LDRB_POST_IMM: 1431 case ARM::LDRB_POST_REG: 1432 case ARM::LDRBT_POST_REG: 1433 case ARM::LDRBT_POST_IMM: 1434 case ARM::LDRT_POST_REG: 1435 case ARM::LDRT_POST_IMM: 1436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1437 return MCDisassembler::Fail; 1438 break; 1439 default: 1440 break; 1441 } 1442 1443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1444 return MCDisassembler::Fail; 1445 1446 ARM_AM::AddrOpc Op = ARM_AM::add; 1447 if (!fieldFromInstruction(Insn, 23, 1)) 1448 Op = ARM_AM::sub; 1449 1450 bool writeback = (P == 0) || (W == 1); 1451 unsigned idx_mode = 0; 1452 if (P && writeback) 1453 idx_mode = ARMII::IndexModePre; 1454 else if (!P && writeback) 1455 idx_mode = ARMII::IndexModePost; 1456 1457 if (writeback && (Rn == 15 || Rn == Rt)) 1458 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1459 1460 if (reg) { 1461 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1462 return MCDisassembler::Fail; 1463 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1464 switch( fieldFromInstruction(Insn, 5, 2)) { 1465 case 0: 1466 Opc = ARM_AM::lsl; 1467 break; 1468 case 1: 1469 Opc = ARM_AM::lsr; 1470 break; 1471 case 2: 1472 Opc = ARM_AM::asr; 1473 break; 1474 case 3: 1475 Opc = ARM_AM::ror; 1476 break; 1477 default: 1478 return MCDisassembler::Fail; 1479 } 1480 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1481 if (Opc == ARM_AM::ror && amt == 0) 1482 Opc = ARM_AM::rrx; 1483 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1484 1485 Inst.addOperand(MCOperand::CreateImm(imm)); 1486 } else { 1487 Inst.addOperand(MCOperand::CreateReg(0)); 1488 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1489 Inst.addOperand(MCOperand::CreateImm(tmp)); 1490 } 1491 1492 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1493 return MCDisassembler::Fail; 1494 1495 return S; 1496 } 1497 1498 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1499 uint64_t Address, const void *Decoder) { 1500 DecodeStatus S = MCDisassembler::Success; 1501 1502 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1503 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1504 unsigned type = fieldFromInstruction(Val, 5, 2); 1505 unsigned imm = fieldFromInstruction(Val, 7, 5); 1506 unsigned U = fieldFromInstruction(Val, 12, 1); 1507 1508 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1509 switch (type) { 1510 case 0: 1511 ShOp = ARM_AM::lsl; 1512 break; 1513 case 1: 1514 ShOp = ARM_AM::lsr; 1515 break; 1516 case 2: 1517 ShOp = ARM_AM::asr; 1518 break; 1519 case 3: 1520 ShOp = ARM_AM::ror; 1521 break; 1522 } 1523 1524 if (ShOp == ARM_AM::ror && imm == 0) 1525 ShOp = ARM_AM::rrx; 1526 1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1528 return MCDisassembler::Fail; 1529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1530 return MCDisassembler::Fail; 1531 unsigned shift; 1532 if (U) 1533 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1534 else 1535 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1536 Inst.addOperand(MCOperand::CreateImm(shift)); 1537 1538 return S; 1539 } 1540 1541 static DecodeStatus 1542 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1543 uint64_t Address, const void *Decoder) { 1544 DecodeStatus S = MCDisassembler::Success; 1545 1546 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1547 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1548 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1549 unsigned type = fieldFromInstruction(Insn, 22, 1); 1550 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1551 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1552 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1553 unsigned W = fieldFromInstruction(Insn, 21, 1); 1554 unsigned P = fieldFromInstruction(Insn, 24, 1); 1555 unsigned Rt2 = Rt + 1; 1556 1557 bool writeback = (W == 1) | (P == 0); 1558 1559 // For {LD,ST}RD, Rt must be even, else undefined. 1560 switch (Inst.getOpcode()) { 1561 case ARM::STRD: 1562 case ARM::STRD_PRE: 1563 case ARM::STRD_POST: 1564 case ARM::LDRD: 1565 case ARM::LDRD_PRE: 1566 case ARM::LDRD_POST: 1567 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1568 break; 1569 default: 1570 break; 1571 } 1572 switch (Inst.getOpcode()) { 1573 case ARM::STRD: 1574 case ARM::STRD_PRE: 1575 case ARM::STRD_POST: 1576 if (P == 0 && W == 1) 1577 S = MCDisassembler::SoftFail; 1578 1579 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1580 S = MCDisassembler::SoftFail; 1581 if (type && Rm == 15) 1582 S = MCDisassembler::SoftFail; 1583 if (Rt2 == 15) 1584 S = MCDisassembler::SoftFail; 1585 if (!type && fieldFromInstruction(Insn, 8, 4)) 1586 S = MCDisassembler::SoftFail; 1587 break; 1588 case ARM::STRH: 1589 case ARM::STRH_PRE: 1590 case ARM::STRH_POST: 1591 if (Rt == 15) 1592 S = MCDisassembler::SoftFail; 1593 if (writeback && (Rn == 15 || Rn == Rt)) 1594 S = MCDisassembler::SoftFail; 1595 if (!type && Rm == 15) 1596 S = MCDisassembler::SoftFail; 1597 break; 1598 case ARM::LDRD: 1599 case ARM::LDRD_PRE: 1600 case ARM::LDRD_POST: 1601 if (type && Rn == 15){ 1602 if (Rt2 == 15) 1603 S = MCDisassembler::SoftFail; 1604 break; 1605 } 1606 if (P == 0 && W == 1) 1607 S = MCDisassembler::SoftFail; 1608 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1609 S = MCDisassembler::SoftFail; 1610 if (!type && writeback && Rn == 15) 1611 S = MCDisassembler::SoftFail; 1612 if (writeback && (Rn == Rt || Rn == Rt2)) 1613 S = MCDisassembler::SoftFail; 1614 break; 1615 case ARM::LDRH: 1616 case ARM::LDRH_PRE: 1617 case ARM::LDRH_POST: 1618 if (type && Rn == 15){ 1619 if (Rt == 15) 1620 S = MCDisassembler::SoftFail; 1621 break; 1622 } 1623 if (Rt == 15) 1624 S = MCDisassembler::SoftFail; 1625 if (!type && Rm == 15) 1626 S = MCDisassembler::SoftFail; 1627 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1628 S = MCDisassembler::SoftFail; 1629 break; 1630 case ARM::LDRSH: 1631 case ARM::LDRSH_PRE: 1632 case ARM::LDRSH_POST: 1633 case ARM::LDRSB: 1634 case ARM::LDRSB_PRE: 1635 case ARM::LDRSB_POST: 1636 if (type && Rn == 15){ 1637 if (Rt == 15) 1638 S = MCDisassembler::SoftFail; 1639 break; 1640 } 1641 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1642 S = MCDisassembler::SoftFail; 1643 if (!type && (Rt == 15 || Rm == 15)) 1644 S = MCDisassembler::SoftFail; 1645 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1646 S = MCDisassembler::SoftFail; 1647 break; 1648 default: 1649 break; 1650 } 1651 1652 if (writeback) { // Writeback 1653 if (P) 1654 U |= ARMII::IndexModePre << 9; 1655 else 1656 U |= ARMII::IndexModePost << 9; 1657 1658 // On stores, the writeback operand precedes Rt. 1659 switch (Inst.getOpcode()) { 1660 case ARM::STRD: 1661 case ARM::STRD_PRE: 1662 case ARM::STRD_POST: 1663 case ARM::STRH: 1664 case ARM::STRH_PRE: 1665 case ARM::STRH_POST: 1666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1667 return MCDisassembler::Fail; 1668 break; 1669 default: 1670 break; 1671 } 1672 } 1673 1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1675 return MCDisassembler::Fail; 1676 switch (Inst.getOpcode()) { 1677 case ARM::STRD: 1678 case ARM::STRD_PRE: 1679 case ARM::STRD_POST: 1680 case ARM::LDRD: 1681 case ARM::LDRD_PRE: 1682 case ARM::LDRD_POST: 1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1684 return MCDisassembler::Fail; 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 if (writeback) { 1691 // On loads, the writeback operand comes after Rt. 1692 switch (Inst.getOpcode()) { 1693 case ARM::LDRD: 1694 case ARM::LDRD_PRE: 1695 case ARM::LDRD_POST: 1696 case ARM::LDRH: 1697 case ARM::LDRH_PRE: 1698 case ARM::LDRH_POST: 1699 case ARM::LDRSH: 1700 case ARM::LDRSH_PRE: 1701 case ARM::LDRSH_POST: 1702 case ARM::LDRSB: 1703 case ARM::LDRSB_PRE: 1704 case ARM::LDRSB_POST: 1705 case ARM::LDRHTr: 1706 case ARM::LDRSBTr: 1707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1708 return MCDisassembler::Fail; 1709 break; 1710 default: 1711 break; 1712 } 1713 } 1714 1715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1716 return MCDisassembler::Fail; 1717 1718 if (type) { 1719 Inst.addOperand(MCOperand::CreateReg(0)); 1720 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1721 } else { 1722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1723 return MCDisassembler::Fail; 1724 Inst.addOperand(MCOperand::CreateImm(U)); 1725 } 1726 1727 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1728 return MCDisassembler::Fail; 1729 1730 return S; 1731 } 1732 1733 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1734 uint64_t Address, const void *Decoder) { 1735 DecodeStatus S = MCDisassembler::Success; 1736 1737 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1738 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1739 1740 switch (mode) { 1741 case 0: 1742 mode = ARM_AM::da; 1743 break; 1744 case 1: 1745 mode = ARM_AM::ia; 1746 break; 1747 case 2: 1748 mode = ARM_AM::db; 1749 break; 1750 case 3: 1751 mode = ARM_AM::ib; 1752 break; 1753 } 1754 1755 Inst.addOperand(MCOperand::CreateImm(mode)); 1756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1757 return MCDisassembler::Fail; 1758 1759 return S; 1760 } 1761 1762 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1763 uint64_t Address, const void *Decoder) { 1764 DecodeStatus S = MCDisassembler::Success; 1765 1766 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1767 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1769 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1770 1771 if (pred == 0xF) 1772 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1773 1774 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1775 return MCDisassembler::Fail; 1776 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1777 return MCDisassembler::Fail; 1778 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1779 return MCDisassembler::Fail; 1780 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1781 return MCDisassembler::Fail; 1782 return S; 1783 } 1784 1785 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1786 unsigned Insn, 1787 uint64_t Address, const void *Decoder) { 1788 DecodeStatus S = MCDisassembler::Success; 1789 1790 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1791 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1792 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1793 1794 if (pred == 0xF) { 1795 // Ambiguous with RFE and SRS 1796 switch (Inst.getOpcode()) { 1797 case ARM::LDMDA: 1798 Inst.setOpcode(ARM::RFEDA); 1799 break; 1800 case ARM::LDMDA_UPD: 1801 Inst.setOpcode(ARM::RFEDA_UPD); 1802 break; 1803 case ARM::LDMDB: 1804 Inst.setOpcode(ARM::RFEDB); 1805 break; 1806 case ARM::LDMDB_UPD: 1807 Inst.setOpcode(ARM::RFEDB_UPD); 1808 break; 1809 case ARM::LDMIA: 1810 Inst.setOpcode(ARM::RFEIA); 1811 break; 1812 case ARM::LDMIA_UPD: 1813 Inst.setOpcode(ARM::RFEIA_UPD); 1814 break; 1815 case ARM::LDMIB: 1816 Inst.setOpcode(ARM::RFEIB); 1817 break; 1818 case ARM::LDMIB_UPD: 1819 Inst.setOpcode(ARM::RFEIB_UPD); 1820 break; 1821 case ARM::STMDA: 1822 Inst.setOpcode(ARM::SRSDA); 1823 break; 1824 case ARM::STMDA_UPD: 1825 Inst.setOpcode(ARM::SRSDA_UPD); 1826 break; 1827 case ARM::STMDB: 1828 Inst.setOpcode(ARM::SRSDB); 1829 break; 1830 case ARM::STMDB_UPD: 1831 Inst.setOpcode(ARM::SRSDB_UPD); 1832 break; 1833 case ARM::STMIA: 1834 Inst.setOpcode(ARM::SRSIA); 1835 break; 1836 case ARM::STMIA_UPD: 1837 Inst.setOpcode(ARM::SRSIA_UPD); 1838 break; 1839 case ARM::STMIB: 1840 Inst.setOpcode(ARM::SRSIB); 1841 break; 1842 case ARM::STMIB_UPD: 1843 Inst.setOpcode(ARM::SRSIB_UPD); 1844 break; 1845 default: 1846 return MCDisassembler::Fail; 1847 } 1848 1849 // For stores (which become SRS's, the only operand is the mode. 1850 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1851 // Check SRS encoding constraints 1852 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1853 fieldFromInstruction(Insn, 20, 1) == 0)) 1854 return MCDisassembler::Fail; 1855 1856 Inst.addOperand( 1857 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1858 return S; 1859 } 1860 1861 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1862 } 1863 1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1865 return MCDisassembler::Fail; 1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1867 return MCDisassembler::Fail; // Tied 1868 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1869 return MCDisassembler::Fail; 1870 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1871 return MCDisassembler::Fail; 1872 1873 return S; 1874 } 1875 1876 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1877 uint64_t Address, const void *Decoder) { 1878 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1879 unsigned M = fieldFromInstruction(Insn, 17, 1); 1880 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1881 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1882 1883 DecodeStatus S = MCDisassembler::Success; 1884 1885 // This decoder is called from multiple location that do not check 1886 // the full encoding is valid before they do. 1887 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1888 fieldFromInstruction(Insn, 16, 1) != 0 || 1889 fieldFromInstruction(Insn, 20, 8) != 0x10) 1890 return MCDisassembler::Fail; 1891 1892 // imod == '01' --> UNPREDICTABLE 1893 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1894 // return failure here. The '01' imod value is unprintable, so there's 1895 // nothing useful we could do even if we returned UNPREDICTABLE. 1896 1897 if (imod == 1) return MCDisassembler::Fail; 1898 1899 if (imod && M) { 1900 Inst.setOpcode(ARM::CPS3p); 1901 Inst.addOperand(MCOperand::CreateImm(imod)); 1902 Inst.addOperand(MCOperand::CreateImm(iflags)); 1903 Inst.addOperand(MCOperand::CreateImm(mode)); 1904 } else if (imod && !M) { 1905 Inst.setOpcode(ARM::CPS2p); 1906 Inst.addOperand(MCOperand::CreateImm(imod)); 1907 Inst.addOperand(MCOperand::CreateImm(iflags)); 1908 if (mode) S = MCDisassembler::SoftFail; 1909 } else if (!imod && M) { 1910 Inst.setOpcode(ARM::CPS1p); 1911 Inst.addOperand(MCOperand::CreateImm(mode)); 1912 if (iflags) S = MCDisassembler::SoftFail; 1913 } else { 1914 // imod == '00' && M == '0' --> UNPREDICTABLE 1915 Inst.setOpcode(ARM::CPS1p); 1916 Inst.addOperand(MCOperand::CreateImm(mode)); 1917 S = MCDisassembler::SoftFail; 1918 } 1919 1920 return S; 1921 } 1922 1923 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1924 uint64_t Address, const void *Decoder) { 1925 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1926 unsigned M = fieldFromInstruction(Insn, 8, 1); 1927 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1928 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1929 1930 DecodeStatus S = MCDisassembler::Success; 1931 1932 // imod == '01' --> UNPREDICTABLE 1933 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1934 // return failure here. The '01' imod value is unprintable, so there's 1935 // nothing useful we could do even if we returned UNPREDICTABLE. 1936 1937 if (imod == 1) return MCDisassembler::Fail; 1938 1939 if (imod && M) { 1940 Inst.setOpcode(ARM::t2CPS3p); 1941 Inst.addOperand(MCOperand::CreateImm(imod)); 1942 Inst.addOperand(MCOperand::CreateImm(iflags)); 1943 Inst.addOperand(MCOperand::CreateImm(mode)); 1944 } else if (imod && !M) { 1945 Inst.setOpcode(ARM::t2CPS2p); 1946 Inst.addOperand(MCOperand::CreateImm(imod)); 1947 Inst.addOperand(MCOperand::CreateImm(iflags)); 1948 if (mode) S = MCDisassembler::SoftFail; 1949 } else if (!imod && M) { 1950 Inst.setOpcode(ARM::t2CPS1p); 1951 Inst.addOperand(MCOperand::CreateImm(mode)); 1952 if (iflags) S = MCDisassembler::SoftFail; 1953 } else { 1954 // imod == '00' && M == '0' --> this is a HINT instruction 1955 int imm = fieldFromInstruction(Insn, 0, 8); 1956 // HINT are defined only for immediate in [0..4] 1957 if(imm > 4) return MCDisassembler::Fail; 1958 Inst.setOpcode(ARM::t2HINT); 1959 Inst.addOperand(MCOperand::CreateImm(imm)); 1960 } 1961 1962 return S; 1963 } 1964 1965 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 DecodeStatus S = MCDisassembler::Success; 1968 1969 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1970 unsigned imm = 0; 1971 1972 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1973 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1974 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1975 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1976 1977 if (Inst.getOpcode() == ARM::t2MOVTi16) 1978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 1983 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1984 Inst.addOperand(MCOperand::CreateImm(imm)); 1985 1986 return S; 1987 } 1988 1989 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1990 uint64_t Address, const void *Decoder) { 1991 DecodeStatus S = MCDisassembler::Success; 1992 1993 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1994 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1995 unsigned imm = 0; 1996 1997 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 1998 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1999 2000 if (Inst.getOpcode() == ARM::MOVTi16) 2001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2002 return MCDisassembler::Fail; 2003 2004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2005 return MCDisassembler::Fail; 2006 2007 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2008 Inst.addOperand(MCOperand::CreateImm(imm)); 2009 2010 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2011 return MCDisassembler::Fail; 2012 2013 return S; 2014 } 2015 2016 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2017 uint64_t Address, const void *Decoder) { 2018 DecodeStatus S = MCDisassembler::Success; 2019 2020 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2021 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2022 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2023 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2024 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2025 2026 if (pred == 0xF) 2027 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2028 2029 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2030 return MCDisassembler::Fail; 2031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2032 return MCDisassembler::Fail; 2033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2036 return MCDisassembler::Fail; 2037 2038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 2041 return S; 2042 } 2043 2044 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2045 uint64_t Address, const void *Decoder) { 2046 DecodeStatus S = MCDisassembler::Success; 2047 2048 unsigned add = fieldFromInstruction(Val, 12, 1); 2049 unsigned imm = fieldFromInstruction(Val, 0, 12); 2050 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2051 2052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2053 return MCDisassembler::Fail; 2054 2055 if (!add) imm *= -1; 2056 if (imm == 0 && !add) imm = INT32_MIN; 2057 Inst.addOperand(MCOperand::CreateImm(imm)); 2058 if (Rn == 15) 2059 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2060 2061 return S; 2062 } 2063 2064 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2065 uint64_t Address, const void *Decoder) { 2066 DecodeStatus S = MCDisassembler::Success; 2067 2068 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2069 unsigned U = fieldFromInstruction(Val, 8, 1); 2070 unsigned imm = fieldFromInstruction(Val, 0, 8); 2071 2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2073 return MCDisassembler::Fail; 2074 2075 if (U) 2076 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2077 else 2078 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2079 2080 return S; 2081 } 2082 2083 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2084 uint64_t Address, const void *Decoder) { 2085 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2086 } 2087 2088 static DecodeStatus 2089 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2090 uint64_t Address, const void *Decoder) { 2091 DecodeStatus Status = MCDisassembler::Success; 2092 2093 // Note the J1 and J2 values are from the encoded instruction. So here 2094 // change them to I1 and I2 values via as documented: 2095 // I1 = NOT(J1 EOR S); 2096 // I2 = NOT(J2 EOR S); 2097 // and build the imm32 with one trailing zero as documented: 2098 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2099 unsigned S = fieldFromInstruction(Insn, 26, 1); 2100 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2101 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2102 unsigned I1 = !(J1 ^ S); 2103 unsigned I2 = !(J2 ^ S); 2104 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2105 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2106 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2107 int imm32 = SignExtend32<24>(tmp << 1); 2108 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2109 true, 4, Inst, Decoder)) 2110 Inst.addOperand(MCOperand::CreateImm(imm32)); 2111 2112 return Status; 2113 } 2114 2115 static DecodeStatus 2116 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2117 uint64_t Address, const void *Decoder) { 2118 DecodeStatus S = MCDisassembler::Success; 2119 2120 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2121 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2122 2123 if (pred == 0xF) { 2124 Inst.setOpcode(ARM::BLXi); 2125 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2126 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2127 true, 4, Inst, Decoder)) 2128 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2129 return S; 2130 } 2131 2132 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2133 true, 4, Inst, Decoder)) 2134 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2135 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 2138 return S; 2139 } 2140 2141 2142 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2143 uint64_t Address, const void *Decoder) { 2144 DecodeStatus S = MCDisassembler::Success; 2145 2146 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2147 unsigned align = fieldFromInstruction(Val, 4, 2); 2148 2149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2150 return MCDisassembler::Fail; 2151 if (!align) 2152 Inst.addOperand(MCOperand::CreateImm(0)); 2153 else 2154 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2155 2156 return S; 2157 } 2158 2159 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2160 uint64_t Address, const void *Decoder) { 2161 DecodeStatus S = MCDisassembler::Success; 2162 2163 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2164 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2165 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2166 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2167 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2168 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2169 2170 // First output register 2171 switch (Inst.getOpcode()) { 2172 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2173 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2174 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2175 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2176 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2177 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2178 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2179 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2180 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2181 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2182 return MCDisassembler::Fail; 2183 break; 2184 case ARM::VLD2b16: 2185 case ARM::VLD2b32: 2186 case ARM::VLD2b8: 2187 case ARM::VLD2b16wb_fixed: 2188 case ARM::VLD2b16wb_register: 2189 case ARM::VLD2b32wb_fixed: 2190 case ARM::VLD2b32wb_register: 2191 case ARM::VLD2b8wb_fixed: 2192 case ARM::VLD2b8wb_register: 2193 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2194 return MCDisassembler::Fail; 2195 break; 2196 default: 2197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 } 2200 2201 // Second output register 2202 switch (Inst.getOpcode()) { 2203 case ARM::VLD3d8: 2204 case ARM::VLD3d16: 2205 case ARM::VLD3d32: 2206 case ARM::VLD3d8_UPD: 2207 case ARM::VLD3d16_UPD: 2208 case ARM::VLD3d32_UPD: 2209 case ARM::VLD4d8: 2210 case ARM::VLD4d16: 2211 case ARM::VLD4d32: 2212 case ARM::VLD4d8_UPD: 2213 case ARM::VLD4d16_UPD: 2214 case ARM::VLD4d32_UPD: 2215 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2216 return MCDisassembler::Fail; 2217 break; 2218 case ARM::VLD3q8: 2219 case ARM::VLD3q16: 2220 case ARM::VLD3q32: 2221 case ARM::VLD3q8_UPD: 2222 case ARM::VLD3q16_UPD: 2223 case ARM::VLD3q32_UPD: 2224 case ARM::VLD4q8: 2225 case ARM::VLD4q16: 2226 case ARM::VLD4q32: 2227 case ARM::VLD4q8_UPD: 2228 case ARM::VLD4q16_UPD: 2229 case ARM::VLD4q32_UPD: 2230 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2231 return MCDisassembler::Fail; 2232 default: 2233 break; 2234 } 2235 2236 // Third output register 2237 switch(Inst.getOpcode()) { 2238 case ARM::VLD3d8: 2239 case ARM::VLD3d16: 2240 case ARM::VLD3d32: 2241 case ARM::VLD3d8_UPD: 2242 case ARM::VLD3d16_UPD: 2243 case ARM::VLD3d32_UPD: 2244 case ARM::VLD4d8: 2245 case ARM::VLD4d16: 2246 case ARM::VLD4d32: 2247 case ARM::VLD4d8_UPD: 2248 case ARM::VLD4d16_UPD: 2249 case ARM::VLD4d32_UPD: 2250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 break; 2253 case ARM::VLD3q8: 2254 case ARM::VLD3q16: 2255 case ARM::VLD3q32: 2256 case ARM::VLD3q8_UPD: 2257 case ARM::VLD3q16_UPD: 2258 case ARM::VLD3q32_UPD: 2259 case ARM::VLD4q8: 2260 case ARM::VLD4q16: 2261 case ARM::VLD4q32: 2262 case ARM::VLD4q8_UPD: 2263 case ARM::VLD4q16_UPD: 2264 case ARM::VLD4q32_UPD: 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 break; 2268 default: 2269 break; 2270 } 2271 2272 // Fourth output register 2273 switch (Inst.getOpcode()) { 2274 case ARM::VLD4d8: 2275 case ARM::VLD4d16: 2276 case ARM::VLD4d32: 2277 case ARM::VLD4d8_UPD: 2278 case ARM::VLD4d16_UPD: 2279 case ARM::VLD4d32_UPD: 2280 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2281 return MCDisassembler::Fail; 2282 break; 2283 case ARM::VLD4q8: 2284 case ARM::VLD4q16: 2285 case ARM::VLD4q32: 2286 case ARM::VLD4q8_UPD: 2287 case ARM::VLD4q16_UPD: 2288 case ARM::VLD4q32_UPD: 2289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2290 return MCDisassembler::Fail; 2291 break; 2292 default: 2293 break; 2294 } 2295 2296 // Writeback operand 2297 switch (Inst.getOpcode()) { 2298 case ARM::VLD1d8wb_fixed: 2299 case ARM::VLD1d16wb_fixed: 2300 case ARM::VLD1d32wb_fixed: 2301 case ARM::VLD1d64wb_fixed: 2302 case ARM::VLD1d8wb_register: 2303 case ARM::VLD1d16wb_register: 2304 case ARM::VLD1d32wb_register: 2305 case ARM::VLD1d64wb_register: 2306 case ARM::VLD1q8wb_fixed: 2307 case ARM::VLD1q16wb_fixed: 2308 case ARM::VLD1q32wb_fixed: 2309 case ARM::VLD1q64wb_fixed: 2310 case ARM::VLD1q8wb_register: 2311 case ARM::VLD1q16wb_register: 2312 case ARM::VLD1q32wb_register: 2313 case ARM::VLD1q64wb_register: 2314 case ARM::VLD1d8Twb_fixed: 2315 case ARM::VLD1d8Twb_register: 2316 case ARM::VLD1d16Twb_fixed: 2317 case ARM::VLD1d16Twb_register: 2318 case ARM::VLD1d32Twb_fixed: 2319 case ARM::VLD1d32Twb_register: 2320 case ARM::VLD1d64Twb_fixed: 2321 case ARM::VLD1d64Twb_register: 2322 case ARM::VLD1d8Qwb_fixed: 2323 case ARM::VLD1d8Qwb_register: 2324 case ARM::VLD1d16Qwb_fixed: 2325 case ARM::VLD1d16Qwb_register: 2326 case ARM::VLD1d32Qwb_fixed: 2327 case ARM::VLD1d32Qwb_register: 2328 case ARM::VLD1d64Qwb_fixed: 2329 case ARM::VLD1d64Qwb_register: 2330 case ARM::VLD2d8wb_fixed: 2331 case ARM::VLD2d16wb_fixed: 2332 case ARM::VLD2d32wb_fixed: 2333 case ARM::VLD2q8wb_fixed: 2334 case ARM::VLD2q16wb_fixed: 2335 case ARM::VLD2q32wb_fixed: 2336 case ARM::VLD2d8wb_register: 2337 case ARM::VLD2d16wb_register: 2338 case ARM::VLD2d32wb_register: 2339 case ARM::VLD2q8wb_register: 2340 case ARM::VLD2q16wb_register: 2341 case ARM::VLD2q32wb_register: 2342 case ARM::VLD2b8wb_fixed: 2343 case ARM::VLD2b16wb_fixed: 2344 case ARM::VLD2b32wb_fixed: 2345 case ARM::VLD2b8wb_register: 2346 case ARM::VLD2b16wb_register: 2347 case ARM::VLD2b32wb_register: 2348 Inst.addOperand(MCOperand::CreateImm(0)); 2349 break; 2350 case ARM::VLD3d8_UPD: 2351 case ARM::VLD3d16_UPD: 2352 case ARM::VLD3d32_UPD: 2353 case ARM::VLD3q8_UPD: 2354 case ARM::VLD3q16_UPD: 2355 case ARM::VLD3q32_UPD: 2356 case ARM::VLD4d8_UPD: 2357 case ARM::VLD4d16_UPD: 2358 case ARM::VLD4d32_UPD: 2359 case ARM::VLD4q8_UPD: 2360 case ARM::VLD4q16_UPD: 2361 case ARM::VLD4q32_UPD: 2362 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2363 return MCDisassembler::Fail; 2364 break; 2365 default: 2366 break; 2367 } 2368 2369 // AddrMode6 Base (register+alignment) 2370 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2371 return MCDisassembler::Fail; 2372 2373 // AddrMode6 Offset (register) 2374 switch (Inst.getOpcode()) { 2375 default: 2376 // The below have been updated to have explicit am6offset split 2377 // between fixed and register offset. For those instructions not 2378 // yet updated, we need to add an additional reg0 operand for the 2379 // fixed variant. 2380 // 2381 // The fixed offset encodes as Rm == 0xd, so we check for that. 2382 if (Rm == 0xd) { 2383 Inst.addOperand(MCOperand::CreateReg(0)); 2384 break; 2385 } 2386 // Fall through to handle the register offset variant. 2387 case ARM::VLD1d8wb_fixed: 2388 case ARM::VLD1d16wb_fixed: 2389 case ARM::VLD1d32wb_fixed: 2390 case ARM::VLD1d64wb_fixed: 2391 case ARM::VLD1d8Twb_fixed: 2392 case ARM::VLD1d16Twb_fixed: 2393 case ARM::VLD1d32Twb_fixed: 2394 case ARM::VLD1d64Twb_fixed: 2395 case ARM::VLD1d8Qwb_fixed: 2396 case ARM::VLD1d16Qwb_fixed: 2397 case ARM::VLD1d32Qwb_fixed: 2398 case ARM::VLD1d64Qwb_fixed: 2399 case ARM::VLD1d8wb_register: 2400 case ARM::VLD1d16wb_register: 2401 case ARM::VLD1d32wb_register: 2402 case ARM::VLD1d64wb_register: 2403 case ARM::VLD1q8wb_fixed: 2404 case ARM::VLD1q16wb_fixed: 2405 case ARM::VLD1q32wb_fixed: 2406 case ARM::VLD1q64wb_fixed: 2407 case ARM::VLD1q8wb_register: 2408 case ARM::VLD1q16wb_register: 2409 case ARM::VLD1q32wb_register: 2410 case ARM::VLD1q64wb_register: 2411 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2412 // variant encodes Rm == 0xf. Anything else is a register offset post- 2413 // increment and we need to add the register operand to the instruction. 2414 if (Rm != 0xD && Rm != 0xF && 2415 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 break; 2418 case ARM::VLD2d8wb_fixed: 2419 case ARM::VLD2d16wb_fixed: 2420 case ARM::VLD2d32wb_fixed: 2421 case ARM::VLD2b8wb_fixed: 2422 case ARM::VLD2b16wb_fixed: 2423 case ARM::VLD2b32wb_fixed: 2424 case ARM::VLD2q8wb_fixed: 2425 case ARM::VLD2q16wb_fixed: 2426 case ARM::VLD2q32wb_fixed: 2427 break; 2428 } 2429 2430 return S; 2431 } 2432 2433 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn, 2434 uint64_t Addr, const void* Decoder) { 2435 unsigned type = fieldFromInstruction(Insn, 8, 4); 2436 unsigned align = fieldFromInstruction(Insn, 4, 2); 2437 if(type == 7 && (align & 2)) return MCDisassembler::Fail; 2438 if(type == 10 && align == 3) return MCDisassembler::Fail; 2439 if(type == 6 && (align & 2)) return MCDisassembler::Fail; 2440 2441 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2442 } 2443 2444 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn, 2445 uint64_t Addr, const void* Decoder) { 2446 unsigned size = fieldFromInstruction(Insn, 6, 2); 2447 if(size == 3) return MCDisassembler::Fail; 2448 2449 unsigned type = fieldFromInstruction(Insn, 8, 4); 2450 unsigned align = fieldFromInstruction(Insn, 4, 2); 2451 if(type == 8 && align == 3) return MCDisassembler::Fail; 2452 if(type == 9 && align == 3) return MCDisassembler::Fail; 2453 2454 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2455 } 2456 2457 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn, 2458 uint64_t Addr, const void* Decoder) { 2459 unsigned size = fieldFromInstruction(Insn, 6, 2); 2460 if(size == 3) return MCDisassembler::Fail; 2461 2462 unsigned align = fieldFromInstruction(Insn, 4, 2); 2463 if(align & 2) return MCDisassembler::Fail; 2464 2465 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2466 } 2467 2468 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn, 2469 uint64_t Addr, const void* Decoder) { 2470 unsigned size = fieldFromInstruction(Insn, 6, 2); 2471 if(size == 3) return MCDisassembler::Fail; 2472 2473 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2474 } 2475 2476 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2477 uint64_t Address, const void *Decoder) { 2478 DecodeStatus S = MCDisassembler::Success; 2479 2480 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2481 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2482 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2483 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2484 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2485 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2486 2487 // Writeback Operand 2488 switch (Inst.getOpcode()) { 2489 case ARM::VST1d8wb_fixed: 2490 case ARM::VST1d16wb_fixed: 2491 case ARM::VST1d32wb_fixed: 2492 case ARM::VST1d64wb_fixed: 2493 case ARM::VST1d8wb_register: 2494 case ARM::VST1d16wb_register: 2495 case ARM::VST1d32wb_register: 2496 case ARM::VST1d64wb_register: 2497 case ARM::VST1q8wb_fixed: 2498 case ARM::VST1q16wb_fixed: 2499 case ARM::VST1q32wb_fixed: 2500 case ARM::VST1q64wb_fixed: 2501 case ARM::VST1q8wb_register: 2502 case ARM::VST1q16wb_register: 2503 case ARM::VST1q32wb_register: 2504 case ARM::VST1q64wb_register: 2505 case ARM::VST1d8Twb_fixed: 2506 case ARM::VST1d16Twb_fixed: 2507 case ARM::VST1d32Twb_fixed: 2508 case ARM::VST1d64Twb_fixed: 2509 case ARM::VST1d8Twb_register: 2510 case ARM::VST1d16Twb_register: 2511 case ARM::VST1d32Twb_register: 2512 case ARM::VST1d64Twb_register: 2513 case ARM::VST1d8Qwb_fixed: 2514 case ARM::VST1d16Qwb_fixed: 2515 case ARM::VST1d32Qwb_fixed: 2516 case ARM::VST1d64Qwb_fixed: 2517 case ARM::VST1d8Qwb_register: 2518 case ARM::VST1d16Qwb_register: 2519 case ARM::VST1d32Qwb_register: 2520 case ARM::VST1d64Qwb_register: 2521 case ARM::VST2d8wb_fixed: 2522 case ARM::VST2d16wb_fixed: 2523 case ARM::VST2d32wb_fixed: 2524 case ARM::VST2d8wb_register: 2525 case ARM::VST2d16wb_register: 2526 case ARM::VST2d32wb_register: 2527 case ARM::VST2q8wb_fixed: 2528 case ARM::VST2q16wb_fixed: 2529 case ARM::VST2q32wb_fixed: 2530 case ARM::VST2q8wb_register: 2531 case ARM::VST2q16wb_register: 2532 case ARM::VST2q32wb_register: 2533 case ARM::VST2b8wb_fixed: 2534 case ARM::VST2b16wb_fixed: 2535 case ARM::VST2b32wb_fixed: 2536 case ARM::VST2b8wb_register: 2537 case ARM::VST2b16wb_register: 2538 case ARM::VST2b32wb_register: 2539 if (Rm == 0xF) 2540 return MCDisassembler::Fail; 2541 Inst.addOperand(MCOperand::CreateImm(0)); 2542 break; 2543 case ARM::VST3d8_UPD: 2544 case ARM::VST3d16_UPD: 2545 case ARM::VST3d32_UPD: 2546 case ARM::VST3q8_UPD: 2547 case ARM::VST3q16_UPD: 2548 case ARM::VST3q32_UPD: 2549 case ARM::VST4d8_UPD: 2550 case ARM::VST4d16_UPD: 2551 case ARM::VST4d32_UPD: 2552 case ARM::VST4q8_UPD: 2553 case ARM::VST4q16_UPD: 2554 case ARM::VST4q32_UPD: 2555 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2556 return MCDisassembler::Fail; 2557 break; 2558 default: 2559 break; 2560 } 2561 2562 // AddrMode6 Base (register+alignment) 2563 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2564 return MCDisassembler::Fail; 2565 2566 // AddrMode6 Offset (register) 2567 switch (Inst.getOpcode()) { 2568 default: 2569 if (Rm == 0xD) 2570 Inst.addOperand(MCOperand::CreateReg(0)); 2571 else if (Rm != 0xF) { 2572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 } 2575 break; 2576 case ARM::VST1d8wb_fixed: 2577 case ARM::VST1d16wb_fixed: 2578 case ARM::VST1d32wb_fixed: 2579 case ARM::VST1d64wb_fixed: 2580 case ARM::VST1q8wb_fixed: 2581 case ARM::VST1q16wb_fixed: 2582 case ARM::VST1q32wb_fixed: 2583 case ARM::VST1q64wb_fixed: 2584 case ARM::VST1d8Twb_fixed: 2585 case ARM::VST1d16Twb_fixed: 2586 case ARM::VST1d32Twb_fixed: 2587 case ARM::VST1d64Twb_fixed: 2588 case ARM::VST1d8Qwb_fixed: 2589 case ARM::VST1d16Qwb_fixed: 2590 case ARM::VST1d32Qwb_fixed: 2591 case ARM::VST1d64Qwb_fixed: 2592 case ARM::VST2d8wb_fixed: 2593 case ARM::VST2d16wb_fixed: 2594 case ARM::VST2d32wb_fixed: 2595 case ARM::VST2q8wb_fixed: 2596 case ARM::VST2q16wb_fixed: 2597 case ARM::VST2q32wb_fixed: 2598 case ARM::VST2b8wb_fixed: 2599 case ARM::VST2b16wb_fixed: 2600 case ARM::VST2b32wb_fixed: 2601 break; 2602 } 2603 2604 2605 // First input register 2606 switch (Inst.getOpcode()) { 2607 case ARM::VST1q16: 2608 case ARM::VST1q32: 2609 case ARM::VST1q64: 2610 case ARM::VST1q8: 2611 case ARM::VST1q16wb_fixed: 2612 case ARM::VST1q16wb_register: 2613 case ARM::VST1q32wb_fixed: 2614 case ARM::VST1q32wb_register: 2615 case ARM::VST1q64wb_fixed: 2616 case ARM::VST1q64wb_register: 2617 case ARM::VST1q8wb_fixed: 2618 case ARM::VST1q8wb_register: 2619 case ARM::VST2d16: 2620 case ARM::VST2d32: 2621 case ARM::VST2d8: 2622 case ARM::VST2d16wb_fixed: 2623 case ARM::VST2d16wb_register: 2624 case ARM::VST2d32wb_fixed: 2625 case ARM::VST2d32wb_register: 2626 case ARM::VST2d8wb_fixed: 2627 case ARM::VST2d8wb_register: 2628 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2629 return MCDisassembler::Fail; 2630 break; 2631 case ARM::VST2b16: 2632 case ARM::VST2b32: 2633 case ARM::VST2b8: 2634 case ARM::VST2b16wb_fixed: 2635 case ARM::VST2b16wb_register: 2636 case ARM::VST2b32wb_fixed: 2637 case ARM::VST2b32wb_register: 2638 case ARM::VST2b8wb_fixed: 2639 case ARM::VST2b8wb_register: 2640 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2641 return MCDisassembler::Fail; 2642 break; 2643 default: 2644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2645 return MCDisassembler::Fail; 2646 } 2647 2648 // Second input register 2649 switch (Inst.getOpcode()) { 2650 case ARM::VST3d8: 2651 case ARM::VST3d16: 2652 case ARM::VST3d32: 2653 case ARM::VST3d8_UPD: 2654 case ARM::VST3d16_UPD: 2655 case ARM::VST3d32_UPD: 2656 case ARM::VST4d8: 2657 case ARM::VST4d16: 2658 case ARM::VST4d32: 2659 case ARM::VST4d8_UPD: 2660 case ARM::VST4d16_UPD: 2661 case ARM::VST4d32_UPD: 2662 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2663 return MCDisassembler::Fail; 2664 break; 2665 case ARM::VST3q8: 2666 case ARM::VST3q16: 2667 case ARM::VST3q32: 2668 case ARM::VST3q8_UPD: 2669 case ARM::VST3q16_UPD: 2670 case ARM::VST3q32_UPD: 2671 case ARM::VST4q8: 2672 case ARM::VST4q16: 2673 case ARM::VST4q32: 2674 case ARM::VST4q8_UPD: 2675 case ARM::VST4q16_UPD: 2676 case ARM::VST4q32_UPD: 2677 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 break; 2680 default: 2681 break; 2682 } 2683 2684 // Third input register 2685 switch (Inst.getOpcode()) { 2686 case ARM::VST3d8: 2687 case ARM::VST3d16: 2688 case ARM::VST3d32: 2689 case ARM::VST3d8_UPD: 2690 case ARM::VST3d16_UPD: 2691 case ARM::VST3d32_UPD: 2692 case ARM::VST4d8: 2693 case ARM::VST4d16: 2694 case ARM::VST4d32: 2695 case ARM::VST4d8_UPD: 2696 case ARM::VST4d16_UPD: 2697 case ARM::VST4d32_UPD: 2698 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 break; 2701 case ARM::VST3q8: 2702 case ARM::VST3q16: 2703 case ARM::VST3q32: 2704 case ARM::VST3q8_UPD: 2705 case ARM::VST3q16_UPD: 2706 case ARM::VST3q32_UPD: 2707 case ARM::VST4q8: 2708 case ARM::VST4q16: 2709 case ARM::VST4q32: 2710 case ARM::VST4q8_UPD: 2711 case ARM::VST4q16_UPD: 2712 case ARM::VST4q32_UPD: 2713 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 break; 2716 default: 2717 break; 2718 } 2719 2720 // Fourth input register 2721 switch (Inst.getOpcode()) { 2722 case ARM::VST4d8: 2723 case ARM::VST4d16: 2724 case ARM::VST4d32: 2725 case ARM::VST4d8_UPD: 2726 case ARM::VST4d16_UPD: 2727 case ARM::VST4d32_UPD: 2728 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 break; 2731 case ARM::VST4q8: 2732 case ARM::VST4q16: 2733 case ARM::VST4q32: 2734 case ARM::VST4q8_UPD: 2735 case ARM::VST4q16_UPD: 2736 case ARM::VST4q32_UPD: 2737 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 break; 2740 default: 2741 break; 2742 } 2743 2744 return S; 2745 } 2746 2747 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2748 uint64_t Address, const void *Decoder) { 2749 DecodeStatus S = MCDisassembler::Success; 2750 2751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2752 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2753 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2754 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2755 unsigned align = fieldFromInstruction(Insn, 4, 1); 2756 unsigned size = fieldFromInstruction(Insn, 6, 2); 2757 2758 if (size == 0 && align == 1) 2759 return MCDisassembler::Fail; 2760 align *= (1 << size); 2761 2762 switch (Inst.getOpcode()) { 2763 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2764 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2765 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2766 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2767 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2768 return MCDisassembler::Fail; 2769 break; 2770 default: 2771 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2772 return MCDisassembler::Fail; 2773 break; 2774 } 2775 if (Rm != 0xF) { 2776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2777 return MCDisassembler::Fail; 2778 } 2779 2780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2781 return MCDisassembler::Fail; 2782 Inst.addOperand(MCOperand::CreateImm(align)); 2783 2784 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2785 // variant encodes Rm == 0xf. Anything else is a register offset post- 2786 // increment and we need to add the register operand to the instruction. 2787 if (Rm != 0xD && Rm != 0xF && 2788 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 2791 return S; 2792 } 2793 2794 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2795 uint64_t Address, const void *Decoder) { 2796 DecodeStatus S = MCDisassembler::Success; 2797 2798 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2799 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2800 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2801 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2802 unsigned align = fieldFromInstruction(Insn, 4, 1); 2803 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2804 align *= 2*size; 2805 2806 switch (Inst.getOpcode()) { 2807 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2808 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2809 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2810 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2811 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 break; 2814 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2815 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2816 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2817 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2818 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 break; 2821 default: 2822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 break; 2825 } 2826 2827 if (Rm != 0xF) 2828 Inst.addOperand(MCOperand::CreateImm(0)); 2829 2830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 Inst.addOperand(MCOperand::CreateImm(align)); 2833 2834 if (Rm != 0xD && Rm != 0xF) { 2835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 } 2838 2839 return S; 2840 } 2841 2842 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2843 uint64_t Address, const void *Decoder) { 2844 DecodeStatus S = MCDisassembler::Success; 2845 2846 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2847 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2848 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2849 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2850 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2851 2852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2853 return MCDisassembler::Fail; 2854 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2855 return MCDisassembler::Fail; 2856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 if (Rm != 0xF) { 2859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 } 2862 2863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2864 return MCDisassembler::Fail; 2865 Inst.addOperand(MCOperand::CreateImm(0)); 2866 2867 if (Rm == 0xD) 2868 Inst.addOperand(MCOperand::CreateReg(0)); 2869 else if (Rm != 0xF) { 2870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2871 return MCDisassembler::Fail; 2872 } 2873 2874 return S; 2875 } 2876 2877 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2878 uint64_t Address, const void *Decoder) { 2879 DecodeStatus S = MCDisassembler::Success; 2880 2881 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2882 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2883 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2884 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2885 unsigned size = fieldFromInstruction(Insn, 6, 2); 2886 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2887 unsigned align = fieldFromInstruction(Insn, 4, 1); 2888 2889 if (size == 0x3) { 2890 if (align == 0) 2891 return MCDisassembler::Fail; 2892 size = 4; 2893 align = 16; 2894 } else { 2895 if (size == 2) { 2896 size = 1 << size; 2897 align *= 8; 2898 } else { 2899 size = 1 << size; 2900 align *= 4*size; 2901 } 2902 } 2903 2904 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2905 return MCDisassembler::Fail; 2906 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2907 return MCDisassembler::Fail; 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2911 return MCDisassembler::Fail; 2912 if (Rm != 0xF) { 2913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2914 return MCDisassembler::Fail; 2915 } 2916 2917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 Inst.addOperand(MCOperand::CreateImm(align)); 2920 2921 if (Rm == 0xD) 2922 Inst.addOperand(MCOperand::CreateReg(0)); 2923 else if (Rm != 0xF) { 2924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 } 2927 2928 return S; 2929 } 2930 2931 static DecodeStatus 2932 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2933 uint64_t Address, const void *Decoder) { 2934 DecodeStatus S = MCDisassembler::Success; 2935 2936 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2937 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2938 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2939 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2940 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2941 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2942 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2943 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2944 2945 if (Q) { 2946 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 } else { 2949 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2950 return MCDisassembler::Fail; 2951 } 2952 2953 Inst.addOperand(MCOperand::CreateImm(imm)); 2954 2955 switch (Inst.getOpcode()) { 2956 case ARM::VORRiv4i16: 2957 case ARM::VORRiv2i32: 2958 case ARM::VBICiv4i16: 2959 case ARM::VBICiv2i32: 2960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 break; 2963 case ARM::VORRiv8i16: 2964 case ARM::VORRiv4i32: 2965 case ARM::VBICiv8i16: 2966 case ARM::VBICiv4i32: 2967 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2968 return MCDisassembler::Fail; 2969 break; 2970 default: 2971 break; 2972 } 2973 2974 return S; 2975 } 2976 2977 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2978 uint64_t Address, const void *Decoder) { 2979 DecodeStatus S = MCDisassembler::Success; 2980 2981 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2982 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2983 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2984 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2985 unsigned size = fieldFromInstruction(Insn, 18, 2); 2986 2987 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2988 return MCDisassembler::Fail; 2989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2992 2993 return S; 2994 } 2995 2996 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2997 uint64_t Address, const void *Decoder) { 2998 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2999 return MCDisassembler::Success; 3000 } 3001 3002 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3003 uint64_t Address, const void *Decoder) { 3004 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3005 return MCDisassembler::Success; 3006 } 3007 3008 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3009 uint64_t Address, const void *Decoder) { 3010 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3011 return MCDisassembler::Success; 3012 } 3013 3014 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3015 uint64_t Address, const void *Decoder) { 3016 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3017 return MCDisassembler::Success; 3018 } 3019 3020 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3021 uint64_t Address, const void *Decoder) { 3022 DecodeStatus S = MCDisassembler::Success; 3023 3024 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3025 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3026 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3027 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3028 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3029 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3030 unsigned op = fieldFromInstruction(Insn, 6, 1); 3031 3032 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 if (op) { 3035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3036 return MCDisassembler::Fail; // Writeback 3037 } 3038 3039 switch (Inst.getOpcode()) { 3040 case ARM::VTBL2: 3041 case ARM::VTBX2: 3042 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3043 return MCDisassembler::Fail; 3044 break; 3045 default: 3046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3047 return MCDisassembler::Fail; 3048 } 3049 3050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 3053 return S; 3054 } 3055 3056 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3057 uint64_t Address, const void *Decoder) { 3058 DecodeStatus S = MCDisassembler::Success; 3059 3060 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3061 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3062 3063 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3064 return MCDisassembler::Fail; 3065 3066 switch(Inst.getOpcode()) { 3067 default: 3068 return MCDisassembler::Fail; 3069 case ARM::tADR: 3070 break; // tADR does not explicitly represent the PC as an operand. 3071 case ARM::tADDrSPi: 3072 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3073 break; 3074 } 3075 3076 Inst.addOperand(MCOperand::CreateImm(imm)); 3077 return S; 3078 } 3079 3080 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3081 uint64_t Address, const void *Decoder) { 3082 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3083 true, 2, Inst, Decoder)) 3084 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3085 return MCDisassembler::Success; 3086 } 3087 3088 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3089 uint64_t Address, const void *Decoder) { 3090 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3091 true, 4, Inst, Decoder)) 3092 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3093 return MCDisassembler::Success; 3094 } 3095 3096 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3097 uint64_t Address, const void *Decoder) { 3098 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3099 true, 2, Inst, Decoder)) 3100 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3101 return MCDisassembler::Success; 3102 } 3103 3104 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3105 uint64_t Address, const void *Decoder) { 3106 DecodeStatus S = MCDisassembler::Success; 3107 3108 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3109 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3110 3111 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3112 return MCDisassembler::Fail; 3113 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3114 return MCDisassembler::Fail; 3115 3116 return S; 3117 } 3118 3119 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3120 uint64_t Address, const void *Decoder) { 3121 DecodeStatus S = MCDisassembler::Success; 3122 3123 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3124 unsigned imm = fieldFromInstruction(Val, 3, 5); 3125 3126 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3127 return MCDisassembler::Fail; 3128 Inst.addOperand(MCOperand::CreateImm(imm)); 3129 3130 return S; 3131 } 3132 3133 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3134 uint64_t Address, const void *Decoder) { 3135 unsigned imm = Val << 2; 3136 3137 Inst.addOperand(MCOperand::CreateImm(imm)); 3138 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3139 3140 return MCDisassembler::Success; 3141 } 3142 3143 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3144 uint64_t Address, const void *Decoder) { 3145 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3146 Inst.addOperand(MCOperand::CreateImm(Val)); 3147 3148 return MCDisassembler::Success; 3149 } 3150 3151 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3152 uint64_t Address, const void *Decoder) { 3153 DecodeStatus S = MCDisassembler::Success; 3154 3155 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3156 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3157 unsigned imm = fieldFromInstruction(Val, 0, 2); 3158 3159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3160 return MCDisassembler::Fail; 3161 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3162 return MCDisassembler::Fail; 3163 Inst.addOperand(MCOperand::CreateImm(imm)); 3164 3165 return S; 3166 } 3167 3168 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3169 uint64_t Address, const void *Decoder) { 3170 DecodeStatus S = MCDisassembler::Success; 3171 3172 switch (Inst.getOpcode()) { 3173 case ARM::t2PLDs: 3174 case ARM::t2PLDWs: 3175 case ARM::t2PLIs: 3176 break; 3177 default: { 3178 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3179 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 } 3182 } 3183 3184 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3185 if (Rn == 0xF) { 3186 switch (Inst.getOpcode()) { 3187 case ARM::t2LDRBs: 3188 Inst.setOpcode(ARM::t2LDRBpci); 3189 break; 3190 case ARM::t2LDRHs: 3191 Inst.setOpcode(ARM::t2LDRHpci); 3192 break; 3193 case ARM::t2LDRSHs: 3194 Inst.setOpcode(ARM::t2LDRSHpci); 3195 break; 3196 case ARM::t2LDRSBs: 3197 Inst.setOpcode(ARM::t2LDRSBpci); 3198 break; 3199 case ARM::t2PLDs: 3200 Inst.setOpcode(ARM::t2PLDi12); 3201 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3202 break; 3203 default: 3204 return MCDisassembler::Fail; 3205 } 3206 3207 int imm = fieldFromInstruction(Insn, 0, 12); 3208 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3209 Inst.addOperand(MCOperand::CreateImm(imm)); 3210 3211 return S; 3212 } 3213 3214 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3215 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3216 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3217 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 3220 return S; 3221 } 3222 3223 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3224 uint64_t Address, const void *Decoder) { 3225 if (Val == 0) 3226 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3227 else { 3228 int imm = Val & 0xFF; 3229 3230 if (!(Val & 0x100)) imm *= -1; 3231 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3232 } 3233 3234 return MCDisassembler::Success; 3235 } 3236 3237 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 DecodeStatus S = MCDisassembler::Success; 3240 3241 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3242 unsigned imm = fieldFromInstruction(Val, 0, 9); 3243 3244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3245 return MCDisassembler::Fail; 3246 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 3249 return S; 3250 } 3251 3252 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3253 uint64_t Address, const void *Decoder) { 3254 DecodeStatus S = MCDisassembler::Success; 3255 3256 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3257 unsigned imm = fieldFromInstruction(Val, 0, 8); 3258 3259 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 3262 Inst.addOperand(MCOperand::CreateImm(imm)); 3263 3264 return S; 3265 } 3266 3267 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3268 uint64_t Address, const void *Decoder) { 3269 int imm = Val & 0xFF; 3270 if (Val == 0) 3271 imm = INT32_MIN; 3272 else if (!(Val & 0x100)) 3273 imm *= -1; 3274 Inst.addOperand(MCOperand::CreateImm(imm)); 3275 3276 return MCDisassembler::Success; 3277 } 3278 3279 3280 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3281 uint64_t Address, const void *Decoder) { 3282 DecodeStatus S = MCDisassembler::Success; 3283 3284 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3285 unsigned imm = fieldFromInstruction(Val, 0, 9); 3286 3287 // Some instructions always use an additive offset. 3288 switch (Inst.getOpcode()) { 3289 case ARM::t2LDRT: 3290 case ARM::t2LDRBT: 3291 case ARM::t2LDRHT: 3292 case ARM::t2LDRSBT: 3293 case ARM::t2LDRSHT: 3294 case ARM::t2STRT: 3295 case ARM::t2STRBT: 3296 case ARM::t2STRHT: 3297 imm |= 0x100; 3298 break; 3299 default: 3300 break; 3301 } 3302 3303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 3308 return S; 3309 } 3310 3311 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3312 uint64_t Address, const void *Decoder) { 3313 DecodeStatus S = MCDisassembler::Success; 3314 3315 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3316 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3317 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3318 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3319 addr |= Rn << 9; 3320 unsigned load = fieldFromInstruction(Insn, 20, 1); 3321 3322 if (!load) { 3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 } 3326 3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 3330 if (load) { 3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 } 3334 3335 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 3338 return S; 3339 } 3340 3341 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3342 uint64_t Address, const void *Decoder) { 3343 DecodeStatus S = MCDisassembler::Success; 3344 3345 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3346 unsigned imm = fieldFromInstruction(Val, 0, 12); 3347 3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 Inst.addOperand(MCOperand::CreateImm(imm)); 3351 3352 return S; 3353 } 3354 3355 3356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3357 uint64_t Address, const void *Decoder) { 3358 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3359 3360 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3361 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3362 Inst.addOperand(MCOperand::CreateImm(imm)); 3363 3364 return MCDisassembler::Success; 3365 } 3366 3367 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3368 uint64_t Address, const void *Decoder) { 3369 DecodeStatus S = MCDisassembler::Success; 3370 3371 if (Inst.getOpcode() == ARM::tADDrSP) { 3372 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3373 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3374 3375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3376 return MCDisassembler::Fail; 3377 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 } else if (Inst.getOpcode() == ARM::tADDspr) { 3381 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3382 3383 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3384 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3386 return MCDisassembler::Fail; 3387 } 3388 3389 return S; 3390 } 3391 3392 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3393 uint64_t Address, const void *Decoder) { 3394 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3395 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3396 3397 Inst.addOperand(MCOperand::CreateImm(imod)); 3398 Inst.addOperand(MCOperand::CreateImm(flags)); 3399 3400 return MCDisassembler::Success; 3401 } 3402 3403 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3404 uint64_t Address, const void *Decoder) { 3405 DecodeStatus S = MCDisassembler::Success; 3406 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3407 unsigned add = fieldFromInstruction(Insn, 4, 1); 3408 3409 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3410 return MCDisassembler::Fail; 3411 Inst.addOperand(MCOperand::CreateImm(add)); 3412 3413 return S; 3414 } 3415 3416 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3417 uint64_t Address, const void *Decoder) { 3418 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3419 // Note only one trailing zero not two. Also the J1 and J2 values are from 3420 // the encoded instruction. So here change to I1 and I2 values via: 3421 // I1 = NOT(J1 EOR S); 3422 // I2 = NOT(J2 EOR S); 3423 // and build the imm32 with two trailing zeros as documented: 3424 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3425 unsigned S = (Val >> 23) & 1; 3426 unsigned J1 = (Val >> 22) & 1; 3427 unsigned J2 = (Val >> 21) & 1; 3428 unsigned I1 = !(J1 ^ S); 3429 unsigned I2 = !(J2 ^ S); 3430 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3431 int imm32 = SignExtend32<25>(tmp << 1); 3432 3433 if (!tryAddingSymbolicOperand(Address, 3434 (Address & ~2u) + imm32 + 4, 3435 true, 4, Inst, Decoder)) 3436 Inst.addOperand(MCOperand::CreateImm(imm32)); 3437 return MCDisassembler::Success; 3438 } 3439 3440 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3441 uint64_t Address, const void *Decoder) { 3442 if (Val == 0xA || Val == 0xB) 3443 return MCDisassembler::Fail; 3444 3445 Inst.addOperand(MCOperand::CreateImm(Val)); 3446 return MCDisassembler::Success; 3447 } 3448 3449 static DecodeStatus 3450 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3451 uint64_t Address, const void *Decoder) { 3452 DecodeStatus S = MCDisassembler::Success; 3453 3454 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3455 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3456 3457 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 return S; 3463 } 3464 3465 static DecodeStatus 3466 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3467 uint64_t Address, const void *Decoder) { 3468 DecodeStatus S = MCDisassembler::Success; 3469 3470 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3471 if (pred == 0xE || pred == 0xF) { 3472 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3473 switch (opc) { 3474 default: 3475 return MCDisassembler::Fail; 3476 case 0xf3bf8f4: 3477 Inst.setOpcode(ARM::t2DSB); 3478 break; 3479 case 0xf3bf8f5: 3480 Inst.setOpcode(ARM::t2DMB); 3481 break; 3482 case 0xf3bf8f6: 3483 Inst.setOpcode(ARM::t2ISB); 3484 break; 3485 } 3486 3487 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3488 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3489 } 3490 3491 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3492 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3493 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3494 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3495 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3496 3497 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3498 return MCDisassembler::Fail; 3499 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 3502 return S; 3503 } 3504 3505 // Decode a shifted immediate operand. These basically consist 3506 // of an 8-bit value, and a 4-bit directive that specifies either 3507 // a splat operation or a rotation. 3508 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3509 uint64_t Address, const void *Decoder) { 3510 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3511 if (ctrl == 0) { 3512 unsigned byte = fieldFromInstruction(Val, 8, 2); 3513 unsigned imm = fieldFromInstruction(Val, 0, 8); 3514 switch (byte) { 3515 case 0: 3516 Inst.addOperand(MCOperand::CreateImm(imm)); 3517 break; 3518 case 1: 3519 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3520 break; 3521 case 2: 3522 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3523 break; 3524 case 3: 3525 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3526 (imm << 8) | imm)); 3527 break; 3528 } 3529 } else { 3530 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3531 unsigned rot = fieldFromInstruction(Val, 7, 5); 3532 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3533 Inst.addOperand(MCOperand::CreateImm(imm)); 3534 } 3535 3536 return MCDisassembler::Success; 3537 } 3538 3539 static DecodeStatus 3540 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3541 uint64_t Address, const void *Decoder){ 3542 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3543 true, 2, Inst, Decoder)) 3544 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3545 return MCDisassembler::Success; 3546 } 3547 3548 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3549 uint64_t Address, const void *Decoder){ 3550 // Val is passed in as S:J1:J2:imm10:imm11 3551 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3552 // the encoded instruction. So here change to I1 and I2 values via: 3553 // I1 = NOT(J1 EOR S); 3554 // I2 = NOT(J2 EOR S); 3555 // and build the imm32 with one trailing zero as documented: 3556 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3557 unsigned S = (Val >> 23) & 1; 3558 unsigned J1 = (Val >> 22) & 1; 3559 unsigned J2 = (Val >> 21) & 1; 3560 unsigned I1 = !(J1 ^ S); 3561 unsigned I2 = !(J2 ^ S); 3562 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3563 int imm32 = SignExtend32<25>(tmp << 1); 3564 3565 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3566 true, 4, Inst, Decoder)) 3567 Inst.addOperand(MCOperand::CreateImm(imm32)); 3568 return MCDisassembler::Success; 3569 } 3570 3571 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3572 uint64_t Address, const void *Decoder) { 3573 if (Val & ~0xf) 3574 return MCDisassembler::Fail; 3575 3576 Inst.addOperand(MCOperand::CreateImm(Val)); 3577 return MCDisassembler::Success; 3578 } 3579 3580 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3581 uint64_t Address, const void *Decoder) { 3582 if (Val & ~0xf) 3583 return MCDisassembler::Fail; 3584 3585 Inst.addOperand(MCOperand::CreateImm(Val)); 3586 return MCDisassembler::Success; 3587 } 3588 3589 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3590 uint64_t Address, const void *Decoder) { 3591 if (!Val) return MCDisassembler::Fail; 3592 Inst.addOperand(MCOperand::CreateImm(Val)); 3593 return MCDisassembler::Success; 3594 } 3595 3596 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3597 uint64_t Address, const void *Decoder) { 3598 DecodeStatus S = MCDisassembler::Success; 3599 3600 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3601 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3602 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3603 3604 if (Rn == 0xF) 3605 S = MCDisassembler::SoftFail; 3606 3607 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 3614 return S; 3615 } 3616 3617 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3618 uint64_t Address, const void *Decoder){ 3619 DecodeStatus S = MCDisassembler::Success; 3620 3621 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3622 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3623 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3624 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3625 3626 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 3629 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 3630 S = MCDisassembler::SoftFail; 3631 3632 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3633 return MCDisassembler::Fail; 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 3639 return S; 3640 } 3641 3642 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3643 uint64_t Address, const void *Decoder) { 3644 DecodeStatus S = MCDisassembler::Success; 3645 3646 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3647 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3648 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3649 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3650 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3651 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3652 3653 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3654 3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3656 return MCDisassembler::Fail; 3657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3658 return MCDisassembler::Fail; 3659 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3662 return MCDisassembler::Fail; 3663 3664 return S; 3665 } 3666 3667 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3668 uint64_t Address, const void *Decoder) { 3669 DecodeStatus S = MCDisassembler::Success; 3670 3671 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3672 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3673 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3674 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3675 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3676 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3677 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3678 3679 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3680 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3681 3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3683 return MCDisassembler::Fail; 3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 3691 return S; 3692 } 3693 3694 3695 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3696 uint64_t Address, const void *Decoder) { 3697 DecodeStatus S = MCDisassembler::Success; 3698 3699 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3700 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3701 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3702 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3703 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3704 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3705 3706 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3707 3708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3715 return MCDisassembler::Fail; 3716 3717 return S; 3718 } 3719 3720 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3721 uint64_t Address, const void *Decoder) { 3722 DecodeStatus S = MCDisassembler::Success; 3723 3724 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3725 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3726 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3727 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3728 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3729 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3730 3731 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3732 3733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3734 return MCDisassembler::Fail; 3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3736 return MCDisassembler::Fail; 3737 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3738 return MCDisassembler::Fail; 3739 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 3742 return S; 3743 } 3744 3745 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3746 uint64_t Address, const void *Decoder) { 3747 DecodeStatus S = MCDisassembler::Success; 3748 3749 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3750 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3752 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3753 unsigned size = fieldFromInstruction(Insn, 10, 2); 3754 3755 unsigned align = 0; 3756 unsigned index = 0; 3757 switch (size) { 3758 default: 3759 return MCDisassembler::Fail; 3760 case 0: 3761 if (fieldFromInstruction(Insn, 4, 1)) 3762 return MCDisassembler::Fail; // UNDEFINED 3763 index = fieldFromInstruction(Insn, 5, 3); 3764 break; 3765 case 1: 3766 if (fieldFromInstruction(Insn, 5, 1)) 3767 return MCDisassembler::Fail; // UNDEFINED 3768 index = fieldFromInstruction(Insn, 6, 2); 3769 if (fieldFromInstruction(Insn, 4, 1)) 3770 align = 2; 3771 break; 3772 case 2: 3773 if (fieldFromInstruction(Insn, 6, 1)) 3774 return MCDisassembler::Fail; // UNDEFINED 3775 index = fieldFromInstruction(Insn, 7, 1); 3776 3777 switch (fieldFromInstruction(Insn, 4, 2)) { 3778 case 0 : 3779 align = 0; break; 3780 case 3: 3781 align = 4; break; 3782 default: 3783 return MCDisassembler::Fail; 3784 } 3785 break; 3786 } 3787 3788 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3789 return MCDisassembler::Fail; 3790 if (Rm != 0xF) { // Writeback 3791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3792 return MCDisassembler::Fail; 3793 } 3794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3795 return MCDisassembler::Fail; 3796 Inst.addOperand(MCOperand::CreateImm(align)); 3797 if (Rm != 0xF) { 3798 if (Rm != 0xD) { 3799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3800 return MCDisassembler::Fail; 3801 } else 3802 Inst.addOperand(MCOperand::CreateReg(0)); 3803 } 3804 3805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3806 return MCDisassembler::Fail; 3807 Inst.addOperand(MCOperand::CreateImm(index)); 3808 3809 return S; 3810 } 3811 3812 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3813 uint64_t Address, const void *Decoder) { 3814 DecodeStatus S = MCDisassembler::Success; 3815 3816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3817 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3818 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3819 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3820 unsigned size = fieldFromInstruction(Insn, 10, 2); 3821 3822 unsigned align = 0; 3823 unsigned index = 0; 3824 switch (size) { 3825 default: 3826 return MCDisassembler::Fail; 3827 case 0: 3828 if (fieldFromInstruction(Insn, 4, 1)) 3829 return MCDisassembler::Fail; // UNDEFINED 3830 index = fieldFromInstruction(Insn, 5, 3); 3831 break; 3832 case 1: 3833 if (fieldFromInstruction(Insn, 5, 1)) 3834 return MCDisassembler::Fail; // UNDEFINED 3835 index = fieldFromInstruction(Insn, 6, 2); 3836 if (fieldFromInstruction(Insn, 4, 1)) 3837 align = 2; 3838 break; 3839 case 2: 3840 if (fieldFromInstruction(Insn, 6, 1)) 3841 return MCDisassembler::Fail; // UNDEFINED 3842 index = fieldFromInstruction(Insn, 7, 1); 3843 3844 switch (fieldFromInstruction(Insn, 4, 2)) { 3845 case 0: 3846 align = 0; break; 3847 case 3: 3848 align = 4; break; 3849 default: 3850 return MCDisassembler::Fail; 3851 } 3852 break; 3853 } 3854 3855 if (Rm != 0xF) { // Writeback 3856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3857 return MCDisassembler::Fail; 3858 } 3859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3860 return MCDisassembler::Fail; 3861 Inst.addOperand(MCOperand::CreateImm(align)); 3862 if (Rm != 0xF) { 3863 if (Rm != 0xD) { 3864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3865 return MCDisassembler::Fail; 3866 } else 3867 Inst.addOperand(MCOperand::CreateReg(0)); 3868 } 3869 3870 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 Inst.addOperand(MCOperand::CreateImm(index)); 3873 3874 return S; 3875 } 3876 3877 3878 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3879 uint64_t Address, const void *Decoder) { 3880 DecodeStatus S = MCDisassembler::Success; 3881 3882 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3883 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3886 unsigned size = fieldFromInstruction(Insn, 10, 2); 3887 3888 unsigned align = 0; 3889 unsigned index = 0; 3890 unsigned inc = 1; 3891 switch (size) { 3892 default: 3893 return MCDisassembler::Fail; 3894 case 0: 3895 index = fieldFromInstruction(Insn, 5, 3); 3896 if (fieldFromInstruction(Insn, 4, 1)) 3897 align = 2; 3898 break; 3899 case 1: 3900 index = fieldFromInstruction(Insn, 6, 2); 3901 if (fieldFromInstruction(Insn, 4, 1)) 3902 align = 4; 3903 if (fieldFromInstruction(Insn, 5, 1)) 3904 inc = 2; 3905 break; 3906 case 2: 3907 if (fieldFromInstruction(Insn, 5, 1)) 3908 return MCDisassembler::Fail; // UNDEFINED 3909 index = fieldFromInstruction(Insn, 7, 1); 3910 if (fieldFromInstruction(Insn, 4, 1) != 0) 3911 align = 8; 3912 if (fieldFromInstruction(Insn, 6, 1)) 3913 inc = 2; 3914 break; 3915 } 3916 3917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3918 return MCDisassembler::Fail; 3919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3920 return MCDisassembler::Fail; 3921 if (Rm != 0xF) { // Writeback 3922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3923 return MCDisassembler::Fail; 3924 } 3925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3926 return MCDisassembler::Fail; 3927 Inst.addOperand(MCOperand::CreateImm(align)); 3928 if (Rm != 0xF) { 3929 if (Rm != 0xD) { 3930 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3931 return MCDisassembler::Fail; 3932 } else 3933 Inst.addOperand(MCOperand::CreateReg(0)); 3934 } 3935 3936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3937 return MCDisassembler::Fail; 3938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3939 return MCDisassembler::Fail; 3940 Inst.addOperand(MCOperand::CreateImm(index)); 3941 3942 return S; 3943 } 3944 3945 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3946 uint64_t Address, const void *Decoder) { 3947 DecodeStatus S = MCDisassembler::Success; 3948 3949 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3950 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3951 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3952 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3953 unsigned size = fieldFromInstruction(Insn, 10, 2); 3954 3955 unsigned align = 0; 3956 unsigned index = 0; 3957 unsigned inc = 1; 3958 switch (size) { 3959 default: 3960 return MCDisassembler::Fail; 3961 case 0: 3962 index = fieldFromInstruction(Insn, 5, 3); 3963 if (fieldFromInstruction(Insn, 4, 1)) 3964 align = 2; 3965 break; 3966 case 1: 3967 index = fieldFromInstruction(Insn, 6, 2); 3968 if (fieldFromInstruction(Insn, 4, 1)) 3969 align = 4; 3970 if (fieldFromInstruction(Insn, 5, 1)) 3971 inc = 2; 3972 break; 3973 case 2: 3974 if (fieldFromInstruction(Insn, 5, 1)) 3975 return MCDisassembler::Fail; // UNDEFINED 3976 index = fieldFromInstruction(Insn, 7, 1); 3977 if (fieldFromInstruction(Insn, 4, 1) != 0) 3978 align = 8; 3979 if (fieldFromInstruction(Insn, 6, 1)) 3980 inc = 2; 3981 break; 3982 } 3983 3984 if (Rm != 0xF) { // Writeback 3985 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3986 return MCDisassembler::Fail; 3987 } 3988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3989 return MCDisassembler::Fail; 3990 Inst.addOperand(MCOperand::CreateImm(align)); 3991 if (Rm != 0xF) { 3992 if (Rm != 0xD) { 3993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 } else 3996 Inst.addOperand(MCOperand::CreateReg(0)); 3997 } 3998 3999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 Inst.addOperand(MCOperand::CreateImm(index)); 4004 4005 return S; 4006 } 4007 4008 4009 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4010 uint64_t Address, const void *Decoder) { 4011 DecodeStatus S = MCDisassembler::Success; 4012 4013 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4014 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4015 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4016 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4017 unsigned size = fieldFromInstruction(Insn, 10, 2); 4018 4019 unsigned align = 0; 4020 unsigned index = 0; 4021 unsigned inc = 1; 4022 switch (size) { 4023 default: 4024 return MCDisassembler::Fail; 4025 case 0: 4026 if (fieldFromInstruction(Insn, 4, 1)) 4027 return MCDisassembler::Fail; // UNDEFINED 4028 index = fieldFromInstruction(Insn, 5, 3); 4029 break; 4030 case 1: 4031 if (fieldFromInstruction(Insn, 4, 1)) 4032 return MCDisassembler::Fail; // UNDEFINED 4033 index = fieldFromInstruction(Insn, 6, 2); 4034 if (fieldFromInstruction(Insn, 5, 1)) 4035 inc = 2; 4036 break; 4037 case 2: 4038 if (fieldFromInstruction(Insn, 4, 2)) 4039 return MCDisassembler::Fail; // UNDEFINED 4040 index = fieldFromInstruction(Insn, 7, 1); 4041 if (fieldFromInstruction(Insn, 6, 1)) 4042 inc = 2; 4043 break; 4044 } 4045 4046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4047 return MCDisassembler::Fail; 4048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4049 return MCDisassembler::Fail; 4050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 4053 if (Rm != 0xF) { // Writeback 4054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4055 return MCDisassembler::Fail; 4056 } 4057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4058 return MCDisassembler::Fail; 4059 Inst.addOperand(MCOperand::CreateImm(align)); 4060 if (Rm != 0xF) { 4061 if (Rm != 0xD) { 4062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 } else 4065 Inst.addOperand(MCOperand::CreateReg(0)); 4066 } 4067 4068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4069 return MCDisassembler::Fail; 4070 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4071 return MCDisassembler::Fail; 4072 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4073 return MCDisassembler::Fail; 4074 Inst.addOperand(MCOperand::CreateImm(index)); 4075 4076 return S; 4077 } 4078 4079 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4080 uint64_t Address, const void *Decoder) { 4081 DecodeStatus S = MCDisassembler::Success; 4082 4083 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4084 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4085 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4086 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4087 unsigned size = fieldFromInstruction(Insn, 10, 2); 4088 4089 unsigned align = 0; 4090 unsigned index = 0; 4091 unsigned inc = 1; 4092 switch (size) { 4093 default: 4094 return MCDisassembler::Fail; 4095 case 0: 4096 if (fieldFromInstruction(Insn, 4, 1)) 4097 return MCDisassembler::Fail; // UNDEFINED 4098 index = fieldFromInstruction(Insn, 5, 3); 4099 break; 4100 case 1: 4101 if (fieldFromInstruction(Insn, 4, 1)) 4102 return MCDisassembler::Fail; // UNDEFINED 4103 index = fieldFromInstruction(Insn, 6, 2); 4104 if (fieldFromInstruction(Insn, 5, 1)) 4105 inc = 2; 4106 break; 4107 case 2: 4108 if (fieldFromInstruction(Insn, 4, 2)) 4109 return MCDisassembler::Fail; // UNDEFINED 4110 index = fieldFromInstruction(Insn, 7, 1); 4111 if (fieldFromInstruction(Insn, 6, 1)) 4112 inc = 2; 4113 break; 4114 } 4115 4116 if (Rm != 0xF) { // Writeback 4117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 } 4120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4121 return MCDisassembler::Fail; 4122 Inst.addOperand(MCOperand::CreateImm(align)); 4123 if (Rm != 0xF) { 4124 if (Rm != 0xD) { 4125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4126 return MCDisassembler::Fail; 4127 } else 4128 Inst.addOperand(MCOperand::CreateReg(0)); 4129 } 4130 4131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4132 return MCDisassembler::Fail; 4133 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4134 return MCDisassembler::Fail; 4135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4136 return MCDisassembler::Fail; 4137 Inst.addOperand(MCOperand::CreateImm(index)); 4138 4139 return S; 4140 } 4141 4142 4143 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4144 uint64_t Address, const void *Decoder) { 4145 DecodeStatus S = MCDisassembler::Success; 4146 4147 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4148 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4149 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4150 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4151 unsigned size = fieldFromInstruction(Insn, 10, 2); 4152 4153 unsigned align = 0; 4154 unsigned index = 0; 4155 unsigned inc = 1; 4156 switch (size) { 4157 default: 4158 return MCDisassembler::Fail; 4159 case 0: 4160 if (fieldFromInstruction(Insn, 4, 1)) 4161 align = 4; 4162 index = fieldFromInstruction(Insn, 5, 3); 4163 break; 4164 case 1: 4165 if (fieldFromInstruction(Insn, 4, 1)) 4166 align = 8; 4167 index = fieldFromInstruction(Insn, 6, 2); 4168 if (fieldFromInstruction(Insn, 5, 1)) 4169 inc = 2; 4170 break; 4171 case 2: 4172 switch (fieldFromInstruction(Insn, 4, 2)) { 4173 case 0: 4174 align = 0; break; 4175 case 3: 4176 return MCDisassembler::Fail; 4177 default: 4178 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4179 } 4180 4181 index = fieldFromInstruction(Insn, 7, 1); 4182 if (fieldFromInstruction(Insn, 6, 1)) 4183 inc = 2; 4184 break; 4185 } 4186 4187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4188 return MCDisassembler::Fail; 4189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4190 return MCDisassembler::Fail; 4191 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4192 return MCDisassembler::Fail; 4193 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4194 return MCDisassembler::Fail; 4195 4196 if (Rm != 0xF) { // Writeback 4197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4198 return MCDisassembler::Fail; 4199 } 4200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4201 return MCDisassembler::Fail; 4202 Inst.addOperand(MCOperand::CreateImm(align)); 4203 if (Rm != 0xF) { 4204 if (Rm != 0xD) { 4205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4206 return MCDisassembler::Fail; 4207 } else 4208 Inst.addOperand(MCOperand::CreateReg(0)); 4209 } 4210 4211 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4214 return MCDisassembler::Fail; 4215 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4216 return MCDisassembler::Fail; 4217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4218 return MCDisassembler::Fail; 4219 Inst.addOperand(MCOperand::CreateImm(index)); 4220 4221 return S; 4222 } 4223 4224 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4225 uint64_t Address, const void *Decoder) { 4226 DecodeStatus S = MCDisassembler::Success; 4227 4228 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4229 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4230 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4231 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4232 unsigned size = fieldFromInstruction(Insn, 10, 2); 4233 4234 unsigned align = 0; 4235 unsigned index = 0; 4236 unsigned inc = 1; 4237 switch (size) { 4238 default: 4239 return MCDisassembler::Fail; 4240 case 0: 4241 if (fieldFromInstruction(Insn, 4, 1)) 4242 align = 4; 4243 index = fieldFromInstruction(Insn, 5, 3); 4244 break; 4245 case 1: 4246 if (fieldFromInstruction(Insn, 4, 1)) 4247 align = 8; 4248 index = fieldFromInstruction(Insn, 6, 2); 4249 if (fieldFromInstruction(Insn, 5, 1)) 4250 inc = 2; 4251 break; 4252 case 2: 4253 switch (fieldFromInstruction(Insn, 4, 2)) { 4254 case 0: 4255 align = 0; break; 4256 case 3: 4257 return MCDisassembler::Fail; 4258 default: 4259 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4260 } 4261 4262 index = fieldFromInstruction(Insn, 7, 1); 4263 if (fieldFromInstruction(Insn, 6, 1)) 4264 inc = 2; 4265 break; 4266 } 4267 4268 if (Rm != 0xF) { // Writeback 4269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 } 4272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4273 return MCDisassembler::Fail; 4274 Inst.addOperand(MCOperand::CreateImm(align)); 4275 if (Rm != 0xF) { 4276 if (Rm != 0xD) { 4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4278 return MCDisassembler::Fail; 4279 } else 4280 Inst.addOperand(MCOperand::CreateReg(0)); 4281 } 4282 4283 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4284 return MCDisassembler::Fail; 4285 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4286 return MCDisassembler::Fail; 4287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4288 return MCDisassembler::Fail; 4289 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 Inst.addOperand(MCOperand::CreateImm(index)); 4292 4293 return S; 4294 } 4295 4296 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4297 uint64_t Address, const void *Decoder) { 4298 DecodeStatus S = MCDisassembler::Success; 4299 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4300 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4301 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4302 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4303 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4304 4305 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4306 S = MCDisassembler::SoftFail; 4307 4308 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4315 return MCDisassembler::Fail; 4316 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4317 return MCDisassembler::Fail; 4318 4319 return S; 4320 } 4321 4322 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4323 uint64_t Address, const void *Decoder) { 4324 DecodeStatus S = MCDisassembler::Success; 4325 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4326 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4327 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4328 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4329 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4330 4331 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4332 S = MCDisassembler::SoftFail; 4333 4334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4335 return MCDisassembler::Fail; 4336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4337 return MCDisassembler::Fail; 4338 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4339 return MCDisassembler::Fail; 4340 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 4345 return S; 4346 } 4347 4348 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4349 uint64_t Address, const void *Decoder) { 4350 DecodeStatus S = MCDisassembler::Success; 4351 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4352 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4353 4354 if (pred == 0xF) { 4355 pred = 0xE; 4356 S = MCDisassembler::SoftFail; 4357 } 4358 4359 if (mask == 0x0) { 4360 mask |= 0x8; 4361 S = MCDisassembler::SoftFail; 4362 } 4363 4364 Inst.addOperand(MCOperand::CreateImm(pred)); 4365 Inst.addOperand(MCOperand::CreateImm(mask)); 4366 return S; 4367 } 4368 4369 static DecodeStatus 4370 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4371 uint64_t Address, const void *Decoder) { 4372 DecodeStatus S = MCDisassembler::Success; 4373 4374 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4375 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4376 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4377 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4378 unsigned W = fieldFromInstruction(Insn, 21, 1); 4379 unsigned U = fieldFromInstruction(Insn, 23, 1); 4380 unsigned P = fieldFromInstruction(Insn, 24, 1); 4381 bool writeback = (W == 1) | (P == 0); 4382 4383 addr |= (U << 8) | (Rn << 9); 4384 4385 if (writeback && (Rn == Rt || Rn == Rt2)) 4386 Check(S, MCDisassembler::SoftFail); 4387 if (Rt == Rt2) 4388 Check(S, MCDisassembler::SoftFail); 4389 4390 // Rt 4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 // Rt2 4394 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 // Writeback operand 4397 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4398 return MCDisassembler::Fail; 4399 // addr 4400 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 4403 return S; 4404 } 4405 4406 static DecodeStatus 4407 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4408 uint64_t Address, const void *Decoder) { 4409 DecodeStatus S = MCDisassembler::Success; 4410 4411 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4412 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4413 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4414 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4415 unsigned W = fieldFromInstruction(Insn, 21, 1); 4416 unsigned U = fieldFromInstruction(Insn, 23, 1); 4417 unsigned P = fieldFromInstruction(Insn, 24, 1); 4418 bool writeback = (W == 1) | (P == 0); 4419 4420 addr |= (U << 8) | (Rn << 9); 4421 4422 if (writeback && (Rn == Rt || Rn == Rt2)) 4423 Check(S, MCDisassembler::SoftFail); 4424 4425 // Writeback operand 4426 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 // Rt 4429 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4430 return MCDisassembler::Fail; 4431 // Rt2 4432 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4433 return MCDisassembler::Fail; 4434 // addr 4435 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 4438 return S; 4439 } 4440 4441 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4442 uint64_t Address, const void *Decoder) { 4443 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4444 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4445 if (sign1 != sign2) return MCDisassembler::Fail; 4446 4447 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4448 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4449 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4450 Val |= sign1 << 12; 4451 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4452 4453 return MCDisassembler::Success; 4454 } 4455 4456 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4457 uint64_t Address, 4458 const void *Decoder) { 4459 DecodeStatus S = MCDisassembler::Success; 4460 4461 // Shift of "asr #32" is not allowed in Thumb2 mode. 4462 if (Val == 0x20) S = MCDisassembler::SoftFail; 4463 Inst.addOperand(MCOperand::CreateImm(Val)); 4464 return S; 4465 } 4466 4467 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4468 uint64_t Address, const void *Decoder) { 4469 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4470 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4471 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4472 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4473 4474 if (pred == 0xF) 4475 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4476 4477 DecodeStatus S = MCDisassembler::Success; 4478 4479 if (Rt == Rn || Rn == Rt2) 4480 S = MCDisassembler::SoftFail; 4481 4482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4483 return MCDisassembler::Fail; 4484 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4485 return MCDisassembler::Fail; 4486 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4487 return MCDisassembler::Fail; 4488 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4489 return MCDisassembler::Fail; 4490 4491 return S; 4492 } 4493 4494 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4495 uint64_t Address, const void *Decoder) { 4496 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4497 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4498 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4499 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4500 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4501 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4502 unsigned op = fieldFromInstruction(Insn, 5, 1); 4503 4504 DecodeStatus S = MCDisassembler::Success; 4505 4506 // VMOVv2f32 is ambiguous with these decodings. 4507 if (!(imm & 0x38) && cmode == 0xF) { 4508 if (op == 1) return MCDisassembler::Fail; 4509 Inst.setOpcode(ARM::VMOVv2f32); 4510 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4511 } 4512 4513 if (!(imm & 0x20)) return MCDisassembler::Fail; 4514 4515 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4518 return MCDisassembler::Fail; 4519 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4520 4521 return S; 4522 } 4523 4524 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4525 uint64_t Address, const void *Decoder) { 4526 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4527 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4528 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4529 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4530 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4531 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4532 unsigned op = fieldFromInstruction(Insn, 5, 1); 4533 4534 DecodeStatus S = MCDisassembler::Success; 4535 4536 // VMOVv4f32 is ambiguous with these decodings. 4537 if (!(imm & 0x38) && cmode == 0xF) { 4538 if (op == 1) return MCDisassembler::Fail; 4539 Inst.setOpcode(ARM::VMOVv4f32); 4540 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4541 } 4542 4543 if (!(imm & 0x20)) return MCDisassembler::Fail; 4544 4545 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4550 4551 return S; 4552 } 4553 4554 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4555 const void *Decoder) 4556 { 4557 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4558 if (Imm > 4) return MCDisassembler::Fail; 4559 Inst.addOperand(MCOperand::CreateImm(Imm)); 4560 return MCDisassembler::Success; 4561 } 4562 4563 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4564 uint64_t Address, const void *Decoder) { 4565 DecodeStatus S = MCDisassembler::Success; 4566 4567 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4568 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4569 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4570 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4571 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4572 4573 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4574 S = MCDisassembler::SoftFail; 4575 4576 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4577 return MCDisassembler::Fail; 4578 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4579 return MCDisassembler::Fail; 4580 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4581 return MCDisassembler::Fail; 4582 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4585 return MCDisassembler::Fail; 4586 4587 return S; 4588 } 4589 4590 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4591 uint64_t Address, const void *Decoder) { 4592 4593 DecodeStatus S = MCDisassembler::Success; 4594 4595 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4596 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4597 unsigned cop = fieldFromInstruction(Val, 8, 4); 4598 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4599 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4600 4601 if ((cop & ~0x1) == 0xa) 4602 return MCDisassembler::Fail; 4603 4604 if (Rt == Rt2) 4605 S = MCDisassembler::SoftFail; 4606 4607 Inst.addOperand(MCOperand::CreateImm(cop)); 4608 Inst.addOperand(MCOperand::CreateImm(opc1)); 4609 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4610 return MCDisassembler::Fail; 4611 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4612 return MCDisassembler::Fail; 4613 Inst.addOperand(MCOperand::CreateImm(CRm)); 4614 4615 return S; 4616 } 4617 4618