1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 183 unsigned RegNo, uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 217 unsigned Insn, 218 uint64_t Adddress, 219 const void *Decoder); 220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 323 const void *Decoder); 324 325 326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 391 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 #include "ARMGenDisassemblerTables.inc" 396 397 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 398 return new ARMDisassembler(STI); 399 } 400 401 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 402 return new ThumbDisassembler(STI); 403 } 404 405 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 const MemoryObject &Region, 407 uint64_t Address, 408 raw_ostream &os, 409 raw_ostream &cs) const { 410 CommentStream = &cs; 411 412 uint8_t bytes[4]; 413 414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 416 417 // We want to read exactly 4 bytes of data. 418 if (Region.readBytes(Address, 4, bytes) == -1) { 419 Size = 0; 420 return MCDisassembler::Fail; 421 } 422 423 // Encoded as a small-endian 32-bit word in the stream. 424 uint32_t insn = (bytes[3] << 24) | 425 (bytes[2] << 16) | 426 (bytes[1] << 8) | 427 (bytes[0] << 0); 428 429 // Calling the auto-generated decoder function. 430 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 431 Address, this, STI); 432 if (result != MCDisassembler::Fail) { 433 Size = 4; 434 return result; 435 } 436 437 // VFP and NEON instructions, similarly, are shared between ARM 438 // and Thumb modes. 439 MI.clear(); 440 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 441 if (result != MCDisassembler::Fail) { 442 Size = 4; 443 return result; 444 } 445 446 MI.clear(); 447 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 448 this, STI); 449 if (result != MCDisassembler::Fail) { 450 Size = 4; 451 // Add a fake predicate operand, because we share these instruction 452 // definitions with Thumb2 where these instructions are predicable. 453 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 454 return MCDisassembler::Fail; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 460 this, STI); 461 if (result != MCDisassembler::Fail) { 462 Size = 4; 463 // Add a fake predicate operand, because we share these instruction 464 // definitions with Thumb2 where these instructions are predicable. 465 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 466 return MCDisassembler::Fail; 467 return result; 468 } 469 470 MI.clear(); 471 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 472 this, STI); 473 if (result != MCDisassembler::Fail) { 474 Size = 4; 475 // Add a fake predicate operand, because we share these instruction 476 // definitions with Thumb2 where these instructions are predicable. 477 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 478 return MCDisassembler::Fail; 479 return result; 480 } 481 482 MI.clear(); 483 484 Size = 0; 485 return MCDisassembler::Fail; 486 } 487 488 namespace llvm { 489 extern const MCInstrDesc ARMInsts[]; 490 } 491 492 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 493 /// immediate Value in the MCInst. The immediate Value has had any PC 494 /// adjustment made by the caller. If the instruction is a branch instruction 495 /// then isBranch is true, else false. If the getOpInfo() function was set as 496 /// part of the setupForSymbolicDisassembly() call then that function is called 497 /// to get any symbolic information at the Address for this instruction. If 498 /// that returns non-zero then the symbolic information it returns is used to 499 /// create an MCExpr and that is added as an operand to the MCInst. If 500 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 501 /// Value is done and if a symbol is found an MCExpr is created with that, else 502 /// an MCExpr with Value is created. This function returns true if it adds an 503 /// operand to the MCInst and false otherwise. 504 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 505 bool isBranch, uint64_t InstSize, 506 MCInst &MI, const void *Decoder) { 507 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 508 // FIXME: Does it make sense for value to be negative? 509 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 510 /* Offset */ 0, InstSize); 511 } 512 513 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 514 /// referenced by a load instruction with the base register that is the Pc. 515 /// These can often be values in a literal pool near the Address of the 516 /// instruction. The Address of the instruction and its immediate Value are 517 /// used as a possible literal pool entry. The SymbolLookUp call back will 518 /// return the name of a symbol referenced by the literal pool's entry if 519 /// the referenced address is that of a symbol. Or it will return a pointer to 520 /// a literal 'C' string if the referenced address of the literal pool's entry 521 /// is an address into a section with 'C' string literals. 522 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 523 const void *Decoder) { 524 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 525 Dis->tryAddingPcLoadReferenceComment(Value, Address); 526 } 527 528 // Thumb1 instructions don't have explicit S bits. Rather, they 529 // implicitly set CPSR. Since it's not represented in the encoding, the 530 // auto-generated decoder won't inject the CPSR operand. We need to fix 531 // that as a post-pass. 532 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 533 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 534 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 535 MCInst::iterator I = MI.begin(); 536 for (unsigned i = 0; i < NumOps; ++i, ++I) { 537 if (I == MI.end()) break; 538 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 539 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 540 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 541 return; 542 } 543 } 544 545 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 546 } 547 548 // Most Thumb instructions don't have explicit predicates in the 549 // encoding, but rather get their predicates from IT context. We need 550 // to fix up the predicate operands using this context information as a 551 // post-pass. 552 MCDisassembler::DecodeStatus 553 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 554 MCDisassembler::DecodeStatus S = Success; 555 556 // A few instructions actually have predicates encoded in them. Don't 557 // try to overwrite it if we're seeing one of those. 558 switch (MI.getOpcode()) { 559 case ARM::tBcc: 560 case ARM::t2Bcc: 561 case ARM::tCBZ: 562 case ARM::tCBNZ: 563 case ARM::tCPS: 564 case ARM::t2CPS3p: 565 case ARM::t2CPS2p: 566 case ARM::t2CPS1p: 567 case ARM::tMOVSr: 568 case ARM::tSETEND: 569 // Some instructions (mostly conditional branches) are not 570 // allowed in IT blocks. 571 if (ITBlock.instrInITBlock()) 572 S = SoftFail; 573 else 574 return Success; 575 break; 576 case ARM::tB: 577 case ARM::t2B: 578 case ARM::t2TBB: 579 case ARM::t2TBH: 580 // Some instructions (mostly unconditional branches) can 581 // only appears at the end of, or outside of, an IT. 582 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 583 S = SoftFail; 584 break; 585 default: 586 break; 587 } 588 589 // If we're in an IT block, base the predicate on that. Otherwise, 590 // assume a predicate of AL. 591 unsigned CC; 592 CC = ITBlock.getITCC(); 593 if (CC == 0xF) 594 CC = ARMCC::AL; 595 if (ITBlock.instrInITBlock()) 596 ITBlock.advanceITState(); 597 598 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 599 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 600 MCInst::iterator I = MI.begin(); 601 for (unsigned i = 0; i < NumOps; ++i, ++I) { 602 if (I == MI.end()) break; 603 if (OpInfo[i].isPredicate()) { 604 I = MI.insert(I, MCOperand::CreateImm(CC)); 605 ++I; 606 if (CC == ARMCC::AL) 607 MI.insert(I, MCOperand::CreateReg(0)); 608 else 609 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 610 return S; 611 } 612 } 613 614 I = MI.insert(I, MCOperand::CreateImm(CC)); 615 ++I; 616 if (CC == ARMCC::AL) 617 MI.insert(I, MCOperand::CreateReg(0)); 618 else 619 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 620 621 return S; 622 } 623 624 // Thumb VFP instructions are a special case. Because we share their 625 // encodings between ARM and Thumb modes, and they are predicable in ARM 626 // mode, the auto-generated decoder will give them an (incorrect) 627 // predicate operand. We need to rewrite these operands based on the IT 628 // context as a post-pass. 629 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 630 unsigned CC; 631 CC = ITBlock.getITCC(); 632 if (ITBlock.instrInITBlock()) 633 ITBlock.advanceITState(); 634 635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 636 MCInst::iterator I = MI.begin(); 637 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 638 for (unsigned i = 0; i < NumOps; ++i, ++I) { 639 if (OpInfo[i].isPredicate() ) { 640 I->setImm(CC); 641 ++I; 642 if (CC == ARMCC::AL) 643 I->setReg(0); 644 else 645 I->setReg(ARM::CPSR); 646 return; 647 } 648 } 649 } 650 651 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 652 const MemoryObject &Region, 653 uint64_t Address, 654 raw_ostream &os, 655 raw_ostream &cs) const { 656 CommentStream = &cs; 657 658 uint8_t bytes[4]; 659 660 assert((STI.getFeatureBits() & ARM::ModeThumb) && 661 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 662 663 // We want to read exactly 2 bytes of data. 664 if (Region.readBytes(Address, 2, bytes) == -1) { 665 Size = 0; 666 return MCDisassembler::Fail; 667 } 668 669 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 670 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 671 Address, this, STI); 672 if (result != MCDisassembler::Fail) { 673 Size = 2; 674 Check(result, AddThumbPredicate(MI)); 675 return result; 676 } 677 678 MI.clear(); 679 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 680 Address, this, STI); 681 if (result) { 682 Size = 2; 683 bool InITBlock = ITBlock.instrInITBlock(); 684 Check(result, AddThumbPredicate(MI)); 685 AddThumb1SBit(MI, InITBlock); 686 return result; 687 } 688 689 MI.clear(); 690 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 691 Address, this, STI); 692 if (result != MCDisassembler::Fail) { 693 Size = 2; 694 695 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 696 // the Thumb predicate. 697 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 698 result = MCDisassembler::SoftFail; 699 700 Check(result, AddThumbPredicate(MI)); 701 702 // If we find an IT instruction, we need to parse its condition 703 // code and mask operands so that we can apply them correctly 704 // to the subsequent instructions. 705 if (MI.getOpcode() == ARM::t2IT) { 706 707 unsigned Firstcond = MI.getOperand(0).getImm(); 708 unsigned Mask = MI.getOperand(1).getImm(); 709 ITBlock.setITState(Firstcond, Mask); 710 } 711 712 return result; 713 } 714 715 // We want to read exactly 4 bytes of data. 716 if (Region.readBytes(Address, 4, bytes) == -1) { 717 Size = 0; 718 return MCDisassembler::Fail; 719 } 720 721 uint32_t insn32 = (bytes[3] << 8) | 722 (bytes[2] << 0) | 723 (bytes[1] << 24) | 724 (bytes[0] << 16); 725 MI.clear(); 726 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 727 this, STI); 728 if (result != MCDisassembler::Fail) { 729 Size = 4; 730 bool InITBlock = ITBlock.instrInITBlock(); 731 Check(result, AddThumbPredicate(MI)); 732 AddThumb1SBit(MI, InITBlock); 733 return result; 734 } 735 736 MI.clear(); 737 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 738 this, STI); 739 if (result != MCDisassembler::Fail) { 740 Size = 4; 741 Check(result, AddThumbPredicate(MI)); 742 return result; 743 } 744 745 MI.clear(); 746 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 747 if (result != MCDisassembler::Fail) { 748 Size = 4; 749 UpdateThumbVFPPredicate(MI); 750 return result; 751 } 752 753 MI.clear(); 754 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 755 this, STI); 756 if (result != MCDisassembler::Fail) { 757 Size = 4; 758 Check(result, AddThumbPredicate(MI)); 759 return result; 760 } 761 762 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 763 MI.clear(); 764 uint32_t NEONLdStInsn = insn32; 765 NEONLdStInsn &= 0xF0FFFFFF; 766 NEONLdStInsn |= 0x04000000; 767 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 768 Address, this, STI); 769 if (result != MCDisassembler::Fail) { 770 Size = 4; 771 Check(result, AddThumbPredicate(MI)); 772 return result; 773 } 774 } 775 776 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 777 MI.clear(); 778 uint32_t NEONDataInsn = insn32; 779 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 780 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 781 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 782 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 783 Address, this, STI); 784 if (result != MCDisassembler::Fail) { 785 Size = 4; 786 Check(result, AddThumbPredicate(MI)); 787 return result; 788 } 789 } 790 791 Size = 0; 792 return MCDisassembler::Fail; 793 } 794 795 796 extern "C" void LLVMInitializeARMDisassembler() { 797 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 798 createARMDisassembler); 799 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 800 createThumbDisassembler); 801 } 802 803 static const uint16_t GPRDecoderTable[] = { 804 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 805 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 806 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 807 ARM::R12, ARM::SP, ARM::LR, ARM::PC 808 }; 809 810 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 811 uint64_t Address, const void *Decoder) { 812 if (RegNo > 15) 813 return MCDisassembler::Fail; 814 815 unsigned Register = GPRDecoderTable[RegNo]; 816 Inst.addOperand(MCOperand::CreateReg(Register)); 817 return MCDisassembler::Success; 818 } 819 820 static DecodeStatus 821 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = MCDisassembler::Success; 824 825 if (RegNo == 15) 826 S = MCDisassembler::SoftFail; 827 828 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 829 830 return S; 831 } 832 833 static DecodeStatus 834 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 835 uint64_t Address, const void *Decoder) { 836 DecodeStatus S = MCDisassembler::Success; 837 838 if (RegNo == 15) 839 { 840 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 841 return MCDisassembler::Success; 842 } 843 844 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 845 return S; 846 } 847 848 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 849 uint64_t Address, const void *Decoder) { 850 if (RegNo > 7) 851 return MCDisassembler::Fail; 852 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 853 } 854 855 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 856 uint64_t Address, const void *Decoder) { 857 unsigned Register = 0; 858 switch (RegNo) { 859 case 0: 860 Register = ARM::R0; 861 break; 862 case 1: 863 Register = ARM::R1; 864 break; 865 case 2: 866 Register = ARM::R2; 867 break; 868 case 3: 869 Register = ARM::R3; 870 break; 871 case 9: 872 Register = ARM::R9; 873 break; 874 case 12: 875 Register = ARM::R12; 876 break; 877 default: 878 return MCDisassembler::Fail; 879 } 880 881 Inst.addOperand(MCOperand::CreateReg(Register)); 882 return MCDisassembler::Success; 883 } 884 885 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 886 uint64_t Address, const void *Decoder) { 887 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 888 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 889 } 890 891 static const uint16_t SPRDecoderTable[] = { 892 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 893 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 894 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 895 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 896 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 897 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 898 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 899 ARM::S28, ARM::S29, ARM::S30, ARM::S31 900 }; 901 902 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 903 uint64_t Address, const void *Decoder) { 904 if (RegNo > 31) 905 return MCDisassembler::Fail; 906 907 unsigned Register = SPRDecoderTable[RegNo]; 908 Inst.addOperand(MCOperand::CreateReg(Register)); 909 return MCDisassembler::Success; 910 } 911 912 static const uint16_t DPRDecoderTable[] = { 913 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 914 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 915 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 916 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 917 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 918 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 919 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 920 ARM::D28, ARM::D29, ARM::D30, ARM::D31 921 }; 922 923 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 31) 926 return MCDisassembler::Fail; 927 928 unsigned Register = DPRDecoderTable[RegNo]; 929 Inst.addOperand(MCOperand::CreateReg(Register)); 930 return MCDisassembler::Success; 931 } 932 933 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 934 uint64_t Address, const void *Decoder) { 935 if (RegNo > 7) 936 return MCDisassembler::Fail; 937 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 938 } 939 940 static DecodeStatus 941 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) { 943 if (RegNo > 15) 944 return MCDisassembler::Fail; 945 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 946 } 947 948 static const uint16_t QPRDecoderTable[] = { 949 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 950 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 951 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 952 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 953 }; 954 955 956 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 957 uint64_t Address, const void *Decoder) { 958 if (RegNo > 31 || (RegNo & 1) != 0) 959 return MCDisassembler::Fail; 960 RegNo >>= 1; 961 962 unsigned Register = QPRDecoderTable[RegNo]; 963 Inst.addOperand(MCOperand::CreateReg(Register)); 964 return MCDisassembler::Success; 965 } 966 967 static const uint16_t DPairDecoderTable[] = { 968 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 969 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 970 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 971 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 972 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 973 ARM::Q15 974 }; 975 976 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 if (RegNo > 30) 979 return MCDisassembler::Fail; 980 981 unsigned Register = DPairDecoderTable[RegNo]; 982 Inst.addOperand(MCOperand::CreateReg(Register)); 983 return MCDisassembler::Success; 984 } 985 986 static const uint16_t DPairSpacedDecoderTable[] = { 987 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 988 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 989 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 990 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 991 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 992 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 993 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 994 ARM::D28_D30, ARM::D29_D31 995 }; 996 997 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 998 unsigned RegNo, 999 uint64_t Address, 1000 const void *Decoder) { 1001 if (RegNo > 29) 1002 return MCDisassembler::Fail; 1003 1004 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1005 Inst.addOperand(MCOperand::CreateReg(Register)); 1006 return MCDisassembler::Success; 1007 } 1008 1009 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1010 uint64_t Address, const void *Decoder) { 1011 if (Val == 0xF) return MCDisassembler::Fail; 1012 // AL predicate is not allowed on Thumb1 branches. 1013 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1014 return MCDisassembler::Fail; 1015 Inst.addOperand(MCOperand::CreateImm(Val)); 1016 if (Val == ARMCC::AL) { 1017 Inst.addOperand(MCOperand::CreateReg(0)); 1018 } else 1019 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1020 return MCDisassembler::Success; 1021 } 1022 1023 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1024 uint64_t Address, const void *Decoder) { 1025 if (Val) 1026 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1027 else 1028 Inst.addOperand(MCOperand::CreateReg(0)); 1029 return MCDisassembler::Success; 1030 } 1031 1032 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1033 uint64_t Address, const void *Decoder) { 1034 uint32_t imm = Val & 0xFF; 1035 uint32_t rot = (Val & 0xF00) >> 7; 1036 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1037 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1038 return MCDisassembler::Success; 1039 } 1040 1041 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1042 uint64_t Address, const void *Decoder) { 1043 DecodeStatus S = MCDisassembler::Success; 1044 1045 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1046 unsigned type = fieldFromInstruction(Val, 5, 2); 1047 unsigned imm = fieldFromInstruction(Val, 7, 5); 1048 1049 // Register-immediate 1050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1051 return MCDisassembler::Fail; 1052 1053 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1054 switch (type) { 1055 case 0: 1056 Shift = ARM_AM::lsl; 1057 break; 1058 case 1: 1059 Shift = ARM_AM::lsr; 1060 break; 1061 case 2: 1062 Shift = ARM_AM::asr; 1063 break; 1064 case 3: 1065 Shift = ARM_AM::ror; 1066 break; 1067 } 1068 1069 if (Shift == ARM_AM::ror && imm == 0) 1070 Shift = ARM_AM::rrx; 1071 1072 unsigned Op = Shift | (imm << 3); 1073 Inst.addOperand(MCOperand::CreateImm(Op)); 1074 1075 return S; 1076 } 1077 1078 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1079 uint64_t Address, const void *Decoder) { 1080 DecodeStatus S = MCDisassembler::Success; 1081 1082 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1083 unsigned type = fieldFromInstruction(Val, 5, 2); 1084 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1085 1086 // Register-register 1087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1088 return MCDisassembler::Fail; 1089 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1090 return MCDisassembler::Fail; 1091 1092 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1093 switch (type) { 1094 case 0: 1095 Shift = ARM_AM::lsl; 1096 break; 1097 case 1: 1098 Shift = ARM_AM::lsr; 1099 break; 1100 case 2: 1101 Shift = ARM_AM::asr; 1102 break; 1103 case 3: 1104 Shift = ARM_AM::ror; 1105 break; 1106 } 1107 1108 Inst.addOperand(MCOperand::CreateImm(Shift)); 1109 1110 return S; 1111 } 1112 1113 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1114 uint64_t Address, const void *Decoder) { 1115 DecodeStatus S = MCDisassembler::Success; 1116 1117 bool writebackLoad = false; 1118 unsigned writebackReg = 0; 1119 switch (Inst.getOpcode()) { 1120 default: 1121 break; 1122 case ARM::LDMIA_UPD: 1123 case ARM::LDMDB_UPD: 1124 case ARM::LDMIB_UPD: 1125 case ARM::LDMDA_UPD: 1126 case ARM::t2LDMIA_UPD: 1127 case ARM::t2LDMDB_UPD: 1128 writebackLoad = true; 1129 writebackReg = Inst.getOperand(0).getReg(); 1130 break; 1131 } 1132 1133 // Empty register lists are not allowed. 1134 if (Val == 0) return MCDisassembler::Fail; 1135 for (unsigned i = 0; i < 16; ++i) { 1136 if (Val & (1 << i)) { 1137 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1138 return MCDisassembler::Fail; 1139 // Writeback not allowed if Rn is in the target list. 1140 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1141 Check(S, MCDisassembler::SoftFail); 1142 } 1143 } 1144 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1153 unsigned regs = fieldFromInstruction(Val, 0, 8); 1154 1155 // In case of unpredictable encoding, tweak the operands. 1156 if (regs == 0 || (Vd + regs) > 32) { 1157 regs = Vd + regs > 32 ? 32 - Vd : regs; 1158 regs = std::max( 1u, regs); 1159 S = MCDisassembler::SoftFail; 1160 } 1161 1162 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 for (unsigned i = 0; i < (regs - 1); ++i) { 1165 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1166 return MCDisassembler::Fail; 1167 } 1168 1169 return S; 1170 } 1171 1172 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1173 uint64_t Address, const void *Decoder) { 1174 DecodeStatus S = MCDisassembler::Success; 1175 1176 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1177 unsigned regs = fieldFromInstruction(Val, 1, 7); 1178 1179 // In case of unpredictable encoding, tweak the operands. 1180 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1181 regs = Vd + regs > 32 ? 32 - Vd : regs; 1182 regs = std::max( 1u, regs); 1183 regs = std::min(16u, regs); 1184 S = MCDisassembler::SoftFail; 1185 } 1186 1187 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1188 return MCDisassembler::Fail; 1189 for (unsigned i = 0; i < (regs - 1); ++i) { 1190 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1191 return MCDisassembler::Fail; 1192 } 1193 1194 return S; 1195 } 1196 1197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1198 uint64_t Address, const void *Decoder) { 1199 // This operand encodes a mask of contiguous zeros between a specified MSB 1200 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1201 // the mask of all bits LSB-and-lower, and then xor them to create 1202 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1203 // create the final mask. 1204 unsigned msb = fieldFromInstruction(Val, 5, 5); 1205 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1206 1207 DecodeStatus S = MCDisassembler::Success; 1208 if (lsb > msb) { 1209 Check(S, MCDisassembler::SoftFail); 1210 // The check above will cause the warning for the "potentially undefined 1211 // instruction encoding" but we can't build a bad MCOperand value here 1212 // with a lsb > msb or else printing the MCInst will cause a crash. 1213 lsb = msb; 1214 } 1215 1216 uint32_t msb_mask = 0xFFFFFFFF; 1217 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1218 uint32_t lsb_mask = (1U << lsb) - 1; 1219 1220 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1221 return S; 1222 } 1223 1224 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1225 uint64_t Address, const void *Decoder) { 1226 DecodeStatus S = MCDisassembler::Success; 1227 1228 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1229 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1230 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1231 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1233 unsigned U = fieldFromInstruction(Insn, 23, 1); 1234 1235 switch (Inst.getOpcode()) { 1236 case ARM::LDC_OFFSET: 1237 case ARM::LDC_PRE: 1238 case ARM::LDC_POST: 1239 case ARM::LDC_OPTION: 1240 case ARM::LDCL_OFFSET: 1241 case ARM::LDCL_PRE: 1242 case ARM::LDCL_POST: 1243 case ARM::LDCL_OPTION: 1244 case ARM::STC_OFFSET: 1245 case ARM::STC_PRE: 1246 case ARM::STC_POST: 1247 case ARM::STC_OPTION: 1248 case ARM::STCL_OFFSET: 1249 case ARM::STCL_PRE: 1250 case ARM::STCL_POST: 1251 case ARM::STCL_OPTION: 1252 case ARM::t2LDC_OFFSET: 1253 case ARM::t2LDC_PRE: 1254 case ARM::t2LDC_POST: 1255 case ARM::t2LDC_OPTION: 1256 case ARM::t2LDCL_OFFSET: 1257 case ARM::t2LDCL_PRE: 1258 case ARM::t2LDCL_POST: 1259 case ARM::t2LDCL_OPTION: 1260 case ARM::t2STC_OFFSET: 1261 case ARM::t2STC_PRE: 1262 case ARM::t2STC_POST: 1263 case ARM::t2STC_OPTION: 1264 case ARM::t2STCL_OFFSET: 1265 case ARM::t2STCL_PRE: 1266 case ARM::t2STCL_POST: 1267 case ARM::t2STCL_OPTION: 1268 if (coproc == 0xA || coproc == 0xB) 1269 return MCDisassembler::Fail; 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 Inst.addOperand(MCOperand::CreateImm(coproc)); 1276 Inst.addOperand(MCOperand::CreateImm(CRd)); 1277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1278 return MCDisassembler::Fail; 1279 1280 switch (Inst.getOpcode()) { 1281 case ARM::t2LDC2_OFFSET: 1282 case ARM::t2LDC2L_OFFSET: 1283 case ARM::t2LDC2_PRE: 1284 case ARM::t2LDC2L_PRE: 1285 case ARM::t2STC2_OFFSET: 1286 case ARM::t2STC2L_OFFSET: 1287 case ARM::t2STC2_PRE: 1288 case ARM::t2STC2L_PRE: 1289 case ARM::LDC2_OFFSET: 1290 case ARM::LDC2L_OFFSET: 1291 case ARM::LDC2_PRE: 1292 case ARM::LDC2L_PRE: 1293 case ARM::STC2_OFFSET: 1294 case ARM::STC2L_OFFSET: 1295 case ARM::STC2_PRE: 1296 case ARM::STC2L_PRE: 1297 case ARM::t2LDC_OFFSET: 1298 case ARM::t2LDCL_OFFSET: 1299 case ARM::t2LDC_PRE: 1300 case ARM::t2LDCL_PRE: 1301 case ARM::t2STC_OFFSET: 1302 case ARM::t2STCL_OFFSET: 1303 case ARM::t2STC_PRE: 1304 case ARM::t2STCL_PRE: 1305 case ARM::LDC_OFFSET: 1306 case ARM::LDCL_OFFSET: 1307 case ARM::LDC_PRE: 1308 case ARM::LDCL_PRE: 1309 case ARM::STC_OFFSET: 1310 case ARM::STCL_OFFSET: 1311 case ARM::STC_PRE: 1312 case ARM::STCL_PRE: 1313 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1314 Inst.addOperand(MCOperand::CreateImm(imm)); 1315 break; 1316 case ARM::t2LDC2_POST: 1317 case ARM::t2LDC2L_POST: 1318 case ARM::t2STC2_POST: 1319 case ARM::t2STC2L_POST: 1320 case ARM::LDC2_POST: 1321 case ARM::LDC2L_POST: 1322 case ARM::STC2_POST: 1323 case ARM::STC2L_POST: 1324 case ARM::t2LDC_POST: 1325 case ARM::t2LDCL_POST: 1326 case ARM::t2STC_POST: 1327 case ARM::t2STCL_POST: 1328 case ARM::LDC_POST: 1329 case ARM::LDCL_POST: 1330 case ARM::STC_POST: 1331 case ARM::STCL_POST: 1332 imm |= U << 8; 1333 // fall through. 1334 default: 1335 // The 'option' variant doesn't encode 'U' in the immediate since 1336 // the immediate is unsigned [0,255]. 1337 Inst.addOperand(MCOperand::CreateImm(imm)); 1338 break; 1339 } 1340 1341 switch (Inst.getOpcode()) { 1342 case ARM::LDC_OFFSET: 1343 case ARM::LDC_PRE: 1344 case ARM::LDC_POST: 1345 case ARM::LDC_OPTION: 1346 case ARM::LDCL_OFFSET: 1347 case ARM::LDCL_PRE: 1348 case ARM::LDCL_POST: 1349 case ARM::LDCL_OPTION: 1350 case ARM::STC_OFFSET: 1351 case ARM::STC_PRE: 1352 case ARM::STC_POST: 1353 case ARM::STC_OPTION: 1354 case ARM::STCL_OFFSET: 1355 case ARM::STCL_PRE: 1356 case ARM::STCL_POST: 1357 case ARM::STCL_OPTION: 1358 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1359 return MCDisassembler::Fail; 1360 break; 1361 default: 1362 break; 1363 } 1364 1365 return S; 1366 } 1367 1368 static DecodeStatus 1369 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1370 uint64_t Address, const void *Decoder) { 1371 DecodeStatus S = MCDisassembler::Success; 1372 1373 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1374 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1375 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1376 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1377 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1378 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1379 unsigned P = fieldFromInstruction(Insn, 24, 1); 1380 unsigned W = fieldFromInstruction(Insn, 21, 1); 1381 1382 // On stores, the writeback operand precedes Rt. 1383 switch (Inst.getOpcode()) { 1384 case ARM::STR_POST_IMM: 1385 case ARM::STR_POST_REG: 1386 case ARM::STRB_POST_IMM: 1387 case ARM::STRB_POST_REG: 1388 case ARM::STRT_POST_REG: 1389 case ARM::STRT_POST_IMM: 1390 case ARM::STRBT_POST_REG: 1391 case ARM::STRBT_POST_IMM: 1392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1393 return MCDisassembler::Fail; 1394 break; 1395 default: 1396 break; 1397 } 1398 1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 1402 // On loads, the writeback operand comes after Rt. 1403 switch (Inst.getOpcode()) { 1404 case ARM::LDR_POST_IMM: 1405 case ARM::LDR_POST_REG: 1406 case ARM::LDRB_POST_IMM: 1407 case ARM::LDRB_POST_REG: 1408 case ARM::LDRBT_POST_REG: 1409 case ARM::LDRBT_POST_IMM: 1410 case ARM::LDRT_POST_REG: 1411 case ARM::LDRT_POST_IMM: 1412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1413 return MCDisassembler::Fail; 1414 break; 1415 default: 1416 break; 1417 } 1418 1419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1420 return MCDisassembler::Fail; 1421 1422 ARM_AM::AddrOpc Op = ARM_AM::add; 1423 if (!fieldFromInstruction(Insn, 23, 1)) 1424 Op = ARM_AM::sub; 1425 1426 bool writeback = (P == 0) || (W == 1); 1427 unsigned idx_mode = 0; 1428 if (P && writeback) 1429 idx_mode = ARMII::IndexModePre; 1430 else if (!P && writeback) 1431 idx_mode = ARMII::IndexModePost; 1432 1433 if (writeback && (Rn == 15 || Rn == Rt)) 1434 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1435 1436 if (reg) { 1437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1438 return MCDisassembler::Fail; 1439 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1440 switch( fieldFromInstruction(Insn, 5, 2)) { 1441 case 0: 1442 Opc = ARM_AM::lsl; 1443 break; 1444 case 1: 1445 Opc = ARM_AM::lsr; 1446 break; 1447 case 2: 1448 Opc = ARM_AM::asr; 1449 break; 1450 case 3: 1451 Opc = ARM_AM::ror; 1452 break; 1453 default: 1454 return MCDisassembler::Fail; 1455 } 1456 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1457 if (Opc == ARM_AM::ror && amt == 0) 1458 Opc = ARM_AM::rrx; 1459 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1460 1461 Inst.addOperand(MCOperand::CreateImm(imm)); 1462 } else { 1463 Inst.addOperand(MCOperand::CreateReg(0)); 1464 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1465 Inst.addOperand(MCOperand::CreateImm(tmp)); 1466 } 1467 1468 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1469 return MCDisassembler::Fail; 1470 1471 return S; 1472 } 1473 1474 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1475 uint64_t Address, const void *Decoder) { 1476 DecodeStatus S = MCDisassembler::Success; 1477 1478 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1479 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1480 unsigned type = fieldFromInstruction(Val, 5, 2); 1481 unsigned imm = fieldFromInstruction(Val, 7, 5); 1482 unsigned U = fieldFromInstruction(Val, 12, 1); 1483 1484 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1485 switch (type) { 1486 case 0: 1487 ShOp = ARM_AM::lsl; 1488 break; 1489 case 1: 1490 ShOp = ARM_AM::lsr; 1491 break; 1492 case 2: 1493 ShOp = ARM_AM::asr; 1494 break; 1495 case 3: 1496 ShOp = ARM_AM::ror; 1497 break; 1498 } 1499 1500 if (ShOp == ARM_AM::ror && imm == 0) 1501 ShOp = ARM_AM::rrx; 1502 1503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 unsigned shift; 1508 if (U) 1509 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1510 else 1511 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1512 Inst.addOperand(MCOperand::CreateImm(shift)); 1513 1514 return S; 1515 } 1516 1517 static DecodeStatus 1518 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1519 uint64_t Address, const void *Decoder) { 1520 DecodeStatus S = MCDisassembler::Success; 1521 1522 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1523 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1524 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1525 unsigned type = fieldFromInstruction(Insn, 22, 1); 1526 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1527 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1528 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1529 unsigned W = fieldFromInstruction(Insn, 21, 1); 1530 unsigned P = fieldFromInstruction(Insn, 24, 1); 1531 unsigned Rt2 = Rt + 1; 1532 1533 bool writeback = (W == 1) | (P == 0); 1534 1535 // For {LD,ST}RD, Rt must be even, else undefined. 1536 switch (Inst.getOpcode()) { 1537 case ARM::STRD: 1538 case ARM::STRD_PRE: 1539 case ARM::STRD_POST: 1540 case ARM::LDRD: 1541 case ARM::LDRD_PRE: 1542 case ARM::LDRD_POST: 1543 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1544 break; 1545 default: 1546 break; 1547 } 1548 switch (Inst.getOpcode()) { 1549 case ARM::STRD: 1550 case ARM::STRD_PRE: 1551 case ARM::STRD_POST: 1552 if (P == 0 && W == 1) 1553 S = MCDisassembler::SoftFail; 1554 1555 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1556 S = MCDisassembler::SoftFail; 1557 if (type && Rm == 15) 1558 S = MCDisassembler::SoftFail; 1559 if (Rt2 == 15) 1560 S = MCDisassembler::SoftFail; 1561 if (!type && fieldFromInstruction(Insn, 8, 4)) 1562 S = MCDisassembler::SoftFail; 1563 break; 1564 case ARM::STRH: 1565 case ARM::STRH_PRE: 1566 case ARM::STRH_POST: 1567 if (Rt == 15) 1568 S = MCDisassembler::SoftFail; 1569 if (writeback && (Rn == 15 || Rn == Rt)) 1570 S = MCDisassembler::SoftFail; 1571 if (!type && Rm == 15) 1572 S = MCDisassembler::SoftFail; 1573 break; 1574 case ARM::LDRD: 1575 case ARM::LDRD_PRE: 1576 case ARM::LDRD_POST: 1577 if (type && Rn == 15){ 1578 if (Rt2 == 15) 1579 S = MCDisassembler::SoftFail; 1580 break; 1581 } 1582 if (P == 0 && W == 1) 1583 S = MCDisassembler::SoftFail; 1584 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1585 S = MCDisassembler::SoftFail; 1586 if (!type && writeback && Rn == 15) 1587 S = MCDisassembler::SoftFail; 1588 if (writeback && (Rn == Rt || Rn == Rt2)) 1589 S = MCDisassembler::SoftFail; 1590 break; 1591 case ARM::LDRH: 1592 case ARM::LDRH_PRE: 1593 case ARM::LDRH_POST: 1594 if (type && Rn == 15){ 1595 if (Rt == 15) 1596 S = MCDisassembler::SoftFail; 1597 break; 1598 } 1599 if (Rt == 15) 1600 S = MCDisassembler::SoftFail; 1601 if (!type && Rm == 15) 1602 S = MCDisassembler::SoftFail; 1603 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1604 S = MCDisassembler::SoftFail; 1605 break; 1606 case ARM::LDRSH: 1607 case ARM::LDRSH_PRE: 1608 case ARM::LDRSH_POST: 1609 case ARM::LDRSB: 1610 case ARM::LDRSB_PRE: 1611 case ARM::LDRSB_POST: 1612 if (type && Rn == 15){ 1613 if (Rt == 15) 1614 S = MCDisassembler::SoftFail; 1615 break; 1616 } 1617 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1618 S = MCDisassembler::SoftFail; 1619 if (!type && (Rt == 15 || Rm == 15)) 1620 S = MCDisassembler::SoftFail; 1621 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1622 S = MCDisassembler::SoftFail; 1623 break; 1624 default: 1625 break; 1626 } 1627 1628 if (writeback) { // Writeback 1629 if (P) 1630 U |= ARMII::IndexModePre << 9; 1631 else 1632 U |= ARMII::IndexModePost << 9; 1633 1634 // On stores, the writeback operand precedes Rt. 1635 switch (Inst.getOpcode()) { 1636 case ARM::STRD: 1637 case ARM::STRD_PRE: 1638 case ARM::STRD_POST: 1639 case ARM::STRH: 1640 case ARM::STRH_PRE: 1641 case ARM::STRH_POST: 1642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1643 return MCDisassembler::Fail; 1644 break; 1645 default: 1646 break; 1647 } 1648 } 1649 1650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1651 return MCDisassembler::Fail; 1652 switch (Inst.getOpcode()) { 1653 case ARM::STRD: 1654 case ARM::STRD_PRE: 1655 case ARM::STRD_POST: 1656 case ARM::LDRD: 1657 case ARM::LDRD_PRE: 1658 case ARM::LDRD_POST: 1659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1660 return MCDisassembler::Fail; 1661 break; 1662 default: 1663 break; 1664 } 1665 1666 if (writeback) { 1667 // On loads, the writeback operand comes after Rt. 1668 switch (Inst.getOpcode()) { 1669 case ARM::LDRD: 1670 case ARM::LDRD_PRE: 1671 case ARM::LDRD_POST: 1672 case ARM::LDRH: 1673 case ARM::LDRH_PRE: 1674 case ARM::LDRH_POST: 1675 case ARM::LDRSH: 1676 case ARM::LDRSH_PRE: 1677 case ARM::LDRSH_POST: 1678 case ARM::LDRSB: 1679 case ARM::LDRSB_PRE: 1680 case ARM::LDRSB_POST: 1681 case ARM::LDRHTr: 1682 case ARM::LDRSBTr: 1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1684 return MCDisassembler::Fail; 1685 break; 1686 default: 1687 break; 1688 } 1689 } 1690 1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1692 return MCDisassembler::Fail; 1693 1694 if (type) { 1695 Inst.addOperand(MCOperand::CreateReg(0)); 1696 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1697 } else { 1698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1699 return MCDisassembler::Fail; 1700 Inst.addOperand(MCOperand::CreateImm(U)); 1701 } 1702 1703 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1704 return MCDisassembler::Fail; 1705 1706 return S; 1707 } 1708 1709 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1710 uint64_t Address, const void *Decoder) { 1711 DecodeStatus S = MCDisassembler::Success; 1712 1713 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1714 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1715 1716 switch (mode) { 1717 case 0: 1718 mode = ARM_AM::da; 1719 break; 1720 case 1: 1721 mode = ARM_AM::ia; 1722 break; 1723 case 2: 1724 mode = ARM_AM::db; 1725 break; 1726 case 3: 1727 mode = ARM_AM::ib; 1728 break; 1729 } 1730 1731 Inst.addOperand(MCOperand::CreateImm(mode)); 1732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1733 return MCDisassembler::Fail; 1734 1735 return S; 1736 } 1737 1738 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1739 uint64_t Address, const void *Decoder) { 1740 DecodeStatus S = MCDisassembler::Success; 1741 1742 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1743 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1744 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1745 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1746 1747 if (pred == 0xF) 1748 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1749 1750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1751 return MCDisassembler::Fail; 1752 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1755 return MCDisassembler::Fail; 1756 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1757 return MCDisassembler::Fail; 1758 return S; 1759 } 1760 1761 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1762 unsigned Insn, 1763 uint64_t Address, const void *Decoder) { 1764 DecodeStatus S = MCDisassembler::Success; 1765 1766 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1767 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1768 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1769 1770 if (pred == 0xF) { 1771 switch (Inst.getOpcode()) { 1772 case ARM::LDMDA: 1773 Inst.setOpcode(ARM::RFEDA); 1774 break; 1775 case ARM::LDMDA_UPD: 1776 Inst.setOpcode(ARM::RFEDA_UPD); 1777 break; 1778 case ARM::LDMDB: 1779 Inst.setOpcode(ARM::RFEDB); 1780 break; 1781 case ARM::LDMDB_UPD: 1782 Inst.setOpcode(ARM::RFEDB_UPD); 1783 break; 1784 case ARM::LDMIA: 1785 Inst.setOpcode(ARM::RFEIA); 1786 break; 1787 case ARM::LDMIA_UPD: 1788 Inst.setOpcode(ARM::RFEIA_UPD); 1789 break; 1790 case ARM::LDMIB: 1791 Inst.setOpcode(ARM::RFEIB); 1792 break; 1793 case ARM::LDMIB_UPD: 1794 Inst.setOpcode(ARM::RFEIB_UPD); 1795 break; 1796 case ARM::STMDA: 1797 Inst.setOpcode(ARM::SRSDA); 1798 break; 1799 case ARM::STMDA_UPD: 1800 Inst.setOpcode(ARM::SRSDA_UPD); 1801 break; 1802 case ARM::STMDB: 1803 Inst.setOpcode(ARM::SRSDB); 1804 break; 1805 case ARM::STMDB_UPD: 1806 Inst.setOpcode(ARM::SRSDB_UPD); 1807 break; 1808 case ARM::STMIA: 1809 Inst.setOpcode(ARM::SRSIA); 1810 break; 1811 case ARM::STMIA_UPD: 1812 Inst.setOpcode(ARM::SRSIA_UPD); 1813 break; 1814 case ARM::STMIB: 1815 Inst.setOpcode(ARM::SRSIB); 1816 break; 1817 case ARM::STMIB_UPD: 1818 Inst.setOpcode(ARM::SRSIB_UPD); 1819 break; 1820 default: 1821 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1822 } 1823 1824 // For stores (which become SRS's, the only operand is the mode. 1825 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1826 Inst.addOperand( 1827 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1828 return S; 1829 } 1830 1831 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1832 } 1833 1834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1835 return MCDisassembler::Fail; 1836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1837 return MCDisassembler::Fail; // Tied 1838 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 1843 return S; 1844 } 1845 1846 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1847 uint64_t Address, const void *Decoder) { 1848 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1849 unsigned M = fieldFromInstruction(Insn, 17, 1); 1850 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1851 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1852 1853 DecodeStatus S = MCDisassembler::Success; 1854 1855 // This decoder is called from multiple location that do not check 1856 // the full encoding is valid before they do. 1857 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1858 fieldFromInstruction(Insn, 16, 1) != 0 || 1859 fieldFromInstruction(Insn, 20, 8) != 0x10) 1860 return MCDisassembler::Fail; 1861 1862 // imod == '01' --> UNPREDICTABLE 1863 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1864 // return failure here. The '01' imod value is unprintable, so there's 1865 // nothing useful we could do even if we returned UNPREDICTABLE. 1866 1867 if (imod == 1) return MCDisassembler::Fail; 1868 1869 if (imod && M) { 1870 Inst.setOpcode(ARM::CPS3p); 1871 Inst.addOperand(MCOperand::CreateImm(imod)); 1872 Inst.addOperand(MCOperand::CreateImm(iflags)); 1873 Inst.addOperand(MCOperand::CreateImm(mode)); 1874 } else if (imod && !M) { 1875 Inst.setOpcode(ARM::CPS2p); 1876 Inst.addOperand(MCOperand::CreateImm(imod)); 1877 Inst.addOperand(MCOperand::CreateImm(iflags)); 1878 if (mode) S = MCDisassembler::SoftFail; 1879 } else if (!imod && M) { 1880 Inst.setOpcode(ARM::CPS1p); 1881 Inst.addOperand(MCOperand::CreateImm(mode)); 1882 if (iflags) S = MCDisassembler::SoftFail; 1883 } else { 1884 // imod == '00' && M == '0' --> UNPREDICTABLE 1885 Inst.setOpcode(ARM::CPS1p); 1886 Inst.addOperand(MCOperand::CreateImm(mode)); 1887 S = MCDisassembler::SoftFail; 1888 } 1889 1890 return S; 1891 } 1892 1893 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1894 uint64_t Address, const void *Decoder) { 1895 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1896 unsigned M = fieldFromInstruction(Insn, 8, 1); 1897 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1898 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1899 1900 DecodeStatus S = MCDisassembler::Success; 1901 1902 // imod == '01' --> UNPREDICTABLE 1903 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1904 // return failure here. The '01' imod value is unprintable, so there's 1905 // nothing useful we could do even if we returned UNPREDICTABLE. 1906 1907 if (imod == 1) return MCDisassembler::Fail; 1908 1909 if (imod && M) { 1910 Inst.setOpcode(ARM::t2CPS3p); 1911 Inst.addOperand(MCOperand::CreateImm(imod)); 1912 Inst.addOperand(MCOperand::CreateImm(iflags)); 1913 Inst.addOperand(MCOperand::CreateImm(mode)); 1914 } else if (imod && !M) { 1915 Inst.setOpcode(ARM::t2CPS2p); 1916 Inst.addOperand(MCOperand::CreateImm(imod)); 1917 Inst.addOperand(MCOperand::CreateImm(iflags)); 1918 if (mode) S = MCDisassembler::SoftFail; 1919 } else if (!imod && M) { 1920 Inst.setOpcode(ARM::t2CPS1p); 1921 Inst.addOperand(MCOperand::CreateImm(mode)); 1922 if (iflags) S = MCDisassembler::SoftFail; 1923 } else { 1924 // imod == '00' && M == '0' --> this is a HINT instruction 1925 int imm = fieldFromInstruction(Insn, 0, 8); 1926 // HINT are defined only for immediate in [0..4] 1927 if(imm > 4) return MCDisassembler::Fail; 1928 Inst.setOpcode(ARM::t2HINT); 1929 Inst.addOperand(MCOperand::CreateImm(imm)); 1930 } 1931 1932 return S; 1933 } 1934 1935 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1936 uint64_t Address, const void *Decoder) { 1937 DecodeStatus S = MCDisassembler::Success; 1938 1939 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1940 unsigned imm = 0; 1941 1942 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1943 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1944 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1945 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1946 1947 if (Inst.getOpcode() == ARM::t2MOVTi16) 1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1951 return MCDisassembler::Fail; 1952 1953 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1954 Inst.addOperand(MCOperand::CreateImm(imm)); 1955 1956 return S; 1957 } 1958 1959 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1960 uint64_t Address, const void *Decoder) { 1961 DecodeStatus S = MCDisassembler::Success; 1962 1963 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1964 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1965 unsigned imm = 0; 1966 1967 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 1968 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1969 1970 if (Inst.getOpcode() == ARM::MOVTi16) 1971 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1972 return MCDisassembler::Fail; 1973 1974 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1975 return MCDisassembler::Fail; 1976 1977 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1978 Inst.addOperand(MCOperand::CreateImm(imm)); 1979 1980 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 1983 return S; 1984 } 1985 1986 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1987 uint64_t Address, const void *Decoder) { 1988 DecodeStatus S = MCDisassembler::Success; 1989 1990 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 1991 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 1992 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 1993 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 1994 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1995 1996 if (pred == 0xF) 1997 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1998 1999 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2000 return MCDisassembler::Fail; 2001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2002 return MCDisassembler::Fail; 2003 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2004 return MCDisassembler::Fail; 2005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2006 return MCDisassembler::Fail; 2007 2008 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2009 return MCDisassembler::Fail; 2010 2011 return S; 2012 } 2013 2014 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2015 uint64_t Address, const void *Decoder) { 2016 DecodeStatus S = MCDisassembler::Success; 2017 2018 unsigned add = fieldFromInstruction(Val, 12, 1); 2019 unsigned imm = fieldFromInstruction(Val, 0, 12); 2020 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2021 2022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2023 return MCDisassembler::Fail; 2024 2025 if (!add) imm *= -1; 2026 if (imm == 0 && !add) imm = INT32_MIN; 2027 Inst.addOperand(MCOperand::CreateImm(imm)); 2028 if (Rn == 15) 2029 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2030 2031 return S; 2032 } 2033 2034 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2035 uint64_t Address, const void *Decoder) { 2036 DecodeStatus S = MCDisassembler::Success; 2037 2038 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2039 unsigned U = fieldFromInstruction(Val, 8, 1); 2040 unsigned imm = fieldFromInstruction(Val, 0, 8); 2041 2042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2043 return MCDisassembler::Fail; 2044 2045 if (U) 2046 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2047 else 2048 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2049 2050 return S; 2051 } 2052 2053 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2054 uint64_t Address, const void *Decoder) { 2055 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2056 } 2057 2058 static DecodeStatus 2059 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2060 uint64_t Address, const void *Decoder) { 2061 DecodeStatus Status = MCDisassembler::Success; 2062 2063 // Note the J1 and J2 values are from the encoded instruction. So here 2064 // change them to I1 and I2 values via as documented: 2065 // I1 = NOT(J1 EOR S); 2066 // I2 = NOT(J2 EOR S); 2067 // and build the imm32 with one trailing zero as documented: 2068 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2069 unsigned S = fieldFromInstruction(Insn, 26, 1); 2070 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2071 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2072 unsigned I1 = !(J1 ^ S); 2073 unsigned I2 = !(J2 ^ S); 2074 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2075 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2076 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2077 int imm32 = SignExtend32<24>(tmp << 1); 2078 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2079 true, 4, Inst, Decoder)) 2080 Inst.addOperand(MCOperand::CreateImm(imm32)); 2081 2082 return Status; 2083 } 2084 2085 static DecodeStatus 2086 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2087 uint64_t Address, const void *Decoder) { 2088 DecodeStatus S = MCDisassembler::Success; 2089 2090 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2091 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2092 2093 if (pred == 0xF) { 2094 Inst.setOpcode(ARM::BLXi); 2095 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2096 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2097 true, 4, Inst, Decoder)) 2098 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2099 return S; 2100 } 2101 2102 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2103 true, 4, Inst, Decoder)) 2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2105 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 2108 return S; 2109 } 2110 2111 2112 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2113 uint64_t Address, const void *Decoder) { 2114 DecodeStatus S = MCDisassembler::Success; 2115 2116 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2117 unsigned align = fieldFromInstruction(Val, 4, 2); 2118 2119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 if (!align) 2122 Inst.addOperand(MCOperand::CreateImm(0)); 2123 else 2124 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2125 2126 return S; 2127 } 2128 2129 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2130 uint64_t Address, const void *Decoder) { 2131 DecodeStatus S = MCDisassembler::Success; 2132 2133 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2134 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2135 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2136 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2137 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2138 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2139 2140 // First output register 2141 switch (Inst.getOpcode()) { 2142 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2143 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2144 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2145 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2146 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2147 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2148 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2149 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2150 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2151 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2152 return MCDisassembler::Fail; 2153 break; 2154 case ARM::VLD2b16: 2155 case ARM::VLD2b32: 2156 case ARM::VLD2b8: 2157 case ARM::VLD2b16wb_fixed: 2158 case ARM::VLD2b16wb_register: 2159 case ARM::VLD2b32wb_fixed: 2160 case ARM::VLD2b32wb_register: 2161 case ARM::VLD2b8wb_fixed: 2162 case ARM::VLD2b8wb_register: 2163 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 break; 2166 default: 2167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2168 return MCDisassembler::Fail; 2169 } 2170 2171 // Second output register 2172 switch (Inst.getOpcode()) { 2173 case ARM::VLD3d8: 2174 case ARM::VLD3d16: 2175 case ARM::VLD3d32: 2176 case ARM::VLD3d8_UPD: 2177 case ARM::VLD3d16_UPD: 2178 case ARM::VLD3d32_UPD: 2179 case ARM::VLD4d8: 2180 case ARM::VLD4d16: 2181 case ARM::VLD4d32: 2182 case ARM::VLD4d8_UPD: 2183 case ARM::VLD4d16_UPD: 2184 case ARM::VLD4d32_UPD: 2185 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2186 return MCDisassembler::Fail; 2187 break; 2188 case ARM::VLD3q8: 2189 case ARM::VLD3q16: 2190 case ARM::VLD3q32: 2191 case ARM::VLD3q8_UPD: 2192 case ARM::VLD3q16_UPD: 2193 case ARM::VLD3q32_UPD: 2194 case ARM::VLD4q8: 2195 case ARM::VLD4q16: 2196 case ARM::VLD4q32: 2197 case ARM::VLD4q8_UPD: 2198 case ARM::VLD4q16_UPD: 2199 case ARM::VLD4q32_UPD: 2200 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2201 return MCDisassembler::Fail; 2202 default: 2203 break; 2204 } 2205 2206 // Third output register 2207 switch(Inst.getOpcode()) { 2208 case ARM::VLD3d8: 2209 case ARM::VLD3d16: 2210 case ARM::VLD3d32: 2211 case ARM::VLD3d8_UPD: 2212 case ARM::VLD3d16_UPD: 2213 case ARM::VLD3d32_UPD: 2214 case ARM::VLD4d8: 2215 case ARM::VLD4d16: 2216 case ARM::VLD4d32: 2217 case ARM::VLD4d8_UPD: 2218 case ARM::VLD4d16_UPD: 2219 case ARM::VLD4d32_UPD: 2220 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2221 return MCDisassembler::Fail; 2222 break; 2223 case ARM::VLD3q8: 2224 case ARM::VLD3q16: 2225 case ARM::VLD3q32: 2226 case ARM::VLD3q8_UPD: 2227 case ARM::VLD3q16_UPD: 2228 case ARM::VLD3q32_UPD: 2229 case ARM::VLD4q8: 2230 case ARM::VLD4q16: 2231 case ARM::VLD4q32: 2232 case ARM::VLD4q8_UPD: 2233 case ARM::VLD4q16_UPD: 2234 case ARM::VLD4q32_UPD: 2235 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2236 return MCDisassembler::Fail; 2237 break; 2238 default: 2239 break; 2240 } 2241 2242 // Fourth output register 2243 switch (Inst.getOpcode()) { 2244 case ARM::VLD4d8: 2245 case ARM::VLD4d16: 2246 case ARM::VLD4d32: 2247 case ARM::VLD4d8_UPD: 2248 case ARM::VLD4d16_UPD: 2249 case ARM::VLD4d32_UPD: 2250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 break; 2253 case ARM::VLD4q8: 2254 case ARM::VLD4q16: 2255 case ARM::VLD4q32: 2256 case ARM::VLD4q8_UPD: 2257 case ARM::VLD4q16_UPD: 2258 case ARM::VLD4q32_UPD: 2259 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2260 return MCDisassembler::Fail; 2261 break; 2262 default: 2263 break; 2264 } 2265 2266 // Writeback operand 2267 switch (Inst.getOpcode()) { 2268 case ARM::VLD1d8wb_fixed: 2269 case ARM::VLD1d16wb_fixed: 2270 case ARM::VLD1d32wb_fixed: 2271 case ARM::VLD1d64wb_fixed: 2272 case ARM::VLD1d8wb_register: 2273 case ARM::VLD1d16wb_register: 2274 case ARM::VLD1d32wb_register: 2275 case ARM::VLD1d64wb_register: 2276 case ARM::VLD1q8wb_fixed: 2277 case ARM::VLD1q16wb_fixed: 2278 case ARM::VLD1q32wb_fixed: 2279 case ARM::VLD1q64wb_fixed: 2280 case ARM::VLD1q8wb_register: 2281 case ARM::VLD1q16wb_register: 2282 case ARM::VLD1q32wb_register: 2283 case ARM::VLD1q64wb_register: 2284 case ARM::VLD1d8Twb_fixed: 2285 case ARM::VLD1d8Twb_register: 2286 case ARM::VLD1d16Twb_fixed: 2287 case ARM::VLD1d16Twb_register: 2288 case ARM::VLD1d32Twb_fixed: 2289 case ARM::VLD1d32Twb_register: 2290 case ARM::VLD1d64Twb_fixed: 2291 case ARM::VLD1d64Twb_register: 2292 case ARM::VLD1d8Qwb_fixed: 2293 case ARM::VLD1d8Qwb_register: 2294 case ARM::VLD1d16Qwb_fixed: 2295 case ARM::VLD1d16Qwb_register: 2296 case ARM::VLD1d32Qwb_fixed: 2297 case ARM::VLD1d32Qwb_register: 2298 case ARM::VLD1d64Qwb_fixed: 2299 case ARM::VLD1d64Qwb_register: 2300 case ARM::VLD2d8wb_fixed: 2301 case ARM::VLD2d16wb_fixed: 2302 case ARM::VLD2d32wb_fixed: 2303 case ARM::VLD2q8wb_fixed: 2304 case ARM::VLD2q16wb_fixed: 2305 case ARM::VLD2q32wb_fixed: 2306 case ARM::VLD2d8wb_register: 2307 case ARM::VLD2d16wb_register: 2308 case ARM::VLD2d32wb_register: 2309 case ARM::VLD2q8wb_register: 2310 case ARM::VLD2q16wb_register: 2311 case ARM::VLD2q32wb_register: 2312 case ARM::VLD2b8wb_fixed: 2313 case ARM::VLD2b16wb_fixed: 2314 case ARM::VLD2b32wb_fixed: 2315 case ARM::VLD2b8wb_register: 2316 case ARM::VLD2b16wb_register: 2317 case ARM::VLD2b32wb_register: 2318 Inst.addOperand(MCOperand::CreateImm(0)); 2319 break; 2320 case ARM::VLD3d8_UPD: 2321 case ARM::VLD3d16_UPD: 2322 case ARM::VLD3d32_UPD: 2323 case ARM::VLD3q8_UPD: 2324 case ARM::VLD3q16_UPD: 2325 case ARM::VLD3q32_UPD: 2326 case ARM::VLD4d8_UPD: 2327 case ARM::VLD4d16_UPD: 2328 case ARM::VLD4d32_UPD: 2329 case ARM::VLD4q8_UPD: 2330 case ARM::VLD4q16_UPD: 2331 case ARM::VLD4q32_UPD: 2332 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2333 return MCDisassembler::Fail; 2334 break; 2335 default: 2336 break; 2337 } 2338 2339 // AddrMode6 Base (register+alignment) 2340 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2341 return MCDisassembler::Fail; 2342 2343 // AddrMode6 Offset (register) 2344 switch (Inst.getOpcode()) { 2345 default: 2346 // The below have been updated to have explicit am6offset split 2347 // between fixed and register offset. For those instructions not 2348 // yet updated, we need to add an additional reg0 operand for the 2349 // fixed variant. 2350 // 2351 // The fixed offset encodes as Rm == 0xd, so we check for that. 2352 if (Rm == 0xd) { 2353 Inst.addOperand(MCOperand::CreateReg(0)); 2354 break; 2355 } 2356 // Fall through to handle the register offset variant. 2357 case ARM::VLD1d8wb_fixed: 2358 case ARM::VLD1d16wb_fixed: 2359 case ARM::VLD1d32wb_fixed: 2360 case ARM::VLD1d64wb_fixed: 2361 case ARM::VLD1d8Twb_fixed: 2362 case ARM::VLD1d16Twb_fixed: 2363 case ARM::VLD1d32Twb_fixed: 2364 case ARM::VLD1d64Twb_fixed: 2365 case ARM::VLD1d8Qwb_fixed: 2366 case ARM::VLD1d16Qwb_fixed: 2367 case ARM::VLD1d32Qwb_fixed: 2368 case ARM::VLD1d64Qwb_fixed: 2369 case ARM::VLD1d8wb_register: 2370 case ARM::VLD1d16wb_register: 2371 case ARM::VLD1d32wb_register: 2372 case ARM::VLD1d64wb_register: 2373 case ARM::VLD1q8wb_fixed: 2374 case ARM::VLD1q16wb_fixed: 2375 case ARM::VLD1q32wb_fixed: 2376 case ARM::VLD1q64wb_fixed: 2377 case ARM::VLD1q8wb_register: 2378 case ARM::VLD1q16wb_register: 2379 case ARM::VLD1q32wb_register: 2380 case ARM::VLD1q64wb_register: 2381 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2382 // variant encodes Rm == 0xf. Anything else is a register offset post- 2383 // increment and we need to add the register operand to the instruction. 2384 if (Rm != 0xD && Rm != 0xF && 2385 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2386 return MCDisassembler::Fail; 2387 break; 2388 case ARM::VLD2d8wb_fixed: 2389 case ARM::VLD2d16wb_fixed: 2390 case ARM::VLD2d32wb_fixed: 2391 case ARM::VLD2b8wb_fixed: 2392 case ARM::VLD2b16wb_fixed: 2393 case ARM::VLD2b32wb_fixed: 2394 case ARM::VLD2q8wb_fixed: 2395 case ARM::VLD2q16wb_fixed: 2396 case ARM::VLD2q32wb_fixed: 2397 break; 2398 } 2399 2400 return S; 2401 } 2402 2403 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn, 2404 uint64_t Addr, const void* Decoder) { 2405 unsigned type = fieldFromInstruction(Insn, 8, 4); 2406 unsigned align = fieldFromInstruction(Insn, 4, 2); 2407 if(type == 7 && (align & 2)) return MCDisassembler::Fail; 2408 if(type == 10 && align == 3) return MCDisassembler::Fail; 2409 if(type == 6 && (align & 2)) return MCDisassembler::Fail; 2410 2411 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2412 } 2413 2414 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn, 2415 uint64_t Addr, const void* Decoder) { 2416 unsigned size = fieldFromInstruction(Insn, 6, 2); 2417 if(size == 3) return MCDisassembler::Fail; 2418 2419 unsigned type = fieldFromInstruction(Insn, 8, 4); 2420 unsigned align = fieldFromInstruction(Insn, 4, 2); 2421 if(type == 8 && align == 3) return MCDisassembler::Fail; 2422 if(type == 9 && align == 3) return MCDisassembler::Fail; 2423 2424 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2425 } 2426 2427 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn, 2428 uint64_t Addr, const void* Decoder) { 2429 unsigned size = fieldFromInstruction(Insn, 6, 2); 2430 if(size == 3) return MCDisassembler::Fail; 2431 2432 unsigned align = fieldFromInstruction(Insn, 4, 2); 2433 if(align & 2) return MCDisassembler::Fail; 2434 2435 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2436 } 2437 2438 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn, 2439 uint64_t Addr, const void* Decoder) { 2440 unsigned size = fieldFromInstruction(Insn, 6, 2); 2441 if(size == 3) return MCDisassembler::Fail; 2442 2443 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2444 } 2445 2446 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2447 uint64_t Address, const void *Decoder) { 2448 DecodeStatus S = MCDisassembler::Success; 2449 2450 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2452 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2453 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2454 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2455 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2456 2457 // Writeback Operand 2458 switch (Inst.getOpcode()) { 2459 case ARM::VST1d8wb_fixed: 2460 case ARM::VST1d16wb_fixed: 2461 case ARM::VST1d32wb_fixed: 2462 case ARM::VST1d64wb_fixed: 2463 case ARM::VST1d8wb_register: 2464 case ARM::VST1d16wb_register: 2465 case ARM::VST1d32wb_register: 2466 case ARM::VST1d64wb_register: 2467 case ARM::VST1q8wb_fixed: 2468 case ARM::VST1q16wb_fixed: 2469 case ARM::VST1q32wb_fixed: 2470 case ARM::VST1q64wb_fixed: 2471 case ARM::VST1q8wb_register: 2472 case ARM::VST1q16wb_register: 2473 case ARM::VST1q32wb_register: 2474 case ARM::VST1q64wb_register: 2475 case ARM::VST1d8Twb_fixed: 2476 case ARM::VST1d16Twb_fixed: 2477 case ARM::VST1d32Twb_fixed: 2478 case ARM::VST1d64Twb_fixed: 2479 case ARM::VST1d8Twb_register: 2480 case ARM::VST1d16Twb_register: 2481 case ARM::VST1d32Twb_register: 2482 case ARM::VST1d64Twb_register: 2483 case ARM::VST1d8Qwb_fixed: 2484 case ARM::VST1d16Qwb_fixed: 2485 case ARM::VST1d32Qwb_fixed: 2486 case ARM::VST1d64Qwb_fixed: 2487 case ARM::VST1d8Qwb_register: 2488 case ARM::VST1d16Qwb_register: 2489 case ARM::VST1d32Qwb_register: 2490 case ARM::VST1d64Qwb_register: 2491 case ARM::VST2d8wb_fixed: 2492 case ARM::VST2d16wb_fixed: 2493 case ARM::VST2d32wb_fixed: 2494 case ARM::VST2d8wb_register: 2495 case ARM::VST2d16wb_register: 2496 case ARM::VST2d32wb_register: 2497 case ARM::VST2q8wb_fixed: 2498 case ARM::VST2q16wb_fixed: 2499 case ARM::VST2q32wb_fixed: 2500 case ARM::VST2q8wb_register: 2501 case ARM::VST2q16wb_register: 2502 case ARM::VST2q32wb_register: 2503 case ARM::VST2b8wb_fixed: 2504 case ARM::VST2b16wb_fixed: 2505 case ARM::VST2b32wb_fixed: 2506 case ARM::VST2b8wb_register: 2507 case ARM::VST2b16wb_register: 2508 case ARM::VST2b32wb_register: 2509 if (Rm == 0xF) 2510 return MCDisassembler::Fail; 2511 Inst.addOperand(MCOperand::CreateImm(0)); 2512 break; 2513 case ARM::VST3d8_UPD: 2514 case ARM::VST3d16_UPD: 2515 case ARM::VST3d32_UPD: 2516 case ARM::VST3q8_UPD: 2517 case ARM::VST3q16_UPD: 2518 case ARM::VST3q32_UPD: 2519 case ARM::VST4d8_UPD: 2520 case ARM::VST4d16_UPD: 2521 case ARM::VST4d32_UPD: 2522 case ARM::VST4q8_UPD: 2523 case ARM::VST4q16_UPD: 2524 case ARM::VST4q32_UPD: 2525 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2526 return MCDisassembler::Fail; 2527 break; 2528 default: 2529 break; 2530 } 2531 2532 // AddrMode6 Base (register+alignment) 2533 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 2536 // AddrMode6 Offset (register) 2537 switch (Inst.getOpcode()) { 2538 default: 2539 if (Rm == 0xD) 2540 Inst.addOperand(MCOperand::CreateReg(0)); 2541 else if (Rm != 0xF) { 2542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2543 return MCDisassembler::Fail; 2544 } 2545 break; 2546 case ARM::VST1d8wb_fixed: 2547 case ARM::VST1d16wb_fixed: 2548 case ARM::VST1d32wb_fixed: 2549 case ARM::VST1d64wb_fixed: 2550 case ARM::VST1q8wb_fixed: 2551 case ARM::VST1q16wb_fixed: 2552 case ARM::VST1q32wb_fixed: 2553 case ARM::VST1q64wb_fixed: 2554 case ARM::VST1d8Twb_fixed: 2555 case ARM::VST1d16Twb_fixed: 2556 case ARM::VST1d32Twb_fixed: 2557 case ARM::VST1d64Twb_fixed: 2558 case ARM::VST1d8Qwb_fixed: 2559 case ARM::VST1d16Qwb_fixed: 2560 case ARM::VST1d32Qwb_fixed: 2561 case ARM::VST1d64Qwb_fixed: 2562 case ARM::VST2d8wb_fixed: 2563 case ARM::VST2d16wb_fixed: 2564 case ARM::VST2d32wb_fixed: 2565 case ARM::VST2q8wb_fixed: 2566 case ARM::VST2q16wb_fixed: 2567 case ARM::VST2q32wb_fixed: 2568 case ARM::VST2b8wb_fixed: 2569 case ARM::VST2b16wb_fixed: 2570 case ARM::VST2b32wb_fixed: 2571 break; 2572 } 2573 2574 2575 // First input register 2576 switch (Inst.getOpcode()) { 2577 case ARM::VST1q16: 2578 case ARM::VST1q32: 2579 case ARM::VST1q64: 2580 case ARM::VST1q8: 2581 case ARM::VST1q16wb_fixed: 2582 case ARM::VST1q16wb_register: 2583 case ARM::VST1q32wb_fixed: 2584 case ARM::VST1q32wb_register: 2585 case ARM::VST1q64wb_fixed: 2586 case ARM::VST1q64wb_register: 2587 case ARM::VST1q8wb_fixed: 2588 case ARM::VST1q8wb_register: 2589 case ARM::VST2d16: 2590 case ARM::VST2d32: 2591 case ARM::VST2d8: 2592 case ARM::VST2d16wb_fixed: 2593 case ARM::VST2d16wb_register: 2594 case ARM::VST2d32wb_fixed: 2595 case ARM::VST2d32wb_register: 2596 case ARM::VST2d8wb_fixed: 2597 case ARM::VST2d8wb_register: 2598 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2599 return MCDisassembler::Fail; 2600 break; 2601 case ARM::VST2b16: 2602 case ARM::VST2b32: 2603 case ARM::VST2b8: 2604 case ARM::VST2b16wb_fixed: 2605 case ARM::VST2b16wb_register: 2606 case ARM::VST2b32wb_fixed: 2607 case ARM::VST2b32wb_register: 2608 case ARM::VST2b8wb_fixed: 2609 case ARM::VST2b8wb_register: 2610 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2611 return MCDisassembler::Fail; 2612 break; 2613 default: 2614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2615 return MCDisassembler::Fail; 2616 } 2617 2618 // Second input register 2619 switch (Inst.getOpcode()) { 2620 case ARM::VST3d8: 2621 case ARM::VST3d16: 2622 case ARM::VST3d32: 2623 case ARM::VST3d8_UPD: 2624 case ARM::VST3d16_UPD: 2625 case ARM::VST3d32_UPD: 2626 case ARM::VST4d8: 2627 case ARM::VST4d16: 2628 case ARM::VST4d32: 2629 case ARM::VST4d8_UPD: 2630 case ARM::VST4d16_UPD: 2631 case ARM::VST4d32_UPD: 2632 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2633 return MCDisassembler::Fail; 2634 break; 2635 case ARM::VST3q8: 2636 case ARM::VST3q16: 2637 case ARM::VST3q32: 2638 case ARM::VST3q8_UPD: 2639 case ARM::VST3q16_UPD: 2640 case ARM::VST3q32_UPD: 2641 case ARM::VST4q8: 2642 case ARM::VST4q16: 2643 case ARM::VST4q32: 2644 case ARM::VST4q8_UPD: 2645 case ARM::VST4q16_UPD: 2646 case ARM::VST4q32_UPD: 2647 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 break; 2650 default: 2651 break; 2652 } 2653 2654 // Third input register 2655 switch (Inst.getOpcode()) { 2656 case ARM::VST3d8: 2657 case ARM::VST3d16: 2658 case ARM::VST3d32: 2659 case ARM::VST3d8_UPD: 2660 case ARM::VST3d16_UPD: 2661 case ARM::VST3d32_UPD: 2662 case ARM::VST4d8: 2663 case ARM::VST4d16: 2664 case ARM::VST4d32: 2665 case ARM::VST4d8_UPD: 2666 case ARM::VST4d16_UPD: 2667 case ARM::VST4d32_UPD: 2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2669 return MCDisassembler::Fail; 2670 break; 2671 case ARM::VST3q8: 2672 case ARM::VST3q16: 2673 case ARM::VST3q32: 2674 case ARM::VST3q8_UPD: 2675 case ARM::VST3q16_UPD: 2676 case ARM::VST3q32_UPD: 2677 case ARM::VST4q8: 2678 case ARM::VST4q16: 2679 case ARM::VST4q32: 2680 case ARM::VST4q8_UPD: 2681 case ARM::VST4q16_UPD: 2682 case ARM::VST4q32_UPD: 2683 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2684 return MCDisassembler::Fail; 2685 break; 2686 default: 2687 break; 2688 } 2689 2690 // Fourth input register 2691 switch (Inst.getOpcode()) { 2692 case ARM::VST4d8: 2693 case ARM::VST4d16: 2694 case ARM::VST4d32: 2695 case ARM::VST4d8_UPD: 2696 case ARM::VST4d16_UPD: 2697 case ARM::VST4d32_UPD: 2698 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 break; 2701 case ARM::VST4q8: 2702 case ARM::VST4q16: 2703 case ARM::VST4q32: 2704 case ARM::VST4q8_UPD: 2705 case ARM::VST4q16_UPD: 2706 case ARM::VST4q32_UPD: 2707 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2708 return MCDisassembler::Fail; 2709 break; 2710 default: 2711 break; 2712 } 2713 2714 return S; 2715 } 2716 2717 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2718 uint64_t Address, const void *Decoder) { 2719 DecodeStatus S = MCDisassembler::Success; 2720 2721 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2722 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2723 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2724 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2725 unsigned align = fieldFromInstruction(Insn, 4, 1); 2726 unsigned size = fieldFromInstruction(Insn, 6, 2); 2727 2728 if (size == 0 && align == 1) 2729 return MCDisassembler::Fail; 2730 align *= (1 << size); 2731 2732 switch (Inst.getOpcode()) { 2733 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2734 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2735 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2736 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2737 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 break; 2740 default: 2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 break; 2744 } 2745 if (Rm != 0xF) { 2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 } 2749 2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 Inst.addOperand(MCOperand::CreateImm(align)); 2753 2754 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2755 // variant encodes Rm == 0xf. Anything else is a register offset post- 2756 // increment and we need to add the register operand to the instruction. 2757 if (Rm != 0xD && Rm != 0xF && 2758 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 2761 return S; 2762 } 2763 2764 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2765 uint64_t Address, const void *Decoder) { 2766 DecodeStatus S = MCDisassembler::Success; 2767 2768 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2769 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2770 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2771 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2772 unsigned align = fieldFromInstruction(Insn, 4, 1); 2773 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2774 align *= 2*size; 2775 2776 switch (Inst.getOpcode()) { 2777 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2778 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2779 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2780 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2781 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 break; 2784 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2785 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2786 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2787 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2788 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 break; 2791 default: 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 break; 2795 } 2796 2797 if (Rm != 0xF) 2798 Inst.addOperand(MCOperand::CreateImm(0)); 2799 2800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2801 return MCDisassembler::Fail; 2802 Inst.addOperand(MCOperand::CreateImm(align)); 2803 2804 if (Rm != 0xD && Rm != 0xF) { 2805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 } 2808 2809 return S; 2810 } 2811 2812 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2813 uint64_t Address, const void *Decoder) { 2814 DecodeStatus S = MCDisassembler::Success; 2815 2816 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2817 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2818 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2819 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2820 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2821 2822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2825 return MCDisassembler::Fail; 2826 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 if (Rm != 0xF) { 2829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2830 return MCDisassembler::Fail; 2831 } 2832 2833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 Inst.addOperand(MCOperand::CreateImm(0)); 2836 2837 if (Rm == 0xD) 2838 Inst.addOperand(MCOperand::CreateReg(0)); 2839 else if (Rm != 0xF) { 2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2841 return MCDisassembler::Fail; 2842 } 2843 2844 return S; 2845 } 2846 2847 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2848 uint64_t Address, const void *Decoder) { 2849 DecodeStatus S = MCDisassembler::Success; 2850 2851 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2852 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2853 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2854 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2855 unsigned size = fieldFromInstruction(Insn, 6, 2); 2856 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2857 unsigned align = fieldFromInstruction(Insn, 4, 1); 2858 2859 if (size == 0x3) { 2860 if (align == 0) 2861 return MCDisassembler::Fail; 2862 size = 4; 2863 align = 16; 2864 } else { 2865 if (size == 2) { 2866 size = 1 << size; 2867 align *= 8; 2868 } else { 2869 size = 1 << size; 2870 align *= 4*size; 2871 } 2872 } 2873 2874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 if (Rm != 0xF) { 2883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 } 2886 2887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 Inst.addOperand(MCOperand::CreateImm(align)); 2890 2891 if (Rm == 0xD) 2892 Inst.addOperand(MCOperand::CreateReg(0)); 2893 else if (Rm != 0xF) { 2894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 } 2897 2898 return S; 2899 } 2900 2901 static DecodeStatus 2902 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2903 uint64_t Address, const void *Decoder) { 2904 DecodeStatus S = MCDisassembler::Success; 2905 2906 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2907 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2908 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2909 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2910 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2911 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2912 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2913 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2914 2915 if (Q) { 2916 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 } else { 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 } 2922 2923 Inst.addOperand(MCOperand::CreateImm(imm)); 2924 2925 switch (Inst.getOpcode()) { 2926 case ARM::VORRiv4i16: 2927 case ARM::VORRiv2i32: 2928 case ARM::VBICiv4i16: 2929 case ARM::VBICiv2i32: 2930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 break; 2933 case ARM::VORRiv8i16: 2934 case ARM::VORRiv4i32: 2935 case ARM::VBICiv8i16: 2936 case ARM::VBICiv4i32: 2937 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 break; 2940 default: 2941 break; 2942 } 2943 2944 return S; 2945 } 2946 2947 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2948 uint64_t Address, const void *Decoder) { 2949 DecodeStatus S = MCDisassembler::Success; 2950 2951 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2952 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2953 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2954 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2955 unsigned size = fieldFromInstruction(Insn, 18, 2); 2956 2957 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2958 return MCDisassembler::Fail; 2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2962 2963 return S; 2964 } 2965 2966 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2967 uint64_t Address, const void *Decoder) { 2968 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2969 return MCDisassembler::Success; 2970 } 2971 2972 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2973 uint64_t Address, const void *Decoder) { 2974 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2975 return MCDisassembler::Success; 2976 } 2977 2978 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2979 uint64_t Address, const void *Decoder) { 2980 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2981 return MCDisassembler::Success; 2982 } 2983 2984 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2985 uint64_t Address, const void *Decoder) { 2986 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2987 return MCDisassembler::Success; 2988 } 2989 2990 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2991 uint64_t Address, const void *Decoder) { 2992 DecodeStatus S = MCDisassembler::Success; 2993 2994 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2995 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2996 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2997 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2998 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2999 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3000 unsigned op = fieldFromInstruction(Insn, 6, 1); 3001 3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 if (op) { 3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3006 return MCDisassembler::Fail; // Writeback 3007 } 3008 3009 switch (Inst.getOpcode()) { 3010 case ARM::VTBL2: 3011 case ARM::VTBX2: 3012 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 break; 3015 default: 3016 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3017 return MCDisassembler::Fail; 3018 } 3019 3020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3021 return MCDisassembler::Fail; 3022 3023 return S; 3024 } 3025 3026 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3027 uint64_t Address, const void *Decoder) { 3028 DecodeStatus S = MCDisassembler::Success; 3029 3030 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3031 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3032 3033 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 3036 switch(Inst.getOpcode()) { 3037 default: 3038 return MCDisassembler::Fail; 3039 case ARM::tADR: 3040 break; // tADR does not explicitly represent the PC as an operand. 3041 case ARM::tADDrSPi: 3042 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3043 break; 3044 } 3045 3046 Inst.addOperand(MCOperand::CreateImm(imm)); 3047 return S; 3048 } 3049 3050 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3051 uint64_t Address, const void *Decoder) { 3052 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3053 true, 2, Inst, Decoder)) 3054 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3055 return MCDisassembler::Success; 3056 } 3057 3058 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3059 uint64_t Address, const void *Decoder) { 3060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3061 true, 4, Inst, Decoder)) 3062 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3063 return MCDisassembler::Success; 3064 } 3065 3066 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3067 uint64_t Address, const void *Decoder) { 3068 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3069 true, 2, Inst, Decoder)) 3070 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3071 return MCDisassembler::Success; 3072 } 3073 3074 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3075 uint64_t Address, const void *Decoder) { 3076 DecodeStatus S = MCDisassembler::Success; 3077 3078 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3079 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3080 3081 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 3086 return S; 3087 } 3088 3089 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3090 uint64_t Address, const void *Decoder) { 3091 DecodeStatus S = MCDisassembler::Success; 3092 3093 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3094 unsigned imm = fieldFromInstruction(Val, 3, 5); 3095 3096 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 Inst.addOperand(MCOperand::CreateImm(imm)); 3099 3100 return S; 3101 } 3102 3103 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3104 uint64_t Address, const void *Decoder) { 3105 unsigned imm = Val << 2; 3106 3107 Inst.addOperand(MCOperand::CreateImm(imm)); 3108 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3109 3110 return MCDisassembler::Success; 3111 } 3112 3113 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3114 uint64_t Address, const void *Decoder) { 3115 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3116 Inst.addOperand(MCOperand::CreateImm(Val)); 3117 3118 return MCDisassembler::Success; 3119 } 3120 3121 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3122 uint64_t Address, const void *Decoder) { 3123 DecodeStatus S = MCDisassembler::Success; 3124 3125 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3126 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3127 unsigned imm = fieldFromInstruction(Val, 0, 2); 3128 3129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 Inst.addOperand(MCOperand::CreateImm(imm)); 3134 3135 return S; 3136 } 3137 3138 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3139 uint64_t Address, const void *Decoder) { 3140 DecodeStatus S = MCDisassembler::Success; 3141 3142 switch (Inst.getOpcode()) { 3143 case ARM::t2PLDs: 3144 case ARM::t2PLDWs: 3145 case ARM::t2PLIs: 3146 break; 3147 default: { 3148 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3149 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3150 return MCDisassembler::Fail; 3151 } 3152 } 3153 3154 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3155 if (Rn == 0xF) { 3156 switch (Inst.getOpcode()) { 3157 case ARM::t2LDRBs: 3158 Inst.setOpcode(ARM::t2LDRBpci); 3159 break; 3160 case ARM::t2LDRHs: 3161 Inst.setOpcode(ARM::t2LDRHpci); 3162 break; 3163 case ARM::t2LDRSHs: 3164 Inst.setOpcode(ARM::t2LDRSHpci); 3165 break; 3166 case ARM::t2LDRSBs: 3167 Inst.setOpcode(ARM::t2LDRSBpci); 3168 break; 3169 case ARM::t2PLDs: 3170 Inst.setOpcode(ARM::t2PLDi12); 3171 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3172 break; 3173 default: 3174 return MCDisassembler::Fail; 3175 } 3176 3177 int imm = fieldFromInstruction(Insn, 0, 12); 3178 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3179 Inst.addOperand(MCOperand::CreateImm(imm)); 3180 3181 return S; 3182 } 3183 3184 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3185 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3186 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3187 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 3190 return S; 3191 } 3192 3193 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3194 uint64_t Address, const void *Decoder) { 3195 if (Val == 0) 3196 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3197 else { 3198 int imm = Val & 0xFF; 3199 3200 if (!(Val & 0x100)) imm *= -1; 3201 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3202 } 3203 3204 return MCDisassembler::Success; 3205 } 3206 3207 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3208 uint64_t Address, const void *Decoder) { 3209 DecodeStatus S = MCDisassembler::Success; 3210 3211 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3212 unsigned imm = fieldFromInstruction(Val, 0, 9); 3213 3214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 3219 return S; 3220 } 3221 3222 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3223 uint64_t Address, const void *Decoder) { 3224 DecodeStatus S = MCDisassembler::Success; 3225 3226 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3227 unsigned imm = fieldFromInstruction(Val, 0, 8); 3228 3229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 3232 Inst.addOperand(MCOperand::CreateImm(imm)); 3233 3234 return S; 3235 } 3236 3237 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 int imm = Val & 0xFF; 3240 if (Val == 0) 3241 imm = INT32_MIN; 3242 else if (!(Val & 0x100)) 3243 imm *= -1; 3244 Inst.addOperand(MCOperand::CreateImm(imm)); 3245 3246 return MCDisassembler::Success; 3247 } 3248 3249 3250 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3251 uint64_t Address, const void *Decoder) { 3252 DecodeStatus S = MCDisassembler::Success; 3253 3254 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3255 unsigned imm = fieldFromInstruction(Val, 0, 9); 3256 3257 // Some instructions always use an additive offset. 3258 switch (Inst.getOpcode()) { 3259 case ARM::t2LDRT: 3260 case ARM::t2LDRBT: 3261 case ARM::t2LDRHT: 3262 case ARM::t2LDRSBT: 3263 case ARM::t2LDRSHT: 3264 case ARM::t2STRT: 3265 case ARM::t2STRBT: 3266 case ARM::t2STRHT: 3267 imm |= 0x100; 3268 break; 3269 default: 3270 break; 3271 } 3272 3273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3274 return MCDisassembler::Fail; 3275 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3276 return MCDisassembler::Fail; 3277 3278 return S; 3279 } 3280 3281 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3282 uint64_t Address, const void *Decoder) { 3283 DecodeStatus S = MCDisassembler::Success; 3284 3285 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3286 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3287 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3288 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3289 addr |= Rn << 9; 3290 unsigned load = fieldFromInstruction(Insn, 20, 1); 3291 3292 if (!load) { 3293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3294 return MCDisassembler::Fail; 3295 } 3296 3297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 3300 if (load) { 3301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 } 3304 3305 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 3308 return S; 3309 } 3310 3311 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3312 uint64_t Address, const void *Decoder) { 3313 DecodeStatus S = MCDisassembler::Success; 3314 3315 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3316 unsigned imm = fieldFromInstruction(Val, 0, 12); 3317 3318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 Inst.addOperand(MCOperand::CreateImm(imm)); 3321 3322 return S; 3323 } 3324 3325 3326 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3327 uint64_t Address, const void *Decoder) { 3328 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3329 3330 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3331 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3332 Inst.addOperand(MCOperand::CreateImm(imm)); 3333 3334 return MCDisassembler::Success; 3335 } 3336 3337 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3338 uint64_t Address, const void *Decoder) { 3339 DecodeStatus S = MCDisassembler::Success; 3340 3341 if (Inst.getOpcode() == ARM::tADDrSP) { 3342 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3343 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3344 3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 } else if (Inst.getOpcode() == ARM::tADDspr) { 3351 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3352 3353 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3354 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 } 3358 3359 return S; 3360 } 3361 3362 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3363 uint64_t Address, const void *Decoder) { 3364 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3365 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3366 3367 Inst.addOperand(MCOperand::CreateImm(imod)); 3368 Inst.addOperand(MCOperand::CreateImm(flags)); 3369 3370 return MCDisassembler::Success; 3371 } 3372 3373 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3374 uint64_t Address, const void *Decoder) { 3375 DecodeStatus S = MCDisassembler::Success; 3376 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3377 unsigned add = fieldFromInstruction(Insn, 4, 1); 3378 3379 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 Inst.addOperand(MCOperand::CreateImm(add)); 3382 3383 return S; 3384 } 3385 3386 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3387 uint64_t Address, const void *Decoder) { 3388 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3389 // Note only one trailing zero not two. Also the J1 and J2 values are from 3390 // the encoded instruction. So here change to I1 and I2 values via: 3391 // I1 = NOT(J1 EOR S); 3392 // I2 = NOT(J2 EOR S); 3393 // and build the imm32 with two trailing zeros as documented: 3394 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3395 unsigned S = (Val >> 23) & 1; 3396 unsigned J1 = (Val >> 22) & 1; 3397 unsigned J2 = (Val >> 21) & 1; 3398 unsigned I1 = !(J1 ^ S); 3399 unsigned I2 = !(J2 ^ S); 3400 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3401 int imm32 = SignExtend32<25>(tmp << 1); 3402 3403 if (!tryAddingSymbolicOperand(Address, 3404 (Address & ~2u) + imm32 + 4, 3405 true, 4, Inst, Decoder)) 3406 Inst.addOperand(MCOperand::CreateImm(imm32)); 3407 return MCDisassembler::Success; 3408 } 3409 3410 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3411 uint64_t Address, const void *Decoder) { 3412 if (Val == 0xA || Val == 0xB) 3413 return MCDisassembler::Fail; 3414 3415 Inst.addOperand(MCOperand::CreateImm(Val)); 3416 return MCDisassembler::Success; 3417 } 3418 3419 static DecodeStatus 3420 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3421 uint64_t Address, const void *Decoder) { 3422 DecodeStatus S = MCDisassembler::Success; 3423 3424 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3425 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3426 3427 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 return S; 3433 } 3434 3435 static DecodeStatus 3436 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3437 uint64_t Address, const void *Decoder) { 3438 DecodeStatus S = MCDisassembler::Success; 3439 3440 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3441 if (pred == 0xE || pred == 0xF) { 3442 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3443 switch (opc) { 3444 default: 3445 return MCDisassembler::Fail; 3446 case 0xf3bf8f4: 3447 Inst.setOpcode(ARM::t2DSB); 3448 break; 3449 case 0xf3bf8f5: 3450 Inst.setOpcode(ARM::t2DMB); 3451 break; 3452 case 0xf3bf8f6: 3453 Inst.setOpcode(ARM::t2ISB); 3454 break; 3455 } 3456 3457 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3458 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3459 } 3460 3461 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3462 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3463 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3464 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3465 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3466 3467 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 3472 return S; 3473 } 3474 3475 // Decode a shifted immediate operand. These basically consist 3476 // of an 8-bit value, and a 4-bit directive that specifies either 3477 // a splat operation or a rotation. 3478 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3479 uint64_t Address, const void *Decoder) { 3480 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3481 if (ctrl == 0) { 3482 unsigned byte = fieldFromInstruction(Val, 8, 2); 3483 unsigned imm = fieldFromInstruction(Val, 0, 8); 3484 switch (byte) { 3485 case 0: 3486 Inst.addOperand(MCOperand::CreateImm(imm)); 3487 break; 3488 case 1: 3489 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3490 break; 3491 case 2: 3492 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3493 break; 3494 case 3: 3495 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3496 (imm << 8) | imm)); 3497 break; 3498 } 3499 } else { 3500 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3501 unsigned rot = fieldFromInstruction(Val, 7, 5); 3502 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3503 Inst.addOperand(MCOperand::CreateImm(imm)); 3504 } 3505 3506 return MCDisassembler::Success; 3507 } 3508 3509 static DecodeStatus 3510 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3511 uint64_t Address, const void *Decoder){ 3512 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3513 true, 2, Inst, Decoder)) 3514 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3515 return MCDisassembler::Success; 3516 } 3517 3518 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3519 uint64_t Address, const void *Decoder){ 3520 // Val is passed in as S:J1:J2:imm10:imm11 3521 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3522 // the encoded instruction. So here change to I1 and I2 values via: 3523 // I1 = NOT(J1 EOR S); 3524 // I2 = NOT(J2 EOR S); 3525 // and build the imm32 with one trailing zero as documented: 3526 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3527 unsigned S = (Val >> 23) & 1; 3528 unsigned J1 = (Val >> 22) & 1; 3529 unsigned J2 = (Val >> 21) & 1; 3530 unsigned I1 = !(J1 ^ S); 3531 unsigned I2 = !(J2 ^ S); 3532 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3533 int imm32 = SignExtend32<25>(tmp << 1); 3534 3535 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3536 true, 4, Inst, Decoder)) 3537 Inst.addOperand(MCOperand::CreateImm(imm32)); 3538 return MCDisassembler::Success; 3539 } 3540 3541 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3542 uint64_t Address, const void *Decoder) { 3543 if (Val & ~0xf) 3544 return MCDisassembler::Fail; 3545 3546 Inst.addOperand(MCOperand::CreateImm(Val)); 3547 return MCDisassembler::Success; 3548 } 3549 3550 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3551 uint64_t Address, const void *Decoder) { 3552 if (!Val) return MCDisassembler::Fail; 3553 Inst.addOperand(MCOperand::CreateImm(Val)); 3554 return MCDisassembler::Success; 3555 } 3556 3557 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3558 uint64_t Address, const void *Decoder) { 3559 DecodeStatus S = MCDisassembler::Success; 3560 3561 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3562 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3563 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3564 3565 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3566 3567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 3576 return S; 3577 } 3578 3579 3580 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3581 uint64_t Address, const void *Decoder){ 3582 DecodeStatus S = MCDisassembler::Success; 3583 3584 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3585 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3586 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3587 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3588 3589 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3590 return MCDisassembler::Fail; 3591 3592 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3593 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3594 3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 3604 return S; 3605 } 3606 3607 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3608 uint64_t Address, const void *Decoder) { 3609 DecodeStatus S = MCDisassembler::Success; 3610 3611 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3612 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3613 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3614 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3615 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3616 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3617 3618 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3619 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3625 return MCDisassembler::Fail; 3626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 3629 return S; 3630 } 3631 3632 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3633 uint64_t Address, const void *Decoder) { 3634 DecodeStatus S = MCDisassembler::Success; 3635 3636 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3637 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3638 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3639 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3640 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3641 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3642 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3643 3644 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3645 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3646 3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3654 return MCDisassembler::Fail; 3655 3656 return S; 3657 } 3658 3659 3660 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3661 uint64_t Address, const void *Decoder) { 3662 DecodeStatus S = MCDisassembler::Success; 3663 3664 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3665 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3666 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3667 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3668 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3669 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3670 3671 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3672 3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3676 return MCDisassembler::Fail; 3677 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 3682 return S; 3683 } 3684 3685 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3686 uint64_t Address, const void *Decoder) { 3687 DecodeStatus S = MCDisassembler::Success; 3688 3689 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3690 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3691 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3692 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3693 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3694 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3695 3696 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3697 3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 3707 return S; 3708 } 3709 3710 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3711 uint64_t Address, const void *Decoder) { 3712 DecodeStatus S = MCDisassembler::Success; 3713 3714 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3715 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3716 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3717 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3718 unsigned size = fieldFromInstruction(Insn, 10, 2); 3719 3720 unsigned align = 0; 3721 unsigned index = 0; 3722 switch (size) { 3723 default: 3724 return MCDisassembler::Fail; 3725 case 0: 3726 if (fieldFromInstruction(Insn, 4, 1)) 3727 return MCDisassembler::Fail; // UNDEFINED 3728 index = fieldFromInstruction(Insn, 5, 3); 3729 break; 3730 case 1: 3731 if (fieldFromInstruction(Insn, 5, 1)) 3732 return MCDisassembler::Fail; // UNDEFINED 3733 index = fieldFromInstruction(Insn, 6, 2); 3734 if (fieldFromInstruction(Insn, 4, 1)) 3735 align = 2; 3736 break; 3737 case 2: 3738 if (fieldFromInstruction(Insn, 6, 1)) 3739 return MCDisassembler::Fail; // UNDEFINED 3740 index = fieldFromInstruction(Insn, 7, 1); 3741 3742 switch (fieldFromInstruction(Insn, 4, 2)) { 3743 case 0 : 3744 align = 0; break; 3745 case 3: 3746 align = 4; break; 3747 default: 3748 return MCDisassembler::Fail; 3749 } 3750 break; 3751 } 3752 3753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 if (Rm != 0xF) { // Writeback 3756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3757 return MCDisassembler::Fail; 3758 } 3759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 Inst.addOperand(MCOperand::CreateImm(align)); 3762 if (Rm != 0xF) { 3763 if (Rm != 0xD) { 3764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3765 return MCDisassembler::Fail; 3766 } else 3767 Inst.addOperand(MCOperand::CreateReg(0)); 3768 } 3769 3770 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 Inst.addOperand(MCOperand::CreateImm(index)); 3773 3774 return S; 3775 } 3776 3777 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3778 uint64_t Address, const void *Decoder) { 3779 DecodeStatus S = MCDisassembler::Success; 3780 3781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3782 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3783 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3784 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3785 unsigned size = fieldFromInstruction(Insn, 10, 2); 3786 3787 unsigned align = 0; 3788 unsigned index = 0; 3789 switch (size) { 3790 default: 3791 return MCDisassembler::Fail; 3792 case 0: 3793 if (fieldFromInstruction(Insn, 4, 1)) 3794 return MCDisassembler::Fail; // UNDEFINED 3795 index = fieldFromInstruction(Insn, 5, 3); 3796 break; 3797 case 1: 3798 if (fieldFromInstruction(Insn, 5, 1)) 3799 return MCDisassembler::Fail; // UNDEFINED 3800 index = fieldFromInstruction(Insn, 6, 2); 3801 if (fieldFromInstruction(Insn, 4, 1)) 3802 align = 2; 3803 break; 3804 case 2: 3805 if (fieldFromInstruction(Insn, 6, 1)) 3806 return MCDisassembler::Fail; // UNDEFINED 3807 index = fieldFromInstruction(Insn, 7, 1); 3808 3809 switch (fieldFromInstruction(Insn, 4, 2)) { 3810 case 0: 3811 align = 0; break; 3812 case 3: 3813 align = 4; break; 3814 default: 3815 return MCDisassembler::Fail; 3816 } 3817 break; 3818 } 3819 3820 if (Rm != 0xF) { // Writeback 3821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 } 3824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3825 return MCDisassembler::Fail; 3826 Inst.addOperand(MCOperand::CreateImm(align)); 3827 if (Rm != 0xF) { 3828 if (Rm != 0xD) { 3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 } else 3832 Inst.addOperand(MCOperand::CreateReg(0)); 3833 } 3834 3835 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 Inst.addOperand(MCOperand::CreateImm(index)); 3838 3839 return S; 3840 } 3841 3842 3843 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3844 uint64_t Address, const void *Decoder) { 3845 DecodeStatus S = MCDisassembler::Success; 3846 3847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3848 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3849 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3850 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3851 unsigned size = fieldFromInstruction(Insn, 10, 2); 3852 3853 unsigned align = 0; 3854 unsigned index = 0; 3855 unsigned inc = 1; 3856 switch (size) { 3857 default: 3858 return MCDisassembler::Fail; 3859 case 0: 3860 index = fieldFromInstruction(Insn, 5, 3); 3861 if (fieldFromInstruction(Insn, 4, 1)) 3862 align = 2; 3863 break; 3864 case 1: 3865 index = fieldFromInstruction(Insn, 6, 2); 3866 if (fieldFromInstruction(Insn, 4, 1)) 3867 align = 4; 3868 if (fieldFromInstruction(Insn, 5, 1)) 3869 inc = 2; 3870 break; 3871 case 2: 3872 if (fieldFromInstruction(Insn, 5, 1)) 3873 return MCDisassembler::Fail; // UNDEFINED 3874 index = fieldFromInstruction(Insn, 7, 1); 3875 if (fieldFromInstruction(Insn, 4, 1) != 0) 3876 align = 8; 3877 if (fieldFromInstruction(Insn, 6, 1)) 3878 inc = 2; 3879 break; 3880 } 3881 3882 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3883 return MCDisassembler::Fail; 3884 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 if (Rm != 0xF) { // Writeback 3887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3888 return MCDisassembler::Fail; 3889 } 3890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 Inst.addOperand(MCOperand::CreateImm(align)); 3893 if (Rm != 0xF) { 3894 if (Rm != 0xD) { 3895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3896 return MCDisassembler::Fail; 3897 } else 3898 Inst.addOperand(MCOperand::CreateReg(0)); 3899 } 3900 3901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3904 return MCDisassembler::Fail; 3905 Inst.addOperand(MCOperand::CreateImm(index)); 3906 3907 return S; 3908 } 3909 3910 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3911 uint64_t Address, const void *Decoder) { 3912 DecodeStatus S = MCDisassembler::Success; 3913 3914 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3915 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3916 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3917 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3918 unsigned size = fieldFromInstruction(Insn, 10, 2); 3919 3920 unsigned align = 0; 3921 unsigned index = 0; 3922 unsigned inc = 1; 3923 switch (size) { 3924 default: 3925 return MCDisassembler::Fail; 3926 case 0: 3927 index = fieldFromInstruction(Insn, 5, 3); 3928 if (fieldFromInstruction(Insn, 4, 1)) 3929 align = 2; 3930 break; 3931 case 1: 3932 index = fieldFromInstruction(Insn, 6, 2); 3933 if (fieldFromInstruction(Insn, 4, 1)) 3934 align = 4; 3935 if (fieldFromInstruction(Insn, 5, 1)) 3936 inc = 2; 3937 break; 3938 case 2: 3939 if (fieldFromInstruction(Insn, 5, 1)) 3940 return MCDisassembler::Fail; // UNDEFINED 3941 index = fieldFromInstruction(Insn, 7, 1); 3942 if (fieldFromInstruction(Insn, 4, 1) != 0) 3943 align = 8; 3944 if (fieldFromInstruction(Insn, 6, 1)) 3945 inc = 2; 3946 break; 3947 } 3948 3949 if (Rm != 0xF) { // Writeback 3950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 } 3953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 Inst.addOperand(MCOperand::CreateImm(align)); 3956 if (Rm != 0xF) { 3957 if (Rm != 0xD) { 3958 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3959 return MCDisassembler::Fail; 3960 } else 3961 Inst.addOperand(MCOperand::CreateReg(0)); 3962 } 3963 3964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3965 return MCDisassembler::Fail; 3966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3967 return MCDisassembler::Fail; 3968 Inst.addOperand(MCOperand::CreateImm(index)); 3969 3970 return S; 3971 } 3972 3973 3974 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3975 uint64_t Address, const void *Decoder) { 3976 DecodeStatus S = MCDisassembler::Success; 3977 3978 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3979 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3980 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3981 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3982 unsigned size = fieldFromInstruction(Insn, 10, 2); 3983 3984 unsigned align = 0; 3985 unsigned index = 0; 3986 unsigned inc = 1; 3987 switch (size) { 3988 default: 3989 return MCDisassembler::Fail; 3990 case 0: 3991 if (fieldFromInstruction(Insn, 4, 1)) 3992 return MCDisassembler::Fail; // UNDEFINED 3993 index = fieldFromInstruction(Insn, 5, 3); 3994 break; 3995 case 1: 3996 if (fieldFromInstruction(Insn, 4, 1)) 3997 return MCDisassembler::Fail; // UNDEFINED 3998 index = fieldFromInstruction(Insn, 6, 2); 3999 if (fieldFromInstruction(Insn, 5, 1)) 4000 inc = 2; 4001 break; 4002 case 2: 4003 if (fieldFromInstruction(Insn, 4, 2)) 4004 return MCDisassembler::Fail; // UNDEFINED 4005 index = fieldFromInstruction(Insn, 7, 1); 4006 if (fieldFromInstruction(Insn, 6, 1)) 4007 inc = 2; 4008 break; 4009 } 4010 4011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 4018 if (Rm != 0xF) { // Writeback 4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 } 4022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 Inst.addOperand(MCOperand::CreateImm(align)); 4025 if (Rm != 0xF) { 4026 if (Rm != 0xD) { 4027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 } else 4030 Inst.addOperand(MCOperand::CreateReg(0)); 4031 } 4032 4033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4038 return MCDisassembler::Fail; 4039 Inst.addOperand(MCOperand::CreateImm(index)); 4040 4041 return S; 4042 } 4043 4044 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4045 uint64_t Address, const void *Decoder) { 4046 DecodeStatus S = MCDisassembler::Success; 4047 4048 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4049 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4050 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4051 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4052 unsigned size = fieldFromInstruction(Insn, 10, 2); 4053 4054 unsigned align = 0; 4055 unsigned index = 0; 4056 unsigned inc = 1; 4057 switch (size) { 4058 default: 4059 return MCDisassembler::Fail; 4060 case 0: 4061 if (fieldFromInstruction(Insn, 4, 1)) 4062 return MCDisassembler::Fail; // UNDEFINED 4063 index = fieldFromInstruction(Insn, 5, 3); 4064 break; 4065 case 1: 4066 if (fieldFromInstruction(Insn, 4, 1)) 4067 return MCDisassembler::Fail; // UNDEFINED 4068 index = fieldFromInstruction(Insn, 6, 2); 4069 if (fieldFromInstruction(Insn, 5, 1)) 4070 inc = 2; 4071 break; 4072 case 2: 4073 if (fieldFromInstruction(Insn, 4, 2)) 4074 return MCDisassembler::Fail; // UNDEFINED 4075 index = fieldFromInstruction(Insn, 7, 1); 4076 if (fieldFromInstruction(Insn, 6, 1)) 4077 inc = 2; 4078 break; 4079 } 4080 4081 if (Rm != 0xF) { // Writeback 4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 } 4085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 Inst.addOperand(MCOperand::CreateImm(align)); 4088 if (Rm != 0xF) { 4089 if (Rm != 0xD) { 4090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 } else 4093 Inst.addOperand(MCOperand::CreateReg(0)); 4094 } 4095 4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4097 return MCDisassembler::Fail; 4098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4099 return MCDisassembler::Fail; 4100 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4101 return MCDisassembler::Fail; 4102 Inst.addOperand(MCOperand::CreateImm(index)); 4103 4104 return S; 4105 } 4106 4107 4108 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4109 uint64_t Address, const void *Decoder) { 4110 DecodeStatus S = MCDisassembler::Success; 4111 4112 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4113 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4114 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4116 unsigned size = fieldFromInstruction(Insn, 10, 2); 4117 4118 unsigned align = 0; 4119 unsigned index = 0; 4120 unsigned inc = 1; 4121 switch (size) { 4122 default: 4123 return MCDisassembler::Fail; 4124 case 0: 4125 if (fieldFromInstruction(Insn, 4, 1)) 4126 align = 4; 4127 index = fieldFromInstruction(Insn, 5, 3); 4128 break; 4129 case 1: 4130 if (fieldFromInstruction(Insn, 4, 1)) 4131 align = 8; 4132 index = fieldFromInstruction(Insn, 6, 2); 4133 if (fieldFromInstruction(Insn, 5, 1)) 4134 inc = 2; 4135 break; 4136 case 2: 4137 switch (fieldFromInstruction(Insn, 4, 2)) { 4138 case 0: 4139 align = 0; break; 4140 case 3: 4141 return MCDisassembler::Fail; 4142 default: 4143 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4144 } 4145 4146 index = fieldFromInstruction(Insn, 7, 1); 4147 if (fieldFromInstruction(Insn, 6, 1)) 4148 inc = 2; 4149 break; 4150 } 4151 4152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4155 return MCDisassembler::Fail; 4156 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 4161 if (Rm != 0xF) { // Writeback 4162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4163 return MCDisassembler::Fail; 4164 } 4165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 Inst.addOperand(MCOperand::CreateImm(align)); 4168 if (Rm != 0xF) { 4169 if (Rm != 0xD) { 4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 } else 4173 Inst.addOperand(MCOperand::CreateReg(0)); 4174 } 4175 4176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4177 return MCDisassembler::Fail; 4178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4179 return MCDisassembler::Fail; 4180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 Inst.addOperand(MCOperand::CreateImm(index)); 4185 4186 return S; 4187 } 4188 4189 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4190 uint64_t Address, const void *Decoder) { 4191 DecodeStatus S = MCDisassembler::Success; 4192 4193 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4194 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4196 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4197 unsigned size = fieldFromInstruction(Insn, 10, 2); 4198 4199 unsigned align = 0; 4200 unsigned index = 0; 4201 unsigned inc = 1; 4202 switch (size) { 4203 default: 4204 return MCDisassembler::Fail; 4205 case 0: 4206 if (fieldFromInstruction(Insn, 4, 1)) 4207 align = 4; 4208 index = fieldFromInstruction(Insn, 5, 3); 4209 break; 4210 case 1: 4211 if (fieldFromInstruction(Insn, 4, 1)) 4212 align = 8; 4213 index = fieldFromInstruction(Insn, 6, 2); 4214 if (fieldFromInstruction(Insn, 5, 1)) 4215 inc = 2; 4216 break; 4217 case 2: 4218 switch (fieldFromInstruction(Insn, 4, 2)) { 4219 case 0: 4220 align = 0; break; 4221 case 3: 4222 return MCDisassembler::Fail; 4223 default: 4224 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4225 } 4226 4227 index = fieldFromInstruction(Insn, 7, 1); 4228 if (fieldFromInstruction(Insn, 6, 1)) 4229 inc = 2; 4230 break; 4231 } 4232 4233 if (Rm != 0xF) { // Writeback 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 } 4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 Inst.addOperand(MCOperand::CreateImm(align)); 4240 if (Rm != 0xF) { 4241 if (Rm != 0xD) { 4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 } else 4245 Inst.addOperand(MCOperand::CreateReg(0)); 4246 } 4247 4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4253 return MCDisassembler::Fail; 4254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4255 return MCDisassembler::Fail; 4256 Inst.addOperand(MCOperand::CreateImm(index)); 4257 4258 return S; 4259 } 4260 4261 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4262 uint64_t Address, const void *Decoder) { 4263 DecodeStatus S = MCDisassembler::Success; 4264 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4265 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4266 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4267 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4268 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4269 4270 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4271 S = MCDisassembler::SoftFail; 4272 4273 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4274 return MCDisassembler::Fail; 4275 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4276 return MCDisassembler::Fail; 4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4278 return MCDisassembler::Fail; 4279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4280 return MCDisassembler::Fail; 4281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4282 return MCDisassembler::Fail; 4283 4284 return S; 4285 } 4286 4287 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4288 uint64_t Address, const void *Decoder) { 4289 DecodeStatus S = MCDisassembler::Success; 4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4291 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4292 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4293 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4294 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4295 4296 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4297 S = MCDisassembler::SoftFail; 4298 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 4310 return S; 4311 } 4312 4313 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4314 uint64_t Address, const void *Decoder) { 4315 DecodeStatus S = MCDisassembler::Success; 4316 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4317 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4318 4319 if (pred == 0xF) { 4320 pred = 0xE; 4321 S = MCDisassembler::SoftFail; 4322 } 4323 4324 if (mask == 0x0) { 4325 mask |= 0x8; 4326 S = MCDisassembler::SoftFail; 4327 } 4328 4329 Inst.addOperand(MCOperand::CreateImm(pred)); 4330 Inst.addOperand(MCOperand::CreateImm(mask)); 4331 return S; 4332 } 4333 4334 static DecodeStatus 4335 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4336 uint64_t Address, const void *Decoder) { 4337 DecodeStatus S = MCDisassembler::Success; 4338 4339 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4340 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4341 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4342 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4343 unsigned W = fieldFromInstruction(Insn, 21, 1); 4344 unsigned U = fieldFromInstruction(Insn, 23, 1); 4345 unsigned P = fieldFromInstruction(Insn, 24, 1); 4346 bool writeback = (W == 1) | (P == 0); 4347 4348 addr |= (U << 8) | (Rn << 9); 4349 4350 if (writeback && (Rn == Rt || Rn == Rt2)) 4351 Check(S, MCDisassembler::SoftFail); 4352 if (Rt == Rt2) 4353 Check(S, MCDisassembler::SoftFail); 4354 4355 // Rt 4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 // Rt2 4359 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 // Writeback operand 4362 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 // addr 4365 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 4368 return S; 4369 } 4370 4371 static DecodeStatus 4372 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4373 uint64_t Address, const void *Decoder) { 4374 DecodeStatus S = MCDisassembler::Success; 4375 4376 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4377 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4378 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4379 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4380 unsigned W = fieldFromInstruction(Insn, 21, 1); 4381 unsigned U = fieldFromInstruction(Insn, 23, 1); 4382 unsigned P = fieldFromInstruction(Insn, 24, 1); 4383 bool writeback = (W == 1) | (P == 0); 4384 4385 addr |= (U << 8) | (Rn << 9); 4386 4387 if (writeback && (Rn == Rt || Rn == Rt2)) 4388 Check(S, MCDisassembler::SoftFail); 4389 4390 // Writeback operand 4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 // Rt 4394 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 // Rt2 4397 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4398 return MCDisassembler::Fail; 4399 // addr 4400 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 4403 return S; 4404 } 4405 4406 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4407 uint64_t Address, const void *Decoder) { 4408 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4409 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4410 if (sign1 != sign2) return MCDisassembler::Fail; 4411 4412 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4413 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4414 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4415 Val |= sign1 << 12; 4416 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4417 4418 return MCDisassembler::Success; 4419 } 4420 4421 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4422 uint64_t Address, 4423 const void *Decoder) { 4424 DecodeStatus S = MCDisassembler::Success; 4425 4426 // Shift of "asr #32" is not allowed in Thumb2 mode. 4427 if (Val == 0x20) S = MCDisassembler::SoftFail; 4428 Inst.addOperand(MCOperand::CreateImm(Val)); 4429 return S; 4430 } 4431 4432 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4433 uint64_t Address, const void *Decoder) { 4434 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4435 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4436 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4437 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4438 4439 if (pred == 0xF) 4440 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4441 4442 DecodeStatus S = MCDisassembler::Success; 4443 4444 if (Rt == Rn || Rn == Rt2) 4445 S = MCDisassembler::SoftFail; 4446 4447 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4450 return MCDisassembler::Fail; 4451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4452 return MCDisassembler::Fail; 4453 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4454 return MCDisassembler::Fail; 4455 4456 return S; 4457 } 4458 4459 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4460 uint64_t Address, const void *Decoder) { 4461 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4462 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4463 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4464 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4465 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4466 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4467 4468 DecodeStatus S = MCDisassembler::Success; 4469 4470 // VMOVv2f32 is ambiguous with these decodings. 4471 if (!(imm & 0x38) && cmode == 0xF) { 4472 Inst.setOpcode(ARM::VMOVv2f32); 4473 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4474 } 4475 4476 if (!(imm & 0x20)) return MCDisassembler::Fail; 4477 4478 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4479 return MCDisassembler::Fail; 4480 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4481 return MCDisassembler::Fail; 4482 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4483 4484 return S; 4485 } 4486 4487 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4488 uint64_t Address, const void *Decoder) { 4489 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4490 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4491 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4492 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4493 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4494 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4495 4496 DecodeStatus S = MCDisassembler::Success; 4497 4498 // VMOVv4f32 is ambiguous with these decodings. 4499 if (!(imm & 0x38) && cmode == 0xF) { 4500 Inst.setOpcode(ARM::VMOVv4f32); 4501 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4502 } 4503 4504 if (!(imm & 0x20)) return MCDisassembler::Fail; 4505 4506 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4507 return MCDisassembler::Fail; 4508 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4509 return MCDisassembler::Fail; 4510 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4511 4512 return S; 4513 } 4514 4515 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4516 const void *Decoder) 4517 { 4518 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4519 if (Imm > 4) return MCDisassembler::Fail; 4520 Inst.addOperand(MCOperand::CreateImm(Imm)); 4521 return MCDisassembler::Success; 4522 } 4523 4524 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4525 uint64_t Address, const void *Decoder) { 4526 DecodeStatus S = MCDisassembler::Success; 4527 4528 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4529 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4530 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4531 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4532 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4533 4534 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4535 S = MCDisassembler::SoftFail; 4536 4537 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4538 return MCDisassembler::Fail; 4539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4542 return MCDisassembler::Fail; 4543 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 4548 return S; 4549 } 4550 4551 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4552 uint64_t Address, const void *Decoder) { 4553 4554 DecodeStatus S = MCDisassembler::Success; 4555 4556 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4557 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4558 unsigned cop = fieldFromInstruction(Val, 8, 4); 4559 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4560 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4561 4562 if ((cop & ~0x1) == 0xa) 4563 return MCDisassembler::Fail; 4564 4565 if (Rt == Rt2) 4566 S = MCDisassembler::SoftFail; 4567 4568 Inst.addOperand(MCOperand::CreateImm(cop)); 4569 Inst.addOperand(MCOperand::CreateImm(opc1)); 4570 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4573 return MCDisassembler::Fail; 4574 Inst.addOperand(MCOperand::CreateImm(CRm)); 4575 4576 return S; 4577 } 4578 4579