1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 327 const void *Decoder); 328 329 330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void* Decoder); 358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 #include "ARMGenDisassemblerTables.inc" 408 409 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 410 return new ARMDisassembler(STI); 411 } 412 413 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 414 return new ThumbDisassembler(STI); 415 } 416 417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 418 const MemoryObject &Region, 419 uint64_t Address, 420 raw_ostream &os, 421 raw_ostream &cs) const { 422 CommentStream = &cs; 423 424 uint8_t bytes[4]; 425 426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 428 429 // We want to read exactly 4 bytes of data. 430 if (Region.readBytes(Address, 4, bytes) == -1) { 431 Size = 0; 432 return MCDisassembler::Fail; 433 } 434 435 // Encoded as a small-endian 32-bit word in the stream. 436 uint32_t insn = (bytes[3] << 24) | 437 (bytes[2] << 16) | 438 (bytes[1] << 8) | 439 (bytes[0] << 0); 440 441 // Calling the auto-generated decoder function. 442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 443 Address, this, STI); 444 if (result != MCDisassembler::Fail) { 445 Size = 4; 446 return result; 447 } 448 449 // VFP and NEON instructions, similarly, are shared between ARM 450 // and Thumb modes. 451 MI.clear(); 452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 460 this, STI); 461 if (result != MCDisassembler::Fail) { 462 Size = 4; 463 // Add a fake predicate operand, because we share these instruction 464 // definitions with Thumb2 where these instructions are predicable. 465 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 466 return MCDisassembler::Fail; 467 return result; 468 } 469 470 MI.clear(); 471 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 472 this, STI); 473 if (result != MCDisassembler::Fail) { 474 Size = 4; 475 // Add a fake predicate operand, because we share these instruction 476 // definitions with Thumb2 where these instructions are predicable. 477 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 478 return MCDisassembler::Fail; 479 return result; 480 } 481 482 MI.clear(); 483 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 484 this, STI); 485 if (result != MCDisassembler::Fail) { 486 Size = 4; 487 // Add a fake predicate operand, because we share these instruction 488 // definitions with Thumb2 where these instructions are predicable. 489 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 490 return MCDisassembler::Fail; 491 return result; 492 } 493 494 MI.clear(); 495 496 Size = 0; 497 return MCDisassembler::Fail; 498 } 499 500 namespace llvm { 501 extern const MCInstrDesc ARMInsts[]; 502 } 503 504 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 505 /// immediate Value in the MCInst. The immediate Value has had any PC 506 /// adjustment made by the caller. If the instruction is a branch instruction 507 /// then isBranch is true, else false. If the getOpInfo() function was set as 508 /// part of the setupForSymbolicDisassembly() call then that function is called 509 /// to get any symbolic information at the Address for this instruction. If 510 /// that returns non-zero then the symbolic information it returns is used to 511 /// create an MCExpr and that is added as an operand to the MCInst. If 512 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 513 /// Value is done and if a symbol is found an MCExpr is created with that, else 514 /// an MCExpr with Value is created. This function returns true if it adds an 515 /// operand to the MCInst and false otherwise. 516 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 517 bool isBranch, uint64_t InstSize, 518 MCInst &MI, const void *Decoder) { 519 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 520 // FIXME: Does it make sense for value to be negative? 521 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 522 /* Offset */ 0, InstSize); 523 } 524 525 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 526 /// referenced by a load instruction with the base register that is the Pc. 527 /// These can often be values in a literal pool near the Address of the 528 /// instruction. The Address of the instruction and its immediate Value are 529 /// used as a possible literal pool entry. The SymbolLookUp call back will 530 /// return the name of a symbol referenced by the literal pool's entry if 531 /// the referenced address is that of a symbol. Or it will return a pointer to 532 /// a literal 'C' string if the referenced address of the literal pool's entry 533 /// is an address into a section with 'C' string literals. 534 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 535 const void *Decoder) { 536 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 537 Dis->tryAddingPcLoadReferenceComment(Value, Address); 538 } 539 540 // Thumb1 instructions don't have explicit S bits. Rather, they 541 // implicitly set CPSR. Since it's not represented in the encoding, the 542 // auto-generated decoder won't inject the CPSR operand. We need to fix 543 // that as a post-pass. 544 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 545 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 546 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 547 MCInst::iterator I = MI.begin(); 548 for (unsigned i = 0; i < NumOps; ++i, ++I) { 549 if (I == MI.end()) break; 550 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 551 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 552 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 553 return; 554 } 555 } 556 557 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 558 } 559 560 // Most Thumb instructions don't have explicit predicates in the 561 // encoding, but rather get their predicates from IT context. We need 562 // to fix up the predicate operands using this context information as a 563 // post-pass. 564 MCDisassembler::DecodeStatus 565 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 566 MCDisassembler::DecodeStatus S = Success; 567 568 // A few instructions actually have predicates encoded in them. Don't 569 // try to overwrite it if we're seeing one of those. 570 switch (MI.getOpcode()) { 571 case ARM::tBcc: 572 case ARM::t2Bcc: 573 case ARM::tCBZ: 574 case ARM::tCBNZ: 575 case ARM::tCPS: 576 case ARM::t2CPS3p: 577 case ARM::t2CPS2p: 578 case ARM::t2CPS1p: 579 case ARM::tMOVSr: 580 case ARM::tSETEND: 581 // Some instructions (mostly conditional branches) are not 582 // allowed in IT blocks. 583 if (ITBlock.instrInITBlock()) 584 S = SoftFail; 585 else 586 return Success; 587 break; 588 case ARM::tB: 589 case ARM::t2B: 590 case ARM::t2TBB: 591 case ARM::t2TBH: 592 // Some instructions (mostly unconditional branches) can 593 // only appears at the end of, or outside of, an IT. 594 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 595 S = SoftFail; 596 break; 597 default: 598 break; 599 } 600 601 // If we're in an IT block, base the predicate on that. Otherwise, 602 // assume a predicate of AL. 603 unsigned CC; 604 CC = ITBlock.getITCC(); 605 if (CC == 0xF) 606 CC = ARMCC::AL; 607 if (ITBlock.instrInITBlock()) 608 ITBlock.advanceITState(); 609 610 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 611 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 612 MCInst::iterator I = MI.begin(); 613 for (unsigned i = 0; i < NumOps; ++i, ++I) { 614 if (I == MI.end()) break; 615 if (OpInfo[i].isPredicate()) { 616 I = MI.insert(I, MCOperand::CreateImm(CC)); 617 ++I; 618 if (CC == ARMCC::AL) 619 MI.insert(I, MCOperand::CreateReg(0)); 620 else 621 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 622 return S; 623 } 624 } 625 626 I = MI.insert(I, MCOperand::CreateImm(CC)); 627 ++I; 628 if (CC == ARMCC::AL) 629 MI.insert(I, MCOperand::CreateReg(0)); 630 else 631 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 632 633 return S; 634 } 635 636 // Thumb VFP instructions are a special case. Because we share their 637 // encodings between ARM and Thumb modes, and they are predicable in ARM 638 // mode, the auto-generated decoder will give them an (incorrect) 639 // predicate operand. We need to rewrite these operands based on the IT 640 // context as a post-pass. 641 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 642 unsigned CC; 643 CC = ITBlock.getITCC(); 644 if (ITBlock.instrInITBlock()) 645 ITBlock.advanceITState(); 646 647 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 648 MCInst::iterator I = MI.begin(); 649 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 650 for (unsigned i = 0; i < NumOps; ++i, ++I) { 651 if (OpInfo[i].isPredicate() ) { 652 I->setImm(CC); 653 ++I; 654 if (CC == ARMCC::AL) 655 I->setReg(0); 656 else 657 I->setReg(ARM::CPSR); 658 return; 659 } 660 } 661 } 662 663 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 664 const MemoryObject &Region, 665 uint64_t Address, 666 raw_ostream &os, 667 raw_ostream &cs) const { 668 CommentStream = &cs; 669 670 uint8_t bytes[4]; 671 672 assert((STI.getFeatureBits() & ARM::ModeThumb) && 673 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 674 675 // We want to read exactly 2 bytes of data. 676 if (Region.readBytes(Address, 2, bytes) == -1) { 677 Size = 0; 678 return MCDisassembler::Fail; 679 } 680 681 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 682 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 683 Address, this, STI); 684 if (result != MCDisassembler::Fail) { 685 Size = 2; 686 Check(result, AddThumbPredicate(MI)); 687 return result; 688 } 689 690 MI.clear(); 691 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 692 Address, this, STI); 693 if (result) { 694 Size = 2; 695 bool InITBlock = ITBlock.instrInITBlock(); 696 Check(result, AddThumbPredicate(MI)); 697 AddThumb1SBit(MI, InITBlock); 698 return result; 699 } 700 701 MI.clear(); 702 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 703 Address, this, STI); 704 if (result != MCDisassembler::Fail) { 705 Size = 2; 706 707 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 708 // the Thumb predicate. 709 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 710 result = MCDisassembler::SoftFail; 711 712 Check(result, AddThumbPredicate(MI)); 713 714 // If we find an IT instruction, we need to parse its condition 715 // code and mask operands so that we can apply them correctly 716 // to the subsequent instructions. 717 if (MI.getOpcode() == ARM::t2IT) { 718 719 unsigned Firstcond = MI.getOperand(0).getImm(); 720 unsigned Mask = MI.getOperand(1).getImm(); 721 ITBlock.setITState(Firstcond, Mask); 722 } 723 724 return result; 725 } 726 727 // We want to read exactly 4 bytes of data. 728 if (Region.readBytes(Address, 4, bytes) == -1) { 729 Size = 0; 730 return MCDisassembler::Fail; 731 } 732 733 uint32_t insn32 = (bytes[3] << 8) | 734 (bytes[2] << 0) | 735 (bytes[1] << 24) | 736 (bytes[0] << 16); 737 MI.clear(); 738 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 739 this, STI); 740 if (result != MCDisassembler::Fail) { 741 Size = 4; 742 bool InITBlock = ITBlock.instrInITBlock(); 743 Check(result, AddThumbPredicate(MI)); 744 AddThumb1SBit(MI, InITBlock); 745 return result; 746 } 747 748 MI.clear(); 749 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 750 this, STI); 751 if (result != MCDisassembler::Fail) { 752 Size = 4; 753 Check(result, AddThumbPredicate(MI)); 754 return result; 755 } 756 757 MI.clear(); 758 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 759 if (result != MCDisassembler::Fail) { 760 Size = 4; 761 UpdateThumbVFPPredicate(MI); 762 return result; 763 } 764 765 MI.clear(); 766 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 767 this, STI); 768 if (result != MCDisassembler::Fail) { 769 Size = 4; 770 Check(result, AddThumbPredicate(MI)); 771 return result; 772 } 773 774 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 775 MI.clear(); 776 uint32_t NEONLdStInsn = insn32; 777 NEONLdStInsn &= 0xF0FFFFFF; 778 NEONLdStInsn |= 0x04000000; 779 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 780 Address, this, STI); 781 if (result != MCDisassembler::Fail) { 782 Size = 4; 783 Check(result, AddThumbPredicate(MI)); 784 return result; 785 } 786 } 787 788 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 789 MI.clear(); 790 uint32_t NEONDataInsn = insn32; 791 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 792 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 793 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 794 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 795 Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 4; 798 Check(result, AddThumbPredicate(MI)); 799 return result; 800 } 801 } 802 803 Size = 0; 804 return MCDisassembler::Fail; 805 } 806 807 808 extern "C" void LLVMInitializeARMDisassembler() { 809 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 810 createARMDisassembler); 811 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 812 createThumbDisassembler); 813 } 814 815 static const uint16_t GPRDecoderTable[] = { 816 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 817 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 818 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 819 ARM::R12, ARM::SP, ARM::LR, ARM::PC 820 }; 821 822 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 823 uint64_t Address, const void *Decoder) { 824 if (RegNo > 15) 825 return MCDisassembler::Fail; 826 827 unsigned Register = GPRDecoderTable[RegNo]; 828 Inst.addOperand(MCOperand::CreateReg(Register)); 829 return MCDisassembler::Success; 830 } 831 832 static DecodeStatus 833 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 834 uint64_t Address, const void *Decoder) { 835 DecodeStatus S = MCDisassembler::Success; 836 837 if (RegNo == 15) 838 S = MCDisassembler::SoftFail; 839 840 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 841 842 return S; 843 } 844 845 static DecodeStatus 846 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 847 uint64_t Address, const void *Decoder) { 848 DecodeStatus S = MCDisassembler::Success; 849 850 if (RegNo == 15) 851 { 852 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 853 return MCDisassembler::Success; 854 } 855 856 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 857 return S; 858 } 859 860 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 861 uint64_t Address, const void *Decoder) { 862 if (RegNo > 7) 863 return MCDisassembler::Fail; 864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 865 } 866 867 static const uint16_t GPRPairDecoderTable[] = { 868 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 869 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 870 }; 871 872 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 873 uint64_t Address, const void *Decoder) { 874 DecodeStatus S = MCDisassembler::Success; 875 876 if (RegNo > 13) 877 return MCDisassembler::Fail; 878 879 if ((RegNo & 1) || RegNo == 0xe) 880 S = MCDisassembler::SoftFail; 881 882 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 883 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 884 return S; 885 } 886 887 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 888 uint64_t Address, const void *Decoder) { 889 unsigned Register = 0; 890 switch (RegNo) { 891 case 0: 892 Register = ARM::R0; 893 break; 894 case 1: 895 Register = ARM::R1; 896 break; 897 case 2: 898 Register = ARM::R2; 899 break; 900 case 3: 901 Register = ARM::R3; 902 break; 903 case 9: 904 Register = ARM::R9; 905 break; 906 case 12: 907 Register = ARM::R12; 908 break; 909 default: 910 return MCDisassembler::Fail; 911 } 912 913 Inst.addOperand(MCOperand::CreateReg(Register)); 914 return MCDisassembler::Success; 915 } 916 917 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 918 uint64_t Address, const void *Decoder) { 919 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 920 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 921 } 922 923 static const uint16_t SPRDecoderTable[] = { 924 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 925 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 926 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 927 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 928 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 929 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 930 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 931 ARM::S28, ARM::S29, ARM::S30, ARM::S31 932 }; 933 934 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 935 uint64_t Address, const void *Decoder) { 936 if (RegNo > 31) 937 return MCDisassembler::Fail; 938 939 unsigned Register = SPRDecoderTable[RegNo]; 940 Inst.addOperand(MCOperand::CreateReg(Register)); 941 return MCDisassembler::Success; 942 } 943 944 static const uint16_t DPRDecoderTable[] = { 945 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 946 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 947 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 948 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 949 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 950 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 951 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 952 ARM::D28, ARM::D29, ARM::D30, ARM::D31 953 }; 954 955 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 956 uint64_t Address, const void *Decoder) { 957 if (RegNo > 31) 958 return MCDisassembler::Fail; 959 960 unsigned Register = DPRDecoderTable[RegNo]; 961 Inst.addOperand(MCOperand::CreateReg(Register)); 962 return MCDisassembler::Success; 963 } 964 965 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 966 uint64_t Address, const void *Decoder) { 967 if (RegNo > 7) 968 return MCDisassembler::Fail; 969 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 970 } 971 972 static DecodeStatus 973 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 974 uint64_t Address, const void *Decoder) { 975 if (RegNo > 15) 976 return MCDisassembler::Fail; 977 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 978 } 979 980 static const uint16_t QPRDecoderTable[] = { 981 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 982 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 983 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 984 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 985 }; 986 987 988 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 989 uint64_t Address, const void *Decoder) { 990 if (RegNo > 31 || (RegNo & 1) != 0) 991 return MCDisassembler::Fail; 992 RegNo >>= 1; 993 994 unsigned Register = QPRDecoderTable[RegNo]; 995 Inst.addOperand(MCOperand::CreateReg(Register)); 996 return MCDisassembler::Success; 997 } 998 999 static const uint16_t DPairDecoderTable[] = { 1000 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1001 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1002 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1003 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1004 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1005 ARM::Q15 1006 }; 1007 1008 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 30) 1011 return MCDisassembler::Fail; 1012 1013 unsigned Register = DPairDecoderTable[RegNo]; 1014 Inst.addOperand(MCOperand::CreateReg(Register)); 1015 return MCDisassembler::Success; 1016 } 1017 1018 static const uint16_t DPairSpacedDecoderTable[] = { 1019 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1020 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1021 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1022 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1023 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1024 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1025 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1026 ARM::D28_D30, ARM::D29_D31 1027 }; 1028 1029 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1030 unsigned RegNo, 1031 uint64_t Address, 1032 const void *Decoder) { 1033 if (RegNo > 29) 1034 return MCDisassembler::Fail; 1035 1036 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1037 Inst.addOperand(MCOperand::CreateReg(Register)); 1038 return MCDisassembler::Success; 1039 } 1040 1041 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1042 uint64_t Address, const void *Decoder) { 1043 if (Val == 0xF) return MCDisassembler::Fail; 1044 // AL predicate is not allowed on Thumb1 branches. 1045 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1046 return MCDisassembler::Fail; 1047 Inst.addOperand(MCOperand::CreateImm(Val)); 1048 if (Val == ARMCC::AL) { 1049 Inst.addOperand(MCOperand::CreateReg(0)); 1050 } else 1051 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1052 return MCDisassembler::Success; 1053 } 1054 1055 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1056 uint64_t Address, const void *Decoder) { 1057 if (Val) 1058 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1059 else 1060 Inst.addOperand(MCOperand::CreateReg(0)); 1061 return MCDisassembler::Success; 1062 } 1063 1064 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1065 uint64_t Address, const void *Decoder) { 1066 uint32_t imm = Val & 0xFF; 1067 uint32_t rot = (Val & 0xF00) >> 7; 1068 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1069 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1070 return MCDisassembler::Success; 1071 } 1072 1073 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1074 uint64_t Address, const void *Decoder) { 1075 DecodeStatus S = MCDisassembler::Success; 1076 1077 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1078 unsigned type = fieldFromInstruction(Val, 5, 2); 1079 unsigned imm = fieldFromInstruction(Val, 7, 5); 1080 1081 // Register-immediate 1082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1083 return MCDisassembler::Fail; 1084 1085 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1086 switch (type) { 1087 case 0: 1088 Shift = ARM_AM::lsl; 1089 break; 1090 case 1: 1091 Shift = ARM_AM::lsr; 1092 break; 1093 case 2: 1094 Shift = ARM_AM::asr; 1095 break; 1096 case 3: 1097 Shift = ARM_AM::ror; 1098 break; 1099 } 1100 1101 if (Shift == ARM_AM::ror && imm == 0) 1102 Shift = ARM_AM::rrx; 1103 1104 unsigned Op = Shift | (imm << 3); 1105 Inst.addOperand(MCOperand::CreateImm(Op)); 1106 1107 return S; 1108 } 1109 1110 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1111 uint64_t Address, const void *Decoder) { 1112 DecodeStatus S = MCDisassembler::Success; 1113 1114 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1115 unsigned type = fieldFromInstruction(Val, 5, 2); 1116 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1117 1118 // Register-register 1119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1120 return MCDisassembler::Fail; 1121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1122 return MCDisassembler::Fail; 1123 1124 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1125 switch (type) { 1126 case 0: 1127 Shift = ARM_AM::lsl; 1128 break; 1129 case 1: 1130 Shift = ARM_AM::lsr; 1131 break; 1132 case 2: 1133 Shift = ARM_AM::asr; 1134 break; 1135 case 3: 1136 Shift = ARM_AM::ror; 1137 break; 1138 } 1139 1140 Inst.addOperand(MCOperand::CreateImm(Shift)); 1141 1142 return S; 1143 } 1144 1145 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1146 uint64_t Address, const void *Decoder) { 1147 DecodeStatus S = MCDisassembler::Success; 1148 1149 bool writebackLoad = false; 1150 unsigned writebackReg = 0; 1151 switch (Inst.getOpcode()) { 1152 default: 1153 break; 1154 case ARM::LDMIA_UPD: 1155 case ARM::LDMDB_UPD: 1156 case ARM::LDMIB_UPD: 1157 case ARM::LDMDA_UPD: 1158 case ARM::t2LDMIA_UPD: 1159 case ARM::t2LDMDB_UPD: 1160 writebackLoad = true; 1161 writebackReg = Inst.getOperand(0).getReg(); 1162 break; 1163 } 1164 1165 // Empty register lists are not allowed. 1166 if (Val == 0) return MCDisassembler::Fail; 1167 for (unsigned i = 0; i < 16; ++i) { 1168 if (Val & (1 << i)) { 1169 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1170 return MCDisassembler::Fail; 1171 // Writeback not allowed if Rn is in the target list. 1172 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1173 Check(S, MCDisassembler::SoftFail); 1174 } 1175 } 1176 1177 return S; 1178 } 1179 1180 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1181 uint64_t Address, const void *Decoder) { 1182 DecodeStatus S = MCDisassembler::Success; 1183 1184 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1185 unsigned regs = fieldFromInstruction(Val, 0, 8); 1186 1187 // In case of unpredictable encoding, tweak the operands. 1188 if (regs == 0 || (Vd + regs) > 32) { 1189 regs = Vd + regs > 32 ? 32 - Vd : regs; 1190 regs = std::max( 1u, regs); 1191 S = MCDisassembler::SoftFail; 1192 } 1193 1194 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1195 return MCDisassembler::Fail; 1196 for (unsigned i = 0; i < (regs - 1); ++i) { 1197 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1198 return MCDisassembler::Fail; 1199 } 1200 1201 return S; 1202 } 1203 1204 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1205 uint64_t Address, const void *Decoder) { 1206 DecodeStatus S = MCDisassembler::Success; 1207 1208 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1209 unsigned regs = fieldFromInstruction(Val, 1, 7); 1210 1211 // In case of unpredictable encoding, tweak the operands. 1212 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1213 regs = Vd + regs > 32 ? 32 - Vd : regs; 1214 regs = std::max( 1u, regs); 1215 regs = std::min(16u, regs); 1216 S = MCDisassembler::SoftFail; 1217 } 1218 1219 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1220 return MCDisassembler::Fail; 1221 for (unsigned i = 0; i < (regs - 1); ++i) { 1222 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1223 return MCDisassembler::Fail; 1224 } 1225 1226 return S; 1227 } 1228 1229 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1230 uint64_t Address, const void *Decoder) { 1231 // This operand encodes a mask of contiguous zeros between a specified MSB 1232 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1233 // the mask of all bits LSB-and-lower, and then xor them to create 1234 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1235 // create the final mask. 1236 unsigned msb = fieldFromInstruction(Val, 5, 5); 1237 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1238 1239 DecodeStatus S = MCDisassembler::Success; 1240 if (lsb > msb) { 1241 Check(S, MCDisassembler::SoftFail); 1242 // The check above will cause the warning for the "potentially undefined 1243 // instruction encoding" but we can't build a bad MCOperand value here 1244 // with a lsb > msb or else printing the MCInst will cause a crash. 1245 lsb = msb; 1246 } 1247 1248 uint32_t msb_mask = 0xFFFFFFFF; 1249 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1250 uint32_t lsb_mask = (1U << lsb) - 1; 1251 1252 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1253 return S; 1254 } 1255 1256 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1257 uint64_t Address, const void *Decoder) { 1258 DecodeStatus S = MCDisassembler::Success; 1259 1260 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1261 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1262 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1263 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1264 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1265 unsigned U = fieldFromInstruction(Insn, 23, 1); 1266 1267 switch (Inst.getOpcode()) { 1268 case ARM::LDC_OFFSET: 1269 case ARM::LDC_PRE: 1270 case ARM::LDC_POST: 1271 case ARM::LDC_OPTION: 1272 case ARM::LDCL_OFFSET: 1273 case ARM::LDCL_PRE: 1274 case ARM::LDCL_POST: 1275 case ARM::LDCL_OPTION: 1276 case ARM::STC_OFFSET: 1277 case ARM::STC_PRE: 1278 case ARM::STC_POST: 1279 case ARM::STC_OPTION: 1280 case ARM::STCL_OFFSET: 1281 case ARM::STCL_PRE: 1282 case ARM::STCL_POST: 1283 case ARM::STCL_OPTION: 1284 case ARM::t2LDC_OFFSET: 1285 case ARM::t2LDC_PRE: 1286 case ARM::t2LDC_POST: 1287 case ARM::t2LDC_OPTION: 1288 case ARM::t2LDCL_OFFSET: 1289 case ARM::t2LDCL_PRE: 1290 case ARM::t2LDCL_POST: 1291 case ARM::t2LDCL_OPTION: 1292 case ARM::t2STC_OFFSET: 1293 case ARM::t2STC_PRE: 1294 case ARM::t2STC_POST: 1295 case ARM::t2STC_OPTION: 1296 case ARM::t2STCL_OFFSET: 1297 case ARM::t2STCL_PRE: 1298 case ARM::t2STCL_POST: 1299 case ARM::t2STCL_OPTION: 1300 if (coproc == 0xA || coproc == 0xB) 1301 return MCDisassembler::Fail; 1302 break; 1303 default: 1304 break; 1305 } 1306 1307 Inst.addOperand(MCOperand::CreateImm(coproc)); 1308 Inst.addOperand(MCOperand::CreateImm(CRd)); 1309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1310 return MCDisassembler::Fail; 1311 1312 switch (Inst.getOpcode()) { 1313 case ARM::t2LDC2_OFFSET: 1314 case ARM::t2LDC2L_OFFSET: 1315 case ARM::t2LDC2_PRE: 1316 case ARM::t2LDC2L_PRE: 1317 case ARM::t2STC2_OFFSET: 1318 case ARM::t2STC2L_OFFSET: 1319 case ARM::t2STC2_PRE: 1320 case ARM::t2STC2L_PRE: 1321 case ARM::LDC2_OFFSET: 1322 case ARM::LDC2L_OFFSET: 1323 case ARM::LDC2_PRE: 1324 case ARM::LDC2L_PRE: 1325 case ARM::STC2_OFFSET: 1326 case ARM::STC2L_OFFSET: 1327 case ARM::STC2_PRE: 1328 case ARM::STC2L_PRE: 1329 case ARM::t2LDC_OFFSET: 1330 case ARM::t2LDCL_OFFSET: 1331 case ARM::t2LDC_PRE: 1332 case ARM::t2LDCL_PRE: 1333 case ARM::t2STC_OFFSET: 1334 case ARM::t2STCL_OFFSET: 1335 case ARM::t2STC_PRE: 1336 case ARM::t2STCL_PRE: 1337 case ARM::LDC_OFFSET: 1338 case ARM::LDCL_OFFSET: 1339 case ARM::LDC_PRE: 1340 case ARM::LDCL_PRE: 1341 case ARM::STC_OFFSET: 1342 case ARM::STCL_OFFSET: 1343 case ARM::STC_PRE: 1344 case ARM::STCL_PRE: 1345 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1346 Inst.addOperand(MCOperand::CreateImm(imm)); 1347 break; 1348 case ARM::t2LDC2_POST: 1349 case ARM::t2LDC2L_POST: 1350 case ARM::t2STC2_POST: 1351 case ARM::t2STC2L_POST: 1352 case ARM::LDC2_POST: 1353 case ARM::LDC2L_POST: 1354 case ARM::STC2_POST: 1355 case ARM::STC2L_POST: 1356 case ARM::t2LDC_POST: 1357 case ARM::t2LDCL_POST: 1358 case ARM::t2STC_POST: 1359 case ARM::t2STCL_POST: 1360 case ARM::LDC_POST: 1361 case ARM::LDCL_POST: 1362 case ARM::STC_POST: 1363 case ARM::STCL_POST: 1364 imm |= U << 8; 1365 // fall through. 1366 default: 1367 // The 'option' variant doesn't encode 'U' in the immediate since 1368 // the immediate is unsigned [0,255]. 1369 Inst.addOperand(MCOperand::CreateImm(imm)); 1370 break; 1371 } 1372 1373 switch (Inst.getOpcode()) { 1374 case ARM::LDC_OFFSET: 1375 case ARM::LDC_PRE: 1376 case ARM::LDC_POST: 1377 case ARM::LDC_OPTION: 1378 case ARM::LDCL_OFFSET: 1379 case ARM::LDCL_PRE: 1380 case ARM::LDCL_POST: 1381 case ARM::LDCL_OPTION: 1382 case ARM::STC_OFFSET: 1383 case ARM::STC_PRE: 1384 case ARM::STC_POST: 1385 case ARM::STC_OPTION: 1386 case ARM::STCL_OFFSET: 1387 case ARM::STCL_PRE: 1388 case ARM::STCL_POST: 1389 case ARM::STCL_OPTION: 1390 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1391 return MCDisassembler::Fail; 1392 break; 1393 default: 1394 break; 1395 } 1396 1397 return S; 1398 } 1399 1400 static DecodeStatus 1401 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1402 uint64_t Address, const void *Decoder) { 1403 DecodeStatus S = MCDisassembler::Success; 1404 1405 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1406 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1407 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1408 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1409 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1410 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1411 unsigned P = fieldFromInstruction(Insn, 24, 1); 1412 unsigned W = fieldFromInstruction(Insn, 21, 1); 1413 1414 // On stores, the writeback operand precedes Rt. 1415 switch (Inst.getOpcode()) { 1416 case ARM::STR_POST_IMM: 1417 case ARM::STR_POST_REG: 1418 case ARM::STRB_POST_IMM: 1419 case ARM::STRB_POST_REG: 1420 case ARM::STRT_POST_REG: 1421 case ARM::STRT_POST_IMM: 1422 case ARM::STRBT_POST_REG: 1423 case ARM::STRBT_POST_IMM: 1424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1425 return MCDisassembler::Fail; 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1432 return MCDisassembler::Fail; 1433 1434 // On loads, the writeback operand comes after Rt. 1435 switch (Inst.getOpcode()) { 1436 case ARM::LDR_POST_IMM: 1437 case ARM::LDR_POST_REG: 1438 case ARM::LDRB_POST_IMM: 1439 case ARM::LDRB_POST_REG: 1440 case ARM::LDRBT_POST_REG: 1441 case ARM::LDRBT_POST_IMM: 1442 case ARM::LDRT_POST_REG: 1443 case ARM::LDRT_POST_IMM: 1444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1445 return MCDisassembler::Fail; 1446 break; 1447 default: 1448 break; 1449 } 1450 1451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1452 return MCDisassembler::Fail; 1453 1454 ARM_AM::AddrOpc Op = ARM_AM::add; 1455 if (!fieldFromInstruction(Insn, 23, 1)) 1456 Op = ARM_AM::sub; 1457 1458 bool writeback = (P == 0) || (W == 1); 1459 unsigned idx_mode = 0; 1460 if (P && writeback) 1461 idx_mode = ARMII::IndexModePre; 1462 else if (!P && writeback) 1463 idx_mode = ARMII::IndexModePost; 1464 1465 if (writeback && (Rn == 15 || Rn == Rt)) 1466 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1467 1468 if (reg) { 1469 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1470 return MCDisassembler::Fail; 1471 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1472 switch( fieldFromInstruction(Insn, 5, 2)) { 1473 case 0: 1474 Opc = ARM_AM::lsl; 1475 break; 1476 case 1: 1477 Opc = ARM_AM::lsr; 1478 break; 1479 case 2: 1480 Opc = ARM_AM::asr; 1481 break; 1482 case 3: 1483 Opc = ARM_AM::ror; 1484 break; 1485 default: 1486 return MCDisassembler::Fail; 1487 } 1488 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1489 if (Opc == ARM_AM::ror && amt == 0) 1490 Opc = ARM_AM::rrx; 1491 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1492 1493 Inst.addOperand(MCOperand::CreateImm(imm)); 1494 } else { 1495 Inst.addOperand(MCOperand::CreateReg(0)); 1496 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1497 Inst.addOperand(MCOperand::CreateImm(tmp)); 1498 } 1499 1500 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1501 return MCDisassembler::Fail; 1502 1503 return S; 1504 } 1505 1506 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1507 uint64_t Address, const void *Decoder) { 1508 DecodeStatus S = MCDisassembler::Success; 1509 1510 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1511 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1512 unsigned type = fieldFromInstruction(Val, 5, 2); 1513 unsigned imm = fieldFromInstruction(Val, 7, 5); 1514 unsigned U = fieldFromInstruction(Val, 12, 1); 1515 1516 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1517 switch (type) { 1518 case 0: 1519 ShOp = ARM_AM::lsl; 1520 break; 1521 case 1: 1522 ShOp = ARM_AM::lsr; 1523 break; 1524 case 2: 1525 ShOp = ARM_AM::asr; 1526 break; 1527 case 3: 1528 ShOp = ARM_AM::ror; 1529 break; 1530 } 1531 1532 if (ShOp == ARM_AM::ror && imm == 0) 1533 ShOp = ARM_AM::rrx; 1534 1535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1536 return MCDisassembler::Fail; 1537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1538 return MCDisassembler::Fail; 1539 unsigned shift; 1540 if (U) 1541 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1542 else 1543 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1544 Inst.addOperand(MCOperand::CreateImm(shift)); 1545 1546 return S; 1547 } 1548 1549 static DecodeStatus 1550 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1551 uint64_t Address, const void *Decoder) { 1552 DecodeStatus S = MCDisassembler::Success; 1553 1554 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1555 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1556 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1557 unsigned type = fieldFromInstruction(Insn, 22, 1); 1558 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1559 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1560 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1561 unsigned W = fieldFromInstruction(Insn, 21, 1); 1562 unsigned P = fieldFromInstruction(Insn, 24, 1); 1563 unsigned Rt2 = Rt + 1; 1564 1565 bool writeback = (W == 1) | (P == 0); 1566 1567 // For {LD,ST}RD, Rt must be even, else undefined. 1568 switch (Inst.getOpcode()) { 1569 case ARM::STRD: 1570 case ARM::STRD_PRE: 1571 case ARM::STRD_POST: 1572 case ARM::LDRD: 1573 case ARM::LDRD_PRE: 1574 case ARM::LDRD_POST: 1575 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1576 break; 1577 default: 1578 break; 1579 } 1580 switch (Inst.getOpcode()) { 1581 case ARM::STRD: 1582 case ARM::STRD_PRE: 1583 case ARM::STRD_POST: 1584 if (P == 0 && W == 1) 1585 S = MCDisassembler::SoftFail; 1586 1587 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1588 S = MCDisassembler::SoftFail; 1589 if (type && Rm == 15) 1590 S = MCDisassembler::SoftFail; 1591 if (Rt2 == 15) 1592 S = MCDisassembler::SoftFail; 1593 if (!type && fieldFromInstruction(Insn, 8, 4)) 1594 S = MCDisassembler::SoftFail; 1595 break; 1596 case ARM::STRH: 1597 case ARM::STRH_PRE: 1598 case ARM::STRH_POST: 1599 if (Rt == 15) 1600 S = MCDisassembler::SoftFail; 1601 if (writeback && (Rn == 15 || Rn == Rt)) 1602 S = MCDisassembler::SoftFail; 1603 if (!type && Rm == 15) 1604 S = MCDisassembler::SoftFail; 1605 break; 1606 case ARM::LDRD: 1607 case ARM::LDRD_PRE: 1608 case ARM::LDRD_POST: 1609 if (type && Rn == 15){ 1610 if (Rt2 == 15) 1611 S = MCDisassembler::SoftFail; 1612 break; 1613 } 1614 if (P == 0 && W == 1) 1615 S = MCDisassembler::SoftFail; 1616 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1617 S = MCDisassembler::SoftFail; 1618 if (!type && writeback && Rn == 15) 1619 S = MCDisassembler::SoftFail; 1620 if (writeback && (Rn == Rt || Rn == Rt2)) 1621 S = MCDisassembler::SoftFail; 1622 break; 1623 case ARM::LDRH: 1624 case ARM::LDRH_PRE: 1625 case ARM::LDRH_POST: 1626 if (type && Rn == 15){ 1627 if (Rt == 15) 1628 S = MCDisassembler::SoftFail; 1629 break; 1630 } 1631 if (Rt == 15) 1632 S = MCDisassembler::SoftFail; 1633 if (!type && Rm == 15) 1634 S = MCDisassembler::SoftFail; 1635 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1636 S = MCDisassembler::SoftFail; 1637 break; 1638 case ARM::LDRSH: 1639 case ARM::LDRSH_PRE: 1640 case ARM::LDRSH_POST: 1641 case ARM::LDRSB: 1642 case ARM::LDRSB_PRE: 1643 case ARM::LDRSB_POST: 1644 if (type && Rn == 15){ 1645 if (Rt == 15) 1646 S = MCDisassembler::SoftFail; 1647 break; 1648 } 1649 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1650 S = MCDisassembler::SoftFail; 1651 if (!type && (Rt == 15 || Rm == 15)) 1652 S = MCDisassembler::SoftFail; 1653 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1654 S = MCDisassembler::SoftFail; 1655 break; 1656 default: 1657 break; 1658 } 1659 1660 if (writeback) { // Writeback 1661 if (P) 1662 U |= ARMII::IndexModePre << 9; 1663 else 1664 U |= ARMII::IndexModePost << 9; 1665 1666 // On stores, the writeback operand precedes Rt. 1667 switch (Inst.getOpcode()) { 1668 case ARM::STRD: 1669 case ARM::STRD_PRE: 1670 case ARM::STRD_POST: 1671 case ARM::STRH: 1672 case ARM::STRH_PRE: 1673 case ARM::STRH_POST: 1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1675 return MCDisassembler::Fail; 1676 break; 1677 default: 1678 break; 1679 } 1680 } 1681 1682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1683 return MCDisassembler::Fail; 1684 switch (Inst.getOpcode()) { 1685 case ARM::STRD: 1686 case ARM::STRD_PRE: 1687 case ARM::STRD_POST: 1688 case ARM::LDRD: 1689 case ARM::LDRD_PRE: 1690 case ARM::LDRD_POST: 1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1692 return MCDisassembler::Fail; 1693 break; 1694 default: 1695 break; 1696 } 1697 1698 if (writeback) { 1699 // On loads, the writeback operand comes after Rt. 1700 switch (Inst.getOpcode()) { 1701 case ARM::LDRD: 1702 case ARM::LDRD_PRE: 1703 case ARM::LDRD_POST: 1704 case ARM::LDRH: 1705 case ARM::LDRH_PRE: 1706 case ARM::LDRH_POST: 1707 case ARM::LDRSH: 1708 case ARM::LDRSH_PRE: 1709 case ARM::LDRSH_POST: 1710 case ARM::LDRSB: 1711 case ARM::LDRSB_PRE: 1712 case ARM::LDRSB_POST: 1713 case ARM::LDRHTr: 1714 case ARM::LDRSBTr: 1715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1716 return MCDisassembler::Fail; 1717 break; 1718 default: 1719 break; 1720 } 1721 } 1722 1723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1724 return MCDisassembler::Fail; 1725 1726 if (type) { 1727 Inst.addOperand(MCOperand::CreateReg(0)); 1728 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1729 } else { 1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1731 return MCDisassembler::Fail; 1732 Inst.addOperand(MCOperand::CreateImm(U)); 1733 } 1734 1735 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1736 return MCDisassembler::Fail; 1737 1738 return S; 1739 } 1740 1741 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1742 uint64_t Address, const void *Decoder) { 1743 DecodeStatus S = MCDisassembler::Success; 1744 1745 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1746 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1747 1748 switch (mode) { 1749 case 0: 1750 mode = ARM_AM::da; 1751 break; 1752 case 1: 1753 mode = ARM_AM::ia; 1754 break; 1755 case 2: 1756 mode = ARM_AM::db; 1757 break; 1758 case 3: 1759 mode = ARM_AM::ib; 1760 break; 1761 } 1762 1763 Inst.addOperand(MCOperand::CreateImm(mode)); 1764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1765 return MCDisassembler::Fail; 1766 1767 return S; 1768 } 1769 1770 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1771 uint64_t Address, const void *Decoder) { 1772 DecodeStatus S = MCDisassembler::Success; 1773 1774 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1775 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1776 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1777 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1778 1779 if (pred == 0xF) 1780 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1781 1782 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1783 return MCDisassembler::Fail; 1784 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1785 return MCDisassembler::Fail; 1786 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1787 return MCDisassembler::Fail; 1788 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1789 return MCDisassembler::Fail; 1790 return S; 1791 } 1792 1793 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1794 unsigned Insn, 1795 uint64_t Address, const void *Decoder) { 1796 DecodeStatus S = MCDisassembler::Success; 1797 1798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1799 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1800 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1801 1802 if (pred == 0xF) { 1803 // Ambiguous with RFE and SRS 1804 switch (Inst.getOpcode()) { 1805 case ARM::LDMDA: 1806 Inst.setOpcode(ARM::RFEDA); 1807 break; 1808 case ARM::LDMDA_UPD: 1809 Inst.setOpcode(ARM::RFEDA_UPD); 1810 break; 1811 case ARM::LDMDB: 1812 Inst.setOpcode(ARM::RFEDB); 1813 break; 1814 case ARM::LDMDB_UPD: 1815 Inst.setOpcode(ARM::RFEDB_UPD); 1816 break; 1817 case ARM::LDMIA: 1818 Inst.setOpcode(ARM::RFEIA); 1819 break; 1820 case ARM::LDMIA_UPD: 1821 Inst.setOpcode(ARM::RFEIA_UPD); 1822 break; 1823 case ARM::LDMIB: 1824 Inst.setOpcode(ARM::RFEIB); 1825 break; 1826 case ARM::LDMIB_UPD: 1827 Inst.setOpcode(ARM::RFEIB_UPD); 1828 break; 1829 case ARM::STMDA: 1830 Inst.setOpcode(ARM::SRSDA); 1831 break; 1832 case ARM::STMDA_UPD: 1833 Inst.setOpcode(ARM::SRSDA_UPD); 1834 break; 1835 case ARM::STMDB: 1836 Inst.setOpcode(ARM::SRSDB); 1837 break; 1838 case ARM::STMDB_UPD: 1839 Inst.setOpcode(ARM::SRSDB_UPD); 1840 break; 1841 case ARM::STMIA: 1842 Inst.setOpcode(ARM::SRSIA); 1843 break; 1844 case ARM::STMIA_UPD: 1845 Inst.setOpcode(ARM::SRSIA_UPD); 1846 break; 1847 case ARM::STMIB: 1848 Inst.setOpcode(ARM::SRSIB); 1849 break; 1850 case ARM::STMIB_UPD: 1851 Inst.setOpcode(ARM::SRSIB_UPD); 1852 break; 1853 default: 1854 return MCDisassembler::Fail; 1855 } 1856 1857 // For stores (which become SRS's, the only operand is the mode. 1858 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1859 // Check SRS encoding constraints 1860 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1861 fieldFromInstruction(Insn, 20, 1) == 0)) 1862 return MCDisassembler::Fail; 1863 1864 Inst.addOperand( 1865 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1866 return S; 1867 } 1868 1869 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1870 } 1871 1872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1873 return MCDisassembler::Fail; 1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1875 return MCDisassembler::Fail; // Tied 1876 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1877 return MCDisassembler::Fail; 1878 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1879 return MCDisassembler::Fail; 1880 1881 return S; 1882 } 1883 1884 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1885 uint64_t Address, const void *Decoder) { 1886 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1887 unsigned M = fieldFromInstruction(Insn, 17, 1); 1888 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1889 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1890 1891 DecodeStatus S = MCDisassembler::Success; 1892 1893 // This decoder is called from multiple location that do not check 1894 // the full encoding is valid before they do. 1895 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1896 fieldFromInstruction(Insn, 16, 1) != 0 || 1897 fieldFromInstruction(Insn, 20, 8) != 0x10) 1898 return MCDisassembler::Fail; 1899 1900 // imod == '01' --> UNPREDICTABLE 1901 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1902 // return failure here. The '01' imod value is unprintable, so there's 1903 // nothing useful we could do even if we returned UNPREDICTABLE. 1904 1905 if (imod == 1) return MCDisassembler::Fail; 1906 1907 if (imod && M) { 1908 Inst.setOpcode(ARM::CPS3p); 1909 Inst.addOperand(MCOperand::CreateImm(imod)); 1910 Inst.addOperand(MCOperand::CreateImm(iflags)); 1911 Inst.addOperand(MCOperand::CreateImm(mode)); 1912 } else if (imod && !M) { 1913 Inst.setOpcode(ARM::CPS2p); 1914 Inst.addOperand(MCOperand::CreateImm(imod)); 1915 Inst.addOperand(MCOperand::CreateImm(iflags)); 1916 if (mode) S = MCDisassembler::SoftFail; 1917 } else if (!imod && M) { 1918 Inst.setOpcode(ARM::CPS1p); 1919 Inst.addOperand(MCOperand::CreateImm(mode)); 1920 if (iflags) S = MCDisassembler::SoftFail; 1921 } else { 1922 // imod == '00' && M == '0' --> UNPREDICTABLE 1923 Inst.setOpcode(ARM::CPS1p); 1924 Inst.addOperand(MCOperand::CreateImm(mode)); 1925 S = MCDisassembler::SoftFail; 1926 } 1927 1928 return S; 1929 } 1930 1931 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1932 uint64_t Address, const void *Decoder) { 1933 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1934 unsigned M = fieldFromInstruction(Insn, 8, 1); 1935 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1936 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1937 1938 DecodeStatus S = MCDisassembler::Success; 1939 1940 // imod == '01' --> UNPREDICTABLE 1941 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1942 // return failure here. The '01' imod value is unprintable, so there's 1943 // nothing useful we could do even if we returned UNPREDICTABLE. 1944 1945 if (imod == 1) return MCDisassembler::Fail; 1946 1947 if (imod && M) { 1948 Inst.setOpcode(ARM::t2CPS3p); 1949 Inst.addOperand(MCOperand::CreateImm(imod)); 1950 Inst.addOperand(MCOperand::CreateImm(iflags)); 1951 Inst.addOperand(MCOperand::CreateImm(mode)); 1952 } else if (imod && !M) { 1953 Inst.setOpcode(ARM::t2CPS2p); 1954 Inst.addOperand(MCOperand::CreateImm(imod)); 1955 Inst.addOperand(MCOperand::CreateImm(iflags)); 1956 if (mode) S = MCDisassembler::SoftFail; 1957 } else if (!imod && M) { 1958 Inst.setOpcode(ARM::t2CPS1p); 1959 Inst.addOperand(MCOperand::CreateImm(mode)); 1960 if (iflags) S = MCDisassembler::SoftFail; 1961 } else { 1962 // imod == '00' && M == '0' --> this is a HINT instruction 1963 int imm = fieldFromInstruction(Insn, 0, 8); 1964 // HINT are defined only for immediate in [0..4] 1965 if(imm > 4) return MCDisassembler::Fail; 1966 Inst.setOpcode(ARM::t2HINT); 1967 Inst.addOperand(MCOperand::CreateImm(imm)); 1968 } 1969 1970 return S; 1971 } 1972 1973 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 DecodeStatus S = MCDisassembler::Success; 1976 1977 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1978 unsigned imm = 0; 1979 1980 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1981 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1982 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1983 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1984 1985 if (Inst.getOpcode() == ARM::t2MOVTi16) 1986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1987 return MCDisassembler::Fail; 1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 1991 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1992 Inst.addOperand(MCOperand::CreateImm(imm)); 1993 1994 return S; 1995 } 1996 1997 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1998 uint64_t Address, const void *Decoder) { 1999 DecodeStatus S = MCDisassembler::Success; 2000 2001 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2002 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2003 unsigned imm = 0; 2004 2005 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2006 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2007 2008 if (Inst.getOpcode() == ARM::MOVTi16) 2009 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 2012 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2013 return MCDisassembler::Fail; 2014 2015 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2016 Inst.addOperand(MCOperand::CreateImm(imm)); 2017 2018 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2019 return MCDisassembler::Fail; 2020 2021 return S; 2022 } 2023 2024 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2025 uint64_t Address, const void *Decoder) { 2026 DecodeStatus S = MCDisassembler::Success; 2027 2028 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2029 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2030 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2031 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2032 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2033 2034 if (pred == 0xF) 2035 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2036 2037 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2038 return MCDisassembler::Fail; 2039 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2040 return MCDisassembler::Fail; 2041 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2042 return MCDisassembler::Fail; 2043 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2044 return MCDisassembler::Fail; 2045 2046 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2047 return MCDisassembler::Fail; 2048 2049 return S; 2050 } 2051 2052 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2053 uint64_t Address, const void *Decoder) { 2054 DecodeStatus S = MCDisassembler::Success; 2055 2056 unsigned add = fieldFromInstruction(Val, 12, 1); 2057 unsigned imm = fieldFromInstruction(Val, 0, 12); 2058 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2059 2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 2063 if (!add) imm *= -1; 2064 if (imm == 0 && !add) imm = INT32_MIN; 2065 Inst.addOperand(MCOperand::CreateImm(imm)); 2066 if (Rn == 15) 2067 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2068 2069 return S; 2070 } 2071 2072 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2073 uint64_t Address, const void *Decoder) { 2074 DecodeStatus S = MCDisassembler::Success; 2075 2076 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2077 unsigned U = fieldFromInstruction(Val, 8, 1); 2078 unsigned imm = fieldFromInstruction(Val, 0, 8); 2079 2080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2081 return MCDisassembler::Fail; 2082 2083 if (U) 2084 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2085 else 2086 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2087 2088 return S; 2089 } 2090 2091 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2092 uint64_t Address, const void *Decoder) { 2093 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2094 } 2095 2096 static DecodeStatus 2097 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2098 uint64_t Address, const void *Decoder) { 2099 DecodeStatus Status = MCDisassembler::Success; 2100 2101 // Note the J1 and J2 values are from the encoded instruction. So here 2102 // change them to I1 and I2 values via as documented: 2103 // I1 = NOT(J1 EOR S); 2104 // I2 = NOT(J2 EOR S); 2105 // and build the imm32 with one trailing zero as documented: 2106 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2107 unsigned S = fieldFromInstruction(Insn, 26, 1); 2108 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2109 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2110 unsigned I1 = !(J1 ^ S); 2111 unsigned I2 = !(J2 ^ S); 2112 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2113 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2114 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2115 int imm32 = SignExtend32<25>(tmp << 1); 2116 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2117 true, 4, Inst, Decoder)) 2118 Inst.addOperand(MCOperand::CreateImm(imm32)); 2119 2120 return Status; 2121 } 2122 2123 static DecodeStatus 2124 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2125 uint64_t Address, const void *Decoder) { 2126 DecodeStatus S = MCDisassembler::Success; 2127 2128 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2129 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2130 2131 if (pred == 0xF) { 2132 Inst.setOpcode(ARM::BLXi); 2133 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2134 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2135 true, 4, Inst, Decoder)) 2136 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2137 return S; 2138 } 2139 2140 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2141 true, 4, Inst, Decoder)) 2142 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2143 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2144 return MCDisassembler::Fail; 2145 2146 return S; 2147 } 2148 2149 2150 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2151 uint64_t Address, const void *Decoder) { 2152 DecodeStatus S = MCDisassembler::Success; 2153 2154 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2155 unsigned align = fieldFromInstruction(Val, 4, 2); 2156 2157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 if (!align) 2160 Inst.addOperand(MCOperand::CreateImm(0)); 2161 else 2162 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2163 2164 return S; 2165 } 2166 2167 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2168 uint64_t Address, const void *Decoder) { 2169 DecodeStatus S = MCDisassembler::Success; 2170 2171 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2172 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2173 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2174 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2175 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2176 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2177 2178 // First output register 2179 switch (Inst.getOpcode()) { 2180 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2181 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2182 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2183 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2184 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2185 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2186 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2187 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2188 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2189 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2190 return MCDisassembler::Fail; 2191 break; 2192 case ARM::VLD2b16: 2193 case ARM::VLD2b32: 2194 case ARM::VLD2b8: 2195 case ARM::VLD2b16wb_fixed: 2196 case ARM::VLD2b16wb_register: 2197 case ARM::VLD2b32wb_fixed: 2198 case ARM::VLD2b32wb_register: 2199 case ARM::VLD2b8wb_fixed: 2200 case ARM::VLD2b8wb_register: 2201 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2202 return MCDisassembler::Fail; 2203 break; 2204 default: 2205 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2206 return MCDisassembler::Fail; 2207 } 2208 2209 // Second output register 2210 switch (Inst.getOpcode()) { 2211 case ARM::VLD3d8: 2212 case ARM::VLD3d16: 2213 case ARM::VLD3d32: 2214 case ARM::VLD3d8_UPD: 2215 case ARM::VLD3d16_UPD: 2216 case ARM::VLD3d32_UPD: 2217 case ARM::VLD4d8: 2218 case ARM::VLD4d16: 2219 case ARM::VLD4d32: 2220 case ARM::VLD4d8_UPD: 2221 case ARM::VLD4d16_UPD: 2222 case ARM::VLD4d32_UPD: 2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2224 return MCDisassembler::Fail; 2225 break; 2226 case ARM::VLD3q8: 2227 case ARM::VLD3q16: 2228 case ARM::VLD3q32: 2229 case ARM::VLD3q8_UPD: 2230 case ARM::VLD3q16_UPD: 2231 case ARM::VLD3q32_UPD: 2232 case ARM::VLD4q8: 2233 case ARM::VLD4q16: 2234 case ARM::VLD4q32: 2235 case ARM::VLD4q8_UPD: 2236 case ARM::VLD4q16_UPD: 2237 case ARM::VLD4q32_UPD: 2238 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2239 return MCDisassembler::Fail; 2240 default: 2241 break; 2242 } 2243 2244 // Third output register 2245 switch(Inst.getOpcode()) { 2246 case ARM::VLD3d8: 2247 case ARM::VLD3d16: 2248 case ARM::VLD3d32: 2249 case ARM::VLD3d8_UPD: 2250 case ARM::VLD3d16_UPD: 2251 case ARM::VLD3d32_UPD: 2252 case ARM::VLD4d8: 2253 case ARM::VLD4d16: 2254 case ARM::VLD4d32: 2255 case ARM::VLD4d8_UPD: 2256 case ARM::VLD4d16_UPD: 2257 case ARM::VLD4d32_UPD: 2258 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2259 return MCDisassembler::Fail; 2260 break; 2261 case ARM::VLD3q8: 2262 case ARM::VLD3q16: 2263 case ARM::VLD3q32: 2264 case ARM::VLD3q8_UPD: 2265 case ARM::VLD3q16_UPD: 2266 case ARM::VLD3q32_UPD: 2267 case ARM::VLD4q8: 2268 case ARM::VLD4q16: 2269 case ARM::VLD4q32: 2270 case ARM::VLD4q8_UPD: 2271 case ARM::VLD4q16_UPD: 2272 case ARM::VLD4q32_UPD: 2273 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2274 return MCDisassembler::Fail; 2275 break; 2276 default: 2277 break; 2278 } 2279 2280 // Fourth output register 2281 switch (Inst.getOpcode()) { 2282 case ARM::VLD4d8: 2283 case ARM::VLD4d16: 2284 case ARM::VLD4d32: 2285 case ARM::VLD4d8_UPD: 2286 case ARM::VLD4d16_UPD: 2287 case ARM::VLD4d32_UPD: 2288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2289 return MCDisassembler::Fail; 2290 break; 2291 case ARM::VLD4q8: 2292 case ARM::VLD4q16: 2293 case ARM::VLD4q32: 2294 case ARM::VLD4q8_UPD: 2295 case ARM::VLD4q16_UPD: 2296 case ARM::VLD4q32_UPD: 2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 break; 2300 default: 2301 break; 2302 } 2303 2304 // Writeback operand 2305 switch (Inst.getOpcode()) { 2306 case ARM::VLD1d8wb_fixed: 2307 case ARM::VLD1d16wb_fixed: 2308 case ARM::VLD1d32wb_fixed: 2309 case ARM::VLD1d64wb_fixed: 2310 case ARM::VLD1d8wb_register: 2311 case ARM::VLD1d16wb_register: 2312 case ARM::VLD1d32wb_register: 2313 case ARM::VLD1d64wb_register: 2314 case ARM::VLD1q8wb_fixed: 2315 case ARM::VLD1q16wb_fixed: 2316 case ARM::VLD1q32wb_fixed: 2317 case ARM::VLD1q64wb_fixed: 2318 case ARM::VLD1q8wb_register: 2319 case ARM::VLD1q16wb_register: 2320 case ARM::VLD1q32wb_register: 2321 case ARM::VLD1q64wb_register: 2322 case ARM::VLD1d8Twb_fixed: 2323 case ARM::VLD1d8Twb_register: 2324 case ARM::VLD1d16Twb_fixed: 2325 case ARM::VLD1d16Twb_register: 2326 case ARM::VLD1d32Twb_fixed: 2327 case ARM::VLD1d32Twb_register: 2328 case ARM::VLD1d64Twb_fixed: 2329 case ARM::VLD1d64Twb_register: 2330 case ARM::VLD1d8Qwb_fixed: 2331 case ARM::VLD1d8Qwb_register: 2332 case ARM::VLD1d16Qwb_fixed: 2333 case ARM::VLD1d16Qwb_register: 2334 case ARM::VLD1d32Qwb_fixed: 2335 case ARM::VLD1d32Qwb_register: 2336 case ARM::VLD1d64Qwb_fixed: 2337 case ARM::VLD1d64Qwb_register: 2338 case ARM::VLD2d8wb_fixed: 2339 case ARM::VLD2d16wb_fixed: 2340 case ARM::VLD2d32wb_fixed: 2341 case ARM::VLD2q8wb_fixed: 2342 case ARM::VLD2q16wb_fixed: 2343 case ARM::VLD2q32wb_fixed: 2344 case ARM::VLD2d8wb_register: 2345 case ARM::VLD2d16wb_register: 2346 case ARM::VLD2d32wb_register: 2347 case ARM::VLD2q8wb_register: 2348 case ARM::VLD2q16wb_register: 2349 case ARM::VLD2q32wb_register: 2350 case ARM::VLD2b8wb_fixed: 2351 case ARM::VLD2b16wb_fixed: 2352 case ARM::VLD2b32wb_fixed: 2353 case ARM::VLD2b8wb_register: 2354 case ARM::VLD2b16wb_register: 2355 case ARM::VLD2b32wb_register: 2356 Inst.addOperand(MCOperand::CreateImm(0)); 2357 break; 2358 case ARM::VLD3d8_UPD: 2359 case ARM::VLD3d16_UPD: 2360 case ARM::VLD3d32_UPD: 2361 case ARM::VLD3q8_UPD: 2362 case ARM::VLD3q16_UPD: 2363 case ARM::VLD3q32_UPD: 2364 case ARM::VLD4d8_UPD: 2365 case ARM::VLD4d16_UPD: 2366 case ARM::VLD4d32_UPD: 2367 case ARM::VLD4q8_UPD: 2368 case ARM::VLD4q16_UPD: 2369 case ARM::VLD4q32_UPD: 2370 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2371 return MCDisassembler::Fail; 2372 break; 2373 default: 2374 break; 2375 } 2376 2377 // AddrMode6 Base (register+alignment) 2378 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 2381 // AddrMode6 Offset (register) 2382 switch (Inst.getOpcode()) { 2383 default: 2384 // The below have been updated to have explicit am6offset split 2385 // between fixed and register offset. For those instructions not 2386 // yet updated, we need to add an additional reg0 operand for the 2387 // fixed variant. 2388 // 2389 // The fixed offset encodes as Rm == 0xd, so we check for that. 2390 if (Rm == 0xd) { 2391 Inst.addOperand(MCOperand::CreateReg(0)); 2392 break; 2393 } 2394 // Fall through to handle the register offset variant. 2395 case ARM::VLD1d8wb_fixed: 2396 case ARM::VLD1d16wb_fixed: 2397 case ARM::VLD1d32wb_fixed: 2398 case ARM::VLD1d64wb_fixed: 2399 case ARM::VLD1d8Twb_fixed: 2400 case ARM::VLD1d16Twb_fixed: 2401 case ARM::VLD1d32Twb_fixed: 2402 case ARM::VLD1d64Twb_fixed: 2403 case ARM::VLD1d8Qwb_fixed: 2404 case ARM::VLD1d16Qwb_fixed: 2405 case ARM::VLD1d32Qwb_fixed: 2406 case ARM::VLD1d64Qwb_fixed: 2407 case ARM::VLD1d8wb_register: 2408 case ARM::VLD1d16wb_register: 2409 case ARM::VLD1d32wb_register: 2410 case ARM::VLD1d64wb_register: 2411 case ARM::VLD1q8wb_fixed: 2412 case ARM::VLD1q16wb_fixed: 2413 case ARM::VLD1q32wb_fixed: 2414 case ARM::VLD1q64wb_fixed: 2415 case ARM::VLD1q8wb_register: 2416 case ARM::VLD1q16wb_register: 2417 case ARM::VLD1q32wb_register: 2418 case ARM::VLD1q64wb_register: 2419 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2420 // variant encodes Rm == 0xf. Anything else is a register offset post- 2421 // increment and we need to add the register operand to the instruction. 2422 if (Rm != 0xD && Rm != 0xF && 2423 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2424 return MCDisassembler::Fail; 2425 break; 2426 case ARM::VLD2d8wb_fixed: 2427 case ARM::VLD2d16wb_fixed: 2428 case ARM::VLD2d32wb_fixed: 2429 case ARM::VLD2b8wb_fixed: 2430 case ARM::VLD2b16wb_fixed: 2431 case ARM::VLD2b32wb_fixed: 2432 case ARM::VLD2q8wb_fixed: 2433 case ARM::VLD2q16wb_fixed: 2434 case ARM::VLD2q32wb_fixed: 2435 break; 2436 } 2437 2438 return S; 2439 } 2440 2441 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2442 uint64_t Address, const void *Decoder) { 2443 unsigned type = fieldFromInstruction(Insn, 8, 4); 2444 unsigned align = fieldFromInstruction(Insn, 4, 2); 2445 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2446 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2447 if (type == 10 && align == 3) return MCDisassembler::Fail; 2448 2449 unsigned load = fieldFromInstruction(Insn, 21, 1); 2450 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2451 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2452 } 2453 2454 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2455 uint64_t Address, const void *Decoder) { 2456 unsigned size = fieldFromInstruction(Insn, 6, 2); 2457 if (size == 3) return MCDisassembler::Fail; 2458 2459 unsigned type = fieldFromInstruction(Insn, 8, 4); 2460 unsigned align = fieldFromInstruction(Insn, 4, 2); 2461 if (type == 8 && align == 3) return MCDisassembler::Fail; 2462 if (type == 9 && align == 3) return MCDisassembler::Fail; 2463 2464 unsigned load = fieldFromInstruction(Insn, 21, 1); 2465 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2466 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2467 } 2468 2469 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2470 uint64_t Address, const void *Decoder) { 2471 unsigned size = fieldFromInstruction(Insn, 6, 2); 2472 if (size == 3) return MCDisassembler::Fail; 2473 2474 unsigned align = fieldFromInstruction(Insn, 4, 2); 2475 if (align & 2) return MCDisassembler::Fail; 2476 2477 unsigned load = fieldFromInstruction(Insn, 21, 1); 2478 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2479 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2480 } 2481 2482 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2483 uint64_t Address, const void *Decoder) { 2484 unsigned size = fieldFromInstruction(Insn, 6, 2); 2485 if (size == 3) return MCDisassembler::Fail; 2486 2487 unsigned load = fieldFromInstruction(Insn, 21, 1); 2488 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2489 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2490 } 2491 2492 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2493 uint64_t Address, const void *Decoder) { 2494 DecodeStatus S = MCDisassembler::Success; 2495 2496 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2497 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2498 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2499 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2500 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2501 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2502 2503 // Writeback Operand 2504 switch (Inst.getOpcode()) { 2505 case ARM::VST1d8wb_fixed: 2506 case ARM::VST1d16wb_fixed: 2507 case ARM::VST1d32wb_fixed: 2508 case ARM::VST1d64wb_fixed: 2509 case ARM::VST1d8wb_register: 2510 case ARM::VST1d16wb_register: 2511 case ARM::VST1d32wb_register: 2512 case ARM::VST1d64wb_register: 2513 case ARM::VST1q8wb_fixed: 2514 case ARM::VST1q16wb_fixed: 2515 case ARM::VST1q32wb_fixed: 2516 case ARM::VST1q64wb_fixed: 2517 case ARM::VST1q8wb_register: 2518 case ARM::VST1q16wb_register: 2519 case ARM::VST1q32wb_register: 2520 case ARM::VST1q64wb_register: 2521 case ARM::VST1d8Twb_fixed: 2522 case ARM::VST1d16Twb_fixed: 2523 case ARM::VST1d32Twb_fixed: 2524 case ARM::VST1d64Twb_fixed: 2525 case ARM::VST1d8Twb_register: 2526 case ARM::VST1d16Twb_register: 2527 case ARM::VST1d32Twb_register: 2528 case ARM::VST1d64Twb_register: 2529 case ARM::VST1d8Qwb_fixed: 2530 case ARM::VST1d16Qwb_fixed: 2531 case ARM::VST1d32Qwb_fixed: 2532 case ARM::VST1d64Qwb_fixed: 2533 case ARM::VST1d8Qwb_register: 2534 case ARM::VST1d16Qwb_register: 2535 case ARM::VST1d32Qwb_register: 2536 case ARM::VST1d64Qwb_register: 2537 case ARM::VST2d8wb_fixed: 2538 case ARM::VST2d16wb_fixed: 2539 case ARM::VST2d32wb_fixed: 2540 case ARM::VST2d8wb_register: 2541 case ARM::VST2d16wb_register: 2542 case ARM::VST2d32wb_register: 2543 case ARM::VST2q8wb_fixed: 2544 case ARM::VST2q16wb_fixed: 2545 case ARM::VST2q32wb_fixed: 2546 case ARM::VST2q8wb_register: 2547 case ARM::VST2q16wb_register: 2548 case ARM::VST2q32wb_register: 2549 case ARM::VST2b8wb_fixed: 2550 case ARM::VST2b16wb_fixed: 2551 case ARM::VST2b32wb_fixed: 2552 case ARM::VST2b8wb_register: 2553 case ARM::VST2b16wb_register: 2554 case ARM::VST2b32wb_register: 2555 if (Rm == 0xF) 2556 return MCDisassembler::Fail; 2557 Inst.addOperand(MCOperand::CreateImm(0)); 2558 break; 2559 case ARM::VST3d8_UPD: 2560 case ARM::VST3d16_UPD: 2561 case ARM::VST3d32_UPD: 2562 case ARM::VST3q8_UPD: 2563 case ARM::VST3q16_UPD: 2564 case ARM::VST3q32_UPD: 2565 case ARM::VST4d8_UPD: 2566 case ARM::VST4d16_UPD: 2567 case ARM::VST4d32_UPD: 2568 case ARM::VST4q8_UPD: 2569 case ARM::VST4q16_UPD: 2570 case ARM::VST4q32_UPD: 2571 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2572 return MCDisassembler::Fail; 2573 break; 2574 default: 2575 break; 2576 } 2577 2578 // AddrMode6 Base (register+alignment) 2579 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2580 return MCDisassembler::Fail; 2581 2582 // AddrMode6 Offset (register) 2583 switch (Inst.getOpcode()) { 2584 default: 2585 if (Rm == 0xD) 2586 Inst.addOperand(MCOperand::CreateReg(0)); 2587 else if (Rm != 0xF) { 2588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2589 return MCDisassembler::Fail; 2590 } 2591 break; 2592 case ARM::VST1d8wb_fixed: 2593 case ARM::VST1d16wb_fixed: 2594 case ARM::VST1d32wb_fixed: 2595 case ARM::VST1d64wb_fixed: 2596 case ARM::VST1q8wb_fixed: 2597 case ARM::VST1q16wb_fixed: 2598 case ARM::VST1q32wb_fixed: 2599 case ARM::VST1q64wb_fixed: 2600 case ARM::VST1d8Twb_fixed: 2601 case ARM::VST1d16Twb_fixed: 2602 case ARM::VST1d32Twb_fixed: 2603 case ARM::VST1d64Twb_fixed: 2604 case ARM::VST1d8Qwb_fixed: 2605 case ARM::VST1d16Qwb_fixed: 2606 case ARM::VST1d32Qwb_fixed: 2607 case ARM::VST1d64Qwb_fixed: 2608 case ARM::VST2d8wb_fixed: 2609 case ARM::VST2d16wb_fixed: 2610 case ARM::VST2d32wb_fixed: 2611 case ARM::VST2q8wb_fixed: 2612 case ARM::VST2q16wb_fixed: 2613 case ARM::VST2q32wb_fixed: 2614 case ARM::VST2b8wb_fixed: 2615 case ARM::VST2b16wb_fixed: 2616 case ARM::VST2b32wb_fixed: 2617 break; 2618 } 2619 2620 2621 // First input register 2622 switch (Inst.getOpcode()) { 2623 case ARM::VST1q16: 2624 case ARM::VST1q32: 2625 case ARM::VST1q64: 2626 case ARM::VST1q8: 2627 case ARM::VST1q16wb_fixed: 2628 case ARM::VST1q16wb_register: 2629 case ARM::VST1q32wb_fixed: 2630 case ARM::VST1q32wb_register: 2631 case ARM::VST1q64wb_fixed: 2632 case ARM::VST1q64wb_register: 2633 case ARM::VST1q8wb_fixed: 2634 case ARM::VST1q8wb_register: 2635 case ARM::VST2d16: 2636 case ARM::VST2d32: 2637 case ARM::VST2d8: 2638 case ARM::VST2d16wb_fixed: 2639 case ARM::VST2d16wb_register: 2640 case ARM::VST2d32wb_fixed: 2641 case ARM::VST2d32wb_register: 2642 case ARM::VST2d8wb_fixed: 2643 case ARM::VST2d8wb_register: 2644 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2645 return MCDisassembler::Fail; 2646 break; 2647 case ARM::VST2b16: 2648 case ARM::VST2b32: 2649 case ARM::VST2b8: 2650 case ARM::VST2b16wb_fixed: 2651 case ARM::VST2b16wb_register: 2652 case ARM::VST2b32wb_fixed: 2653 case ARM::VST2b32wb_register: 2654 case ARM::VST2b8wb_fixed: 2655 case ARM::VST2b8wb_register: 2656 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2657 return MCDisassembler::Fail; 2658 break; 2659 default: 2660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2661 return MCDisassembler::Fail; 2662 } 2663 2664 // Second input register 2665 switch (Inst.getOpcode()) { 2666 case ARM::VST3d8: 2667 case ARM::VST3d16: 2668 case ARM::VST3d32: 2669 case ARM::VST3d8_UPD: 2670 case ARM::VST3d16_UPD: 2671 case ARM::VST3d32_UPD: 2672 case ARM::VST4d8: 2673 case ARM::VST4d16: 2674 case ARM::VST4d32: 2675 case ARM::VST4d8_UPD: 2676 case ARM::VST4d16_UPD: 2677 case ARM::VST4d32_UPD: 2678 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 break; 2681 case ARM::VST3q8: 2682 case ARM::VST3q16: 2683 case ARM::VST3q32: 2684 case ARM::VST3q8_UPD: 2685 case ARM::VST3q16_UPD: 2686 case ARM::VST3q32_UPD: 2687 case ARM::VST4q8: 2688 case ARM::VST4q16: 2689 case ARM::VST4q32: 2690 case ARM::VST4q8_UPD: 2691 case ARM::VST4q16_UPD: 2692 case ARM::VST4q32_UPD: 2693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2694 return MCDisassembler::Fail; 2695 break; 2696 default: 2697 break; 2698 } 2699 2700 // Third input register 2701 switch (Inst.getOpcode()) { 2702 case ARM::VST3d8: 2703 case ARM::VST3d16: 2704 case ARM::VST3d32: 2705 case ARM::VST3d8_UPD: 2706 case ARM::VST3d16_UPD: 2707 case ARM::VST3d32_UPD: 2708 case ARM::VST4d8: 2709 case ARM::VST4d16: 2710 case ARM::VST4d32: 2711 case ARM::VST4d8_UPD: 2712 case ARM::VST4d16_UPD: 2713 case ARM::VST4d32_UPD: 2714 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2715 return MCDisassembler::Fail; 2716 break; 2717 case ARM::VST3q8: 2718 case ARM::VST3q16: 2719 case ARM::VST3q32: 2720 case ARM::VST3q8_UPD: 2721 case ARM::VST3q16_UPD: 2722 case ARM::VST3q32_UPD: 2723 case ARM::VST4q8: 2724 case ARM::VST4q16: 2725 case ARM::VST4q32: 2726 case ARM::VST4q8_UPD: 2727 case ARM::VST4q16_UPD: 2728 case ARM::VST4q32_UPD: 2729 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2730 return MCDisassembler::Fail; 2731 break; 2732 default: 2733 break; 2734 } 2735 2736 // Fourth input register 2737 switch (Inst.getOpcode()) { 2738 case ARM::VST4d8: 2739 case ARM::VST4d16: 2740 case ARM::VST4d32: 2741 case ARM::VST4d8_UPD: 2742 case ARM::VST4d16_UPD: 2743 case ARM::VST4d32_UPD: 2744 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 break; 2747 case ARM::VST4q8: 2748 case ARM::VST4q16: 2749 case ARM::VST4q32: 2750 case ARM::VST4q8_UPD: 2751 case ARM::VST4q16_UPD: 2752 case ARM::VST4q32_UPD: 2753 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 break; 2756 default: 2757 break; 2758 } 2759 2760 return S; 2761 } 2762 2763 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2764 uint64_t Address, const void *Decoder) { 2765 DecodeStatus S = MCDisassembler::Success; 2766 2767 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2768 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2769 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2770 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2771 unsigned align = fieldFromInstruction(Insn, 4, 1); 2772 unsigned size = fieldFromInstruction(Insn, 6, 2); 2773 2774 if (size == 0 && align == 1) 2775 return MCDisassembler::Fail; 2776 align *= (1 << size); 2777 2778 switch (Inst.getOpcode()) { 2779 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2780 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2781 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2782 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2783 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 break; 2786 default: 2787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 break; 2790 } 2791 if (Rm != 0xF) { 2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 } 2795 2796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2797 return MCDisassembler::Fail; 2798 Inst.addOperand(MCOperand::CreateImm(align)); 2799 2800 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2801 // variant encodes Rm == 0xf. Anything else is a register offset post- 2802 // increment and we need to add the register operand to the instruction. 2803 if (Rm != 0xD && Rm != 0xF && 2804 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 2807 return S; 2808 } 2809 2810 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2811 uint64_t Address, const void *Decoder) { 2812 DecodeStatus S = MCDisassembler::Success; 2813 2814 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2815 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2817 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2818 unsigned align = fieldFromInstruction(Insn, 4, 1); 2819 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2820 align *= 2*size; 2821 2822 switch (Inst.getOpcode()) { 2823 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2824 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2825 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2826 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2827 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2828 return MCDisassembler::Fail; 2829 break; 2830 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2831 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2832 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2833 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2834 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 break; 2837 default: 2838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2839 return MCDisassembler::Fail; 2840 break; 2841 } 2842 2843 if (Rm != 0xF) 2844 Inst.addOperand(MCOperand::CreateImm(0)); 2845 2846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 Inst.addOperand(MCOperand::CreateImm(align)); 2849 2850 if (Rm != 0xD && Rm != 0xF) { 2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2852 return MCDisassembler::Fail; 2853 } 2854 2855 return S; 2856 } 2857 2858 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2859 uint64_t Address, const void *Decoder) { 2860 DecodeStatus S = MCDisassembler::Success; 2861 2862 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2863 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2864 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2865 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2866 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2867 2868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2871 return MCDisassembler::Fail; 2872 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 if (Rm != 0xF) { 2875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2876 return MCDisassembler::Fail; 2877 } 2878 2879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2880 return MCDisassembler::Fail; 2881 Inst.addOperand(MCOperand::CreateImm(0)); 2882 2883 if (Rm == 0xD) 2884 Inst.addOperand(MCOperand::CreateReg(0)); 2885 else if (Rm != 0xF) { 2886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2887 return MCDisassembler::Fail; 2888 } 2889 2890 return S; 2891 } 2892 2893 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2894 uint64_t Address, const void *Decoder) { 2895 DecodeStatus S = MCDisassembler::Success; 2896 2897 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2898 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2899 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2900 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2901 unsigned size = fieldFromInstruction(Insn, 6, 2); 2902 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2903 unsigned align = fieldFromInstruction(Insn, 4, 1); 2904 2905 if (size == 0x3) { 2906 if (align == 0) 2907 return MCDisassembler::Fail; 2908 size = 4; 2909 align = 16; 2910 } else { 2911 if (size == 2) { 2912 size = 1 << size; 2913 align *= 8; 2914 } else { 2915 size = 1 << size; 2916 align *= 4*size; 2917 } 2918 } 2919 2920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2921 return MCDisassembler::Fail; 2922 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2923 return MCDisassembler::Fail; 2924 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 if (Rm != 0xF) { 2929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 } 2932 2933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2934 return MCDisassembler::Fail; 2935 Inst.addOperand(MCOperand::CreateImm(align)); 2936 2937 if (Rm == 0xD) 2938 Inst.addOperand(MCOperand::CreateReg(0)); 2939 else if (Rm != 0xF) { 2940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2941 return MCDisassembler::Fail; 2942 } 2943 2944 return S; 2945 } 2946 2947 static DecodeStatus 2948 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2949 uint64_t Address, const void *Decoder) { 2950 DecodeStatus S = MCDisassembler::Success; 2951 2952 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2953 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2954 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2955 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2956 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2957 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2958 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2959 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2960 2961 if (Q) { 2962 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2963 return MCDisassembler::Fail; 2964 } else { 2965 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2966 return MCDisassembler::Fail; 2967 } 2968 2969 Inst.addOperand(MCOperand::CreateImm(imm)); 2970 2971 switch (Inst.getOpcode()) { 2972 case ARM::VORRiv4i16: 2973 case ARM::VORRiv2i32: 2974 case ARM::VBICiv4i16: 2975 case ARM::VBICiv2i32: 2976 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 break; 2979 case ARM::VORRiv8i16: 2980 case ARM::VORRiv4i32: 2981 case ARM::VBICiv8i16: 2982 case ARM::VBICiv4i32: 2983 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 break; 2986 default: 2987 break; 2988 } 2989 2990 return S; 2991 } 2992 2993 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2994 uint64_t Address, const void *Decoder) { 2995 DecodeStatus S = MCDisassembler::Success; 2996 2997 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2998 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2999 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3000 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3001 unsigned size = fieldFromInstruction(Insn, 18, 2); 3002 3003 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3008 3009 return S; 3010 } 3011 3012 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3013 uint64_t Address, const void *Decoder) { 3014 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3015 return MCDisassembler::Success; 3016 } 3017 3018 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3019 uint64_t Address, const void *Decoder) { 3020 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3021 return MCDisassembler::Success; 3022 } 3023 3024 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3025 uint64_t Address, const void *Decoder) { 3026 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3027 return MCDisassembler::Success; 3028 } 3029 3030 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3031 uint64_t Address, const void *Decoder) { 3032 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3033 return MCDisassembler::Success; 3034 } 3035 3036 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3037 uint64_t Address, const void *Decoder) { 3038 DecodeStatus S = MCDisassembler::Success; 3039 3040 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3041 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3043 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3044 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3045 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3046 unsigned op = fieldFromInstruction(Insn, 6, 1); 3047 3048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 if (op) { 3051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3052 return MCDisassembler::Fail; // Writeback 3053 } 3054 3055 switch (Inst.getOpcode()) { 3056 case ARM::VTBL2: 3057 case ARM::VTBX2: 3058 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 break; 3061 default: 3062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 } 3065 3066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3067 return MCDisassembler::Fail; 3068 3069 return S; 3070 } 3071 3072 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3073 uint64_t Address, const void *Decoder) { 3074 DecodeStatus S = MCDisassembler::Success; 3075 3076 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3077 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3078 3079 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 3082 switch(Inst.getOpcode()) { 3083 default: 3084 return MCDisassembler::Fail; 3085 case ARM::tADR: 3086 break; // tADR does not explicitly represent the PC as an operand. 3087 case ARM::tADDrSPi: 3088 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3089 break; 3090 } 3091 3092 Inst.addOperand(MCOperand::CreateImm(imm)); 3093 return S; 3094 } 3095 3096 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3097 uint64_t Address, const void *Decoder) { 3098 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3099 true, 2, Inst, Decoder)) 3100 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3101 return MCDisassembler::Success; 3102 } 3103 3104 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3105 uint64_t Address, const void *Decoder) { 3106 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3107 true, 4, Inst, Decoder)) 3108 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3109 return MCDisassembler::Success; 3110 } 3111 3112 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3113 uint64_t Address, const void *Decoder) { 3114 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3115 true, 2, Inst, Decoder)) 3116 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3117 return MCDisassembler::Success; 3118 } 3119 3120 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3121 uint64_t Address, const void *Decoder) { 3122 DecodeStatus S = MCDisassembler::Success; 3123 3124 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3125 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3126 3127 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 3132 return S; 3133 } 3134 3135 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3136 uint64_t Address, const void *Decoder) { 3137 DecodeStatus S = MCDisassembler::Success; 3138 3139 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3140 unsigned imm = fieldFromInstruction(Val, 3, 5); 3141 3142 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3143 return MCDisassembler::Fail; 3144 Inst.addOperand(MCOperand::CreateImm(imm)); 3145 3146 return S; 3147 } 3148 3149 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3150 uint64_t Address, const void *Decoder) { 3151 unsigned imm = Val << 2; 3152 3153 Inst.addOperand(MCOperand::CreateImm(imm)); 3154 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3155 3156 return MCDisassembler::Success; 3157 } 3158 3159 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3160 uint64_t Address, const void *Decoder) { 3161 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3162 Inst.addOperand(MCOperand::CreateImm(Val)); 3163 3164 return MCDisassembler::Success; 3165 } 3166 3167 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3168 uint64_t Address, const void *Decoder) { 3169 DecodeStatus S = MCDisassembler::Success; 3170 3171 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3172 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3173 unsigned imm = fieldFromInstruction(Val, 0, 2); 3174 3175 // Thumb stores cannot use PC as dest register. 3176 switch (Inst.getOpcode()) { 3177 case ARM::t2STRHs: 3178 case ARM::t2STRBs: 3179 case ARM::t2STRs: 3180 if (Rn == 15) 3181 return MCDisassembler::Fail; 3182 default: 3183 break; 3184 } 3185 3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 Inst.addOperand(MCOperand::CreateImm(imm)); 3191 3192 return S; 3193 } 3194 3195 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3196 uint64_t Address, const void *Decoder) { 3197 DecodeStatus S = MCDisassembler::Success; 3198 3199 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3201 3202 if (Rn == 15) { 3203 switch (Inst.getOpcode()) { 3204 case ARM::t2LDRBs: 3205 Inst.setOpcode(ARM::t2LDRBpci); 3206 break; 3207 case ARM::t2LDRHs: 3208 Inst.setOpcode(ARM::t2LDRHpci); 3209 break; 3210 case ARM::t2LDRSHs: 3211 Inst.setOpcode(ARM::t2LDRSHpci); 3212 break; 3213 case ARM::t2LDRSBs: 3214 Inst.setOpcode(ARM::t2LDRSBpci); 3215 break; 3216 case ARM::t2LDRs: 3217 Inst.setOpcode(ARM::t2LDRpci); 3218 break; 3219 case ARM::t2PLDs: 3220 Inst.setOpcode(ARM::t2PLDpci); 3221 break; 3222 case ARM::t2PLIs: 3223 Inst.setOpcode(ARM::t2PLIpci); 3224 break; 3225 default: 3226 return MCDisassembler::Fail; 3227 } 3228 3229 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3230 } 3231 3232 if (Rt == 15) { 3233 switch (Inst.getOpcode()) { 3234 case ARM::t2LDRSHs: 3235 return MCDisassembler::Fail; 3236 case ARM::t2LDRHs: 3237 // FIXME: this instruction is only available with MP extensions, 3238 // this should be checked first but we don't have access to the 3239 // feature bits here. 3240 Inst.setOpcode(ARM::t2PLDWs); 3241 break; 3242 default: 3243 break; 3244 } 3245 } 3246 3247 switch (Inst.getOpcode()) { 3248 case ARM::t2PLDs: 3249 case ARM::t2PLDWs: 3250 case ARM::t2PLIs: 3251 break; 3252 default: 3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3254 return MCDisassembler::Fail; 3255 } 3256 3257 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3258 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3259 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3260 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 3263 return S; 3264 } 3265 3266 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3267 uint64_t Address, const void* Decoder) { 3268 DecodeStatus S = MCDisassembler::Success; 3269 3270 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3271 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3272 unsigned U = fieldFromInstruction(Insn, 9, 1); 3273 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3274 imm |= (U << 8); 3275 imm |= (Rn << 9); 3276 3277 if (Rn == 15) { 3278 switch (Inst.getOpcode()) { 3279 case ARM::t2LDRi8: 3280 Inst.setOpcode(ARM::t2LDRpci); 3281 break; 3282 case ARM::t2LDRBi8: 3283 Inst.setOpcode(ARM::t2LDRBpci); 3284 break; 3285 case ARM::t2LDRSBi8: 3286 Inst.setOpcode(ARM::t2LDRSBpci); 3287 break; 3288 case ARM::t2LDRHi8: 3289 Inst.setOpcode(ARM::t2LDRHpci); 3290 break; 3291 case ARM::t2LDRSHi8: 3292 Inst.setOpcode(ARM::t2LDRSHpci); 3293 break; 3294 case ARM::t2PLDi8: 3295 Inst.setOpcode(ARM::t2PLDpci); 3296 break; 3297 case ARM::t2PLIi8: 3298 Inst.setOpcode(ARM::t2PLIpci); 3299 break; 3300 default: 3301 return MCDisassembler::Fail; 3302 } 3303 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3304 } 3305 3306 if (Rt == 15) { 3307 switch (Inst.getOpcode()) { 3308 case ARM::t2LDRSHi8: 3309 return MCDisassembler::Fail; 3310 default: 3311 break; 3312 } 3313 } 3314 3315 switch (Inst.getOpcode()) { 3316 case ARM::t2PLDi8: 3317 case ARM::t2PLIi8: 3318 break; 3319 default: 3320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3321 return MCDisassembler::Fail; 3322 } 3323 3324 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3325 return MCDisassembler::Fail; 3326 return S; 3327 } 3328 3329 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3330 uint64_t Address, const void* Decoder) { 3331 DecodeStatus S = MCDisassembler::Success; 3332 3333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3334 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3335 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3336 imm |= (Rn << 13); 3337 3338 if (Rn == 15) { 3339 switch (Inst.getOpcode()) { 3340 case ARM::t2LDRi12: 3341 Inst.setOpcode(ARM::t2LDRpci); 3342 break; 3343 case ARM::t2LDRHi12: 3344 Inst.setOpcode(ARM::t2LDRHpci); 3345 break; 3346 case ARM::t2LDRSHi12: 3347 Inst.setOpcode(ARM::t2LDRSHpci); 3348 break; 3349 case ARM::t2LDRBi12: 3350 Inst.setOpcode(ARM::t2LDRBpci); 3351 break; 3352 case ARM::t2LDRSBi12: 3353 Inst.setOpcode(ARM::t2LDRSBpci); 3354 break; 3355 case ARM::t2PLDi12: 3356 Inst.setOpcode(ARM::t2PLDpci); 3357 break; 3358 case ARM::t2PLIi12: 3359 Inst.setOpcode(ARM::t2PLIpci); 3360 break; 3361 default: 3362 return MCDisassembler::Fail; 3363 } 3364 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3365 } 3366 3367 if (Rt == 15) { 3368 switch (Inst.getOpcode()) { 3369 case ARM::t2LDRSHi12: 3370 return MCDisassembler::Fail; 3371 case ARM::t2LDRHi12: 3372 Inst.setOpcode(ARM::t2PLDi12); 3373 break; 3374 default: 3375 break; 3376 } 3377 } 3378 3379 switch (Inst.getOpcode()) { 3380 case ARM::t2PLDi12: 3381 case ARM::t2PLIi12: 3382 break; 3383 default: 3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 } 3387 3388 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3389 return MCDisassembler::Fail; 3390 return S; 3391 } 3392 3393 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3394 uint64_t Address, const void* Decoder) { 3395 DecodeStatus S = MCDisassembler::Success; 3396 3397 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3398 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3399 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3400 imm |= (Rn << 9); 3401 3402 if (Rn == 15) { 3403 switch (Inst.getOpcode()) { 3404 case ARM::t2LDRT: 3405 Inst.setOpcode(ARM::t2LDRpci); 3406 break; 3407 case ARM::t2LDRBT: 3408 Inst.setOpcode(ARM::t2LDRBpci); 3409 break; 3410 case ARM::t2LDRHT: 3411 Inst.setOpcode(ARM::t2LDRHpci); 3412 break; 3413 case ARM::t2LDRSBT: 3414 Inst.setOpcode(ARM::t2LDRSBpci); 3415 break; 3416 case ARM::t2LDRSHT: 3417 Inst.setOpcode(ARM::t2LDRSHpci); 3418 break; 3419 default: 3420 return MCDisassembler::Fail; 3421 } 3422 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3423 } 3424 3425 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3428 return MCDisassembler::Fail; 3429 return S; 3430 } 3431 3432 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3433 uint64_t Address, const void* Decoder) { 3434 DecodeStatus S = MCDisassembler::Success; 3435 3436 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3437 unsigned U = fieldFromInstruction(Insn, 23, 1); 3438 int imm = fieldFromInstruction(Insn, 0, 12); 3439 3440 if (Rt == 15) { 3441 switch (Inst.getOpcode()) { 3442 case ARM::t2LDRBpci: 3443 case ARM::t2LDRHpci: 3444 Inst.setOpcode(ARM::t2PLDpci); 3445 break; 3446 case ARM::t2LDRSBpci: 3447 Inst.setOpcode(ARM::t2PLIpci); 3448 break; 3449 case ARM::t2LDRSHpci: 3450 return MCDisassembler::Fail; 3451 default: 3452 break; 3453 } 3454 } 3455 3456 switch(Inst.getOpcode()) { 3457 case ARM::t2PLDpci: 3458 case ARM::t2PLIpci: 3459 break; 3460 default: 3461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 } 3464 3465 if (!U) { 3466 // Special case for #-0. 3467 if (imm == 0) 3468 imm = INT32_MIN; 3469 else 3470 imm = -imm; 3471 } 3472 Inst.addOperand(MCOperand::CreateImm(imm)); 3473 3474 return S; 3475 } 3476 3477 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3478 uint64_t Address, const void *Decoder) { 3479 if (Val == 0) 3480 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3481 else { 3482 int imm = Val & 0xFF; 3483 3484 if (!(Val & 0x100)) imm *= -1; 3485 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3486 } 3487 3488 return MCDisassembler::Success; 3489 } 3490 3491 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3492 uint64_t Address, const void *Decoder) { 3493 DecodeStatus S = MCDisassembler::Success; 3494 3495 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3496 unsigned imm = fieldFromInstruction(Val, 0, 9); 3497 3498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3499 return MCDisassembler::Fail; 3500 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3501 return MCDisassembler::Fail; 3502 3503 return S; 3504 } 3505 3506 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3507 uint64_t Address, const void *Decoder) { 3508 DecodeStatus S = MCDisassembler::Success; 3509 3510 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3511 unsigned imm = fieldFromInstruction(Val, 0, 8); 3512 3513 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 3516 Inst.addOperand(MCOperand::CreateImm(imm)); 3517 3518 return S; 3519 } 3520 3521 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3522 uint64_t Address, const void *Decoder) { 3523 int imm = Val & 0xFF; 3524 if (Val == 0) 3525 imm = INT32_MIN; 3526 else if (!(Val & 0x100)) 3527 imm *= -1; 3528 Inst.addOperand(MCOperand::CreateImm(imm)); 3529 3530 return MCDisassembler::Success; 3531 } 3532 3533 3534 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3535 uint64_t Address, const void *Decoder) { 3536 DecodeStatus S = MCDisassembler::Success; 3537 3538 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3539 unsigned imm = fieldFromInstruction(Val, 0, 9); 3540 3541 // Thumb stores cannot use PC as dest register. 3542 switch (Inst.getOpcode()) { 3543 case ARM::t2STRT: 3544 case ARM::t2STRBT: 3545 case ARM::t2STRHT: 3546 case ARM::t2STRi8: 3547 case ARM::t2STRHi8: 3548 case ARM::t2STRBi8: 3549 if (Rn == 15) 3550 return MCDisassembler::Fail; 3551 break; 3552 default: 3553 break; 3554 } 3555 3556 // Some instructions always use an additive offset. 3557 switch (Inst.getOpcode()) { 3558 case ARM::t2LDRT: 3559 case ARM::t2LDRBT: 3560 case ARM::t2LDRHT: 3561 case ARM::t2LDRSBT: 3562 case ARM::t2LDRSHT: 3563 case ARM::t2STRT: 3564 case ARM::t2STRBT: 3565 case ARM::t2STRHT: 3566 imm |= 0x100; 3567 break; 3568 default: 3569 break; 3570 } 3571 3572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 3577 return S; 3578 } 3579 3580 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3581 uint64_t Address, const void *Decoder) { 3582 DecodeStatus S = MCDisassembler::Success; 3583 3584 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3586 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3587 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3588 addr |= Rn << 9; 3589 unsigned load = fieldFromInstruction(Insn, 20, 1); 3590 3591 if (Rn == 15) { 3592 switch (Inst.getOpcode()) { 3593 case ARM::t2LDR_PRE: 3594 case ARM::t2LDR_POST: 3595 Inst.setOpcode(ARM::t2LDRpci); 3596 break; 3597 case ARM::t2LDRB_PRE: 3598 case ARM::t2LDRB_POST: 3599 Inst.setOpcode(ARM::t2LDRBpci); 3600 break; 3601 case ARM::t2LDRH_PRE: 3602 case ARM::t2LDRH_POST: 3603 Inst.setOpcode(ARM::t2LDRHpci); 3604 break; 3605 case ARM::t2LDRSB_PRE: 3606 case ARM::t2LDRSB_POST: 3607 if (Rt == 15) 3608 Inst.setOpcode(ARM::t2PLIpci); 3609 else 3610 Inst.setOpcode(ARM::t2LDRSBpci); 3611 break; 3612 case ARM::t2LDRSH_PRE: 3613 case ARM::t2LDRSH_POST: 3614 Inst.setOpcode(ARM::t2LDRSHpci); 3615 break; 3616 default: 3617 return MCDisassembler::Fail; 3618 } 3619 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3620 } 3621 3622 if (!load) { 3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 } 3626 3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3628 return MCDisassembler::Fail; 3629 3630 if (load) { 3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 } 3634 3635 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 3638 return S; 3639 } 3640 3641 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3642 uint64_t Address, const void *Decoder) { 3643 DecodeStatus S = MCDisassembler::Success; 3644 3645 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3646 unsigned imm = fieldFromInstruction(Val, 0, 12); 3647 3648 // Thumb stores cannot use PC as dest register. 3649 switch (Inst.getOpcode()) { 3650 case ARM::t2STRi12: 3651 case ARM::t2STRBi12: 3652 case ARM::t2STRHi12: 3653 if (Rn == 15) 3654 return MCDisassembler::Fail; 3655 default: 3656 break; 3657 } 3658 3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 Inst.addOperand(MCOperand::CreateImm(imm)); 3662 3663 return S; 3664 } 3665 3666 3667 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3668 uint64_t Address, const void *Decoder) { 3669 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3670 3671 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3672 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3673 Inst.addOperand(MCOperand::CreateImm(imm)); 3674 3675 return MCDisassembler::Success; 3676 } 3677 3678 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3679 uint64_t Address, const void *Decoder) { 3680 DecodeStatus S = MCDisassembler::Success; 3681 3682 if (Inst.getOpcode() == ARM::tADDrSP) { 3683 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3684 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3685 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 } else if (Inst.getOpcode() == ARM::tADDspr) { 3692 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3693 3694 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3695 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 } 3699 3700 return S; 3701 } 3702 3703 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3704 uint64_t Address, const void *Decoder) { 3705 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3706 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3707 3708 Inst.addOperand(MCOperand::CreateImm(imod)); 3709 Inst.addOperand(MCOperand::CreateImm(flags)); 3710 3711 return MCDisassembler::Success; 3712 } 3713 3714 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3715 uint64_t Address, const void *Decoder) { 3716 DecodeStatus S = MCDisassembler::Success; 3717 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3718 unsigned add = fieldFromInstruction(Insn, 4, 1); 3719 3720 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3721 return MCDisassembler::Fail; 3722 Inst.addOperand(MCOperand::CreateImm(add)); 3723 3724 return S; 3725 } 3726 3727 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3728 uint64_t Address, const void *Decoder) { 3729 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3730 // Note only one trailing zero not two. Also the J1 and J2 values are from 3731 // the encoded instruction. So here change to I1 and I2 values via: 3732 // I1 = NOT(J1 EOR S); 3733 // I2 = NOT(J2 EOR S); 3734 // and build the imm32 with two trailing zeros as documented: 3735 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3736 unsigned S = (Val >> 23) & 1; 3737 unsigned J1 = (Val >> 22) & 1; 3738 unsigned J2 = (Val >> 21) & 1; 3739 unsigned I1 = !(J1 ^ S); 3740 unsigned I2 = !(J2 ^ S); 3741 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3742 int imm32 = SignExtend32<25>(tmp << 1); 3743 3744 if (!tryAddingSymbolicOperand(Address, 3745 (Address & ~2u) + imm32 + 4, 3746 true, 4, Inst, Decoder)) 3747 Inst.addOperand(MCOperand::CreateImm(imm32)); 3748 return MCDisassembler::Success; 3749 } 3750 3751 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3752 uint64_t Address, const void *Decoder) { 3753 if (Val == 0xA || Val == 0xB) 3754 return MCDisassembler::Fail; 3755 3756 Inst.addOperand(MCOperand::CreateImm(Val)); 3757 return MCDisassembler::Success; 3758 } 3759 3760 static DecodeStatus 3761 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3762 uint64_t Address, const void *Decoder) { 3763 DecodeStatus S = MCDisassembler::Success; 3764 3765 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3766 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3767 3768 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3770 return MCDisassembler::Fail; 3771 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3772 return MCDisassembler::Fail; 3773 return S; 3774 } 3775 3776 static DecodeStatus 3777 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3778 uint64_t Address, const void *Decoder) { 3779 DecodeStatus S = MCDisassembler::Success; 3780 3781 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3782 if (pred == 0xE || pred == 0xF) { 3783 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3784 switch (opc) { 3785 default: 3786 return MCDisassembler::Fail; 3787 case 0xf3bf8f4: 3788 Inst.setOpcode(ARM::t2DSB); 3789 break; 3790 case 0xf3bf8f5: 3791 Inst.setOpcode(ARM::t2DMB); 3792 break; 3793 case 0xf3bf8f6: 3794 Inst.setOpcode(ARM::t2ISB); 3795 break; 3796 } 3797 3798 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3799 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3800 } 3801 3802 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3803 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3804 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3805 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3806 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3807 3808 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 3813 return S; 3814 } 3815 3816 // Decode a shifted immediate operand. These basically consist 3817 // of an 8-bit value, and a 4-bit directive that specifies either 3818 // a splat operation or a rotation. 3819 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3820 uint64_t Address, const void *Decoder) { 3821 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3822 if (ctrl == 0) { 3823 unsigned byte = fieldFromInstruction(Val, 8, 2); 3824 unsigned imm = fieldFromInstruction(Val, 0, 8); 3825 switch (byte) { 3826 case 0: 3827 Inst.addOperand(MCOperand::CreateImm(imm)); 3828 break; 3829 case 1: 3830 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3831 break; 3832 case 2: 3833 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3834 break; 3835 case 3: 3836 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3837 (imm << 8) | imm)); 3838 break; 3839 } 3840 } else { 3841 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3842 unsigned rot = fieldFromInstruction(Val, 7, 5); 3843 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3844 Inst.addOperand(MCOperand::CreateImm(imm)); 3845 } 3846 3847 return MCDisassembler::Success; 3848 } 3849 3850 static DecodeStatus 3851 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3852 uint64_t Address, const void *Decoder){ 3853 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3854 true, 2, Inst, Decoder)) 3855 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3856 return MCDisassembler::Success; 3857 } 3858 3859 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3860 uint64_t Address, const void *Decoder){ 3861 // Val is passed in as S:J1:J2:imm10:imm11 3862 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3863 // the encoded instruction. So here change to I1 and I2 values via: 3864 // I1 = NOT(J1 EOR S); 3865 // I2 = NOT(J2 EOR S); 3866 // and build the imm32 with one trailing zero as documented: 3867 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3868 unsigned S = (Val >> 23) & 1; 3869 unsigned J1 = (Val >> 22) & 1; 3870 unsigned J2 = (Val >> 21) & 1; 3871 unsigned I1 = !(J1 ^ S); 3872 unsigned I2 = !(J2 ^ S); 3873 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3874 int imm32 = SignExtend32<25>(tmp << 1); 3875 3876 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3877 true, 4, Inst, Decoder)) 3878 Inst.addOperand(MCOperand::CreateImm(imm32)); 3879 return MCDisassembler::Success; 3880 } 3881 3882 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3883 uint64_t Address, const void *Decoder) { 3884 if (Val & ~0xf) 3885 return MCDisassembler::Fail; 3886 3887 Inst.addOperand(MCOperand::CreateImm(Val)); 3888 return MCDisassembler::Success; 3889 } 3890 3891 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3892 uint64_t Address, const void *Decoder) { 3893 if (Val & ~0xf) 3894 return MCDisassembler::Fail; 3895 3896 Inst.addOperand(MCOperand::CreateImm(Val)); 3897 return MCDisassembler::Success; 3898 } 3899 3900 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3901 uint64_t Address, const void *Decoder) { 3902 if (!Val) return MCDisassembler::Fail; 3903 Inst.addOperand(MCOperand::CreateImm(Val)); 3904 return MCDisassembler::Success; 3905 } 3906 3907 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3908 uint64_t Address, const void *Decoder) { 3909 DecodeStatus S = MCDisassembler::Success; 3910 3911 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3912 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3913 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3914 3915 if (Rn == 0xF) 3916 S = MCDisassembler::SoftFail; 3917 3918 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3919 return MCDisassembler::Fail; 3920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3921 return MCDisassembler::Fail; 3922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3923 return MCDisassembler::Fail; 3924 3925 return S; 3926 } 3927 3928 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3929 uint64_t Address, const void *Decoder){ 3930 DecodeStatus S = MCDisassembler::Success; 3931 3932 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3933 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3935 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3936 3937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3938 return MCDisassembler::Fail; 3939 3940 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 3941 S = MCDisassembler::SoftFail; 3942 3943 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3946 return MCDisassembler::Fail; 3947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3948 return MCDisassembler::Fail; 3949 3950 return S; 3951 } 3952 3953 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3954 uint64_t Address, const void *Decoder) { 3955 DecodeStatus S = MCDisassembler::Success; 3956 3957 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3958 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3959 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3960 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3961 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3962 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3963 3964 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3965 3966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3967 return MCDisassembler::Fail; 3968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3969 return MCDisassembler::Fail; 3970 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3971 return MCDisassembler::Fail; 3972 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3973 return MCDisassembler::Fail; 3974 3975 return S; 3976 } 3977 3978 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3979 uint64_t Address, const void *Decoder) { 3980 DecodeStatus S = MCDisassembler::Success; 3981 3982 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3983 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3984 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3985 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3986 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3987 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3988 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3989 3990 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3991 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3992 3993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3998 return MCDisassembler::Fail; 3999 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 4002 return S; 4003 } 4004 4005 4006 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4007 uint64_t Address, const void *Decoder) { 4008 DecodeStatus S = MCDisassembler::Success; 4009 4010 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4011 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4012 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4013 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4014 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4015 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4016 4017 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4018 4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4024 return MCDisassembler::Fail; 4025 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 4028 return S; 4029 } 4030 4031 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4032 uint64_t Address, const void *Decoder) { 4033 DecodeStatus S = MCDisassembler::Success; 4034 4035 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4036 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4037 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4038 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4039 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4040 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4041 4042 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4043 4044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4045 return MCDisassembler::Fail; 4046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4047 return MCDisassembler::Fail; 4048 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4049 return MCDisassembler::Fail; 4050 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 4053 return S; 4054 } 4055 4056 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4057 uint64_t Address, const void *Decoder) { 4058 DecodeStatus S = MCDisassembler::Success; 4059 4060 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4061 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4062 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4063 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4064 unsigned size = fieldFromInstruction(Insn, 10, 2); 4065 4066 unsigned align = 0; 4067 unsigned index = 0; 4068 switch (size) { 4069 default: 4070 return MCDisassembler::Fail; 4071 case 0: 4072 if (fieldFromInstruction(Insn, 4, 1)) 4073 return MCDisassembler::Fail; // UNDEFINED 4074 index = fieldFromInstruction(Insn, 5, 3); 4075 break; 4076 case 1: 4077 if (fieldFromInstruction(Insn, 5, 1)) 4078 return MCDisassembler::Fail; // UNDEFINED 4079 index = fieldFromInstruction(Insn, 6, 2); 4080 if (fieldFromInstruction(Insn, 4, 1)) 4081 align = 2; 4082 break; 4083 case 2: 4084 if (fieldFromInstruction(Insn, 6, 1)) 4085 return MCDisassembler::Fail; // UNDEFINED 4086 index = fieldFromInstruction(Insn, 7, 1); 4087 4088 switch (fieldFromInstruction(Insn, 4, 2)) { 4089 case 0 : 4090 align = 0; break; 4091 case 3: 4092 align = 4; break; 4093 default: 4094 return MCDisassembler::Fail; 4095 } 4096 break; 4097 } 4098 4099 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4100 return MCDisassembler::Fail; 4101 if (Rm != 0xF) { // Writeback 4102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4103 return MCDisassembler::Fail; 4104 } 4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 Inst.addOperand(MCOperand::CreateImm(align)); 4108 if (Rm != 0xF) { 4109 if (Rm != 0xD) { 4110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4111 return MCDisassembler::Fail; 4112 } else 4113 Inst.addOperand(MCOperand::CreateReg(0)); 4114 } 4115 4116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4117 return MCDisassembler::Fail; 4118 Inst.addOperand(MCOperand::CreateImm(index)); 4119 4120 return S; 4121 } 4122 4123 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4124 uint64_t Address, const void *Decoder) { 4125 DecodeStatus S = MCDisassembler::Success; 4126 4127 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4128 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4129 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4130 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4131 unsigned size = fieldFromInstruction(Insn, 10, 2); 4132 4133 unsigned align = 0; 4134 unsigned index = 0; 4135 switch (size) { 4136 default: 4137 return MCDisassembler::Fail; 4138 case 0: 4139 if (fieldFromInstruction(Insn, 4, 1)) 4140 return MCDisassembler::Fail; // UNDEFINED 4141 index = fieldFromInstruction(Insn, 5, 3); 4142 break; 4143 case 1: 4144 if (fieldFromInstruction(Insn, 5, 1)) 4145 return MCDisassembler::Fail; // UNDEFINED 4146 index = fieldFromInstruction(Insn, 6, 2); 4147 if (fieldFromInstruction(Insn, 4, 1)) 4148 align = 2; 4149 break; 4150 case 2: 4151 if (fieldFromInstruction(Insn, 6, 1)) 4152 return MCDisassembler::Fail; // UNDEFINED 4153 index = fieldFromInstruction(Insn, 7, 1); 4154 4155 switch (fieldFromInstruction(Insn, 4, 2)) { 4156 case 0: 4157 align = 0; break; 4158 case 3: 4159 align = 4; break; 4160 default: 4161 return MCDisassembler::Fail; 4162 } 4163 break; 4164 } 4165 4166 if (Rm != 0xF) { // Writeback 4167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4168 return MCDisassembler::Fail; 4169 } 4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 Inst.addOperand(MCOperand::CreateImm(align)); 4173 if (Rm != 0xF) { 4174 if (Rm != 0xD) { 4175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 } else 4178 Inst.addOperand(MCOperand::CreateReg(0)); 4179 } 4180 4181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4182 return MCDisassembler::Fail; 4183 Inst.addOperand(MCOperand::CreateImm(index)); 4184 4185 return S; 4186 } 4187 4188 4189 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4190 uint64_t Address, const void *Decoder) { 4191 DecodeStatus S = MCDisassembler::Success; 4192 4193 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4194 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4196 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4197 unsigned size = fieldFromInstruction(Insn, 10, 2); 4198 4199 unsigned align = 0; 4200 unsigned index = 0; 4201 unsigned inc = 1; 4202 switch (size) { 4203 default: 4204 return MCDisassembler::Fail; 4205 case 0: 4206 index = fieldFromInstruction(Insn, 5, 3); 4207 if (fieldFromInstruction(Insn, 4, 1)) 4208 align = 2; 4209 break; 4210 case 1: 4211 index = fieldFromInstruction(Insn, 6, 2); 4212 if (fieldFromInstruction(Insn, 4, 1)) 4213 align = 4; 4214 if (fieldFromInstruction(Insn, 5, 1)) 4215 inc = 2; 4216 break; 4217 case 2: 4218 if (fieldFromInstruction(Insn, 5, 1)) 4219 return MCDisassembler::Fail; // UNDEFINED 4220 index = fieldFromInstruction(Insn, 7, 1); 4221 if (fieldFromInstruction(Insn, 4, 1) != 0) 4222 align = 8; 4223 if (fieldFromInstruction(Insn, 6, 1)) 4224 inc = 2; 4225 break; 4226 } 4227 4228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 if (Rm != 0xF) { // Writeback 4233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 } 4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 Inst.addOperand(MCOperand::CreateImm(align)); 4239 if (Rm != 0xF) { 4240 if (Rm != 0xD) { 4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 } else 4244 Inst.addOperand(MCOperand::CreateReg(0)); 4245 } 4246 4247 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 Inst.addOperand(MCOperand::CreateImm(index)); 4252 4253 return S; 4254 } 4255 4256 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4257 uint64_t Address, const void *Decoder) { 4258 DecodeStatus S = MCDisassembler::Success; 4259 4260 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4261 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4262 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4263 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4264 unsigned size = fieldFromInstruction(Insn, 10, 2); 4265 4266 unsigned align = 0; 4267 unsigned index = 0; 4268 unsigned inc = 1; 4269 switch (size) { 4270 default: 4271 return MCDisassembler::Fail; 4272 case 0: 4273 index = fieldFromInstruction(Insn, 5, 3); 4274 if (fieldFromInstruction(Insn, 4, 1)) 4275 align = 2; 4276 break; 4277 case 1: 4278 index = fieldFromInstruction(Insn, 6, 2); 4279 if (fieldFromInstruction(Insn, 4, 1)) 4280 align = 4; 4281 if (fieldFromInstruction(Insn, 5, 1)) 4282 inc = 2; 4283 break; 4284 case 2: 4285 if (fieldFromInstruction(Insn, 5, 1)) 4286 return MCDisassembler::Fail; // UNDEFINED 4287 index = fieldFromInstruction(Insn, 7, 1); 4288 if (fieldFromInstruction(Insn, 4, 1) != 0) 4289 align = 8; 4290 if (fieldFromInstruction(Insn, 6, 1)) 4291 inc = 2; 4292 break; 4293 } 4294 4295 if (Rm != 0xF) { // Writeback 4296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 } 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 Inst.addOperand(MCOperand::CreateImm(align)); 4302 if (Rm != 0xF) { 4303 if (Rm != 0xD) { 4304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4305 return MCDisassembler::Fail; 4306 } else 4307 Inst.addOperand(MCOperand::CreateReg(0)); 4308 } 4309 4310 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 Inst.addOperand(MCOperand::CreateImm(index)); 4315 4316 return S; 4317 } 4318 4319 4320 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4321 uint64_t Address, const void *Decoder) { 4322 DecodeStatus S = MCDisassembler::Success; 4323 4324 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4325 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4326 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4327 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4328 unsigned size = fieldFromInstruction(Insn, 10, 2); 4329 4330 unsigned align = 0; 4331 unsigned index = 0; 4332 unsigned inc = 1; 4333 switch (size) { 4334 default: 4335 return MCDisassembler::Fail; 4336 case 0: 4337 if (fieldFromInstruction(Insn, 4, 1)) 4338 return MCDisassembler::Fail; // UNDEFINED 4339 index = fieldFromInstruction(Insn, 5, 3); 4340 break; 4341 case 1: 4342 if (fieldFromInstruction(Insn, 4, 1)) 4343 return MCDisassembler::Fail; // UNDEFINED 4344 index = fieldFromInstruction(Insn, 6, 2); 4345 if (fieldFromInstruction(Insn, 5, 1)) 4346 inc = 2; 4347 break; 4348 case 2: 4349 if (fieldFromInstruction(Insn, 4, 2)) 4350 return MCDisassembler::Fail; // UNDEFINED 4351 index = fieldFromInstruction(Insn, 7, 1); 4352 if (fieldFromInstruction(Insn, 6, 1)) 4353 inc = 2; 4354 break; 4355 } 4356 4357 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4358 return MCDisassembler::Fail; 4359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4362 return MCDisassembler::Fail; 4363 4364 if (Rm != 0xF) { // Writeback 4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 } 4368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 Inst.addOperand(MCOperand::CreateImm(align)); 4371 if (Rm != 0xF) { 4372 if (Rm != 0xD) { 4373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4374 return MCDisassembler::Fail; 4375 } else 4376 Inst.addOperand(MCOperand::CreateReg(0)); 4377 } 4378 4379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4380 return MCDisassembler::Fail; 4381 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4382 return MCDisassembler::Fail; 4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4384 return MCDisassembler::Fail; 4385 Inst.addOperand(MCOperand::CreateImm(index)); 4386 4387 return S; 4388 } 4389 4390 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4391 uint64_t Address, const void *Decoder) { 4392 DecodeStatus S = MCDisassembler::Success; 4393 4394 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4395 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4396 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4397 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4398 unsigned size = fieldFromInstruction(Insn, 10, 2); 4399 4400 unsigned align = 0; 4401 unsigned index = 0; 4402 unsigned inc = 1; 4403 switch (size) { 4404 default: 4405 return MCDisassembler::Fail; 4406 case 0: 4407 if (fieldFromInstruction(Insn, 4, 1)) 4408 return MCDisassembler::Fail; // UNDEFINED 4409 index = fieldFromInstruction(Insn, 5, 3); 4410 break; 4411 case 1: 4412 if (fieldFromInstruction(Insn, 4, 1)) 4413 return MCDisassembler::Fail; // UNDEFINED 4414 index = fieldFromInstruction(Insn, 6, 2); 4415 if (fieldFromInstruction(Insn, 5, 1)) 4416 inc = 2; 4417 break; 4418 case 2: 4419 if (fieldFromInstruction(Insn, 4, 2)) 4420 return MCDisassembler::Fail; // UNDEFINED 4421 index = fieldFromInstruction(Insn, 7, 1); 4422 if (fieldFromInstruction(Insn, 6, 1)) 4423 inc = 2; 4424 break; 4425 } 4426 4427 if (Rm != 0xF) { // Writeback 4428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 } 4431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 Inst.addOperand(MCOperand::CreateImm(align)); 4434 if (Rm != 0xF) { 4435 if (Rm != 0xD) { 4436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4437 return MCDisassembler::Fail; 4438 } else 4439 Inst.addOperand(MCOperand::CreateReg(0)); 4440 } 4441 4442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 Inst.addOperand(MCOperand::CreateImm(index)); 4449 4450 return S; 4451 } 4452 4453 4454 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4455 uint64_t Address, const void *Decoder) { 4456 DecodeStatus S = MCDisassembler::Success; 4457 4458 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4459 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4460 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4461 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4462 unsigned size = fieldFromInstruction(Insn, 10, 2); 4463 4464 unsigned align = 0; 4465 unsigned index = 0; 4466 unsigned inc = 1; 4467 switch (size) { 4468 default: 4469 return MCDisassembler::Fail; 4470 case 0: 4471 if (fieldFromInstruction(Insn, 4, 1)) 4472 align = 4; 4473 index = fieldFromInstruction(Insn, 5, 3); 4474 break; 4475 case 1: 4476 if (fieldFromInstruction(Insn, 4, 1)) 4477 align = 8; 4478 index = fieldFromInstruction(Insn, 6, 2); 4479 if (fieldFromInstruction(Insn, 5, 1)) 4480 inc = 2; 4481 break; 4482 case 2: 4483 switch (fieldFromInstruction(Insn, 4, 2)) { 4484 case 0: 4485 align = 0; break; 4486 case 3: 4487 return MCDisassembler::Fail; 4488 default: 4489 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4490 } 4491 4492 index = fieldFromInstruction(Insn, 7, 1); 4493 if (fieldFromInstruction(Insn, 6, 1)) 4494 inc = 2; 4495 break; 4496 } 4497 4498 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4499 return MCDisassembler::Fail; 4500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4501 return MCDisassembler::Fail; 4502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4505 return MCDisassembler::Fail; 4506 4507 if (Rm != 0xF) { // Writeback 4508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4509 return MCDisassembler::Fail; 4510 } 4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 Inst.addOperand(MCOperand::CreateImm(align)); 4514 if (Rm != 0xF) { 4515 if (Rm != 0xD) { 4516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4517 return MCDisassembler::Fail; 4518 } else 4519 Inst.addOperand(MCOperand::CreateReg(0)); 4520 } 4521 4522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4523 return MCDisassembler::Fail; 4524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4525 return MCDisassembler::Fail; 4526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 Inst.addOperand(MCOperand::CreateImm(index)); 4531 4532 return S; 4533 } 4534 4535 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4536 uint64_t Address, const void *Decoder) { 4537 DecodeStatus S = MCDisassembler::Success; 4538 4539 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4540 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4541 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4542 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4543 unsigned size = fieldFromInstruction(Insn, 10, 2); 4544 4545 unsigned align = 0; 4546 unsigned index = 0; 4547 unsigned inc = 1; 4548 switch (size) { 4549 default: 4550 return MCDisassembler::Fail; 4551 case 0: 4552 if (fieldFromInstruction(Insn, 4, 1)) 4553 align = 4; 4554 index = fieldFromInstruction(Insn, 5, 3); 4555 break; 4556 case 1: 4557 if (fieldFromInstruction(Insn, 4, 1)) 4558 align = 8; 4559 index = fieldFromInstruction(Insn, 6, 2); 4560 if (fieldFromInstruction(Insn, 5, 1)) 4561 inc = 2; 4562 break; 4563 case 2: 4564 switch (fieldFromInstruction(Insn, 4, 2)) { 4565 case 0: 4566 align = 0; break; 4567 case 3: 4568 return MCDisassembler::Fail; 4569 default: 4570 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4571 } 4572 4573 index = fieldFromInstruction(Insn, 7, 1); 4574 if (fieldFromInstruction(Insn, 6, 1)) 4575 inc = 2; 4576 break; 4577 } 4578 4579 if (Rm != 0xF) { // Writeback 4580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4581 return MCDisassembler::Fail; 4582 } 4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4584 return MCDisassembler::Fail; 4585 Inst.addOperand(MCOperand::CreateImm(align)); 4586 if (Rm != 0xF) { 4587 if (Rm != 0xD) { 4588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 } else 4591 Inst.addOperand(MCOperand::CreateReg(0)); 4592 } 4593 4594 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4595 return MCDisassembler::Fail; 4596 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4597 return MCDisassembler::Fail; 4598 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4599 return MCDisassembler::Fail; 4600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4601 return MCDisassembler::Fail; 4602 Inst.addOperand(MCOperand::CreateImm(index)); 4603 4604 return S; 4605 } 4606 4607 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4608 uint64_t Address, const void *Decoder) { 4609 DecodeStatus S = MCDisassembler::Success; 4610 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4611 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4612 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4613 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4614 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4615 4616 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4617 S = MCDisassembler::SoftFail; 4618 4619 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4620 return MCDisassembler::Fail; 4621 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4624 return MCDisassembler::Fail; 4625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4626 return MCDisassembler::Fail; 4627 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4628 return MCDisassembler::Fail; 4629 4630 return S; 4631 } 4632 4633 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4634 uint64_t Address, const void *Decoder) { 4635 DecodeStatus S = MCDisassembler::Success; 4636 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4637 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4638 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4639 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4640 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4641 4642 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4643 S = MCDisassembler::SoftFail; 4644 4645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4646 return MCDisassembler::Fail; 4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4654 return MCDisassembler::Fail; 4655 4656 return S; 4657 } 4658 4659 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4660 uint64_t Address, const void *Decoder) { 4661 DecodeStatus S = MCDisassembler::Success; 4662 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4663 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4664 4665 if (pred == 0xF) { 4666 pred = 0xE; 4667 S = MCDisassembler::SoftFail; 4668 } 4669 4670 if (mask == 0x0) { 4671 mask |= 0x8; 4672 S = MCDisassembler::SoftFail; 4673 } 4674 4675 Inst.addOperand(MCOperand::CreateImm(pred)); 4676 Inst.addOperand(MCOperand::CreateImm(mask)); 4677 return S; 4678 } 4679 4680 static DecodeStatus 4681 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4682 uint64_t Address, const void *Decoder) { 4683 DecodeStatus S = MCDisassembler::Success; 4684 4685 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4686 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4687 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4688 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4689 unsigned W = fieldFromInstruction(Insn, 21, 1); 4690 unsigned U = fieldFromInstruction(Insn, 23, 1); 4691 unsigned P = fieldFromInstruction(Insn, 24, 1); 4692 bool writeback = (W == 1) | (P == 0); 4693 4694 addr |= (U << 8) | (Rn << 9); 4695 4696 if (writeback && (Rn == Rt || Rn == Rt2)) 4697 Check(S, MCDisassembler::SoftFail); 4698 if (Rt == Rt2) 4699 Check(S, MCDisassembler::SoftFail); 4700 4701 // Rt 4702 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4703 return MCDisassembler::Fail; 4704 // Rt2 4705 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 // Writeback operand 4708 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 // addr 4711 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4712 return MCDisassembler::Fail; 4713 4714 return S; 4715 } 4716 4717 static DecodeStatus 4718 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4719 uint64_t Address, const void *Decoder) { 4720 DecodeStatus S = MCDisassembler::Success; 4721 4722 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4723 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4724 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4725 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4726 unsigned W = fieldFromInstruction(Insn, 21, 1); 4727 unsigned U = fieldFromInstruction(Insn, 23, 1); 4728 unsigned P = fieldFromInstruction(Insn, 24, 1); 4729 bool writeback = (W == 1) | (P == 0); 4730 4731 addr |= (U << 8) | (Rn << 9); 4732 4733 if (writeback && (Rn == Rt || Rn == Rt2)) 4734 Check(S, MCDisassembler::SoftFail); 4735 4736 // Writeback operand 4737 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4738 return MCDisassembler::Fail; 4739 // Rt 4740 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4741 return MCDisassembler::Fail; 4742 // Rt2 4743 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4744 return MCDisassembler::Fail; 4745 // addr 4746 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4747 return MCDisassembler::Fail; 4748 4749 return S; 4750 } 4751 4752 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4753 uint64_t Address, const void *Decoder) { 4754 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4755 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4756 if (sign1 != sign2) return MCDisassembler::Fail; 4757 4758 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4759 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4760 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4761 Val |= sign1 << 12; 4762 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4763 4764 return MCDisassembler::Success; 4765 } 4766 4767 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4768 uint64_t Address, 4769 const void *Decoder) { 4770 DecodeStatus S = MCDisassembler::Success; 4771 4772 // Shift of "asr #32" is not allowed in Thumb2 mode. 4773 if (Val == 0x20) S = MCDisassembler::SoftFail; 4774 Inst.addOperand(MCOperand::CreateImm(Val)); 4775 return S; 4776 } 4777 4778 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4779 uint64_t Address, const void *Decoder) { 4780 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4781 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4782 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4783 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4784 4785 if (pred == 0xF) 4786 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4787 4788 DecodeStatus S = MCDisassembler::Success; 4789 4790 if (Rt == Rn || Rn == Rt2) 4791 S = MCDisassembler::SoftFail; 4792 4793 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4794 return MCDisassembler::Fail; 4795 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4796 return MCDisassembler::Fail; 4797 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4798 return MCDisassembler::Fail; 4799 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 4802 return S; 4803 } 4804 4805 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4806 uint64_t Address, const void *Decoder) { 4807 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4808 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4809 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4810 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4811 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4812 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4813 unsigned op = fieldFromInstruction(Insn, 5, 1); 4814 4815 DecodeStatus S = MCDisassembler::Success; 4816 4817 // VMOVv2f32 is ambiguous with these decodings. 4818 if (!(imm & 0x38) && cmode == 0xF) { 4819 if (op == 1) return MCDisassembler::Fail; 4820 Inst.setOpcode(ARM::VMOVv2f32); 4821 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4822 } 4823 4824 if (!(imm & 0x20)) return MCDisassembler::Fail; 4825 4826 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4827 return MCDisassembler::Fail; 4828 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4829 return MCDisassembler::Fail; 4830 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4831 4832 return S; 4833 } 4834 4835 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4836 uint64_t Address, const void *Decoder) { 4837 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4838 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4839 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4840 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4841 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4842 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4843 unsigned op = fieldFromInstruction(Insn, 5, 1); 4844 4845 DecodeStatus S = MCDisassembler::Success; 4846 4847 // VMOVv4f32 is ambiguous with these decodings. 4848 if (!(imm & 0x38) && cmode == 0xF) { 4849 if (op == 1) return MCDisassembler::Fail; 4850 Inst.setOpcode(ARM::VMOVv4f32); 4851 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4852 } 4853 4854 if (!(imm & 0x20)) return MCDisassembler::Fail; 4855 4856 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4859 return MCDisassembler::Fail; 4860 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4861 4862 return S; 4863 } 4864 4865 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4866 const void *Decoder) 4867 { 4868 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4869 if (Imm > 4) return MCDisassembler::Fail; 4870 Inst.addOperand(MCOperand::CreateImm(Imm)); 4871 return MCDisassembler::Success; 4872 } 4873 4874 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4875 uint64_t Address, const void *Decoder) { 4876 DecodeStatus S = MCDisassembler::Success; 4877 4878 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4879 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4880 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4881 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4882 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4883 4884 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4885 S = MCDisassembler::SoftFail; 4886 4887 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4888 return MCDisassembler::Fail; 4889 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4890 return MCDisassembler::Fail; 4891 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4892 return MCDisassembler::Fail; 4893 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4894 return MCDisassembler::Fail; 4895 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4896 return MCDisassembler::Fail; 4897 4898 return S; 4899 } 4900 4901 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4902 uint64_t Address, const void *Decoder) { 4903 4904 DecodeStatus S = MCDisassembler::Success; 4905 4906 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4907 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4908 unsigned cop = fieldFromInstruction(Val, 8, 4); 4909 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4910 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4911 4912 if ((cop & ~0x1) == 0xa) 4913 return MCDisassembler::Fail; 4914 4915 if (Rt == Rt2) 4916 S = MCDisassembler::SoftFail; 4917 4918 Inst.addOperand(MCOperand::CreateImm(cop)); 4919 Inst.addOperand(MCOperand::CreateImm(opc1)); 4920 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4921 return MCDisassembler::Fail; 4922 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4923 return MCDisassembler::Fail; 4924 Inst.addOperand(MCOperand::CreateImm(CRm)); 4925 4926 return S; 4927 } 4928 4929