1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 183 unsigned RegNo, uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 217 unsigned Insn, 218 uint64_t Adddress, 219 const void *Decoder); 220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 323 const void *Decoder); 324 325 326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 389 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 #include "ARMGenDisassemblerTables.inc" 394 395 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 396 return new ARMDisassembler(STI); 397 } 398 399 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 400 return new ThumbDisassembler(STI); 401 } 402 403 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 404 const MemoryObject &Region, 405 uint64_t Address, 406 raw_ostream &os, 407 raw_ostream &cs) const { 408 CommentStream = &cs; 409 410 uint8_t bytes[4]; 411 412 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 413 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 414 415 // We want to read exactly 4 bytes of data. 416 if (Region.readBytes(Address, 4, bytes) == -1) { 417 Size = 0; 418 return MCDisassembler::Fail; 419 } 420 421 // Encoded as a small-endian 32-bit word in the stream. 422 uint32_t insn = (bytes[3] << 24) | 423 (bytes[2] << 16) | 424 (bytes[1] << 8) | 425 (bytes[0] << 0); 426 427 // Calling the auto-generated decoder function. 428 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 429 Address, this, STI); 430 if (result != MCDisassembler::Fail) { 431 Size = 4; 432 return result; 433 } 434 435 // VFP and NEON instructions, similarly, are shared between ARM 436 // and Thumb modes. 437 MI.clear(); 438 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 439 if (result != MCDisassembler::Fail) { 440 Size = 4; 441 return result; 442 } 443 444 MI.clear(); 445 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 446 this, STI); 447 if (result != MCDisassembler::Fail) { 448 Size = 4; 449 // Add a fake predicate operand, because we share these instruction 450 // definitions with Thumb2 where these instructions are predicable. 451 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 452 return MCDisassembler::Fail; 453 return result; 454 } 455 456 MI.clear(); 457 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 458 this, STI); 459 if (result != MCDisassembler::Fail) { 460 Size = 4; 461 // Add a fake predicate operand, because we share these instruction 462 // definitions with Thumb2 where these instructions are predicable. 463 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 464 return MCDisassembler::Fail; 465 return result; 466 } 467 468 MI.clear(); 469 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 470 this, STI); 471 if (result != MCDisassembler::Fail) { 472 Size = 4; 473 // Add a fake predicate operand, because we share these instruction 474 // definitions with Thumb2 where these instructions are predicable. 475 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 476 return MCDisassembler::Fail; 477 return result; 478 } 479 480 MI.clear(); 481 482 Size = 0; 483 return MCDisassembler::Fail; 484 } 485 486 namespace llvm { 487 extern const MCInstrDesc ARMInsts[]; 488 } 489 490 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 491 /// immediate Value in the MCInst. The immediate Value has had any PC 492 /// adjustment made by the caller. If the instruction is a branch instruction 493 /// then isBranch is true, else false. If the getOpInfo() function was set as 494 /// part of the setupForSymbolicDisassembly() call then that function is called 495 /// to get any symbolic information at the Address for this instruction. If 496 /// that returns non-zero then the symbolic information it returns is used to 497 /// create an MCExpr and that is added as an operand to the MCInst. If 498 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 499 /// Value is done and if a symbol is found an MCExpr is created with that, else 500 /// an MCExpr with Value is created. This function returns true if it adds an 501 /// operand to the MCInst and false otherwise. 502 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 503 bool isBranch, uint64_t InstSize, 504 MCInst &MI, const void *Decoder) { 505 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 506 // FIXME: Does it make sense for value to be negative? 507 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 508 /* Offset */ 0, InstSize); 509 } 510 511 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 512 /// referenced by a load instruction with the base register that is the Pc. 513 /// These can often be values in a literal pool near the Address of the 514 /// instruction. The Address of the instruction and its immediate Value are 515 /// used as a possible literal pool entry. The SymbolLookUp call back will 516 /// return the name of a symbol referenced by the literal pool's entry if 517 /// the referenced address is that of a symbol. Or it will return a pointer to 518 /// a literal 'C' string if the referenced address of the literal pool's entry 519 /// is an address into a section with 'C' string literals. 520 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 521 const void *Decoder) { 522 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 523 Dis->tryAddingPcLoadReferenceComment(Value, Address); 524 } 525 526 // Thumb1 instructions don't have explicit S bits. Rather, they 527 // implicitly set CPSR. Since it's not represented in the encoding, the 528 // auto-generated decoder won't inject the CPSR operand. We need to fix 529 // that as a post-pass. 530 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 531 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 532 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 533 MCInst::iterator I = MI.begin(); 534 for (unsigned i = 0; i < NumOps; ++i, ++I) { 535 if (I == MI.end()) break; 536 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 537 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 538 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 539 return; 540 } 541 } 542 543 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 544 } 545 546 // Most Thumb instructions don't have explicit predicates in the 547 // encoding, but rather get their predicates from IT context. We need 548 // to fix up the predicate operands using this context information as a 549 // post-pass. 550 MCDisassembler::DecodeStatus 551 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 552 MCDisassembler::DecodeStatus S = Success; 553 554 // A few instructions actually have predicates encoded in them. Don't 555 // try to overwrite it if we're seeing one of those. 556 switch (MI.getOpcode()) { 557 case ARM::tBcc: 558 case ARM::t2Bcc: 559 case ARM::tCBZ: 560 case ARM::tCBNZ: 561 case ARM::tCPS: 562 case ARM::t2CPS3p: 563 case ARM::t2CPS2p: 564 case ARM::t2CPS1p: 565 case ARM::tMOVSr: 566 case ARM::tSETEND: 567 // Some instructions (mostly conditional branches) are not 568 // allowed in IT blocks. 569 if (ITBlock.instrInITBlock()) 570 S = SoftFail; 571 else 572 return Success; 573 break; 574 case ARM::tB: 575 case ARM::t2B: 576 case ARM::t2TBB: 577 case ARM::t2TBH: 578 // Some instructions (mostly unconditional branches) can 579 // only appears at the end of, or outside of, an IT. 580 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 581 S = SoftFail; 582 break; 583 default: 584 break; 585 } 586 587 // If we're in an IT block, base the predicate on that. Otherwise, 588 // assume a predicate of AL. 589 unsigned CC; 590 CC = ITBlock.getITCC(); 591 if (CC == 0xF) 592 CC = ARMCC::AL; 593 if (ITBlock.instrInITBlock()) 594 ITBlock.advanceITState(); 595 596 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 597 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 598 MCInst::iterator I = MI.begin(); 599 for (unsigned i = 0; i < NumOps; ++i, ++I) { 600 if (I == MI.end()) break; 601 if (OpInfo[i].isPredicate()) { 602 I = MI.insert(I, MCOperand::CreateImm(CC)); 603 ++I; 604 if (CC == ARMCC::AL) 605 MI.insert(I, MCOperand::CreateReg(0)); 606 else 607 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 608 return S; 609 } 610 } 611 612 I = MI.insert(I, MCOperand::CreateImm(CC)); 613 ++I; 614 if (CC == ARMCC::AL) 615 MI.insert(I, MCOperand::CreateReg(0)); 616 else 617 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 618 619 return S; 620 } 621 622 // Thumb VFP instructions are a special case. Because we share their 623 // encodings between ARM and Thumb modes, and they are predicable in ARM 624 // mode, the auto-generated decoder will give them an (incorrect) 625 // predicate operand. We need to rewrite these operands based on the IT 626 // context as a post-pass. 627 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 628 unsigned CC; 629 CC = ITBlock.getITCC(); 630 if (ITBlock.instrInITBlock()) 631 ITBlock.advanceITState(); 632 633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 634 MCInst::iterator I = MI.begin(); 635 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 636 for (unsigned i = 0; i < NumOps; ++i, ++I) { 637 if (OpInfo[i].isPredicate() ) { 638 I->setImm(CC); 639 ++I; 640 if (CC == ARMCC::AL) 641 I->setReg(0); 642 else 643 I->setReg(ARM::CPSR); 644 return; 645 } 646 } 647 } 648 649 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 650 const MemoryObject &Region, 651 uint64_t Address, 652 raw_ostream &os, 653 raw_ostream &cs) const { 654 CommentStream = &cs; 655 656 uint8_t bytes[4]; 657 658 assert((STI.getFeatureBits() & ARM::ModeThumb) && 659 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 660 661 // We want to read exactly 2 bytes of data. 662 if (Region.readBytes(Address, 2, bytes) == -1) { 663 Size = 0; 664 return MCDisassembler::Fail; 665 } 666 667 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 668 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 669 Address, this, STI); 670 if (result != MCDisassembler::Fail) { 671 Size = 2; 672 Check(result, AddThumbPredicate(MI)); 673 return result; 674 } 675 676 MI.clear(); 677 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 678 Address, this, STI); 679 if (result) { 680 Size = 2; 681 bool InITBlock = ITBlock.instrInITBlock(); 682 Check(result, AddThumbPredicate(MI)); 683 AddThumb1SBit(MI, InITBlock); 684 return result; 685 } 686 687 MI.clear(); 688 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 689 Address, this, STI); 690 if (result != MCDisassembler::Fail) { 691 Size = 2; 692 693 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 694 // the Thumb predicate. 695 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 696 result = MCDisassembler::SoftFail; 697 698 Check(result, AddThumbPredicate(MI)); 699 700 // If we find an IT instruction, we need to parse its condition 701 // code and mask operands so that we can apply them correctly 702 // to the subsequent instructions. 703 if (MI.getOpcode() == ARM::t2IT) { 704 705 unsigned Firstcond = MI.getOperand(0).getImm(); 706 unsigned Mask = MI.getOperand(1).getImm(); 707 ITBlock.setITState(Firstcond, Mask); 708 } 709 710 return result; 711 } 712 713 // We want to read exactly 4 bytes of data. 714 if (Region.readBytes(Address, 4, bytes) == -1) { 715 Size = 0; 716 return MCDisassembler::Fail; 717 } 718 719 uint32_t insn32 = (bytes[3] << 8) | 720 (bytes[2] << 0) | 721 (bytes[1] << 24) | 722 (bytes[0] << 16); 723 MI.clear(); 724 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 725 this, STI); 726 if (result != MCDisassembler::Fail) { 727 Size = 4; 728 bool InITBlock = ITBlock.instrInITBlock(); 729 Check(result, AddThumbPredicate(MI)); 730 AddThumb1SBit(MI, InITBlock); 731 return result; 732 } 733 734 MI.clear(); 735 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 736 this, STI); 737 if (result != MCDisassembler::Fail) { 738 Size = 4; 739 Check(result, AddThumbPredicate(MI)); 740 return result; 741 } 742 743 MI.clear(); 744 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 745 if (result != MCDisassembler::Fail) { 746 Size = 4; 747 UpdateThumbVFPPredicate(MI); 748 return result; 749 } 750 751 MI.clear(); 752 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 753 this, STI); 754 if (result != MCDisassembler::Fail) { 755 Size = 4; 756 Check(result, AddThumbPredicate(MI)); 757 return result; 758 } 759 760 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 761 MI.clear(); 762 uint32_t NEONLdStInsn = insn32; 763 NEONLdStInsn &= 0xF0FFFFFF; 764 NEONLdStInsn |= 0x04000000; 765 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 766 Address, this, STI); 767 if (result != MCDisassembler::Fail) { 768 Size = 4; 769 Check(result, AddThumbPredicate(MI)); 770 return result; 771 } 772 } 773 774 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 775 MI.clear(); 776 uint32_t NEONDataInsn = insn32; 777 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 778 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 779 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 780 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 781 Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 4; 784 Check(result, AddThumbPredicate(MI)); 785 return result; 786 } 787 } 788 789 Size = 0; 790 return MCDisassembler::Fail; 791 } 792 793 794 extern "C" void LLVMInitializeARMDisassembler() { 795 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 796 createARMDisassembler); 797 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 798 createThumbDisassembler); 799 } 800 801 static const uint16_t GPRDecoderTable[] = { 802 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 803 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 804 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 805 ARM::R12, ARM::SP, ARM::LR, ARM::PC 806 }; 807 808 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 809 uint64_t Address, const void *Decoder) { 810 if (RegNo > 15) 811 return MCDisassembler::Fail; 812 813 unsigned Register = GPRDecoderTable[RegNo]; 814 Inst.addOperand(MCOperand::CreateReg(Register)); 815 return MCDisassembler::Success; 816 } 817 818 static DecodeStatus 819 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 820 uint64_t Address, const void *Decoder) { 821 DecodeStatus S = MCDisassembler::Success; 822 823 if (RegNo == 15) 824 S = MCDisassembler::SoftFail; 825 826 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 827 828 return S; 829 } 830 831 static DecodeStatus 832 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 833 uint64_t Address, const void *Decoder) { 834 DecodeStatus S = MCDisassembler::Success; 835 836 if (RegNo == 15) 837 { 838 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 839 return MCDisassembler::Success; 840 } 841 842 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 843 return S; 844 } 845 846 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 847 uint64_t Address, const void *Decoder) { 848 if (RegNo > 7) 849 return MCDisassembler::Fail; 850 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 851 } 852 853 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 854 uint64_t Address, const void *Decoder) { 855 unsigned Register = 0; 856 switch (RegNo) { 857 case 0: 858 Register = ARM::R0; 859 break; 860 case 1: 861 Register = ARM::R1; 862 break; 863 case 2: 864 Register = ARM::R2; 865 break; 866 case 3: 867 Register = ARM::R3; 868 break; 869 case 9: 870 Register = ARM::R9; 871 break; 872 case 12: 873 Register = ARM::R12; 874 break; 875 default: 876 return MCDisassembler::Fail; 877 } 878 879 Inst.addOperand(MCOperand::CreateReg(Register)); 880 return MCDisassembler::Success; 881 } 882 883 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 886 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 887 } 888 889 static const uint16_t SPRDecoderTable[] = { 890 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 891 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 892 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 893 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 894 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 895 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 896 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 897 ARM::S28, ARM::S29, ARM::S30, ARM::S31 898 }; 899 900 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 if (RegNo > 31) 903 return MCDisassembler::Fail; 904 905 unsigned Register = SPRDecoderTable[RegNo]; 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static const uint16_t DPRDecoderTable[] = { 911 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 912 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 913 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 914 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 915 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 916 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 917 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 918 ARM::D28, ARM::D29, ARM::D30, ARM::D31 919 }; 920 921 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 922 uint64_t Address, const void *Decoder) { 923 if (RegNo > 31) 924 return MCDisassembler::Fail; 925 926 unsigned Register = DPRDecoderTable[RegNo]; 927 Inst.addOperand(MCOperand::CreateReg(Register)); 928 return MCDisassembler::Success; 929 } 930 931 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 932 uint64_t Address, const void *Decoder) { 933 if (RegNo > 7) 934 return MCDisassembler::Fail; 935 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 936 } 937 938 static DecodeStatus 939 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 940 uint64_t Address, const void *Decoder) { 941 if (RegNo > 15) 942 return MCDisassembler::Fail; 943 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 944 } 945 946 static const uint16_t QPRDecoderTable[] = { 947 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 948 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 949 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 950 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 951 }; 952 953 954 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 955 uint64_t Address, const void *Decoder) { 956 if (RegNo > 31 || (RegNo & 1) != 0) 957 return MCDisassembler::Fail; 958 RegNo >>= 1; 959 960 unsigned Register = QPRDecoderTable[RegNo]; 961 Inst.addOperand(MCOperand::CreateReg(Register)); 962 return MCDisassembler::Success; 963 } 964 965 static const uint16_t DPairDecoderTable[] = { 966 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 967 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 968 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 969 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 970 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 971 ARM::Q15 972 }; 973 974 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 975 uint64_t Address, const void *Decoder) { 976 if (RegNo > 30) 977 return MCDisassembler::Fail; 978 979 unsigned Register = DPairDecoderTable[RegNo]; 980 Inst.addOperand(MCOperand::CreateReg(Register)); 981 return MCDisassembler::Success; 982 } 983 984 static const uint16_t DPairSpacedDecoderTable[] = { 985 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 986 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 987 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 988 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 989 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 990 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 991 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 992 ARM::D28_D30, ARM::D29_D31 993 }; 994 995 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 996 unsigned RegNo, 997 uint64_t Address, 998 const void *Decoder) { 999 if (RegNo > 29) 1000 return MCDisassembler::Fail; 1001 1002 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1003 Inst.addOperand(MCOperand::CreateReg(Register)); 1004 return MCDisassembler::Success; 1005 } 1006 1007 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1008 uint64_t Address, const void *Decoder) { 1009 if (Val == 0xF) return MCDisassembler::Fail; 1010 // AL predicate is not allowed on Thumb1 branches. 1011 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1012 return MCDisassembler::Fail; 1013 Inst.addOperand(MCOperand::CreateImm(Val)); 1014 if (Val == ARMCC::AL) { 1015 Inst.addOperand(MCOperand::CreateReg(0)); 1016 } else 1017 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1018 return MCDisassembler::Success; 1019 } 1020 1021 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1022 uint64_t Address, const void *Decoder) { 1023 if (Val) 1024 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1025 else 1026 Inst.addOperand(MCOperand::CreateReg(0)); 1027 return MCDisassembler::Success; 1028 } 1029 1030 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1031 uint64_t Address, const void *Decoder) { 1032 uint32_t imm = Val & 0xFF; 1033 uint32_t rot = (Val & 0xF00) >> 7; 1034 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1035 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1036 return MCDisassembler::Success; 1037 } 1038 1039 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1040 uint64_t Address, const void *Decoder) { 1041 DecodeStatus S = MCDisassembler::Success; 1042 1043 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1044 unsigned type = fieldFromInstruction(Val, 5, 2); 1045 unsigned imm = fieldFromInstruction(Val, 7, 5); 1046 1047 // Register-immediate 1048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1049 return MCDisassembler::Fail; 1050 1051 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1052 switch (type) { 1053 case 0: 1054 Shift = ARM_AM::lsl; 1055 break; 1056 case 1: 1057 Shift = ARM_AM::lsr; 1058 break; 1059 case 2: 1060 Shift = ARM_AM::asr; 1061 break; 1062 case 3: 1063 Shift = ARM_AM::ror; 1064 break; 1065 } 1066 1067 if (Shift == ARM_AM::ror && imm == 0) 1068 Shift = ARM_AM::rrx; 1069 1070 unsigned Op = Shift | (imm << 3); 1071 Inst.addOperand(MCOperand::CreateImm(Op)); 1072 1073 return S; 1074 } 1075 1076 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1077 uint64_t Address, const void *Decoder) { 1078 DecodeStatus S = MCDisassembler::Success; 1079 1080 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1081 unsigned type = fieldFromInstruction(Val, 5, 2); 1082 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1083 1084 // Register-register 1085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1086 return MCDisassembler::Fail; 1087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1088 return MCDisassembler::Fail; 1089 1090 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1091 switch (type) { 1092 case 0: 1093 Shift = ARM_AM::lsl; 1094 break; 1095 case 1: 1096 Shift = ARM_AM::lsr; 1097 break; 1098 case 2: 1099 Shift = ARM_AM::asr; 1100 break; 1101 case 3: 1102 Shift = ARM_AM::ror; 1103 break; 1104 } 1105 1106 Inst.addOperand(MCOperand::CreateImm(Shift)); 1107 1108 return S; 1109 } 1110 1111 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1112 uint64_t Address, const void *Decoder) { 1113 DecodeStatus S = MCDisassembler::Success; 1114 1115 bool writebackLoad = false; 1116 unsigned writebackReg = 0; 1117 switch (Inst.getOpcode()) { 1118 default: 1119 break; 1120 case ARM::LDMIA_UPD: 1121 case ARM::LDMDB_UPD: 1122 case ARM::LDMIB_UPD: 1123 case ARM::LDMDA_UPD: 1124 case ARM::t2LDMIA_UPD: 1125 case ARM::t2LDMDB_UPD: 1126 writebackLoad = true; 1127 writebackReg = Inst.getOperand(0).getReg(); 1128 break; 1129 } 1130 1131 // Empty register lists are not allowed. 1132 if (Val == 0) return MCDisassembler::Fail; 1133 for (unsigned i = 0; i < 16; ++i) { 1134 if (Val & (1 << i)) { 1135 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1136 return MCDisassembler::Fail; 1137 // Writeback not allowed if Rn is in the target list. 1138 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1139 Check(S, MCDisassembler::SoftFail); 1140 } 1141 } 1142 1143 return S; 1144 } 1145 1146 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1147 uint64_t Address, const void *Decoder) { 1148 DecodeStatus S = MCDisassembler::Success; 1149 1150 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1151 unsigned regs = fieldFromInstruction(Val, 0, 8); 1152 1153 // In case of unpredictable encoding, tweak the operands. 1154 if (regs == 0 || (Vd + regs) > 32) { 1155 regs = Vd + regs > 32 ? 32 - Vd : regs; 1156 regs = std::max( 1u, regs); 1157 S = MCDisassembler::SoftFail; 1158 } 1159 1160 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1161 return MCDisassembler::Fail; 1162 for (unsigned i = 0; i < (regs - 1); ++i) { 1163 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1164 return MCDisassembler::Fail; 1165 } 1166 1167 return S; 1168 } 1169 1170 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1171 uint64_t Address, const void *Decoder) { 1172 DecodeStatus S = MCDisassembler::Success; 1173 1174 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1175 unsigned regs = fieldFromInstruction(Val, 1, 7); 1176 1177 // In case of unpredictable encoding, tweak the operands. 1178 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1179 regs = Vd + regs > 32 ? 32 - Vd : regs; 1180 regs = std::max( 1u, regs); 1181 regs = std::min(16u, regs); 1182 S = MCDisassembler::SoftFail; 1183 } 1184 1185 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1186 return MCDisassembler::Fail; 1187 for (unsigned i = 0; i < (regs - 1); ++i) { 1188 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1189 return MCDisassembler::Fail; 1190 } 1191 1192 return S; 1193 } 1194 1195 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1196 uint64_t Address, const void *Decoder) { 1197 // This operand encodes a mask of contiguous zeros between a specified MSB 1198 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1199 // the mask of all bits LSB-and-lower, and then xor them to create 1200 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1201 // create the final mask. 1202 unsigned msb = fieldFromInstruction(Val, 5, 5); 1203 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1204 1205 DecodeStatus S = MCDisassembler::Success; 1206 if (lsb > msb) { 1207 Check(S, MCDisassembler::SoftFail); 1208 // The check above will cause the warning for the "potentially undefined 1209 // instruction encoding" but we can't build a bad MCOperand value here 1210 // with a lsb > msb or else printing the MCInst will cause a crash. 1211 lsb = msb; 1212 } 1213 1214 uint32_t msb_mask = 0xFFFFFFFF; 1215 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1216 uint32_t lsb_mask = (1U << lsb) - 1; 1217 1218 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1219 return S; 1220 } 1221 1222 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1223 uint64_t Address, const void *Decoder) { 1224 DecodeStatus S = MCDisassembler::Success; 1225 1226 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1227 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1228 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1229 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1230 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1231 unsigned U = fieldFromInstruction(Insn, 23, 1); 1232 1233 switch (Inst.getOpcode()) { 1234 case ARM::LDC_OFFSET: 1235 case ARM::LDC_PRE: 1236 case ARM::LDC_POST: 1237 case ARM::LDC_OPTION: 1238 case ARM::LDCL_OFFSET: 1239 case ARM::LDCL_PRE: 1240 case ARM::LDCL_POST: 1241 case ARM::LDCL_OPTION: 1242 case ARM::STC_OFFSET: 1243 case ARM::STC_PRE: 1244 case ARM::STC_POST: 1245 case ARM::STC_OPTION: 1246 case ARM::STCL_OFFSET: 1247 case ARM::STCL_PRE: 1248 case ARM::STCL_POST: 1249 case ARM::STCL_OPTION: 1250 case ARM::t2LDC_OFFSET: 1251 case ARM::t2LDC_PRE: 1252 case ARM::t2LDC_POST: 1253 case ARM::t2LDC_OPTION: 1254 case ARM::t2LDCL_OFFSET: 1255 case ARM::t2LDCL_PRE: 1256 case ARM::t2LDCL_POST: 1257 case ARM::t2LDCL_OPTION: 1258 case ARM::t2STC_OFFSET: 1259 case ARM::t2STC_PRE: 1260 case ARM::t2STC_POST: 1261 case ARM::t2STC_OPTION: 1262 case ARM::t2STCL_OFFSET: 1263 case ARM::t2STCL_PRE: 1264 case ARM::t2STCL_POST: 1265 case ARM::t2STCL_OPTION: 1266 if (coproc == 0xA || coproc == 0xB) 1267 return MCDisassembler::Fail; 1268 break; 1269 default: 1270 break; 1271 } 1272 1273 Inst.addOperand(MCOperand::CreateImm(coproc)); 1274 Inst.addOperand(MCOperand::CreateImm(CRd)); 1275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1276 return MCDisassembler::Fail; 1277 1278 switch (Inst.getOpcode()) { 1279 case ARM::t2LDC2_OFFSET: 1280 case ARM::t2LDC2L_OFFSET: 1281 case ARM::t2LDC2_PRE: 1282 case ARM::t2LDC2L_PRE: 1283 case ARM::t2STC2_OFFSET: 1284 case ARM::t2STC2L_OFFSET: 1285 case ARM::t2STC2_PRE: 1286 case ARM::t2STC2L_PRE: 1287 case ARM::LDC2_OFFSET: 1288 case ARM::LDC2L_OFFSET: 1289 case ARM::LDC2_PRE: 1290 case ARM::LDC2L_PRE: 1291 case ARM::STC2_OFFSET: 1292 case ARM::STC2L_OFFSET: 1293 case ARM::STC2_PRE: 1294 case ARM::STC2L_PRE: 1295 case ARM::t2LDC_OFFSET: 1296 case ARM::t2LDCL_OFFSET: 1297 case ARM::t2LDC_PRE: 1298 case ARM::t2LDCL_PRE: 1299 case ARM::t2STC_OFFSET: 1300 case ARM::t2STCL_OFFSET: 1301 case ARM::t2STC_PRE: 1302 case ARM::t2STCL_PRE: 1303 case ARM::LDC_OFFSET: 1304 case ARM::LDCL_OFFSET: 1305 case ARM::LDC_PRE: 1306 case ARM::LDCL_PRE: 1307 case ARM::STC_OFFSET: 1308 case ARM::STCL_OFFSET: 1309 case ARM::STC_PRE: 1310 case ARM::STCL_PRE: 1311 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1312 Inst.addOperand(MCOperand::CreateImm(imm)); 1313 break; 1314 case ARM::t2LDC2_POST: 1315 case ARM::t2LDC2L_POST: 1316 case ARM::t2STC2_POST: 1317 case ARM::t2STC2L_POST: 1318 case ARM::LDC2_POST: 1319 case ARM::LDC2L_POST: 1320 case ARM::STC2_POST: 1321 case ARM::STC2L_POST: 1322 case ARM::t2LDC_POST: 1323 case ARM::t2LDCL_POST: 1324 case ARM::t2STC_POST: 1325 case ARM::t2STCL_POST: 1326 case ARM::LDC_POST: 1327 case ARM::LDCL_POST: 1328 case ARM::STC_POST: 1329 case ARM::STCL_POST: 1330 imm |= U << 8; 1331 // fall through. 1332 default: 1333 // The 'option' variant doesn't encode 'U' in the immediate since 1334 // the immediate is unsigned [0,255]. 1335 Inst.addOperand(MCOperand::CreateImm(imm)); 1336 break; 1337 } 1338 1339 switch (Inst.getOpcode()) { 1340 case ARM::LDC_OFFSET: 1341 case ARM::LDC_PRE: 1342 case ARM::LDC_POST: 1343 case ARM::LDC_OPTION: 1344 case ARM::LDCL_OFFSET: 1345 case ARM::LDCL_PRE: 1346 case ARM::LDCL_POST: 1347 case ARM::LDCL_OPTION: 1348 case ARM::STC_OFFSET: 1349 case ARM::STC_PRE: 1350 case ARM::STC_POST: 1351 case ARM::STC_OPTION: 1352 case ARM::STCL_OFFSET: 1353 case ARM::STCL_PRE: 1354 case ARM::STCL_POST: 1355 case ARM::STCL_OPTION: 1356 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1357 return MCDisassembler::Fail; 1358 break; 1359 default: 1360 break; 1361 } 1362 1363 return S; 1364 } 1365 1366 static DecodeStatus 1367 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1368 uint64_t Address, const void *Decoder) { 1369 DecodeStatus S = MCDisassembler::Success; 1370 1371 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1372 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1373 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1374 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1375 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1376 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1377 unsigned P = fieldFromInstruction(Insn, 24, 1); 1378 unsigned W = fieldFromInstruction(Insn, 21, 1); 1379 1380 // On stores, the writeback operand precedes Rt. 1381 switch (Inst.getOpcode()) { 1382 case ARM::STR_POST_IMM: 1383 case ARM::STR_POST_REG: 1384 case ARM::STRB_POST_IMM: 1385 case ARM::STRB_POST_REG: 1386 case ARM::STRT_POST_REG: 1387 case ARM::STRT_POST_IMM: 1388 case ARM::STRBT_POST_REG: 1389 case ARM::STRBT_POST_IMM: 1390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1391 return MCDisassembler::Fail; 1392 break; 1393 default: 1394 break; 1395 } 1396 1397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1398 return MCDisassembler::Fail; 1399 1400 // On loads, the writeback operand comes after Rt. 1401 switch (Inst.getOpcode()) { 1402 case ARM::LDR_POST_IMM: 1403 case ARM::LDR_POST_REG: 1404 case ARM::LDRB_POST_IMM: 1405 case ARM::LDRB_POST_REG: 1406 case ARM::LDRBT_POST_REG: 1407 case ARM::LDRBT_POST_IMM: 1408 case ARM::LDRT_POST_REG: 1409 case ARM::LDRT_POST_IMM: 1410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1411 return MCDisassembler::Fail; 1412 break; 1413 default: 1414 break; 1415 } 1416 1417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1418 return MCDisassembler::Fail; 1419 1420 ARM_AM::AddrOpc Op = ARM_AM::add; 1421 if (!fieldFromInstruction(Insn, 23, 1)) 1422 Op = ARM_AM::sub; 1423 1424 bool writeback = (P == 0) || (W == 1); 1425 unsigned idx_mode = 0; 1426 if (P && writeback) 1427 idx_mode = ARMII::IndexModePre; 1428 else if (!P && writeback) 1429 idx_mode = ARMII::IndexModePost; 1430 1431 if (writeback && (Rn == 15 || Rn == Rt)) 1432 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1433 1434 if (reg) { 1435 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1436 return MCDisassembler::Fail; 1437 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1438 switch( fieldFromInstruction(Insn, 5, 2)) { 1439 case 0: 1440 Opc = ARM_AM::lsl; 1441 break; 1442 case 1: 1443 Opc = ARM_AM::lsr; 1444 break; 1445 case 2: 1446 Opc = ARM_AM::asr; 1447 break; 1448 case 3: 1449 Opc = ARM_AM::ror; 1450 break; 1451 default: 1452 return MCDisassembler::Fail; 1453 } 1454 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1455 if (Opc == ARM_AM::ror && amt == 0) 1456 Opc = ARM_AM::rrx; 1457 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1458 1459 Inst.addOperand(MCOperand::CreateImm(imm)); 1460 } else { 1461 Inst.addOperand(MCOperand::CreateReg(0)); 1462 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1463 Inst.addOperand(MCOperand::CreateImm(tmp)); 1464 } 1465 1466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1467 return MCDisassembler::Fail; 1468 1469 return S; 1470 } 1471 1472 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1473 uint64_t Address, const void *Decoder) { 1474 DecodeStatus S = MCDisassembler::Success; 1475 1476 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1477 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1478 unsigned type = fieldFromInstruction(Val, 5, 2); 1479 unsigned imm = fieldFromInstruction(Val, 7, 5); 1480 unsigned U = fieldFromInstruction(Val, 12, 1); 1481 1482 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1483 switch (type) { 1484 case 0: 1485 ShOp = ARM_AM::lsl; 1486 break; 1487 case 1: 1488 ShOp = ARM_AM::lsr; 1489 break; 1490 case 2: 1491 ShOp = ARM_AM::asr; 1492 break; 1493 case 3: 1494 ShOp = ARM_AM::ror; 1495 break; 1496 } 1497 1498 if (ShOp == ARM_AM::ror && imm == 0) 1499 ShOp = ARM_AM::rrx; 1500 1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 unsigned shift; 1506 if (U) 1507 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1508 else 1509 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1510 Inst.addOperand(MCOperand::CreateImm(shift)); 1511 1512 return S; 1513 } 1514 1515 static DecodeStatus 1516 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1517 uint64_t Address, const void *Decoder) { 1518 DecodeStatus S = MCDisassembler::Success; 1519 1520 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1521 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1522 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1523 unsigned type = fieldFromInstruction(Insn, 22, 1); 1524 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1525 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1526 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1527 unsigned W = fieldFromInstruction(Insn, 21, 1); 1528 unsigned P = fieldFromInstruction(Insn, 24, 1); 1529 unsigned Rt2 = Rt + 1; 1530 1531 bool writeback = (W == 1) | (P == 0); 1532 1533 // For {LD,ST}RD, Rt must be even, else undefined. 1534 switch (Inst.getOpcode()) { 1535 case ARM::STRD: 1536 case ARM::STRD_PRE: 1537 case ARM::STRD_POST: 1538 case ARM::LDRD: 1539 case ARM::LDRD_PRE: 1540 case ARM::LDRD_POST: 1541 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1542 break; 1543 default: 1544 break; 1545 } 1546 switch (Inst.getOpcode()) { 1547 case ARM::STRD: 1548 case ARM::STRD_PRE: 1549 case ARM::STRD_POST: 1550 if (P == 0 && W == 1) 1551 S = MCDisassembler::SoftFail; 1552 1553 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1554 S = MCDisassembler::SoftFail; 1555 if (type && Rm == 15) 1556 S = MCDisassembler::SoftFail; 1557 if (Rt2 == 15) 1558 S = MCDisassembler::SoftFail; 1559 if (!type && fieldFromInstruction(Insn, 8, 4)) 1560 S = MCDisassembler::SoftFail; 1561 break; 1562 case ARM::STRH: 1563 case ARM::STRH_PRE: 1564 case ARM::STRH_POST: 1565 if (Rt == 15) 1566 S = MCDisassembler::SoftFail; 1567 if (writeback && (Rn == 15 || Rn == Rt)) 1568 S = MCDisassembler::SoftFail; 1569 if (!type && Rm == 15) 1570 S = MCDisassembler::SoftFail; 1571 break; 1572 case ARM::LDRD: 1573 case ARM::LDRD_PRE: 1574 case ARM::LDRD_POST: 1575 if (type && Rn == 15){ 1576 if (Rt2 == 15) 1577 S = MCDisassembler::SoftFail; 1578 break; 1579 } 1580 if (P == 0 && W == 1) 1581 S = MCDisassembler::SoftFail; 1582 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1583 S = MCDisassembler::SoftFail; 1584 if (!type && writeback && Rn == 15) 1585 S = MCDisassembler::SoftFail; 1586 if (writeback && (Rn == Rt || Rn == Rt2)) 1587 S = MCDisassembler::SoftFail; 1588 break; 1589 case ARM::LDRH: 1590 case ARM::LDRH_PRE: 1591 case ARM::LDRH_POST: 1592 if (type && Rn == 15){ 1593 if (Rt == 15) 1594 S = MCDisassembler::SoftFail; 1595 break; 1596 } 1597 if (Rt == 15) 1598 S = MCDisassembler::SoftFail; 1599 if (!type && Rm == 15) 1600 S = MCDisassembler::SoftFail; 1601 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1602 S = MCDisassembler::SoftFail; 1603 break; 1604 case ARM::LDRSH: 1605 case ARM::LDRSH_PRE: 1606 case ARM::LDRSH_POST: 1607 case ARM::LDRSB: 1608 case ARM::LDRSB_PRE: 1609 case ARM::LDRSB_POST: 1610 if (type && Rn == 15){ 1611 if (Rt == 15) 1612 S = MCDisassembler::SoftFail; 1613 break; 1614 } 1615 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1616 S = MCDisassembler::SoftFail; 1617 if (!type && (Rt == 15 || Rm == 15)) 1618 S = MCDisassembler::SoftFail; 1619 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1620 S = MCDisassembler::SoftFail; 1621 break; 1622 default: 1623 break; 1624 } 1625 1626 if (writeback) { // Writeback 1627 if (P) 1628 U |= ARMII::IndexModePre << 9; 1629 else 1630 U |= ARMII::IndexModePost << 9; 1631 1632 // On stores, the writeback operand precedes Rt. 1633 switch (Inst.getOpcode()) { 1634 case ARM::STRD: 1635 case ARM::STRD_PRE: 1636 case ARM::STRD_POST: 1637 case ARM::STRH: 1638 case ARM::STRH_PRE: 1639 case ARM::STRH_POST: 1640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1641 return MCDisassembler::Fail; 1642 break; 1643 default: 1644 break; 1645 } 1646 } 1647 1648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1649 return MCDisassembler::Fail; 1650 switch (Inst.getOpcode()) { 1651 case ARM::STRD: 1652 case ARM::STRD_PRE: 1653 case ARM::STRD_POST: 1654 case ARM::LDRD: 1655 case ARM::LDRD_PRE: 1656 case ARM::LDRD_POST: 1657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1658 return MCDisassembler::Fail; 1659 break; 1660 default: 1661 break; 1662 } 1663 1664 if (writeback) { 1665 // On loads, the writeback operand comes after Rt. 1666 switch (Inst.getOpcode()) { 1667 case ARM::LDRD: 1668 case ARM::LDRD_PRE: 1669 case ARM::LDRD_POST: 1670 case ARM::LDRH: 1671 case ARM::LDRH_PRE: 1672 case ARM::LDRH_POST: 1673 case ARM::LDRSH: 1674 case ARM::LDRSH_PRE: 1675 case ARM::LDRSH_POST: 1676 case ARM::LDRSB: 1677 case ARM::LDRSB_PRE: 1678 case ARM::LDRSB_POST: 1679 case ARM::LDRHTr: 1680 case ARM::LDRSBTr: 1681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1682 return MCDisassembler::Fail; 1683 break; 1684 default: 1685 break; 1686 } 1687 } 1688 1689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1690 return MCDisassembler::Fail; 1691 1692 if (type) { 1693 Inst.addOperand(MCOperand::CreateReg(0)); 1694 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1695 } else { 1696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1697 return MCDisassembler::Fail; 1698 Inst.addOperand(MCOperand::CreateImm(U)); 1699 } 1700 1701 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1702 return MCDisassembler::Fail; 1703 1704 return S; 1705 } 1706 1707 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1708 uint64_t Address, const void *Decoder) { 1709 DecodeStatus S = MCDisassembler::Success; 1710 1711 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1712 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1713 1714 switch (mode) { 1715 case 0: 1716 mode = ARM_AM::da; 1717 break; 1718 case 1: 1719 mode = ARM_AM::ia; 1720 break; 1721 case 2: 1722 mode = ARM_AM::db; 1723 break; 1724 case 3: 1725 mode = ARM_AM::ib; 1726 break; 1727 } 1728 1729 Inst.addOperand(MCOperand::CreateImm(mode)); 1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1731 return MCDisassembler::Fail; 1732 1733 return S; 1734 } 1735 1736 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1737 unsigned Insn, 1738 uint64_t Address, const void *Decoder) { 1739 DecodeStatus S = MCDisassembler::Success; 1740 1741 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1742 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1743 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1744 1745 if (pred == 0xF) { 1746 switch (Inst.getOpcode()) { 1747 case ARM::LDMDA: 1748 Inst.setOpcode(ARM::RFEDA); 1749 break; 1750 case ARM::LDMDA_UPD: 1751 Inst.setOpcode(ARM::RFEDA_UPD); 1752 break; 1753 case ARM::LDMDB: 1754 Inst.setOpcode(ARM::RFEDB); 1755 break; 1756 case ARM::LDMDB_UPD: 1757 Inst.setOpcode(ARM::RFEDB_UPD); 1758 break; 1759 case ARM::LDMIA: 1760 Inst.setOpcode(ARM::RFEIA); 1761 break; 1762 case ARM::LDMIA_UPD: 1763 Inst.setOpcode(ARM::RFEIA_UPD); 1764 break; 1765 case ARM::LDMIB: 1766 Inst.setOpcode(ARM::RFEIB); 1767 break; 1768 case ARM::LDMIB_UPD: 1769 Inst.setOpcode(ARM::RFEIB_UPD); 1770 break; 1771 case ARM::STMDA: 1772 Inst.setOpcode(ARM::SRSDA); 1773 break; 1774 case ARM::STMDA_UPD: 1775 Inst.setOpcode(ARM::SRSDA_UPD); 1776 break; 1777 case ARM::STMDB: 1778 Inst.setOpcode(ARM::SRSDB); 1779 break; 1780 case ARM::STMDB_UPD: 1781 Inst.setOpcode(ARM::SRSDB_UPD); 1782 break; 1783 case ARM::STMIA: 1784 Inst.setOpcode(ARM::SRSIA); 1785 break; 1786 case ARM::STMIA_UPD: 1787 Inst.setOpcode(ARM::SRSIA_UPD); 1788 break; 1789 case ARM::STMIB: 1790 Inst.setOpcode(ARM::SRSIB); 1791 break; 1792 case ARM::STMIB_UPD: 1793 Inst.setOpcode(ARM::SRSIB_UPD); 1794 break; 1795 default: 1796 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1797 } 1798 1799 // For stores (which become SRS's, the only operand is the mode. 1800 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1801 Inst.addOperand( 1802 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1803 return S; 1804 } 1805 1806 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1807 } 1808 1809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1810 return MCDisassembler::Fail; 1811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1812 return MCDisassembler::Fail; // Tied 1813 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1814 return MCDisassembler::Fail; 1815 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1816 return MCDisassembler::Fail; 1817 1818 return S; 1819 } 1820 1821 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1822 uint64_t Address, const void *Decoder) { 1823 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1824 unsigned M = fieldFromInstruction(Insn, 17, 1); 1825 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1826 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1827 1828 DecodeStatus S = MCDisassembler::Success; 1829 1830 // imod == '01' --> UNPREDICTABLE 1831 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1832 // return failure here. The '01' imod value is unprintable, so there's 1833 // nothing useful we could do even if we returned UNPREDICTABLE. 1834 1835 if (imod == 1) return MCDisassembler::Fail; 1836 1837 if (imod && M) { 1838 Inst.setOpcode(ARM::CPS3p); 1839 Inst.addOperand(MCOperand::CreateImm(imod)); 1840 Inst.addOperand(MCOperand::CreateImm(iflags)); 1841 Inst.addOperand(MCOperand::CreateImm(mode)); 1842 } else if (imod && !M) { 1843 Inst.setOpcode(ARM::CPS2p); 1844 Inst.addOperand(MCOperand::CreateImm(imod)); 1845 Inst.addOperand(MCOperand::CreateImm(iflags)); 1846 if (mode) S = MCDisassembler::SoftFail; 1847 } else if (!imod && M) { 1848 Inst.setOpcode(ARM::CPS1p); 1849 Inst.addOperand(MCOperand::CreateImm(mode)); 1850 if (iflags) S = MCDisassembler::SoftFail; 1851 } else { 1852 // imod == '00' && M == '0' --> UNPREDICTABLE 1853 Inst.setOpcode(ARM::CPS1p); 1854 Inst.addOperand(MCOperand::CreateImm(mode)); 1855 S = MCDisassembler::SoftFail; 1856 } 1857 1858 return S; 1859 } 1860 1861 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1862 uint64_t Address, const void *Decoder) { 1863 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1864 unsigned M = fieldFromInstruction(Insn, 8, 1); 1865 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1866 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1867 1868 DecodeStatus S = MCDisassembler::Success; 1869 1870 // imod == '01' --> UNPREDICTABLE 1871 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1872 // return failure here. The '01' imod value is unprintable, so there's 1873 // nothing useful we could do even if we returned UNPREDICTABLE. 1874 1875 if (imod == 1) return MCDisassembler::Fail; 1876 1877 if (imod && M) { 1878 Inst.setOpcode(ARM::t2CPS3p); 1879 Inst.addOperand(MCOperand::CreateImm(imod)); 1880 Inst.addOperand(MCOperand::CreateImm(iflags)); 1881 Inst.addOperand(MCOperand::CreateImm(mode)); 1882 } else if (imod && !M) { 1883 Inst.setOpcode(ARM::t2CPS2p); 1884 Inst.addOperand(MCOperand::CreateImm(imod)); 1885 Inst.addOperand(MCOperand::CreateImm(iflags)); 1886 if (mode) S = MCDisassembler::SoftFail; 1887 } else if (!imod && M) { 1888 Inst.setOpcode(ARM::t2CPS1p); 1889 Inst.addOperand(MCOperand::CreateImm(mode)); 1890 if (iflags) S = MCDisassembler::SoftFail; 1891 } else { 1892 // imod == '00' && M == '0' --> this is a HINT instruction 1893 int imm = fieldFromInstruction(Insn, 0, 8); 1894 // HINT are defined only for immediate in [0..4] 1895 if(imm > 4) return MCDisassembler::Fail; 1896 Inst.setOpcode(ARM::t2HINT); 1897 Inst.addOperand(MCOperand::CreateImm(imm)); 1898 } 1899 1900 return S; 1901 } 1902 1903 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1908 unsigned imm = 0; 1909 1910 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1911 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1912 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1913 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1914 1915 if (Inst.getOpcode() == ARM::t2MOVTi16) 1916 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1917 return MCDisassembler::Fail; 1918 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1919 return MCDisassembler::Fail; 1920 1921 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1922 Inst.addOperand(MCOperand::CreateImm(imm)); 1923 1924 return S; 1925 } 1926 1927 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1928 uint64_t Address, const void *Decoder) { 1929 DecodeStatus S = MCDisassembler::Success; 1930 1931 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1932 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1933 unsigned imm = 0; 1934 1935 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 1936 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1937 1938 if (Inst.getOpcode() == ARM::MOVTi16) 1939 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1940 return MCDisassembler::Fail; 1941 1942 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1943 return MCDisassembler::Fail; 1944 1945 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1946 Inst.addOperand(MCOperand::CreateImm(imm)); 1947 1948 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 return S; 1952 } 1953 1954 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1955 uint64_t Address, const void *Decoder) { 1956 DecodeStatus S = MCDisassembler::Success; 1957 1958 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 1959 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 1960 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 1961 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 1962 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1963 1964 if (pred == 0xF) 1965 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1966 1967 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1970 return MCDisassembler::Fail; 1971 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1972 return MCDisassembler::Fail; 1973 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 1976 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1977 return MCDisassembler::Fail; 1978 1979 return S; 1980 } 1981 1982 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 1983 uint64_t Address, const void *Decoder) { 1984 DecodeStatus S = MCDisassembler::Success; 1985 1986 unsigned add = fieldFromInstruction(Val, 12, 1); 1987 unsigned imm = fieldFromInstruction(Val, 0, 12); 1988 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1989 1990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1991 return MCDisassembler::Fail; 1992 1993 if (!add) imm *= -1; 1994 if (imm == 0 && !add) imm = INT32_MIN; 1995 Inst.addOperand(MCOperand::CreateImm(imm)); 1996 if (Rn == 15) 1997 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1998 1999 return S; 2000 } 2001 2002 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2003 uint64_t Address, const void *Decoder) { 2004 DecodeStatus S = MCDisassembler::Success; 2005 2006 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2007 unsigned U = fieldFromInstruction(Val, 8, 1); 2008 unsigned imm = fieldFromInstruction(Val, 0, 8); 2009 2010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2011 return MCDisassembler::Fail; 2012 2013 if (U) 2014 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2015 else 2016 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2017 2018 return S; 2019 } 2020 2021 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2022 uint64_t Address, const void *Decoder) { 2023 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2024 } 2025 2026 static DecodeStatus 2027 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2028 uint64_t Address, const void *Decoder) { 2029 DecodeStatus Status = MCDisassembler::Success; 2030 2031 // Note the J1 and J2 values are from the encoded instruction. So here 2032 // change them to I1 and I2 values via as documented: 2033 // I1 = NOT(J1 EOR S); 2034 // I2 = NOT(J2 EOR S); 2035 // and build the imm32 with one trailing zero as documented: 2036 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2037 unsigned S = fieldFromInstruction(Insn, 26, 1); 2038 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2039 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2040 unsigned I1 = !(J1 ^ S); 2041 unsigned I2 = !(J2 ^ S); 2042 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2043 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2044 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2045 int imm32 = SignExtend32<24>(tmp << 1); 2046 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2047 true, 4, Inst, Decoder)) 2048 Inst.addOperand(MCOperand::CreateImm(imm32)); 2049 2050 return Status; 2051 } 2052 2053 static DecodeStatus 2054 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2055 uint64_t Address, const void *Decoder) { 2056 DecodeStatus S = MCDisassembler::Success; 2057 2058 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2059 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2060 2061 if (pred == 0xF) { 2062 Inst.setOpcode(ARM::BLXi); 2063 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2064 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2065 true, 4, Inst, Decoder)) 2066 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2067 return S; 2068 } 2069 2070 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2071 true, 4, Inst, Decoder)) 2072 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2073 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2074 return MCDisassembler::Fail; 2075 2076 return S; 2077 } 2078 2079 2080 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2081 uint64_t Address, const void *Decoder) { 2082 DecodeStatus S = MCDisassembler::Success; 2083 2084 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2085 unsigned align = fieldFromInstruction(Val, 4, 2); 2086 2087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 if (!align) 2090 Inst.addOperand(MCOperand::CreateImm(0)); 2091 else 2092 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2093 2094 return S; 2095 } 2096 2097 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2098 uint64_t Address, const void *Decoder) { 2099 DecodeStatus S = MCDisassembler::Success; 2100 2101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2102 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2103 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2104 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2105 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2106 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2107 2108 // First output register 2109 switch (Inst.getOpcode()) { 2110 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2111 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2112 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2113 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2114 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2115 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2116 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2117 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2118 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2119 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 break; 2122 case ARM::VLD2b16: 2123 case ARM::VLD2b32: 2124 case ARM::VLD2b8: 2125 case ARM::VLD2b16wb_fixed: 2126 case ARM::VLD2b16wb_register: 2127 case ARM::VLD2b32wb_fixed: 2128 case ARM::VLD2b32wb_register: 2129 case ARM::VLD2b8wb_fixed: 2130 case ARM::VLD2b8wb_register: 2131 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 break; 2134 default: 2135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 } 2138 2139 // Second output register 2140 switch (Inst.getOpcode()) { 2141 case ARM::VLD3d8: 2142 case ARM::VLD3d16: 2143 case ARM::VLD3d32: 2144 case ARM::VLD3d8_UPD: 2145 case ARM::VLD3d16_UPD: 2146 case ARM::VLD3d32_UPD: 2147 case ARM::VLD4d8: 2148 case ARM::VLD4d16: 2149 case ARM::VLD4d32: 2150 case ARM::VLD4d8_UPD: 2151 case ARM::VLD4d16_UPD: 2152 case ARM::VLD4d32_UPD: 2153 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2154 return MCDisassembler::Fail; 2155 break; 2156 case ARM::VLD3q8: 2157 case ARM::VLD3q16: 2158 case ARM::VLD3q32: 2159 case ARM::VLD3q8_UPD: 2160 case ARM::VLD3q16_UPD: 2161 case ARM::VLD3q32_UPD: 2162 case ARM::VLD4q8: 2163 case ARM::VLD4q16: 2164 case ARM::VLD4q32: 2165 case ARM::VLD4q8_UPD: 2166 case ARM::VLD4q16_UPD: 2167 case ARM::VLD4q32_UPD: 2168 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2169 return MCDisassembler::Fail; 2170 default: 2171 break; 2172 } 2173 2174 // Third output register 2175 switch(Inst.getOpcode()) { 2176 case ARM::VLD3d8: 2177 case ARM::VLD3d16: 2178 case ARM::VLD3d32: 2179 case ARM::VLD3d8_UPD: 2180 case ARM::VLD3d16_UPD: 2181 case ARM::VLD3d32_UPD: 2182 case ARM::VLD4d8: 2183 case ARM::VLD4d16: 2184 case ARM::VLD4d32: 2185 case ARM::VLD4d8_UPD: 2186 case ARM::VLD4d16_UPD: 2187 case ARM::VLD4d32_UPD: 2188 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2189 return MCDisassembler::Fail; 2190 break; 2191 case ARM::VLD3q8: 2192 case ARM::VLD3q16: 2193 case ARM::VLD3q32: 2194 case ARM::VLD3q8_UPD: 2195 case ARM::VLD3q16_UPD: 2196 case ARM::VLD3q32_UPD: 2197 case ARM::VLD4q8: 2198 case ARM::VLD4q16: 2199 case ARM::VLD4q32: 2200 case ARM::VLD4q8_UPD: 2201 case ARM::VLD4q16_UPD: 2202 case ARM::VLD4q32_UPD: 2203 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2204 return MCDisassembler::Fail; 2205 break; 2206 default: 2207 break; 2208 } 2209 2210 // Fourth output register 2211 switch (Inst.getOpcode()) { 2212 case ARM::VLD4d8: 2213 case ARM::VLD4d16: 2214 case ARM::VLD4d32: 2215 case ARM::VLD4d8_UPD: 2216 case ARM::VLD4d16_UPD: 2217 case ARM::VLD4d32_UPD: 2218 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2219 return MCDisassembler::Fail; 2220 break; 2221 case ARM::VLD4q8: 2222 case ARM::VLD4q16: 2223 case ARM::VLD4q32: 2224 case ARM::VLD4q8_UPD: 2225 case ARM::VLD4q16_UPD: 2226 case ARM::VLD4q32_UPD: 2227 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 break; 2230 default: 2231 break; 2232 } 2233 2234 // Writeback operand 2235 switch (Inst.getOpcode()) { 2236 case ARM::VLD1d8wb_fixed: 2237 case ARM::VLD1d16wb_fixed: 2238 case ARM::VLD1d32wb_fixed: 2239 case ARM::VLD1d64wb_fixed: 2240 case ARM::VLD1d8wb_register: 2241 case ARM::VLD1d16wb_register: 2242 case ARM::VLD1d32wb_register: 2243 case ARM::VLD1d64wb_register: 2244 case ARM::VLD1q8wb_fixed: 2245 case ARM::VLD1q16wb_fixed: 2246 case ARM::VLD1q32wb_fixed: 2247 case ARM::VLD1q64wb_fixed: 2248 case ARM::VLD1q8wb_register: 2249 case ARM::VLD1q16wb_register: 2250 case ARM::VLD1q32wb_register: 2251 case ARM::VLD1q64wb_register: 2252 case ARM::VLD1d8Twb_fixed: 2253 case ARM::VLD1d8Twb_register: 2254 case ARM::VLD1d16Twb_fixed: 2255 case ARM::VLD1d16Twb_register: 2256 case ARM::VLD1d32Twb_fixed: 2257 case ARM::VLD1d32Twb_register: 2258 case ARM::VLD1d64Twb_fixed: 2259 case ARM::VLD1d64Twb_register: 2260 case ARM::VLD1d8Qwb_fixed: 2261 case ARM::VLD1d8Qwb_register: 2262 case ARM::VLD1d16Qwb_fixed: 2263 case ARM::VLD1d16Qwb_register: 2264 case ARM::VLD1d32Qwb_fixed: 2265 case ARM::VLD1d32Qwb_register: 2266 case ARM::VLD1d64Qwb_fixed: 2267 case ARM::VLD1d64Qwb_register: 2268 case ARM::VLD2d8wb_fixed: 2269 case ARM::VLD2d16wb_fixed: 2270 case ARM::VLD2d32wb_fixed: 2271 case ARM::VLD2q8wb_fixed: 2272 case ARM::VLD2q16wb_fixed: 2273 case ARM::VLD2q32wb_fixed: 2274 case ARM::VLD2d8wb_register: 2275 case ARM::VLD2d16wb_register: 2276 case ARM::VLD2d32wb_register: 2277 case ARM::VLD2q8wb_register: 2278 case ARM::VLD2q16wb_register: 2279 case ARM::VLD2q32wb_register: 2280 case ARM::VLD2b8wb_fixed: 2281 case ARM::VLD2b16wb_fixed: 2282 case ARM::VLD2b32wb_fixed: 2283 case ARM::VLD2b8wb_register: 2284 case ARM::VLD2b16wb_register: 2285 case ARM::VLD2b32wb_register: 2286 Inst.addOperand(MCOperand::CreateImm(0)); 2287 break; 2288 case ARM::VLD3d8_UPD: 2289 case ARM::VLD3d16_UPD: 2290 case ARM::VLD3d32_UPD: 2291 case ARM::VLD3q8_UPD: 2292 case ARM::VLD3q16_UPD: 2293 case ARM::VLD3q32_UPD: 2294 case ARM::VLD4d8_UPD: 2295 case ARM::VLD4d16_UPD: 2296 case ARM::VLD4d32_UPD: 2297 case ARM::VLD4q8_UPD: 2298 case ARM::VLD4q16_UPD: 2299 case ARM::VLD4q32_UPD: 2300 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 break; 2303 default: 2304 break; 2305 } 2306 2307 // AddrMode6 Base (register+alignment) 2308 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2309 return MCDisassembler::Fail; 2310 2311 // AddrMode6 Offset (register) 2312 switch (Inst.getOpcode()) { 2313 default: 2314 // The below have been updated to have explicit am6offset split 2315 // between fixed and register offset. For those instructions not 2316 // yet updated, we need to add an additional reg0 operand for the 2317 // fixed variant. 2318 // 2319 // The fixed offset encodes as Rm == 0xd, so we check for that. 2320 if (Rm == 0xd) { 2321 Inst.addOperand(MCOperand::CreateReg(0)); 2322 break; 2323 } 2324 // Fall through to handle the register offset variant. 2325 case ARM::VLD1d8wb_fixed: 2326 case ARM::VLD1d16wb_fixed: 2327 case ARM::VLD1d32wb_fixed: 2328 case ARM::VLD1d64wb_fixed: 2329 case ARM::VLD1d8Twb_fixed: 2330 case ARM::VLD1d16Twb_fixed: 2331 case ARM::VLD1d32Twb_fixed: 2332 case ARM::VLD1d64Twb_fixed: 2333 case ARM::VLD1d8Qwb_fixed: 2334 case ARM::VLD1d16Qwb_fixed: 2335 case ARM::VLD1d32Qwb_fixed: 2336 case ARM::VLD1d64Qwb_fixed: 2337 case ARM::VLD1d8wb_register: 2338 case ARM::VLD1d16wb_register: 2339 case ARM::VLD1d32wb_register: 2340 case ARM::VLD1d64wb_register: 2341 case ARM::VLD1q8wb_fixed: 2342 case ARM::VLD1q16wb_fixed: 2343 case ARM::VLD1q32wb_fixed: 2344 case ARM::VLD1q64wb_fixed: 2345 case ARM::VLD1q8wb_register: 2346 case ARM::VLD1q16wb_register: 2347 case ARM::VLD1q32wb_register: 2348 case ARM::VLD1q64wb_register: 2349 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2350 // variant encodes Rm == 0xf. Anything else is a register offset post- 2351 // increment and we need to add the register operand to the instruction. 2352 if (Rm != 0xD && Rm != 0xF && 2353 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2354 return MCDisassembler::Fail; 2355 break; 2356 case ARM::VLD2d8wb_fixed: 2357 case ARM::VLD2d16wb_fixed: 2358 case ARM::VLD2d32wb_fixed: 2359 case ARM::VLD2b8wb_fixed: 2360 case ARM::VLD2b16wb_fixed: 2361 case ARM::VLD2b32wb_fixed: 2362 case ARM::VLD2q8wb_fixed: 2363 case ARM::VLD2q16wb_fixed: 2364 case ARM::VLD2q32wb_fixed: 2365 break; 2366 } 2367 2368 return S; 2369 } 2370 2371 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn, 2372 uint64_t Addr, const void* Decoder) { 2373 unsigned type = fieldFromInstruction(Insn, 8, 4); 2374 unsigned align = fieldFromInstruction(Insn, 4, 2); 2375 if(type == 7 && (align & 2)) return MCDisassembler::Fail; 2376 if(type == 10 && align == 3) return MCDisassembler::Fail; 2377 if(type == 6 && (align & 2)) return MCDisassembler::Fail; 2378 2379 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2380 } 2381 2382 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn, 2383 uint64_t Addr, const void* Decoder) { 2384 unsigned size = fieldFromInstruction(Insn, 6, 2); 2385 if(size == 3) return MCDisassembler::Fail; 2386 2387 unsigned type = fieldFromInstruction(Insn, 8, 4); 2388 unsigned align = fieldFromInstruction(Insn, 4, 2); 2389 if(type == 8 && align == 3) return MCDisassembler::Fail; 2390 if(type == 9 && align == 3) return MCDisassembler::Fail; 2391 2392 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2393 } 2394 2395 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn, 2396 uint64_t Addr, const void* Decoder) { 2397 unsigned size = fieldFromInstruction(Insn, 6, 2); 2398 if(size == 3) return MCDisassembler::Fail; 2399 2400 unsigned align = fieldFromInstruction(Insn, 4, 2); 2401 if(align & 2) return MCDisassembler::Fail; 2402 2403 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2404 } 2405 2406 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn, 2407 uint64_t Addr, const void* Decoder) { 2408 unsigned size = fieldFromInstruction(Insn, 6, 2); 2409 if(size == 3) return MCDisassembler::Fail; 2410 2411 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2412 } 2413 2414 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2415 uint64_t Address, const void *Decoder) { 2416 DecodeStatus S = MCDisassembler::Success; 2417 2418 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2419 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2420 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2421 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2422 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2423 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2424 2425 // Writeback Operand 2426 switch (Inst.getOpcode()) { 2427 case ARM::VST1d8wb_fixed: 2428 case ARM::VST1d16wb_fixed: 2429 case ARM::VST1d32wb_fixed: 2430 case ARM::VST1d64wb_fixed: 2431 case ARM::VST1d8wb_register: 2432 case ARM::VST1d16wb_register: 2433 case ARM::VST1d32wb_register: 2434 case ARM::VST1d64wb_register: 2435 case ARM::VST1q8wb_fixed: 2436 case ARM::VST1q16wb_fixed: 2437 case ARM::VST1q32wb_fixed: 2438 case ARM::VST1q64wb_fixed: 2439 case ARM::VST1q8wb_register: 2440 case ARM::VST1q16wb_register: 2441 case ARM::VST1q32wb_register: 2442 case ARM::VST1q64wb_register: 2443 case ARM::VST1d8Twb_fixed: 2444 case ARM::VST1d16Twb_fixed: 2445 case ARM::VST1d32Twb_fixed: 2446 case ARM::VST1d64Twb_fixed: 2447 case ARM::VST1d8Twb_register: 2448 case ARM::VST1d16Twb_register: 2449 case ARM::VST1d32Twb_register: 2450 case ARM::VST1d64Twb_register: 2451 case ARM::VST1d8Qwb_fixed: 2452 case ARM::VST1d16Qwb_fixed: 2453 case ARM::VST1d32Qwb_fixed: 2454 case ARM::VST1d64Qwb_fixed: 2455 case ARM::VST1d8Qwb_register: 2456 case ARM::VST1d16Qwb_register: 2457 case ARM::VST1d32Qwb_register: 2458 case ARM::VST1d64Qwb_register: 2459 case ARM::VST2d8wb_fixed: 2460 case ARM::VST2d16wb_fixed: 2461 case ARM::VST2d32wb_fixed: 2462 case ARM::VST2d8wb_register: 2463 case ARM::VST2d16wb_register: 2464 case ARM::VST2d32wb_register: 2465 case ARM::VST2q8wb_fixed: 2466 case ARM::VST2q16wb_fixed: 2467 case ARM::VST2q32wb_fixed: 2468 case ARM::VST2q8wb_register: 2469 case ARM::VST2q16wb_register: 2470 case ARM::VST2q32wb_register: 2471 case ARM::VST2b8wb_fixed: 2472 case ARM::VST2b16wb_fixed: 2473 case ARM::VST2b32wb_fixed: 2474 case ARM::VST2b8wb_register: 2475 case ARM::VST2b16wb_register: 2476 case ARM::VST2b32wb_register: 2477 if (Rm == 0xF) 2478 return MCDisassembler::Fail; 2479 Inst.addOperand(MCOperand::CreateImm(0)); 2480 break; 2481 case ARM::VST3d8_UPD: 2482 case ARM::VST3d16_UPD: 2483 case ARM::VST3d32_UPD: 2484 case ARM::VST3q8_UPD: 2485 case ARM::VST3q16_UPD: 2486 case ARM::VST3q32_UPD: 2487 case ARM::VST4d8_UPD: 2488 case ARM::VST4d16_UPD: 2489 case ARM::VST4d32_UPD: 2490 case ARM::VST4q8_UPD: 2491 case ARM::VST4q16_UPD: 2492 case ARM::VST4q32_UPD: 2493 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2494 return MCDisassembler::Fail; 2495 break; 2496 default: 2497 break; 2498 } 2499 2500 // AddrMode6 Base (register+alignment) 2501 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2502 return MCDisassembler::Fail; 2503 2504 // AddrMode6 Offset (register) 2505 switch (Inst.getOpcode()) { 2506 default: 2507 if (Rm == 0xD) 2508 Inst.addOperand(MCOperand::CreateReg(0)); 2509 else if (Rm != 0xF) { 2510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2511 return MCDisassembler::Fail; 2512 } 2513 break; 2514 case ARM::VST1d8wb_fixed: 2515 case ARM::VST1d16wb_fixed: 2516 case ARM::VST1d32wb_fixed: 2517 case ARM::VST1d64wb_fixed: 2518 case ARM::VST1q8wb_fixed: 2519 case ARM::VST1q16wb_fixed: 2520 case ARM::VST1q32wb_fixed: 2521 case ARM::VST1q64wb_fixed: 2522 case ARM::VST1d8Twb_fixed: 2523 case ARM::VST1d16Twb_fixed: 2524 case ARM::VST1d32Twb_fixed: 2525 case ARM::VST1d64Twb_fixed: 2526 case ARM::VST1d8Qwb_fixed: 2527 case ARM::VST1d16Qwb_fixed: 2528 case ARM::VST1d32Qwb_fixed: 2529 case ARM::VST1d64Qwb_fixed: 2530 case ARM::VST2d8wb_fixed: 2531 case ARM::VST2d16wb_fixed: 2532 case ARM::VST2d32wb_fixed: 2533 case ARM::VST2q8wb_fixed: 2534 case ARM::VST2q16wb_fixed: 2535 case ARM::VST2q32wb_fixed: 2536 case ARM::VST2b8wb_fixed: 2537 case ARM::VST2b16wb_fixed: 2538 case ARM::VST2b32wb_fixed: 2539 break; 2540 } 2541 2542 2543 // First input register 2544 switch (Inst.getOpcode()) { 2545 case ARM::VST1q16: 2546 case ARM::VST1q32: 2547 case ARM::VST1q64: 2548 case ARM::VST1q8: 2549 case ARM::VST1q16wb_fixed: 2550 case ARM::VST1q16wb_register: 2551 case ARM::VST1q32wb_fixed: 2552 case ARM::VST1q32wb_register: 2553 case ARM::VST1q64wb_fixed: 2554 case ARM::VST1q64wb_register: 2555 case ARM::VST1q8wb_fixed: 2556 case ARM::VST1q8wb_register: 2557 case ARM::VST2d16: 2558 case ARM::VST2d32: 2559 case ARM::VST2d8: 2560 case ARM::VST2d16wb_fixed: 2561 case ARM::VST2d16wb_register: 2562 case ARM::VST2d32wb_fixed: 2563 case ARM::VST2d32wb_register: 2564 case ARM::VST2d8wb_fixed: 2565 case ARM::VST2d8wb_register: 2566 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2567 return MCDisassembler::Fail; 2568 break; 2569 case ARM::VST2b16: 2570 case ARM::VST2b32: 2571 case ARM::VST2b8: 2572 case ARM::VST2b16wb_fixed: 2573 case ARM::VST2b16wb_register: 2574 case ARM::VST2b32wb_fixed: 2575 case ARM::VST2b32wb_register: 2576 case ARM::VST2b8wb_fixed: 2577 case ARM::VST2b8wb_register: 2578 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 break; 2581 default: 2582 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2583 return MCDisassembler::Fail; 2584 } 2585 2586 // Second input register 2587 switch (Inst.getOpcode()) { 2588 case ARM::VST3d8: 2589 case ARM::VST3d16: 2590 case ARM::VST3d32: 2591 case ARM::VST3d8_UPD: 2592 case ARM::VST3d16_UPD: 2593 case ARM::VST3d32_UPD: 2594 case ARM::VST4d8: 2595 case ARM::VST4d16: 2596 case ARM::VST4d32: 2597 case ARM::VST4d8_UPD: 2598 case ARM::VST4d16_UPD: 2599 case ARM::VST4d32_UPD: 2600 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2601 return MCDisassembler::Fail; 2602 break; 2603 case ARM::VST3q8: 2604 case ARM::VST3q16: 2605 case ARM::VST3q32: 2606 case ARM::VST3q8_UPD: 2607 case ARM::VST3q16_UPD: 2608 case ARM::VST3q32_UPD: 2609 case ARM::VST4q8: 2610 case ARM::VST4q16: 2611 case ARM::VST4q32: 2612 case ARM::VST4q8_UPD: 2613 case ARM::VST4q16_UPD: 2614 case ARM::VST4q32_UPD: 2615 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2616 return MCDisassembler::Fail; 2617 break; 2618 default: 2619 break; 2620 } 2621 2622 // Third input register 2623 switch (Inst.getOpcode()) { 2624 case ARM::VST3d8: 2625 case ARM::VST3d16: 2626 case ARM::VST3d32: 2627 case ARM::VST3d8_UPD: 2628 case ARM::VST3d16_UPD: 2629 case ARM::VST3d32_UPD: 2630 case ARM::VST4d8: 2631 case ARM::VST4d16: 2632 case ARM::VST4d32: 2633 case ARM::VST4d8_UPD: 2634 case ARM::VST4d16_UPD: 2635 case ARM::VST4d32_UPD: 2636 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2637 return MCDisassembler::Fail; 2638 break; 2639 case ARM::VST3q8: 2640 case ARM::VST3q16: 2641 case ARM::VST3q32: 2642 case ARM::VST3q8_UPD: 2643 case ARM::VST3q16_UPD: 2644 case ARM::VST3q32_UPD: 2645 case ARM::VST4q8: 2646 case ARM::VST4q16: 2647 case ARM::VST4q32: 2648 case ARM::VST4q8_UPD: 2649 case ARM::VST4q16_UPD: 2650 case ARM::VST4q32_UPD: 2651 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2652 return MCDisassembler::Fail; 2653 break; 2654 default: 2655 break; 2656 } 2657 2658 // Fourth input register 2659 switch (Inst.getOpcode()) { 2660 case ARM::VST4d8: 2661 case ARM::VST4d16: 2662 case ARM::VST4d32: 2663 case ARM::VST4d8_UPD: 2664 case ARM::VST4d16_UPD: 2665 case ARM::VST4d32_UPD: 2666 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2667 return MCDisassembler::Fail; 2668 break; 2669 case ARM::VST4q8: 2670 case ARM::VST4q16: 2671 case ARM::VST4q32: 2672 case ARM::VST4q8_UPD: 2673 case ARM::VST4q16_UPD: 2674 case ARM::VST4q32_UPD: 2675 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2676 return MCDisassembler::Fail; 2677 break; 2678 default: 2679 break; 2680 } 2681 2682 return S; 2683 } 2684 2685 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2686 uint64_t Address, const void *Decoder) { 2687 DecodeStatus S = MCDisassembler::Success; 2688 2689 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2690 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2691 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2692 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2693 unsigned align = fieldFromInstruction(Insn, 4, 1); 2694 unsigned size = fieldFromInstruction(Insn, 6, 2); 2695 2696 if (size == 0 && align == 1) 2697 return MCDisassembler::Fail; 2698 align *= (1 << size); 2699 2700 switch (Inst.getOpcode()) { 2701 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2702 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2703 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2704 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2705 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2706 return MCDisassembler::Fail; 2707 break; 2708 default: 2709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2710 return MCDisassembler::Fail; 2711 break; 2712 } 2713 if (Rm != 0xF) { 2714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2715 return MCDisassembler::Fail; 2716 } 2717 2718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 Inst.addOperand(MCOperand::CreateImm(align)); 2721 2722 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2723 // variant encodes Rm == 0xf. Anything else is a register offset post- 2724 // increment and we need to add the register operand to the instruction. 2725 if (Rm != 0xD && Rm != 0xF && 2726 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 2729 return S; 2730 } 2731 2732 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2733 uint64_t Address, const void *Decoder) { 2734 DecodeStatus S = MCDisassembler::Success; 2735 2736 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2737 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2738 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2739 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2740 unsigned align = fieldFromInstruction(Insn, 4, 1); 2741 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2742 align *= 2*size; 2743 2744 switch (Inst.getOpcode()) { 2745 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2746 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2747 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2748 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2749 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2750 return MCDisassembler::Fail; 2751 break; 2752 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2753 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2754 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2755 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2756 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 break; 2759 default: 2760 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 break; 2763 } 2764 2765 if (Rm != 0xF) 2766 Inst.addOperand(MCOperand::CreateImm(0)); 2767 2768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2769 return MCDisassembler::Fail; 2770 Inst.addOperand(MCOperand::CreateImm(align)); 2771 2772 if (Rm != 0xD && Rm != 0xF) { 2773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 } 2776 2777 return S; 2778 } 2779 2780 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2781 uint64_t Address, const void *Decoder) { 2782 DecodeStatus S = MCDisassembler::Success; 2783 2784 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2785 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2786 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2787 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2788 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2789 2790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2791 return MCDisassembler::Fail; 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 if (Rm != 0xF) { 2797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2798 return MCDisassembler::Fail; 2799 } 2800 2801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 Inst.addOperand(MCOperand::CreateImm(0)); 2804 2805 if (Rm == 0xD) 2806 Inst.addOperand(MCOperand::CreateReg(0)); 2807 else if (Rm != 0xF) { 2808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 } 2811 2812 return S; 2813 } 2814 2815 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2816 uint64_t Address, const void *Decoder) { 2817 DecodeStatus S = MCDisassembler::Success; 2818 2819 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2820 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2821 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2822 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2823 unsigned size = fieldFromInstruction(Insn, 6, 2); 2824 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2825 unsigned align = fieldFromInstruction(Insn, 4, 1); 2826 2827 if (size == 0x3) { 2828 if (align == 0) 2829 return MCDisassembler::Fail; 2830 size = 4; 2831 align = 16; 2832 } else { 2833 if (size == 2) { 2834 size = 1 << size; 2835 align *= 8; 2836 } else { 2837 size = 1 << size; 2838 align *= 4*size; 2839 } 2840 } 2841 2842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2843 return MCDisassembler::Fail; 2844 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2845 return MCDisassembler::Fail; 2846 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2849 return MCDisassembler::Fail; 2850 if (Rm != 0xF) { 2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2852 return MCDisassembler::Fail; 2853 } 2854 2855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2856 return MCDisassembler::Fail; 2857 Inst.addOperand(MCOperand::CreateImm(align)); 2858 2859 if (Rm == 0xD) 2860 Inst.addOperand(MCOperand::CreateReg(0)); 2861 else if (Rm != 0xF) { 2862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 } 2865 2866 return S; 2867 } 2868 2869 static DecodeStatus 2870 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2871 uint64_t Address, const void *Decoder) { 2872 DecodeStatus S = MCDisassembler::Success; 2873 2874 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2875 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2876 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2877 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2878 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2879 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2880 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2881 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2882 2883 if (Q) { 2884 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2885 return MCDisassembler::Fail; 2886 } else { 2887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 } 2890 2891 Inst.addOperand(MCOperand::CreateImm(imm)); 2892 2893 switch (Inst.getOpcode()) { 2894 case ARM::VORRiv4i16: 2895 case ARM::VORRiv2i32: 2896 case ARM::VBICiv4i16: 2897 case ARM::VBICiv2i32: 2898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2899 return MCDisassembler::Fail; 2900 break; 2901 case ARM::VORRiv8i16: 2902 case ARM::VORRiv4i32: 2903 case ARM::VBICiv8i16: 2904 case ARM::VBICiv4i32: 2905 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 break; 2908 default: 2909 break; 2910 } 2911 2912 return S; 2913 } 2914 2915 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2916 uint64_t Address, const void *Decoder) { 2917 DecodeStatus S = MCDisassembler::Success; 2918 2919 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2920 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2921 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2922 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2923 unsigned size = fieldFromInstruction(Insn, 18, 2); 2924 2925 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2930 2931 return S; 2932 } 2933 2934 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2935 uint64_t Address, const void *Decoder) { 2936 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2937 return MCDisassembler::Success; 2938 } 2939 2940 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2941 uint64_t Address, const void *Decoder) { 2942 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2943 return MCDisassembler::Success; 2944 } 2945 2946 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2947 uint64_t Address, const void *Decoder) { 2948 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2949 return MCDisassembler::Success; 2950 } 2951 2952 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2953 uint64_t Address, const void *Decoder) { 2954 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2955 return MCDisassembler::Success; 2956 } 2957 2958 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2959 uint64_t Address, const void *Decoder) { 2960 DecodeStatus S = MCDisassembler::Success; 2961 2962 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2963 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2964 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2965 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2966 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2967 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2968 unsigned op = fieldFromInstruction(Insn, 6, 1); 2969 2970 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 if (op) { 2973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2974 return MCDisassembler::Fail; // Writeback 2975 } 2976 2977 switch (Inst.getOpcode()) { 2978 case ARM::VTBL2: 2979 case ARM::VTBX2: 2980 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 break; 2983 default: 2984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2985 return MCDisassembler::Fail; 2986 } 2987 2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2989 return MCDisassembler::Fail; 2990 2991 return S; 2992 } 2993 2994 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2995 uint64_t Address, const void *Decoder) { 2996 DecodeStatus S = MCDisassembler::Success; 2997 2998 unsigned dst = fieldFromInstruction(Insn, 8, 3); 2999 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3000 3001 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 3004 switch(Inst.getOpcode()) { 3005 default: 3006 return MCDisassembler::Fail; 3007 case ARM::tADR: 3008 break; // tADR does not explicitly represent the PC as an operand. 3009 case ARM::tADDrSPi: 3010 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3011 break; 3012 } 3013 3014 Inst.addOperand(MCOperand::CreateImm(imm)); 3015 return S; 3016 } 3017 3018 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3019 uint64_t Address, const void *Decoder) { 3020 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3021 true, 2, Inst, Decoder)) 3022 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3023 return MCDisassembler::Success; 3024 } 3025 3026 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3027 uint64_t Address, const void *Decoder) { 3028 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3029 true, 4, Inst, Decoder)) 3030 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3031 return MCDisassembler::Success; 3032 } 3033 3034 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3035 uint64_t Address, const void *Decoder) { 3036 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3037 true, 2, Inst, Decoder)) 3038 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3039 return MCDisassembler::Success; 3040 } 3041 3042 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3043 uint64_t Address, const void *Decoder) { 3044 DecodeStatus S = MCDisassembler::Success; 3045 3046 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3047 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3048 3049 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3050 return MCDisassembler::Fail; 3051 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3052 return MCDisassembler::Fail; 3053 3054 return S; 3055 } 3056 3057 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3058 uint64_t Address, const void *Decoder) { 3059 DecodeStatus S = MCDisassembler::Success; 3060 3061 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3062 unsigned imm = fieldFromInstruction(Val, 3, 5); 3063 3064 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 Inst.addOperand(MCOperand::CreateImm(imm)); 3067 3068 return S; 3069 } 3070 3071 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3072 uint64_t Address, const void *Decoder) { 3073 unsigned imm = Val << 2; 3074 3075 Inst.addOperand(MCOperand::CreateImm(imm)); 3076 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3077 3078 return MCDisassembler::Success; 3079 } 3080 3081 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3082 uint64_t Address, const void *Decoder) { 3083 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3084 Inst.addOperand(MCOperand::CreateImm(Val)); 3085 3086 return MCDisassembler::Success; 3087 } 3088 3089 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3090 uint64_t Address, const void *Decoder) { 3091 DecodeStatus S = MCDisassembler::Success; 3092 3093 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3094 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3095 unsigned imm = fieldFromInstruction(Val, 0, 2); 3096 3097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3098 return MCDisassembler::Fail; 3099 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3100 return MCDisassembler::Fail; 3101 Inst.addOperand(MCOperand::CreateImm(imm)); 3102 3103 return S; 3104 } 3105 3106 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3107 uint64_t Address, const void *Decoder) { 3108 DecodeStatus S = MCDisassembler::Success; 3109 3110 switch (Inst.getOpcode()) { 3111 case ARM::t2PLDs: 3112 case ARM::t2PLDWs: 3113 case ARM::t2PLIs: 3114 break; 3115 default: { 3116 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3117 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 } 3120 } 3121 3122 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3123 if (Rn == 0xF) { 3124 switch (Inst.getOpcode()) { 3125 case ARM::t2LDRBs: 3126 Inst.setOpcode(ARM::t2LDRBpci); 3127 break; 3128 case ARM::t2LDRHs: 3129 Inst.setOpcode(ARM::t2LDRHpci); 3130 break; 3131 case ARM::t2LDRSHs: 3132 Inst.setOpcode(ARM::t2LDRSHpci); 3133 break; 3134 case ARM::t2LDRSBs: 3135 Inst.setOpcode(ARM::t2LDRSBpci); 3136 break; 3137 case ARM::t2PLDs: 3138 Inst.setOpcode(ARM::t2PLDi12); 3139 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3140 break; 3141 default: 3142 return MCDisassembler::Fail; 3143 } 3144 3145 int imm = fieldFromInstruction(Insn, 0, 12); 3146 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3147 Inst.addOperand(MCOperand::CreateImm(imm)); 3148 3149 return S; 3150 } 3151 3152 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3153 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3154 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3155 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3156 return MCDisassembler::Fail; 3157 3158 return S; 3159 } 3160 3161 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3162 uint64_t Address, const void *Decoder) { 3163 if (Val == 0) 3164 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3165 else { 3166 int imm = Val & 0xFF; 3167 3168 if (!(Val & 0x100)) imm *= -1; 3169 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3170 } 3171 3172 return MCDisassembler::Success; 3173 } 3174 3175 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3176 uint64_t Address, const void *Decoder) { 3177 DecodeStatus S = MCDisassembler::Success; 3178 3179 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3180 unsigned imm = fieldFromInstruction(Val, 0, 9); 3181 3182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3183 return MCDisassembler::Fail; 3184 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 3187 return S; 3188 } 3189 3190 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3191 uint64_t Address, const void *Decoder) { 3192 DecodeStatus S = MCDisassembler::Success; 3193 3194 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3195 unsigned imm = fieldFromInstruction(Val, 0, 8); 3196 3197 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3198 return MCDisassembler::Fail; 3199 3200 Inst.addOperand(MCOperand::CreateImm(imm)); 3201 3202 return S; 3203 } 3204 3205 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3206 uint64_t Address, const void *Decoder) { 3207 int imm = Val & 0xFF; 3208 if (Val == 0) 3209 imm = INT32_MIN; 3210 else if (!(Val & 0x100)) 3211 imm *= -1; 3212 Inst.addOperand(MCOperand::CreateImm(imm)); 3213 3214 return MCDisassembler::Success; 3215 } 3216 3217 3218 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3219 uint64_t Address, const void *Decoder) { 3220 DecodeStatus S = MCDisassembler::Success; 3221 3222 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3223 unsigned imm = fieldFromInstruction(Val, 0, 9); 3224 3225 // Some instructions always use an additive offset. 3226 switch (Inst.getOpcode()) { 3227 case ARM::t2LDRT: 3228 case ARM::t2LDRBT: 3229 case ARM::t2LDRHT: 3230 case ARM::t2LDRSBT: 3231 case ARM::t2LDRSHT: 3232 case ARM::t2STRT: 3233 case ARM::t2STRBT: 3234 case ARM::t2STRHT: 3235 imm |= 0x100; 3236 break; 3237 default: 3238 break; 3239 } 3240 3241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3242 return MCDisassembler::Fail; 3243 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 3246 return S; 3247 } 3248 3249 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3250 uint64_t Address, const void *Decoder) { 3251 DecodeStatus S = MCDisassembler::Success; 3252 3253 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3254 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3255 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3256 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3257 addr |= Rn << 9; 3258 unsigned load = fieldFromInstruction(Insn, 20, 1); 3259 3260 if (!load) { 3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3262 return MCDisassembler::Fail; 3263 } 3264 3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3266 return MCDisassembler::Fail; 3267 3268 if (load) { 3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 } 3272 3273 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3274 return MCDisassembler::Fail; 3275 3276 return S; 3277 } 3278 3279 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3280 uint64_t Address, const void *Decoder) { 3281 DecodeStatus S = MCDisassembler::Success; 3282 3283 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3284 unsigned imm = fieldFromInstruction(Val, 0, 12); 3285 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 Inst.addOperand(MCOperand::CreateImm(imm)); 3289 3290 return S; 3291 } 3292 3293 3294 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3295 uint64_t Address, const void *Decoder) { 3296 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3297 3298 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3299 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3300 Inst.addOperand(MCOperand::CreateImm(imm)); 3301 3302 return MCDisassembler::Success; 3303 } 3304 3305 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3306 uint64_t Address, const void *Decoder) { 3307 DecodeStatus S = MCDisassembler::Success; 3308 3309 if (Inst.getOpcode() == ARM::tADDrSP) { 3310 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3311 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3312 3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3314 return MCDisassembler::Fail; 3315 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3317 return MCDisassembler::Fail; 3318 } else if (Inst.getOpcode() == ARM::tADDspr) { 3319 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3320 3321 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3322 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 } 3326 3327 return S; 3328 } 3329 3330 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3331 uint64_t Address, const void *Decoder) { 3332 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3333 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3334 3335 Inst.addOperand(MCOperand::CreateImm(imod)); 3336 Inst.addOperand(MCOperand::CreateImm(flags)); 3337 3338 return MCDisassembler::Success; 3339 } 3340 3341 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3342 uint64_t Address, const void *Decoder) { 3343 DecodeStatus S = MCDisassembler::Success; 3344 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3345 unsigned add = fieldFromInstruction(Insn, 4, 1); 3346 3347 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3348 return MCDisassembler::Fail; 3349 Inst.addOperand(MCOperand::CreateImm(add)); 3350 3351 return S; 3352 } 3353 3354 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3355 uint64_t Address, const void *Decoder) { 3356 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3357 // Note only one trailing zero not two. Also the J1 and J2 values are from 3358 // the encoded instruction. So here change to I1 and I2 values via: 3359 // I1 = NOT(J1 EOR S); 3360 // I2 = NOT(J2 EOR S); 3361 // and build the imm32 with two trailing zeros as documented: 3362 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3363 unsigned S = (Val >> 23) & 1; 3364 unsigned J1 = (Val >> 22) & 1; 3365 unsigned J2 = (Val >> 21) & 1; 3366 unsigned I1 = !(J1 ^ S); 3367 unsigned I2 = !(J2 ^ S); 3368 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3369 int imm32 = SignExtend32<25>(tmp << 1); 3370 3371 if (!tryAddingSymbolicOperand(Address, 3372 (Address & ~2u) + imm32 + 4, 3373 true, 4, Inst, Decoder)) 3374 Inst.addOperand(MCOperand::CreateImm(imm32)); 3375 return MCDisassembler::Success; 3376 } 3377 3378 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3379 uint64_t Address, const void *Decoder) { 3380 if (Val == 0xA || Val == 0xB) 3381 return MCDisassembler::Fail; 3382 3383 Inst.addOperand(MCOperand::CreateImm(Val)); 3384 return MCDisassembler::Success; 3385 } 3386 3387 static DecodeStatus 3388 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3389 uint64_t Address, const void *Decoder) { 3390 DecodeStatus S = MCDisassembler::Success; 3391 3392 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3393 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3394 3395 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3397 return MCDisassembler::Fail; 3398 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3399 return MCDisassembler::Fail; 3400 return S; 3401 } 3402 3403 static DecodeStatus 3404 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3405 uint64_t Address, const void *Decoder) { 3406 DecodeStatus S = MCDisassembler::Success; 3407 3408 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3409 if (pred == 0xE || pred == 0xF) { 3410 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3411 switch (opc) { 3412 default: 3413 return MCDisassembler::Fail; 3414 case 0xf3bf8f4: 3415 Inst.setOpcode(ARM::t2DSB); 3416 break; 3417 case 0xf3bf8f5: 3418 Inst.setOpcode(ARM::t2DMB); 3419 break; 3420 case 0xf3bf8f6: 3421 Inst.setOpcode(ARM::t2ISB); 3422 break; 3423 } 3424 3425 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3426 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3427 } 3428 3429 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3430 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3431 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3432 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3433 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3434 3435 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 3440 return S; 3441 } 3442 3443 // Decode a shifted immediate operand. These basically consist 3444 // of an 8-bit value, and a 4-bit directive that specifies either 3445 // a splat operation or a rotation. 3446 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3447 uint64_t Address, const void *Decoder) { 3448 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3449 if (ctrl == 0) { 3450 unsigned byte = fieldFromInstruction(Val, 8, 2); 3451 unsigned imm = fieldFromInstruction(Val, 0, 8); 3452 switch (byte) { 3453 case 0: 3454 Inst.addOperand(MCOperand::CreateImm(imm)); 3455 break; 3456 case 1: 3457 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3458 break; 3459 case 2: 3460 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3461 break; 3462 case 3: 3463 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3464 (imm << 8) | imm)); 3465 break; 3466 } 3467 } else { 3468 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3469 unsigned rot = fieldFromInstruction(Val, 7, 5); 3470 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3471 Inst.addOperand(MCOperand::CreateImm(imm)); 3472 } 3473 3474 return MCDisassembler::Success; 3475 } 3476 3477 static DecodeStatus 3478 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3479 uint64_t Address, const void *Decoder){ 3480 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3481 true, 2, Inst, Decoder)) 3482 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3483 return MCDisassembler::Success; 3484 } 3485 3486 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3487 uint64_t Address, const void *Decoder){ 3488 // Val is passed in as S:J1:J2:imm10:imm11 3489 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3490 // the encoded instruction. So here change to I1 and I2 values via: 3491 // I1 = NOT(J1 EOR S); 3492 // I2 = NOT(J2 EOR S); 3493 // and build the imm32 with one trailing zero as documented: 3494 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3495 unsigned S = (Val >> 23) & 1; 3496 unsigned J1 = (Val >> 22) & 1; 3497 unsigned J2 = (Val >> 21) & 1; 3498 unsigned I1 = !(J1 ^ S); 3499 unsigned I2 = !(J2 ^ S); 3500 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3501 int imm32 = SignExtend32<25>(tmp << 1); 3502 3503 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3504 true, 4, Inst, Decoder)) 3505 Inst.addOperand(MCOperand::CreateImm(imm32)); 3506 return MCDisassembler::Success; 3507 } 3508 3509 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3510 uint64_t Address, const void *Decoder) { 3511 if (Val & ~0xf) 3512 return MCDisassembler::Fail; 3513 3514 Inst.addOperand(MCOperand::CreateImm(Val)); 3515 return MCDisassembler::Success; 3516 } 3517 3518 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3519 uint64_t Address, const void *Decoder) { 3520 if (!Val) return MCDisassembler::Fail; 3521 Inst.addOperand(MCOperand::CreateImm(Val)); 3522 return MCDisassembler::Success; 3523 } 3524 3525 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3526 uint64_t Address, const void *Decoder) { 3527 DecodeStatus S = MCDisassembler::Success; 3528 3529 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3530 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3531 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3532 3533 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3534 3535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3536 return MCDisassembler::Fail; 3537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3538 return MCDisassembler::Fail; 3539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3540 return MCDisassembler::Fail; 3541 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 3544 return S; 3545 } 3546 3547 3548 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3549 uint64_t Address, const void *Decoder){ 3550 DecodeStatus S = MCDisassembler::Success; 3551 3552 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3553 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3554 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3555 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3556 3557 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 3560 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3561 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3562 3563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3564 return MCDisassembler::Fail; 3565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 3572 return S; 3573 } 3574 3575 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3576 uint64_t Address, const void *Decoder) { 3577 DecodeStatus S = MCDisassembler::Success; 3578 3579 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3580 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3581 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3582 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3583 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3584 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3585 3586 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3587 3588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3593 return MCDisassembler::Fail; 3594 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 3597 return S; 3598 } 3599 3600 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3601 uint64_t Address, const void *Decoder) { 3602 DecodeStatus S = MCDisassembler::Success; 3603 3604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3605 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3606 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3607 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3608 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3609 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3610 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3611 3612 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3613 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3614 3615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 3624 return S; 3625 } 3626 3627 3628 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3629 uint64_t Address, const void *Decoder) { 3630 DecodeStatus S = MCDisassembler::Success; 3631 3632 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3633 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3634 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3635 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3636 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3637 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3638 3639 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3640 3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3644 return MCDisassembler::Fail; 3645 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 3650 return S; 3651 } 3652 3653 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3654 uint64_t Address, const void *Decoder) { 3655 DecodeStatus S = MCDisassembler::Success; 3656 3657 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3658 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3659 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3660 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3661 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3662 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3663 3664 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3665 3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3667 return MCDisassembler::Fail; 3668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3671 return MCDisassembler::Fail; 3672 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 3675 return S; 3676 } 3677 3678 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3679 uint64_t Address, const void *Decoder) { 3680 DecodeStatus S = MCDisassembler::Success; 3681 3682 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3683 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3684 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3685 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3686 unsigned size = fieldFromInstruction(Insn, 10, 2); 3687 3688 unsigned align = 0; 3689 unsigned index = 0; 3690 switch (size) { 3691 default: 3692 return MCDisassembler::Fail; 3693 case 0: 3694 if (fieldFromInstruction(Insn, 4, 1)) 3695 return MCDisassembler::Fail; // UNDEFINED 3696 index = fieldFromInstruction(Insn, 5, 3); 3697 break; 3698 case 1: 3699 if (fieldFromInstruction(Insn, 5, 1)) 3700 return MCDisassembler::Fail; // UNDEFINED 3701 index = fieldFromInstruction(Insn, 6, 2); 3702 if (fieldFromInstruction(Insn, 4, 1)) 3703 align = 2; 3704 break; 3705 case 2: 3706 if (fieldFromInstruction(Insn, 6, 1)) 3707 return MCDisassembler::Fail; // UNDEFINED 3708 index = fieldFromInstruction(Insn, 7, 1); 3709 3710 switch (fieldFromInstruction(Insn, 4, 2)) { 3711 case 0 : 3712 align = 0; break; 3713 case 3: 3714 align = 4; break; 3715 default: 3716 return MCDisassembler::Fail; 3717 } 3718 break; 3719 } 3720 3721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 if (Rm != 0xF) { // Writeback 3724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3725 return MCDisassembler::Fail; 3726 } 3727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 Inst.addOperand(MCOperand::CreateImm(align)); 3730 if (Rm != 0xF) { 3731 if (Rm != 0xD) { 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 } else 3735 Inst.addOperand(MCOperand::CreateReg(0)); 3736 } 3737 3738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 Inst.addOperand(MCOperand::CreateImm(index)); 3741 3742 return S; 3743 } 3744 3745 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3746 uint64_t Address, const void *Decoder) { 3747 DecodeStatus S = MCDisassembler::Success; 3748 3749 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3750 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3752 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3753 unsigned size = fieldFromInstruction(Insn, 10, 2); 3754 3755 unsigned align = 0; 3756 unsigned index = 0; 3757 switch (size) { 3758 default: 3759 return MCDisassembler::Fail; 3760 case 0: 3761 if (fieldFromInstruction(Insn, 4, 1)) 3762 return MCDisassembler::Fail; // UNDEFINED 3763 index = fieldFromInstruction(Insn, 5, 3); 3764 break; 3765 case 1: 3766 if (fieldFromInstruction(Insn, 5, 1)) 3767 return MCDisassembler::Fail; // UNDEFINED 3768 index = fieldFromInstruction(Insn, 6, 2); 3769 if (fieldFromInstruction(Insn, 4, 1)) 3770 align = 2; 3771 break; 3772 case 2: 3773 if (fieldFromInstruction(Insn, 6, 1)) 3774 return MCDisassembler::Fail; // UNDEFINED 3775 index = fieldFromInstruction(Insn, 7, 1); 3776 3777 switch (fieldFromInstruction(Insn, 4, 2)) { 3778 case 0: 3779 align = 0; break; 3780 case 3: 3781 align = 4; break; 3782 default: 3783 return MCDisassembler::Fail; 3784 } 3785 break; 3786 } 3787 3788 if (Rm != 0xF) { // Writeback 3789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3790 return MCDisassembler::Fail; 3791 } 3792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3793 return MCDisassembler::Fail; 3794 Inst.addOperand(MCOperand::CreateImm(align)); 3795 if (Rm != 0xF) { 3796 if (Rm != 0xD) { 3797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3798 return MCDisassembler::Fail; 3799 } else 3800 Inst.addOperand(MCOperand::CreateReg(0)); 3801 } 3802 3803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3804 return MCDisassembler::Fail; 3805 Inst.addOperand(MCOperand::CreateImm(index)); 3806 3807 return S; 3808 } 3809 3810 3811 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3812 uint64_t Address, const void *Decoder) { 3813 DecodeStatus S = MCDisassembler::Success; 3814 3815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3816 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3817 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3818 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3819 unsigned size = fieldFromInstruction(Insn, 10, 2); 3820 3821 unsigned align = 0; 3822 unsigned index = 0; 3823 unsigned inc = 1; 3824 switch (size) { 3825 default: 3826 return MCDisassembler::Fail; 3827 case 0: 3828 index = fieldFromInstruction(Insn, 5, 3); 3829 if (fieldFromInstruction(Insn, 4, 1)) 3830 align = 2; 3831 break; 3832 case 1: 3833 index = fieldFromInstruction(Insn, 6, 2); 3834 if (fieldFromInstruction(Insn, 4, 1)) 3835 align = 4; 3836 if (fieldFromInstruction(Insn, 5, 1)) 3837 inc = 2; 3838 break; 3839 case 2: 3840 if (fieldFromInstruction(Insn, 5, 1)) 3841 return MCDisassembler::Fail; // UNDEFINED 3842 index = fieldFromInstruction(Insn, 7, 1); 3843 if (fieldFromInstruction(Insn, 4, 1) != 0) 3844 align = 8; 3845 if (fieldFromInstruction(Insn, 6, 1)) 3846 inc = 2; 3847 break; 3848 } 3849 3850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3851 return MCDisassembler::Fail; 3852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3853 return MCDisassembler::Fail; 3854 if (Rm != 0xF) { // Writeback 3855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 } 3858 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 Inst.addOperand(MCOperand::CreateImm(align)); 3861 if (Rm != 0xF) { 3862 if (Rm != 0xD) { 3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 } else 3866 Inst.addOperand(MCOperand::CreateReg(0)); 3867 } 3868 3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 Inst.addOperand(MCOperand::CreateImm(index)); 3874 3875 return S; 3876 } 3877 3878 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3879 uint64_t Address, const void *Decoder) { 3880 DecodeStatus S = MCDisassembler::Success; 3881 3882 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3883 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3886 unsigned size = fieldFromInstruction(Insn, 10, 2); 3887 3888 unsigned align = 0; 3889 unsigned index = 0; 3890 unsigned inc = 1; 3891 switch (size) { 3892 default: 3893 return MCDisassembler::Fail; 3894 case 0: 3895 index = fieldFromInstruction(Insn, 5, 3); 3896 if (fieldFromInstruction(Insn, 4, 1)) 3897 align = 2; 3898 break; 3899 case 1: 3900 index = fieldFromInstruction(Insn, 6, 2); 3901 if (fieldFromInstruction(Insn, 4, 1)) 3902 align = 4; 3903 if (fieldFromInstruction(Insn, 5, 1)) 3904 inc = 2; 3905 break; 3906 case 2: 3907 if (fieldFromInstruction(Insn, 5, 1)) 3908 return MCDisassembler::Fail; // UNDEFINED 3909 index = fieldFromInstruction(Insn, 7, 1); 3910 if (fieldFromInstruction(Insn, 4, 1) != 0) 3911 align = 8; 3912 if (fieldFromInstruction(Insn, 6, 1)) 3913 inc = 2; 3914 break; 3915 } 3916 3917 if (Rm != 0xF) { // Writeback 3918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3919 return MCDisassembler::Fail; 3920 } 3921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 Inst.addOperand(MCOperand::CreateImm(align)); 3924 if (Rm != 0xF) { 3925 if (Rm != 0xD) { 3926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3927 return MCDisassembler::Fail; 3928 } else 3929 Inst.addOperand(MCOperand::CreateReg(0)); 3930 } 3931 3932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3933 return MCDisassembler::Fail; 3934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3935 return MCDisassembler::Fail; 3936 Inst.addOperand(MCOperand::CreateImm(index)); 3937 3938 return S; 3939 } 3940 3941 3942 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3943 uint64_t Address, const void *Decoder) { 3944 DecodeStatus S = MCDisassembler::Success; 3945 3946 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3947 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3948 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3949 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3950 unsigned size = fieldFromInstruction(Insn, 10, 2); 3951 3952 unsigned align = 0; 3953 unsigned index = 0; 3954 unsigned inc = 1; 3955 switch (size) { 3956 default: 3957 return MCDisassembler::Fail; 3958 case 0: 3959 if (fieldFromInstruction(Insn, 4, 1)) 3960 return MCDisassembler::Fail; // UNDEFINED 3961 index = fieldFromInstruction(Insn, 5, 3); 3962 break; 3963 case 1: 3964 if (fieldFromInstruction(Insn, 4, 1)) 3965 return MCDisassembler::Fail; // UNDEFINED 3966 index = fieldFromInstruction(Insn, 6, 2); 3967 if (fieldFromInstruction(Insn, 5, 1)) 3968 inc = 2; 3969 break; 3970 case 2: 3971 if (fieldFromInstruction(Insn, 4, 2)) 3972 return MCDisassembler::Fail; // UNDEFINED 3973 index = fieldFromInstruction(Insn, 7, 1); 3974 if (fieldFromInstruction(Insn, 6, 1)) 3975 inc = 2; 3976 break; 3977 } 3978 3979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3982 return MCDisassembler::Fail; 3983 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3984 return MCDisassembler::Fail; 3985 3986 if (Rm != 0xF) { // Writeback 3987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3988 return MCDisassembler::Fail; 3989 } 3990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 Inst.addOperand(MCOperand::CreateImm(align)); 3993 if (Rm != 0xF) { 3994 if (Rm != 0xD) { 3995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 } else 3998 Inst.addOperand(MCOperand::CreateReg(0)); 3999 } 4000 4001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4004 return MCDisassembler::Fail; 4005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 Inst.addOperand(MCOperand::CreateImm(index)); 4008 4009 return S; 4010 } 4011 4012 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4013 uint64_t Address, const void *Decoder) { 4014 DecodeStatus S = MCDisassembler::Success; 4015 4016 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4017 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4018 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4019 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4020 unsigned size = fieldFromInstruction(Insn, 10, 2); 4021 4022 unsigned align = 0; 4023 unsigned index = 0; 4024 unsigned inc = 1; 4025 switch (size) { 4026 default: 4027 return MCDisassembler::Fail; 4028 case 0: 4029 if (fieldFromInstruction(Insn, 4, 1)) 4030 return MCDisassembler::Fail; // UNDEFINED 4031 index = fieldFromInstruction(Insn, 5, 3); 4032 break; 4033 case 1: 4034 if (fieldFromInstruction(Insn, 4, 1)) 4035 return MCDisassembler::Fail; // UNDEFINED 4036 index = fieldFromInstruction(Insn, 6, 2); 4037 if (fieldFromInstruction(Insn, 5, 1)) 4038 inc = 2; 4039 break; 4040 case 2: 4041 if (fieldFromInstruction(Insn, 4, 2)) 4042 return MCDisassembler::Fail; // UNDEFINED 4043 index = fieldFromInstruction(Insn, 7, 1); 4044 if (fieldFromInstruction(Insn, 6, 1)) 4045 inc = 2; 4046 break; 4047 } 4048 4049 if (Rm != 0xF) { // Writeback 4050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 } 4053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4054 return MCDisassembler::Fail; 4055 Inst.addOperand(MCOperand::CreateImm(align)); 4056 if (Rm != 0xF) { 4057 if (Rm != 0xD) { 4058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4059 return MCDisassembler::Fail; 4060 } else 4061 Inst.addOperand(MCOperand::CreateReg(0)); 4062 } 4063 4064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4065 return MCDisassembler::Fail; 4066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4067 return MCDisassembler::Fail; 4068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4069 return MCDisassembler::Fail; 4070 Inst.addOperand(MCOperand::CreateImm(index)); 4071 4072 return S; 4073 } 4074 4075 4076 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4077 uint64_t Address, const void *Decoder) { 4078 DecodeStatus S = MCDisassembler::Success; 4079 4080 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4081 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4082 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4083 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4084 unsigned size = fieldFromInstruction(Insn, 10, 2); 4085 4086 unsigned align = 0; 4087 unsigned index = 0; 4088 unsigned inc = 1; 4089 switch (size) { 4090 default: 4091 return MCDisassembler::Fail; 4092 case 0: 4093 if (fieldFromInstruction(Insn, 4, 1)) 4094 align = 4; 4095 index = fieldFromInstruction(Insn, 5, 3); 4096 break; 4097 case 1: 4098 if (fieldFromInstruction(Insn, 4, 1)) 4099 align = 8; 4100 index = fieldFromInstruction(Insn, 6, 2); 4101 if (fieldFromInstruction(Insn, 5, 1)) 4102 inc = 2; 4103 break; 4104 case 2: 4105 switch (fieldFromInstruction(Insn, 4, 2)) { 4106 case 0: 4107 align = 0; break; 4108 case 3: 4109 return MCDisassembler::Fail; 4110 default: 4111 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4112 } 4113 4114 index = fieldFromInstruction(Insn, 7, 1); 4115 if (fieldFromInstruction(Insn, 6, 1)) 4116 inc = 2; 4117 break; 4118 } 4119 4120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4121 return MCDisassembler::Fail; 4122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4123 return MCDisassembler::Fail; 4124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4125 return MCDisassembler::Fail; 4126 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4127 return MCDisassembler::Fail; 4128 4129 if (Rm != 0xF) { // Writeback 4130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4131 return MCDisassembler::Fail; 4132 } 4133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4134 return MCDisassembler::Fail; 4135 Inst.addOperand(MCOperand::CreateImm(align)); 4136 if (Rm != 0xF) { 4137 if (Rm != 0xD) { 4138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4139 return MCDisassembler::Fail; 4140 } else 4141 Inst.addOperand(MCOperand::CreateReg(0)); 4142 } 4143 4144 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4151 return MCDisassembler::Fail; 4152 Inst.addOperand(MCOperand::CreateImm(index)); 4153 4154 return S; 4155 } 4156 4157 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4158 uint64_t Address, const void *Decoder) { 4159 DecodeStatus S = MCDisassembler::Success; 4160 4161 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4162 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4163 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4164 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4165 unsigned size = fieldFromInstruction(Insn, 10, 2); 4166 4167 unsigned align = 0; 4168 unsigned index = 0; 4169 unsigned inc = 1; 4170 switch (size) { 4171 default: 4172 return MCDisassembler::Fail; 4173 case 0: 4174 if (fieldFromInstruction(Insn, 4, 1)) 4175 align = 4; 4176 index = fieldFromInstruction(Insn, 5, 3); 4177 break; 4178 case 1: 4179 if (fieldFromInstruction(Insn, 4, 1)) 4180 align = 8; 4181 index = fieldFromInstruction(Insn, 6, 2); 4182 if (fieldFromInstruction(Insn, 5, 1)) 4183 inc = 2; 4184 break; 4185 case 2: 4186 switch (fieldFromInstruction(Insn, 4, 2)) { 4187 case 0: 4188 align = 0; break; 4189 case 3: 4190 return MCDisassembler::Fail; 4191 default: 4192 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4193 } 4194 4195 index = fieldFromInstruction(Insn, 7, 1); 4196 if (fieldFromInstruction(Insn, 6, 1)) 4197 inc = 2; 4198 break; 4199 } 4200 4201 if (Rm != 0xF) { // Writeback 4202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4203 return MCDisassembler::Fail; 4204 } 4205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4206 return MCDisassembler::Fail; 4207 Inst.addOperand(MCOperand::CreateImm(align)); 4208 if (Rm != 0xF) { 4209 if (Rm != 0xD) { 4210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4211 return MCDisassembler::Fail; 4212 } else 4213 Inst.addOperand(MCOperand::CreateReg(0)); 4214 } 4215 4216 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4217 return MCDisassembler::Fail; 4218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4219 return MCDisassembler::Fail; 4220 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4221 return MCDisassembler::Fail; 4222 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4223 return MCDisassembler::Fail; 4224 Inst.addOperand(MCOperand::CreateImm(index)); 4225 4226 return S; 4227 } 4228 4229 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4230 uint64_t Address, const void *Decoder) { 4231 DecodeStatus S = MCDisassembler::Success; 4232 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4233 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4234 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4235 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4236 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4237 4238 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4239 S = MCDisassembler::SoftFail; 4240 4241 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4246 return MCDisassembler::Fail; 4247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 4252 return S; 4253 } 4254 4255 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4256 uint64_t Address, const void *Decoder) { 4257 DecodeStatus S = MCDisassembler::Success; 4258 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4259 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4260 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4261 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4262 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4263 4264 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4265 S = MCDisassembler::SoftFail; 4266 4267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4272 return MCDisassembler::Fail; 4273 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4274 return MCDisassembler::Fail; 4275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4276 return MCDisassembler::Fail; 4277 4278 return S; 4279 } 4280 4281 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4282 uint64_t Address, const void *Decoder) { 4283 DecodeStatus S = MCDisassembler::Success; 4284 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4285 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4286 4287 if (pred == 0xF) { 4288 pred = 0xE; 4289 S = MCDisassembler::SoftFail; 4290 } 4291 4292 if (mask == 0x0) { 4293 mask |= 0x8; 4294 S = MCDisassembler::SoftFail; 4295 } 4296 4297 Inst.addOperand(MCOperand::CreateImm(pred)); 4298 Inst.addOperand(MCOperand::CreateImm(mask)); 4299 return S; 4300 } 4301 4302 static DecodeStatus 4303 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4304 uint64_t Address, const void *Decoder) { 4305 DecodeStatus S = MCDisassembler::Success; 4306 4307 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4308 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4310 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4311 unsigned W = fieldFromInstruction(Insn, 21, 1); 4312 unsigned U = fieldFromInstruction(Insn, 23, 1); 4313 unsigned P = fieldFromInstruction(Insn, 24, 1); 4314 bool writeback = (W == 1) | (P == 0); 4315 4316 addr |= (U << 8) | (Rn << 9); 4317 4318 if (writeback && (Rn == Rt || Rn == Rt2)) 4319 Check(S, MCDisassembler::SoftFail); 4320 if (Rt == Rt2) 4321 Check(S, MCDisassembler::SoftFail); 4322 4323 // Rt 4324 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4325 return MCDisassembler::Fail; 4326 // Rt2 4327 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4328 return MCDisassembler::Fail; 4329 // Writeback operand 4330 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4331 return MCDisassembler::Fail; 4332 // addr 4333 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 4336 return S; 4337 } 4338 4339 static DecodeStatus 4340 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4341 uint64_t Address, const void *Decoder) { 4342 DecodeStatus S = MCDisassembler::Success; 4343 4344 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4345 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4346 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4347 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4348 unsigned W = fieldFromInstruction(Insn, 21, 1); 4349 unsigned U = fieldFromInstruction(Insn, 23, 1); 4350 unsigned P = fieldFromInstruction(Insn, 24, 1); 4351 bool writeback = (W == 1) | (P == 0); 4352 4353 addr |= (U << 8) | (Rn << 9); 4354 4355 if (writeback && (Rn == Rt || Rn == Rt2)) 4356 Check(S, MCDisassembler::SoftFail); 4357 4358 // Writeback operand 4359 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 // Rt 4362 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 // Rt2 4365 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 // addr 4368 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 4371 return S; 4372 } 4373 4374 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4375 uint64_t Address, const void *Decoder) { 4376 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4377 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4378 if (sign1 != sign2) return MCDisassembler::Fail; 4379 4380 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4381 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4382 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4383 Val |= sign1 << 12; 4384 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4385 4386 return MCDisassembler::Success; 4387 } 4388 4389 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4390 uint64_t Address, 4391 const void *Decoder) { 4392 DecodeStatus S = MCDisassembler::Success; 4393 4394 // Shift of "asr #32" is not allowed in Thumb2 mode. 4395 if (Val == 0x20) S = MCDisassembler::SoftFail; 4396 Inst.addOperand(MCOperand::CreateImm(Val)); 4397 return S; 4398 } 4399 4400 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4401 uint64_t Address, const void *Decoder) { 4402 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4403 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4404 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4405 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4406 4407 if (pred == 0xF) 4408 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4409 4410 DecodeStatus S = MCDisassembler::Success; 4411 4412 if (Rt == Rn || Rn == Rt2) 4413 S = MCDisassembler::SoftFail; 4414 4415 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4416 return MCDisassembler::Fail; 4417 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4418 return MCDisassembler::Fail; 4419 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4420 return MCDisassembler::Fail; 4421 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4422 return MCDisassembler::Fail; 4423 4424 return S; 4425 } 4426 4427 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4428 uint64_t Address, const void *Decoder) { 4429 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4430 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4431 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4432 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4433 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4434 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4435 4436 DecodeStatus S = MCDisassembler::Success; 4437 4438 // VMOVv2f32 is ambiguous with these decodings. 4439 if (!(imm & 0x38) && cmode == 0xF) { 4440 Inst.setOpcode(ARM::VMOVv2f32); 4441 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4442 } 4443 4444 if (!(imm & 0x20)) return MCDisassembler::Fail; 4445 4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4449 return MCDisassembler::Fail; 4450 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4451 4452 return S; 4453 } 4454 4455 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4456 uint64_t Address, const void *Decoder) { 4457 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4458 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4459 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4460 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4461 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4462 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4463 4464 DecodeStatus S = MCDisassembler::Success; 4465 4466 // VMOVv4f32 is ambiguous with these decodings. 4467 if (!(imm & 0x38) && cmode == 0xF) { 4468 Inst.setOpcode(ARM::VMOVv4f32); 4469 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4470 } 4471 4472 if (!(imm & 0x20)) return MCDisassembler::Fail; 4473 4474 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4475 return MCDisassembler::Fail; 4476 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4477 return MCDisassembler::Fail; 4478 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4479 4480 return S; 4481 } 4482 4483 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4484 const void *Decoder) 4485 { 4486 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4487 if (Imm > 4) return MCDisassembler::Fail; 4488 Inst.addOperand(MCOperand::CreateImm(Imm)); 4489 return MCDisassembler::Success; 4490 } 4491 4492 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4493 uint64_t Address, const void *Decoder) { 4494 DecodeStatus S = MCDisassembler::Success; 4495 4496 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4497 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4498 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4499 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4500 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4501 4502 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4503 S = MCDisassembler::SoftFail; 4504 4505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4506 return MCDisassembler::Fail; 4507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4508 return MCDisassembler::Fail; 4509 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4514 return MCDisassembler::Fail; 4515 4516 return S; 4517 } 4518 4519 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4520 uint64_t Address, const void *Decoder) { 4521 4522 DecodeStatus S = MCDisassembler::Success; 4523 4524 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4525 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4526 unsigned cop = fieldFromInstruction(Val, 8, 4); 4527 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4528 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4529 4530 if ((cop & ~0x1) == 0xa) 4531 return MCDisassembler::Fail; 4532 4533 if (Rt == Rt2) 4534 S = MCDisassembler::SoftFail; 4535 4536 Inst.addOperand(MCOperand::CreateImm(cop)); 4537 Inst.addOperand(MCOperand::CreateImm(opc1)); 4538 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4539 return MCDisassembler::Fail; 4540 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4541 return MCDisassembler::Fail; 4542 Inst.addOperand(MCOperand::CreateImm(CRm)); 4543 4544 return S; 4545 } 4546 4547