1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 327 const void *Decoder); 328 329 330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void* Decoder); 358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 #include "ARMGenDisassemblerTables.inc" 408 409 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 410 return new ARMDisassembler(STI); 411 } 412 413 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 414 return new ThumbDisassembler(STI); 415 } 416 417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 418 const MemoryObject &Region, 419 uint64_t Address, 420 raw_ostream &os, 421 raw_ostream &cs) const { 422 CommentStream = &cs; 423 424 uint8_t bytes[4]; 425 426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 428 429 // We want to read exactly 4 bytes of data. 430 if (Region.readBytes(Address, 4, bytes) == -1) { 431 Size = 0; 432 return MCDisassembler::Fail; 433 } 434 435 // Encoded as a small-endian 32-bit word in the stream. 436 uint32_t insn = (bytes[3] << 24) | 437 (bytes[2] << 16) | 438 (bytes[1] << 8) | 439 (bytes[0] << 0); 440 441 // Calling the auto-generated decoder function. 442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 443 Address, this, STI); 444 if (result != MCDisassembler::Fail) { 445 Size = 4; 446 return result; 447 } 448 449 // VFP and NEON instructions, similarly, are shared between ARM 450 // and Thumb modes. 451 MI.clear(); 452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 460 this, STI); 461 if (result != MCDisassembler::Fail) { 462 Size = 4; 463 // Add a fake predicate operand, because we share these instruction 464 // definitions with Thumb2 where these instructions are predicable. 465 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 466 return MCDisassembler::Fail; 467 return result; 468 } 469 470 MI.clear(); 471 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 472 this, STI); 473 if (result != MCDisassembler::Fail) { 474 Size = 4; 475 // Add a fake predicate operand, because we share these instruction 476 // definitions with Thumb2 where these instructions are predicable. 477 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 478 return MCDisassembler::Fail; 479 return result; 480 } 481 482 MI.clear(); 483 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 484 this, STI); 485 if (result != MCDisassembler::Fail) { 486 Size = 4; 487 // Add a fake predicate operand, because we share these instruction 488 // definitions with Thumb2 where these instructions are predicable. 489 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 490 return MCDisassembler::Fail; 491 return result; 492 } 493 494 MI.clear(); 495 496 Size = 0; 497 return MCDisassembler::Fail; 498 } 499 500 namespace llvm { 501 extern const MCInstrDesc ARMInsts[]; 502 } 503 504 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 505 /// immediate Value in the MCInst. The immediate Value has had any PC 506 /// adjustment made by the caller. If the instruction is a branch instruction 507 /// then isBranch is true, else false. If the getOpInfo() function was set as 508 /// part of the setupForSymbolicDisassembly() call then that function is called 509 /// to get any symbolic information at the Address for this instruction. If 510 /// that returns non-zero then the symbolic information it returns is used to 511 /// create an MCExpr and that is added as an operand to the MCInst. If 512 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 513 /// Value is done and if a symbol is found an MCExpr is created with that, else 514 /// an MCExpr with Value is created. This function returns true if it adds an 515 /// operand to the MCInst and false otherwise. 516 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 517 bool isBranch, uint64_t InstSize, 518 MCInst &MI, const void *Decoder) { 519 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 520 // FIXME: Does it make sense for value to be negative? 521 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 522 /* Offset */ 0, InstSize); 523 } 524 525 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 526 /// referenced by a load instruction with the base register that is the Pc. 527 /// These can often be values in a literal pool near the Address of the 528 /// instruction. The Address of the instruction and its immediate Value are 529 /// used as a possible literal pool entry. The SymbolLookUp call back will 530 /// return the name of a symbol referenced by the literal pool's entry if 531 /// the referenced address is that of a symbol. Or it will return a pointer to 532 /// a literal 'C' string if the referenced address of the literal pool's entry 533 /// is an address into a section with 'C' string literals. 534 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 535 const void *Decoder) { 536 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 537 Dis->tryAddingPcLoadReferenceComment(Value, Address); 538 } 539 540 // Thumb1 instructions don't have explicit S bits. Rather, they 541 // implicitly set CPSR. Since it's not represented in the encoding, the 542 // auto-generated decoder won't inject the CPSR operand. We need to fix 543 // that as a post-pass. 544 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 545 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 546 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 547 MCInst::iterator I = MI.begin(); 548 for (unsigned i = 0; i < NumOps; ++i, ++I) { 549 if (I == MI.end()) break; 550 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 551 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 552 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 553 return; 554 } 555 } 556 557 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 558 } 559 560 // Most Thumb instructions don't have explicit predicates in the 561 // encoding, but rather get their predicates from IT context. We need 562 // to fix up the predicate operands using this context information as a 563 // post-pass. 564 MCDisassembler::DecodeStatus 565 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 566 MCDisassembler::DecodeStatus S = Success; 567 568 // A few instructions actually have predicates encoded in them. Don't 569 // try to overwrite it if we're seeing one of those. 570 switch (MI.getOpcode()) { 571 case ARM::tBcc: 572 case ARM::t2Bcc: 573 case ARM::tCBZ: 574 case ARM::tCBNZ: 575 case ARM::tCPS: 576 case ARM::t2CPS3p: 577 case ARM::t2CPS2p: 578 case ARM::t2CPS1p: 579 case ARM::tMOVSr: 580 case ARM::tSETEND: 581 // Some instructions (mostly conditional branches) are not 582 // allowed in IT blocks. 583 if (ITBlock.instrInITBlock()) 584 S = SoftFail; 585 else 586 return Success; 587 break; 588 case ARM::tB: 589 case ARM::t2B: 590 case ARM::t2TBB: 591 case ARM::t2TBH: 592 // Some instructions (mostly unconditional branches) can 593 // only appears at the end of, or outside of, an IT. 594 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 595 S = SoftFail; 596 break; 597 default: 598 break; 599 } 600 601 // If we're in an IT block, base the predicate on that. Otherwise, 602 // assume a predicate of AL. 603 unsigned CC; 604 CC = ITBlock.getITCC(); 605 if (CC == 0xF) 606 CC = ARMCC::AL; 607 if (ITBlock.instrInITBlock()) 608 ITBlock.advanceITState(); 609 610 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 611 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 612 MCInst::iterator I = MI.begin(); 613 for (unsigned i = 0; i < NumOps; ++i, ++I) { 614 if (I == MI.end()) break; 615 if (OpInfo[i].isPredicate()) { 616 I = MI.insert(I, MCOperand::CreateImm(CC)); 617 ++I; 618 if (CC == ARMCC::AL) 619 MI.insert(I, MCOperand::CreateReg(0)); 620 else 621 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 622 return S; 623 } 624 } 625 626 I = MI.insert(I, MCOperand::CreateImm(CC)); 627 ++I; 628 if (CC == ARMCC::AL) 629 MI.insert(I, MCOperand::CreateReg(0)); 630 else 631 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 632 633 return S; 634 } 635 636 // Thumb VFP instructions are a special case. Because we share their 637 // encodings between ARM and Thumb modes, and they are predicable in ARM 638 // mode, the auto-generated decoder will give them an (incorrect) 639 // predicate operand. We need to rewrite these operands based on the IT 640 // context as a post-pass. 641 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 642 unsigned CC; 643 CC = ITBlock.getITCC(); 644 if (ITBlock.instrInITBlock()) 645 ITBlock.advanceITState(); 646 647 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 648 MCInst::iterator I = MI.begin(); 649 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 650 for (unsigned i = 0; i < NumOps; ++i, ++I) { 651 if (OpInfo[i].isPredicate() ) { 652 I->setImm(CC); 653 ++I; 654 if (CC == ARMCC::AL) 655 I->setReg(0); 656 else 657 I->setReg(ARM::CPSR); 658 return; 659 } 660 } 661 } 662 663 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 664 const MemoryObject &Region, 665 uint64_t Address, 666 raw_ostream &os, 667 raw_ostream &cs) const { 668 CommentStream = &cs; 669 670 uint8_t bytes[4]; 671 672 assert((STI.getFeatureBits() & ARM::ModeThumb) && 673 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 674 675 // We want to read exactly 2 bytes of data. 676 if (Region.readBytes(Address, 2, bytes) == -1) { 677 Size = 0; 678 return MCDisassembler::Fail; 679 } 680 681 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 682 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 683 Address, this, STI); 684 if (result != MCDisassembler::Fail) { 685 Size = 2; 686 Check(result, AddThumbPredicate(MI)); 687 return result; 688 } 689 690 MI.clear(); 691 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 692 Address, this, STI); 693 if (result) { 694 Size = 2; 695 bool InITBlock = ITBlock.instrInITBlock(); 696 Check(result, AddThumbPredicate(MI)); 697 AddThumb1SBit(MI, InITBlock); 698 return result; 699 } 700 701 MI.clear(); 702 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 703 Address, this, STI); 704 if (result != MCDisassembler::Fail) { 705 Size = 2; 706 707 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 708 // the Thumb predicate. 709 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 710 result = MCDisassembler::SoftFail; 711 712 Check(result, AddThumbPredicate(MI)); 713 714 // If we find an IT instruction, we need to parse its condition 715 // code and mask operands so that we can apply them correctly 716 // to the subsequent instructions. 717 if (MI.getOpcode() == ARM::t2IT) { 718 719 unsigned Firstcond = MI.getOperand(0).getImm(); 720 unsigned Mask = MI.getOperand(1).getImm(); 721 ITBlock.setITState(Firstcond, Mask); 722 } 723 724 return result; 725 } 726 727 // We want to read exactly 4 bytes of data. 728 if (Region.readBytes(Address, 4, bytes) == -1) { 729 Size = 0; 730 return MCDisassembler::Fail; 731 } 732 733 uint32_t insn32 = (bytes[3] << 8) | 734 (bytes[2] << 0) | 735 (bytes[1] << 24) | 736 (bytes[0] << 16); 737 MI.clear(); 738 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 739 this, STI); 740 if (result != MCDisassembler::Fail) { 741 Size = 4; 742 bool InITBlock = ITBlock.instrInITBlock(); 743 Check(result, AddThumbPredicate(MI)); 744 AddThumb1SBit(MI, InITBlock); 745 return result; 746 } 747 748 MI.clear(); 749 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 750 this, STI); 751 if (result != MCDisassembler::Fail) { 752 Size = 4; 753 Check(result, AddThumbPredicate(MI)); 754 return result; 755 } 756 757 MI.clear(); 758 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 759 if (result != MCDisassembler::Fail) { 760 Size = 4; 761 UpdateThumbVFPPredicate(MI); 762 return result; 763 } 764 765 MI.clear(); 766 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 767 this, STI); 768 if (result != MCDisassembler::Fail) { 769 Size = 4; 770 Check(result, AddThumbPredicate(MI)); 771 return result; 772 } 773 774 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 775 MI.clear(); 776 uint32_t NEONLdStInsn = insn32; 777 NEONLdStInsn &= 0xF0FFFFFF; 778 NEONLdStInsn |= 0x04000000; 779 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 780 Address, this, STI); 781 if (result != MCDisassembler::Fail) { 782 Size = 4; 783 Check(result, AddThumbPredicate(MI)); 784 return result; 785 } 786 } 787 788 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 789 MI.clear(); 790 uint32_t NEONDataInsn = insn32; 791 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 792 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 793 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 794 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 795 Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 4; 798 Check(result, AddThumbPredicate(MI)); 799 return result; 800 } 801 } 802 803 Size = 0; 804 return MCDisassembler::Fail; 805 } 806 807 808 extern "C" void LLVMInitializeARMDisassembler() { 809 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 810 createARMDisassembler); 811 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 812 createThumbDisassembler); 813 } 814 815 static const uint16_t GPRDecoderTable[] = { 816 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 817 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 818 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 819 ARM::R12, ARM::SP, ARM::LR, ARM::PC 820 }; 821 822 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 823 uint64_t Address, const void *Decoder) { 824 if (RegNo > 15) 825 return MCDisassembler::Fail; 826 827 unsigned Register = GPRDecoderTable[RegNo]; 828 Inst.addOperand(MCOperand::CreateReg(Register)); 829 return MCDisassembler::Success; 830 } 831 832 static DecodeStatus 833 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 834 uint64_t Address, const void *Decoder) { 835 DecodeStatus S = MCDisassembler::Success; 836 837 if (RegNo == 15) 838 S = MCDisassembler::SoftFail; 839 840 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 841 842 return S; 843 } 844 845 static DecodeStatus 846 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 847 uint64_t Address, const void *Decoder) { 848 DecodeStatus S = MCDisassembler::Success; 849 850 if (RegNo == 15) 851 { 852 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 853 return MCDisassembler::Success; 854 } 855 856 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 857 return S; 858 } 859 860 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 861 uint64_t Address, const void *Decoder) { 862 if (RegNo > 7) 863 return MCDisassembler::Fail; 864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 865 } 866 867 static const uint16_t GPRPairDecoderTable[] = { 868 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 869 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 870 }; 871 872 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 873 uint64_t Address, const void *Decoder) { 874 DecodeStatus S = MCDisassembler::Success; 875 876 if (RegNo > 13) 877 return MCDisassembler::Fail; 878 879 if ((RegNo & 1) || RegNo == 0xe) 880 S = MCDisassembler::SoftFail; 881 882 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 883 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 884 return S; 885 } 886 887 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 888 uint64_t Address, const void *Decoder) { 889 unsigned Register = 0; 890 switch (RegNo) { 891 case 0: 892 Register = ARM::R0; 893 break; 894 case 1: 895 Register = ARM::R1; 896 break; 897 case 2: 898 Register = ARM::R2; 899 break; 900 case 3: 901 Register = ARM::R3; 902 break; 903 case 9: 904 Register = ARM::R9; 905 break; 906 case 12: 907 Register = ARM::R12; 908 break; 909 default: 910 return MCDisassembler::Fail; 911 } 912 913 Inst.addOperand(MCOperand::CreateReg(Register)); 914 return MCDisassembler::Success; 915 } 916 917 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 918 uint64_t Address, const void *Decoder) { 919 DecodeStatus S = MCDisassembler::Success; 920 if (RegNo == 13 || RegNo == 15) 921 S = MCDisassembler::SoftFail; 922 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 923 return S; 924 } 925 926 static const uint16_t SPRDecoderTable[] = { 927 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 928 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 929 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 930 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 931 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 932 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 933 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 934 ARM::S28, ARM::S29, ARM::S30, ARM::S31 935 }; 936 937 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 938 uint64_t Address, const void *Decoder) { 939 if (RegNo > 31) 940 return MCDisassembler::Fail; 941 942 unsigned Register = SPRDecoderTable[RegNo]; 943 Inst.addOperand(MCOperand::CreateReg(Register)); 944 return MCDisassembler::Success; 945 } 946 947 static const uint16_t DPRDecoderTable[] = { 948 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 949 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 950 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 951 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 952 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 953 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 954 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 955 ARM::D28, ARM::D29, ARM::D30, ARM::D31 956 }; 957 958 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 if (RegNo > 31) 961 return MCDisassembler::Fail; 962 963 unsigned Register = DPRDecoderTable[RegNo]; 964 Inst.addOperand(MCOperand::CreateReg(Register)); 965 return MCDisassembler::Success; 966 } 967 968 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 969 uint64_t Address, const void *Decoder) { 970 if (RegNo > 7) 971 return MCDisassembler::Fail; 972 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 973 } 974 975 static DecodeStatus 976 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 if (RegNo > 15) 979 return MCDisassembler::Fail; 980 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 981 } 982 983 static const uint16_t QPRDecoderTable[] = { 984 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 985 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 986 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 987 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 988 }; 989 990 991 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 992 uint64_t Address, const void *Decoder) { 993 if (RegNo > 31 || (RegNo & 1) != 0) 994 return MCDisassembler::Fail; 995 RegNo >>= 1; 996 997 unsigned Register = QPRDecoderTable[RegNo]; 998 Inst.addOperand(MCOperand::CreateReg(Register)); 999 return MCDisassembler::Success; 1000 } 1001 1002 static const uint16_t DPairDecoderTable[] = { 1003 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1004 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1005 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1006 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1007 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1008 ARM::Q15 1009 }; 1010 1011 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1012 uint64_t Address, const void *Decoder) { 1013 if (RegNo > 30) 1014 return MCDisassembler::Fail; 1015 1016 unsigned Register = DPairDecoderTable[RegNo]; 1017 Inst.addOperand(MCOperand::CreateReg(Register)); 1018 return MCDisassembler::Success; 1019 } 1020 1021 static const uint16_t DPairSpacedDecoderTable[] = { 1022 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1023 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1024 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1025 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1026 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1027 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1028 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1029 ARM::D28_D30, ARM::D29_D31 1030 }; 1031 1032 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1033 unsigned RegNo, 1034 uint64_t Address, 1035 const void *Decoder) { 1036 if (RegNo > 29) 1037 return MCDisassembler::Fail; 1038 1039 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1040 Inst.addOperand(MCOperand::CreateReg(Register)); 1041 return MCDisassembler::Success; 1042 } 1043 1044 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1045 uint64_t Address, const void *Decoder) { 1046 if (Val == 0xF) return MCDisassembler::Fail; 1047 // AL predicate is not allowed on Thumb1 branches. 1048 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1049 return MCDisassembler::Fail; 1050 Inst.addOperand(MCOperand::CreateImm(Val)); 1051 if (Val == ARMCC::AL) { 1052 Inst.addOperand(MCOperand::CreateReg(0)); 1053 } else 1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1055 return MCDisassembler::Success; 1056 } 1057 1058 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1059 uint64_t Address, const void *Decoder) { 1060 if (Val) 1061 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1062 else 1063 Inst.addOperand(MCOperand::CreateReg(0)); 1064 return MCDisassembler::Success; 1065 } 1066 1067 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1068 uint64_t Address, const void *Decoder) { 1069 uint32_t imm = Val & 0xFF; 1070 uint32_t rot = (Val & 0xF00) >> 7; 1071 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1072 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1073 return MCDisassembler::Success; 1074 } 1075 1076 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1077 uint64_t Address, const void *Decoder) { 1078 DecodeStatus S = MCDisassembler::Success; 1079 1080 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1081 unsigned type = fieldFromInstruction(Val, 5, 2); 1082 unsigned imm = fieldFromInstruction(Val, 7, 5); 1083 1084 // Register-immediate 1085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1086 return MCDisassembler::Fail; 1087 1088 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1089 switch (type) { 1090 case 0: 1091 Shift = ARM_AM::lsl; 1092 break; 1093 case 1: 1094 Shift = ARM_AM::lsr; 1095 break; 1096 case 2: 1097 Shift = ARM_AM::asr; 1098 break; 1099 case 3: 1100 Shift = ARM_AM::ror; 1101 break; 1102 } 1103 1104 if (Shift == ARM_AM::ror && imm == 0) 1105 Shift = ARM_AM::rrx; 1106 1107 unsigned Op = Shift | (imm << 3); 1108 Inst.addOperand(MCOperand::CreateImm(Op)); 1109 1110 return S; 1111 } 1112 1113 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1114 uint64_t Address, const void *Decoder) { 1115 DecodeStatus S = MCDisassembler::Success; 1116 1117 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1118 unsigned type = fieldFromInstruction(Val, 5, 2); 1119 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1120 1121 // Register-register 1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1123 return MCDisassembler::Fail; 1124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1125 return MCDisassembler::Fail; 1126 1127 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1128 switch (type) { 1129 case 0: 1130 Shift = ARM_AM::lsl; 1131 break; 1132 case 1: 1133 Shift = ARM_AM::lsr; 1134 break; 1135 case 2: 1136 Shift = ARM_AM::asr; 1137 break; 1138 case 3: 1139 Shift = ARM_AM::ror; 1140 break; 1141 } 1142 1143 Inst.addOperand(MCOperand::CreateImm(Shift)); 1144 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 bool writebackLoad = false; 1153 unsigned writebackReg = 0; 1154 switch (Inst.getOpcode()) { 1155 default: 1156 break; 1157 case ARM::LDMIA_UPD: 1158 case ARM::LDMDB_UPD: 1159 case ARM::LDMIB_UPD: 1160 case ARM::LDMDA_UPD: 1161 case ARM::t2LDMIA_UPD: 1162 case ARM::t2LDMDB_UPD: 1163 writebackLoad = true; 1164 writebackReg = Inst.getOperand(0).getReg(); 1165 break; 1166 } 1167 1168 // Empty register lists are not allowed. 1169 if (Val == 0) return MCDisassembler::Fail; 1170 for (unsigned i = 0; i < 16; ++i) { 1171 if (Val & (1 << i)) { 1172 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1173 return MCDisassembler::Fail; 1174 // Writeback not allowed if Rn is in the target list. 1175 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1176 Check(S, MCDisassembler::SoftFail); 1177 } 1178 } 1179 1180 return S; 1181 } 1182 1183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1184 uint64_t Address, const void *Decoder) { 1185 DecodeStatus S = MCDisassembler::Success; 1186 1187 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1188 unsigned regs = fieldFromInstruction(Val, 0, 8); 1189 1190 // In case of unpredictable encoding, tweak the operands. 1191 if (regs == 0 || (Vd + regs) > 32) { 1192 regs = Vd + regs > 32 ? 32 - Vd : regs; 1193 regs = std::max( 1u, regs); 1194 S = MCDisassembler::SoftFail; 1195 } 1196 1197 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1198 return MCDisassembler::Fail; 1199 for (unsigned i = 0; i < (regs - 1); ++i) { 1200 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1201 return MCDisassembler::Fail; 1202 } 1203 1204 return S; 1205 } 1206 1207 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1208 uint64_t Address, const void *Decoder) { 1209 DecodeStatus S = MCDisassembler::Success; 1210 1211 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1212 unsigned regs = fieldFromInstruction(Val, 1, 7); 1213 1214 // In case of unpredictable encoding, tweak the operands. 1215 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1216 regs = Vd + regs > 32 ? 32 - Vd : regs; 1217 regs = std::max( 1u, regs); 1218 regs = std::min(16u, regs); 1219 S = MCDisassembler::SoftFail; 1220 } 1221 1222 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1223 return MCDisassembler::Fail; 1224 for (unsigned i = 0; i < (regs - 1); ++i) { 1225 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1226 return MCDisassembler::Fail; 1227 } 1228 1229 return S; 1230 } 1231 1232 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1233 uint64_t Address, const void *Decoder) { 1234 // This operand encodes a mask of contiguous zeros between a specified MSB 1235 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1236 // the mask of all bits LSB-and-lower, and then xor them to create 1237 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1238 // create the final mask. 1239 unsigned msb = fieldFromInstruction(Val, 5, 5); 1240 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1241 1242 DecodeStatus S = MCDisassembler::Success; 1243 if (lsb > msb) { 1244 Check(S, MCDisassembler::SoftFail); 1245 // The check above will cause the warning for the "potentially undefined 1246 // instruction encoding" but we can't build a bad MCOperand value here 1247 // with a lsb > msb or else printing the MCInst will cause a crash. 1248 lsb = msb; 1249 } 1250 1251 uint32_t msb_mask = 0xFFFFFFFF; 1252 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1253 uint32_t lsb_mask = (1U << lsb) - 1; 1254 1255 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1256 return S; 1257 } 1258 1259 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1260 uint64_t Address, const void *Decoder) { 1261 DecodeStatus S = MCDisassembler::Success; 1262 1263 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1264 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1265 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1266 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1267 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1268 unsigned U = fieldFromInstruction(Insn, 23, 1); 1269 1270 switch (Inst.getOpcode()) { 1271 case ARM::LDC_OFFSET: 1272 case ARM::LDC_PRE: 1273 case ARM::LDC_POST: 1274 case ARM::LDC_OPTION: 1275 case ARM::LDCL_OFFSET: 1276 case ARM::LDCL_PRE: 1277 case ARM::LDCL_POST: 1278 case ARM::LDCL_OPTION: 1279 case ARM::STC_OFFSET: 1280 case ARM::STC_PRE: 1281 case ARM::STC_POST: 1282 case ARM::STC_OPTION: 1283 case ARM::STCL_OFFSET: 1284 case ARM::STCL_PRE: 1285 case ARM::STCL_POST: 1286 case ARM::STCL_OPTION: 1287 case ARM::t2LDC_OFFSET: 1288 case ARM::t2LDC_PRE: 1289 case ARM::t2LDC_POST: 1290 case ARM::t2LDC_OPTION: 1291 case ARM::t2LDCL_OFFSET: 1292 case ARM::t2LDCL_PRE: 1293 case ARM::t2LDCL_POST: 1294 case ARM::t2LDCL_OPTION: 1295 case ARM::t2STC_OFFSET: 1296 case ARM::t2STC_PRE: 1297 case ARM::t2STC_POST: 1298 case ARM::t2STC_OPTION: 1299 case ARM::t2STCL_OFFSET: 1300 case ARM::t2STCL_PRE: 1301 case ARM::t2STCL_POST: 1302 case ARM::t2STCL_OPTION: 1303 if (coproc == 0xA || coproc == 0xB) 1304 return MCDisassembler::Fail; 1305 break; 1306 default: 1307 break; 1308 } 1309 1310 Inst.addOperand(MCOperand::CreateImm(coproc)); 1311 Inst.addOperand(MCOperand::CreateImm(CRd)); 1312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1313 return MCDisassembler::Fail; 1314 1315 switch (Inst.getOpcode()) { 1316 case ARM::t2LDC2_OFFSET: 1317 case ARM::t2LDC2L_OFFSET: 1318 case ARM::t2LDC2_PRE: 1319 case ARM::t2LDC2L_PRE: 1320 case ARM::t2STC2_OFFSET: 1321 case ARM::t2STC2L_OFFSET: 1322 case ARM::t2STC2_PRE: 1323 case ARM::t2STC2L_PRE: 1324 case ARM::LDC2_OFFSET: 1325 case ARM::LDC2L_OFFSET: 1326 case ARM::LDC2_PRE: 1327 case ARM::LDC2L_PRE: 1328 case ARM::STC2_OFFSET: 1329 case ARM::STC2L_OFFSET: 1330 case ARM::STC2_PRE: 1331 case ARM::STC2L_PRE: 1332 case ARM::t2LDC_OFFSET: 1333 case ARM::t2LDCL_OFFSET: 1334 case ARM::t2LDC_PRE: 1335 case ARM::t2LDCL_PRE: 1336 case ARM::t2STC_OFFSET: 1337 case ARM::t2STCL_OFFSET: 1338 case ARM::t2STC_PRE: 1339 case ARM::t2STCL_PRE: 1340 case ARM::LDC_OFFSET: 1341 case ARM::LDCL_OFFSET: 1342 case ARM::LDC_PRE: 1343 case ARM::LDCL_PRE: 1344 case ARM::STC_OFFSET: 1345 case ARM::STCL_OFFSET: 1346 case ARM::STC_PRE: 1347 case ARM::STCL_PRE: 1348 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1349 Inst.addOperand(MCOperand::CreateImm(imm)); 1350 break; 1351 case ARM::t2LDC2_POST: 1352 case ARM::t2LDC2L_POST: 1353 case ARM::t2STC2_POST: 1354 case ARM::t2STC2L_POST: 1355 case ARM::LDC2_POST: 1356 case ARM::LDC2L_POST: 1357 case ARM::STC2_POST: 1358 case ARM::STC2L_POST: 1359 case ARM::t2LDC_POST: 1360 case ARM::t2LDCL_POST: 1361 case ARM::t2STC_POST: 1362 case ARM::t2STCL_POST: 1363 case ARM::LDC_POST: 1364 case ARM::LDCL_POST: 1365 case ARM::STC_POST: 1366 case ARM::STCL_POST: 1367 imm |= U << 8; 1368 // fall through. 1369 default: 1370 // The 'option' variant doesn't encode 'U' in the immediate since 1371 // the immediate is unsigned [0,255]. 1372 Inst.addOperand(MCOperand::CreateImm(imm)); 1373 break; 1374 } 1375 1376 switch (Inst.getOpcode()) { 1377 case ARM::LDC_OFFSET: 1378 case ARM::LDC_PRE: 1379 case ARM::LDC_POST: 1380 case ARM::LDC_OPTION: 1381 case ARM::LDCL_OFFSET: 1382 case ARM::LDCL_PRE: 1383 case ARM::LDCL_POST: 1384 case ARM::LDCL_OPTION: 1385 case ARM::STC_OFFSET: 1386 case ARM::STC_PRE: 1387 case ARM::STC_POST: 1388 case ARM::STC_OPTION: 1389 case ARM::STCL_OFFSET: 1390 case ARM::STCL_PRE: 1391 case ARM::STCL_POST: 1392 case ARM::STCL_OPTION: 1393 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1394 return MCDisassembler::Fail; 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 return S; 1401 } 1402 1403 static DecodeStatus 1404 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1405 uint64_t Address, const void *Decoder) { 1406 DecodeStatus S = MCDisassembler::Success; 1407 1408 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1409 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1410 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1411 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1412 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1413 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1414 unsigned P = fieldFromInstruction(Insn, 24, 1); 1415 unsigned W = fieldFromInstruction(Insn, 21, 1); 1416 1417 // On stores, the writeback operand precedes Rt. 1418 switch (Inst.getOpcode()) { 1419 case ARM::STR_POST_IMM: 1420 case ARM::STR_POST_REG: 1421 case ARM::STRB_POST_IMM: 1422 case ARM::STRB_POST_REG: 1423 case ARM::STRT_POST_REG: 1424 case ARM::STRT_POST_IMM: 1425 case ARM::STRBT_POST_REG: 1426 case ARM::STRBT_POST_IMM: 1427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1428 return MCDisassembler::Fail; 1429 break; 1430 default: 1431 break; 1432 } 1433 1434 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1435 return MCDisassembler::Fail; 1436 1437 // On loads, the writeback operand comes after Rt. 1438 switch (Inst.getOpcode()) { 1439 case ARM::LDR_POST_IMM: 1440 case ARM::LDR_POST_REG: 1441 case ARM::LDRB_POST_IMM: 1442 case ARM::LDRB_POST_REG: 1443 case ARM::LDRBT_POST_REG: 1444 case ARM::LDRBT_POST_IMM: 1445 case ARM::LDRT_POST_REG: 1446 case ARM::LDRT_POST_IMM: 1447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1448 return MCDisassembler::Fail; 1449 break; 1450 default: 1451 break; 1452 } 1453 1454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1455 return MCDisassembler::Fail; 1456 1457 ARM_AM::AddrOpc Op = ARM_AM::add; 1458 if (!fieldFromInstruction(Insn, 23, 1)) 1459 Op = ARM_AM::sub; 1460 1461 bool writeback = (P == 0) || (W == 1); 1462 unsigned idx_mode = 0; 1463 if (P && writeback) 1464 idx_mode = ARMII::IndexModePre; 1465 else if (!P && writeback) 1466 idx_mode = ARMII::IndexModePost; 1467 1468 if (writeback && (Rn == 15 || Rn == Rt)) 1469 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1470 1471 if (reg) { 1472 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1473 return MCDisassembler::Fail; 1474 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1475 switch( fieldFromInstruction(Insn, 5, 2)) { 1476 case 0: 1477 Opc = ARM_AM::lsl; 1478 break; 1479 case 1: 1480 Opc = ARM_AM::lsr; 1481 break; 1482 case 2: 1483 Opc = ARM_AM::asr; 1484 break; 1485 case 3: 1486 Opc = ARM_AM::ror; 1487 break; 1488 default: 1489 return MCDisassembler::Fail; 1490 } 1491 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1492 if (Opc == ARM_AM::ror && amt == 0) 1493 Opc = ARM_AM::rrx; 1494 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1495 1496 Inst.addOperand(MCOperand::CreateImm(imm)); 1497 } else { 1498 Inst.addOperand(MCOperand::CreateReg(0)); 1499 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1500 Inst.addOperand(MCOperand::CreateImm(tmp)); 1501 } 1502 1503 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 1506 return S; 1507 } 1508 1509 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1510 uint64_t Address, const void *Decoder) { 1511 DecodeStatus S = MCDisassembler::Success; 1512 1513 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1514 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1515 unsigned type = fieldFromInstruction(Val, 5, 2); 1516 unsigned imm = fieldFromInstruction(Val, 7, 5); 1517 unsigned U = fieldFromInstruction(Val, 12, 1); 1518 1519 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1520 switch (type) { 1521 case 0: 1522 ShOp = ARM_AM::lsl; 1523 break; 1524 case 1: 1525 ShOp = ARM_AM::lsr; 1526 break; 1527 case 2: 1528 ShOp = ARM_AM::asr; 1529 break; 1530 case 3: 1531 ShOp = ARM_AM::ror; 1532 break; 1533 } 1534 1535 if (ShOp == ARM_AM::ror && imm == 0) 1536 ShOp = ARM_AM::rrx; 1537 1538 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1539 return MCDisassembler::Fail; 1540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1541 return MCDisassembler::Fail; 1542 unsigned shift; 1543 if (U) 1544 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1545 else 1546 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1547 Inst.addOperand(MCOperand::CreateImm(shift)); 1548 1549 return S; 1550 } 1551 1552 static DecodeStatus 1553 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1554 uint64_t Address, const void *Decoder) { 1555 DecodeStatus S = MCDisassembler::Success; 1556 1557 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1558 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1559 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1560 unsigned type = fieldFromInstruction(Insn, 22, 1); 1561 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1562 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1563 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1564 unsigned W = fieldFromInstruction(Insn, 21, 1); 1565 unsigned P = fieldFromInstruction(Insn, 24, 1); 1566 unsigned Rt2 = Rt + 1; 1567 1568 bool writeback = (W == 1) | (P == 0); 1569 1570 // For {LD,ST}RD, Rt must be even, else undefined. 1571 switch (Inst.getOpcode()) { 1572 case ARM::STRD: 1573 case ARM::STRD_PRE: 1574 case ARM::STRD_POST: 1575 case ARM::LDRD: 1576 case ARM::LDRD_PRE: 1577 case ARM::LDRD_POST: 1578 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1579 break; 1580 default: 1581 break; 1582 } 1583 switch (Inst.getOpcode()) { 1584 case ARM::STRD: 1585 case ARM::STRD_PRE: 1586 case ARM::STRD_POST: 1587 if (P == 0 && W == 1) 1588 S = MCDisassembler::SoftFail; 1589 1590 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1591 S = MCDisassembler::SoftFail; 1592 if (type && Rm == 15) 1593 S = MCDisassembler::SoftFail; 1594 if (Rt2 == 15) 1595 S = MCDisassembler::SoftFail; 1596 if (!type && fieldFromInstruction(Insn, 8, 4)) 1597 S = MCDisassembler::SoftFail; 1598 break; 1599 case ARM::STRH: 1600 case ARM::STRH_PRE: 1601 case ARM::STRH_POST: 1602 if (Rt == 15) 1603 S = MCDisassembler::SoftFail; 1604 if (writeback && (Rn == 15 || Rn == Rt)) 1605 S = MCDisassembler::SoftFail; 1606 if (!type && Rm == 15) 1607 S = MCDisassembler::SoftFail; 1608 break; 1609 case ARM::LDRD: 1610 case ARM::LDRD_PRE: 1611 case ARM::LDRD_POST: 1612 if (type && Rn == 15){ 1613 if (Rt2 == 15) 1614 S = MCDisassembler::SoftFail; 1615 break; 1616 } 1617 if (P == 0 && W == 1) 1618 S = MCDisassembler::SoftFail; 1619 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1620 S = MCDisassembler::SoftFail; 1621 if (!type && writeback && Rn == 15) 1622 S = MCDisassembler::SoftFail; 1623 if (writeback && (Rn == Rt || Rn == Rt2)) 1624 S = MCDisassembler::SoftFail; 1625 break; 1626 case ARM::LDRH: 1627 case ARM::LDRH_PRE: 1628 case ARM::LDRH_POST: 1629 if (type && Rn == 15){ 1630 if (Rt == 15) 1631 S = MCDisassembler::SoftFail; 1632 break; 1633 } 1634 if (Rt == 15) 1635 S = MCDisassembler::SoftFail; 1636 if (!type && Rm == 15) 1637 S = MCDisassembler::SoftFail; 1638 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1639 S = MCDisassembler::SoftFail; 1640 break; 1641 case ARM::LDRSH: 1642 case ARM::LDRSH_PRE: 1643 case ARM::LDRSH_POST: 1644 case ARM::LDRSB: 1645 case ARM::LDRSB_PRE: 1646 case ARM::LDRSB_POST: 1647 if (type && Rn == 15){ 1648 if (Rt == 15) 1649 S = MCDisassembler::SoftFail; 1650 break; 1651 } 1652 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1653 S = MCDisassembler::SoftFail; 1654 if (!type && (Rt == 15 || Rm == 15)) 1655 S = MCDisassembler::SoftFail; 1656 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1657 S = MCDisassembler::SoftFail; 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 if (writeback) { // Writeback 1664 if (P) 1665 U |= ARMII::IndexModePre << 9; 1666 else 1667 U |= ARMII::IndexModePost << 9; 1668 1669 // On stores, the writeback operand precedes Rt. 1670 switch (Inst.getOpcode()) { 1671 case ARM::STRD: 1672 case ARM::STRD_PRE: 1673 case ARM::STRD_POST: 1674 case ARM::STRH: 1675 case ARM::STRH_PRE: 1676 case ARM::STRH_POST: 1677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1678 return MCDisassembler::Fail; 1679 break; 1680 default: 1681 break; 1682 } 1683 } 1684 1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1686 return MCDisassembler::Fail; 1687 switch (Inst.getOpcode()) { 1688 case ARM::STRD: 1689 case ARM::STRD_PRE: 1690 case ARM::STRD_POST: 1691 case ARM::LDRD: 1692 case ARM::LDRD_PRE: 1693 case ARM::LDRD_POST: 1694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1695 return MCDisassembler::Fail; 1696 break; 1697 default: 1698 break; 1699 } 1700 1701 if (writeback) { 1702 // On loads, the writeback operand comes after Rt. 1703 switch (Inst.getOpcode()) { 1704 case ARM::LDRD: 1705 case ARM::LDRD_PRE: 1706 case ARM::LDRD_POST: 1707 case ARM::LDRH: 1708 case ARM::LDRH_PRE: 1709 case ARM::LDRH_POST: 1710 case ARM::LDRSH: 1711 case ARM::LDRSH_PRE: 1712 case ARM::LDRSH_POST: 1713 case ARM::LDRSB: 1714 case ARM::LDRSB_PRE: 1715 case ARM::LDRSB_POST: 1716 case ARM::LDRHTr: 1717 case ARM::LDRSBTr: 1718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1719 return MCDisassembler::Fail; 1720 break; 1721 default: 1722 break; 1723 } 1724 } 1725 1726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1727 return MCDisassembler::Fail; 1728 1729 if (type) { 1730 Inst.addOperand(MCOperand::CreateReg(0)); 1731 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1732 } else { 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 Inst.addOperand(MCOperand::CreateImm(U)); 1736 } 1737 1738 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1739 return MCDisassembler::Fail; 1740 1741 return S; 1742 } 1743 1744 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1745 uint64_t Address, const void *Decoder) { 1746 DecodeStatus S = MCDisassembler::Success; 1747 1748 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1749 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1750 1751 switch (mode) { 1752 case 0: 1753 mode = ARM_AM::da; 1754 break; 1755 case 1: 1756 mode = ARM_AM::ia; 1757 break; 1758 case 2: 1759 mode = ARM_AM::db; 1760 break; 1761 case 3: 1762 mode = ARM_AM::ib; 1763 break; 1764 } 1765 1766 Inst.addOperand(MCOperand::CreateImm(mode)); 1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1768 return MCDisassembler::Fail; 1769 1770 return S; 1771 } 1772 1773 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1774 uint64_t Address, const void *Decoder) { 1775 DecodeStatus S = MCDisassembler::Success; 1776 1777 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1778 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1779 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1780 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1781 1782 if (pred == 0xF) 1783 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1784 1785 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1788 return MCDisassembler::Fail; 1789 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1790 return MCDisassembler::Fail; 1791 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1792 return MCDisassembler::Fail; 1793 return S; 1794 } 1795 1796 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1797 unsigned Insn, 1798 uint64_t Address, const void *Decoder) { 1799 DecodeStatus S = MCDisassembler::Success; 1800 1801 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1802 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1803 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1804 1805 if (pred == 0xF) { 1806 // Ambiguous with RFE and SRS 1807 switch (Inst.getOpcode()) { 1808 case ARM::LDMDA: 1809 Inst.setOpcode(ARM::RFEDA); 1810 break; 1811 case ARM::LDMDA_UPD: 1812 Inst.setOpcode(ARM::RFEDA_UPD); 1813 break; 1814 case ARM::LDMDB: 1815 Inst.setOpcode(ARM::RFEDB); 1816 break; 1817 case ARM::LDMDB_UPD: 1818 Inst.setOpcode(ARM::RFEDB_UPD); 1819 break; 1820 case ARM::LDMIA: 1821 Inst.setOpcode(ARM::RFEIA); 1822 break; 1823 case ARM::LDMIA_UPD: 1824 Inst.setOpcode(ARM::RFEIA_UPD); 1825 break; 1826 case ARM::LDMIB: 1827 Inst.setOpcode(ARM::RFEIB); 1828 break; 1829 case ARM::LDMIB_UPD: 1830 Inst.setOpcode(ARM::RFEIB_UPD); 1831 break; 1832 case ARM::STMDA: 1833 Inst.setOpcode(ARM::SRSDA); 1834 break; 1835 case ARM::STMDA_UPD: 1836 Inst.setOpcode(ARM::SRSDA_UPD); 1837 break; 1838 case ARM::STMDB: 1839 Inst.setOpcode(ARM::SRSDB); 1840 break; 1841 case ARM::STMDB_UPD: 1842 Inst.setOpcode(ARM::SRSDB_UPD); 1843 break; 1844 case ARM::STMIA: 1845 Inst.setOpcode(ARM::SRSIA); 1846 break; 1847 case ARM::STMIA_UPD: 1848 Inst.setOpcode(ARM::SRSIA_UPD); 1849 break; 1850 case ARM::STMIB: 1851 Inst.setOpcode(ARM::SRSIB); 1852 break; 1853 case ARM::STMIB_UPD: 1854 Inst.setOpcode(ARM::SRSIB_UPD); 1855 break; 1856 default: 1857 return MCDisassembler::Fail; 1858 } 1859 1860 // For stores (which become SRS's, the only operand is the mode. 1861 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1862 // Check SRS encoding constraints 1863 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1864 fieldFromInstruction(Insn, 20, 1) == 0)) 1865 return MCDisassembler::Fail; 1866 1867 Inst.addOperand( 1868 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1869 return S; 1870 } 1871 1872 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1873 } 1874 1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1876 return MCDisassembler::Fail; 1877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1878 return MCDisassembler::Fail; // Tied 1879 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1882 return MCDisassembler::Fail; 1883 1884 return S; 1885 } 1886 1887 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1888 uint64_t Address, const void *Decoder) { 1889 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1890 unsigned M = fieldFromInstruction(Insn, 17, 1); 1891 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1892 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1893 1894 DecodeStatus S = MCDisassembler::Success; 1895 1896 // This decoder is called from multiple location that do not check 1897 // the full encoding is valid before they do. 1898 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1899 fieldFromInstruction(Insn, 16, 1) != 0 || 1900 fieldFromInstruction(Insn, 20, 8) != 0x10) 1901 return MCDisassembler::Fail; 1902 1903 // imod == '01' --> UNPREDICTABLE 1904 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1905 // return failure here. The '01' imod value is unprintable, so there's 1906 // nothing useful we could do even if we returned UNPREDICTABLE. 1907 1908 if (imod == 1) return MCDisassembler::Fail; 1909 1910 if (imod && M) { 1911 Inst.setOpcode(ARM::CPS3p); 1912 Inst.addOperand(MCOperand::CreateImm(imod)); 1913 Inst.addOperand(MCOperand::CreateImm(iflags)); 1914 Inst.addOperand(MCOperand::CreateImm(mode)); 1915 } else if (imod && !M) { 1916 Inst.setOpcode(ARM::CPS2p); 1917 Inst.addOperand(MCOperand::CreateImm(imod)); 1918 Inst.addOperand(MCOperand::CreateImm(iflags)); 1919 if (mode) S = MCDisassembler::SoftFail; 1920 } else if (!imod && M) { 1921 Inst.setOpcode(ARM::CPS1p); 1922 Inst.addOperand(MCOperand::CreateImm(mode)); 1923 if (iflags) S = MCDisassembler::SoftFail; 1924 } else { 1925 // imod == '00' && M == '0' --> UNPREDICTABLE 1926 Inst.setOpcode(ARM::CPS1p); 1927 Inst.addOperand(MCOperand::CreateImm(mode)); 1928 S = MCDisassembler::SoftFail; 1929 } 1930 1931 return S; 1932 } 1933 1934 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1935 uint64_t Address, const void *Decoder) { 1936 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1937 unsigned M = fieldFromInstruction(Insn, 8, 1); 1938 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1939 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1940 1941 DecodeStatus S = MCDisassembler::Success; 1942 1943 // imod == '01' --> UNPREDICTABLE 1944 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1945 // return failure here. The '01' imod value is unprintable, so there's 1946 // nothing useful we could do even if we returned UNPREDICTABLE. 1947 1948 if (imod == 1) return MCDisassembler::Fail; 1949 1950 if (imod && M) { 1951 Inst.setOpcode(ARM::t2CPS3p); 1952 Inst.addOperand(MCOperand::CreateImm(imod)); 1953 Inst.addOperand(MCOperand::CreateImm(iflags)); 1954 Inst.addOperand(MCOperand::CreateImm(mode)); 1955 } else if (imod && !M) { 1956 Inst.setOpcode(ARM::t2CPS2p); 1957 Inst.addOperand(MCOperand::CreateImm(imod)); 1958 Inst.addOperand(MCOperand::CreateImm(iflags)); 1959 if (mode) S = MCDisassembler::SoftFail; 1960 } else if (!imod && M) { 1961 Inst.setOpcode(ARM::t2CPS1p); 1962 Inst.addOperand(MCOperand::CreateImm(mode)); 1963 if (iflags) S = MCDisassembler::SoftFail; 1964 } else { 1965 // imod == '00' && M == '0' --> this is a HINT instruction 1966 int imm = fieldFromInstruction(Insn, 0, 8); 1967 // HINT are defined only for immediate in [0..4] 1968 if(imm > 4) return MCDisassembler::Fail; 1969 Inst.setOpcode(ARM::t2HINT); 1970 Inst.addOperand(MCOperand::CreateImm(imm)); 1971 } 1972 1973 return S; 1974 } 1975 1976 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1977 uint64_t Address, const void *Decoder) { 1978 DecodeStatus S = MCDisassembler::Success; 1979 1980 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1981 unsigned imm = 0; 1982 1983 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1984 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1985 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1986 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1987 1988 if (Inst.getOpcode() == ARM::t2MOVTi16) 1989 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1990 return MCDisassembler::Fail; 1991 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1992 return MCDisassembler::Fail; 1993 1994 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1995 Inst.addOperand(MCOperand::CreateImm(imm)); 1996 1997 return S; 1998 } 1999 2000 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2001 uint64_t Address, const void *Decoder) { 2002 DecodeStatus S = MCDisassembler::Success; 2003 2004 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2005 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2006 unsigned imm = 0; 2007 2008 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2009 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2010 2011 if (Inst.getOpcode() == ARM::MOVTi16) 2012 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2013 return MCDisassembler::Fail; 2014 2015 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2016 return MCDisassembler::Fail; 2017 2018 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2019 Inst.addOperand(MCOperand::CreateImm(imm)); 2020 2021 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2022 return MCDisassembler::Fail; 2023 2024 return S; 2025 } 2026 2027 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2028 uint64_t Address, const void *Decoder) { 2029 DecodeStatus S = MCDisassembler::Success; 2030 2031 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2032 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2033 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2034 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2035 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2036 2037 if (pred == 0xF) 2038 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2039 2040 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2041 return MCDisassembler::Fail; 2042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2043 return MCDisassembler::Fail; 2044 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2045 return MCDisassembler::Fail; 2046 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2047 return MCDisassembler::Fail; 2048 2049 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2050 return MCDisassembler::Fail; 2051 2052 return S; 2053 } 2054 2055 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2056 uint64_t Address, const void *Decoder) { 2057 DecodeStatus S = MCDisassembler::Success; 2058 2059 unsigned add = fieldFromInstruction(Val, 12, 1); 2060 unsigned imm = fieldFromInstruction(Val, 0, 12); 2061 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2062 2063 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2064 return MCDisassembler::Fail; 2065 2066 if (!add) imm *= -1; 2067 if (imm == 0 && !add) imm = INT32_MIN; 2068 Inst.addOperand(MCOperand::CreateImm(imm)); 2069 if (Rn == 15) 2070 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2071 2072 return S; 2073 } 2074 2075 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2076 uint64_t Address, const void *Decoder) { 2077 DecodeStatus S = MCDisassembler::Success; 2078 2079 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2080 unsigned U = fieldFromInstruction(Val, 8, 1); 2081 unsigned imm = fieldFromInstruction(Val, 0, 8); 2082 2083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2084 return MCDisassembler::Fail; 2085 2086 if (U) 2087 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2088 else 2089 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2090 2091 return S; 2092 } 2093 2094 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2095 uint64_t Address, const void *Decoder) { 2096 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2097 } 2098 2099 static DecodeStatus 2100 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2101 uint64_t Address, const void *Decoder) { 2102 DecodeStatus Status = MCDisassembler::Success; 2103 2104 // Note the J1 and J2 values are from the encoded instruction. So here 2105 // change them to I1 and I2 values via as documented: 2106 // I1 = NOT(J1 EOR S); 2107 // I2 = NOT(J2 EOR S); 2108 // and build the imm32 with one trailing zero as documented: 2109 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2110 unsigned S = fieldFromInstruction(Insn, 26, 1); 2111 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2112 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2113 unsigned I1 = !(J1 ^ S); 2114 unsigned I2 = !(J2 ^ S); 2115 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2116 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2117 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2118 int imm32 = SignExtend32<25>(tmp << 1); 2119 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2120 true, 4, Inst, Decoder)) 2121 Inst.addOperand(MCOperand::CreateImm(imm32)); 2122 2123 return Status; 2124 } 2125 2126 static DecodeStatus 2127 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2128 uint64_t Address, const void *Decoder) { 2129 DecodeStatus S = MCDisassembler::Success; 2130 2131 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2132 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2133 2134 if (pred == 0xF) { 2135 Inst.setOpcode(ARM::BLXi); 2136 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2137 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2138 true, 4, Inst, Decoder)) 2139 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2140 return S; 2141 } 2142 2143 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2144 true, 4, Inst, Decoder)) 2145 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2146 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2147 return MCDisassembler::Fail; 2148 2149 return S; 2150 } 2151 2152 2153 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2154 uint64_t Address, const void *Decoder) { 2155 DecodeStatus S = MCDisassembler::Success; 2156 2157 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2158 unsigned align = fieldFromInstruction(Val, 4, 2); 2159 2160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2161 return MCDisassembler::Fail; 2162 if (!align) 2163 Inst.addOperand(MCOperand::CreateImm(0)); 2164 else 2165 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2166 2167 return S; 2168 } 2169 2170 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2171 uint64_t Address, const void *Decoder) { 2172 DecodeStatus S = MCDisassembler::Success; 2173 2174 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2175 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2176 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2177 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2178 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2179 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2180 2181 // First output register 2182 switch (Inst.getOpcode()) { 2183 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2184 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2185 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2186 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2187 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2188 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2189 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2190 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2191 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2192 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2193 return MCDisassembler::Fail; 2194 break; 2195 case ARM::VLD2b16: 2196 case ARM::VLD2b32: 2197 case ARM::VLD2b8: 2198 case ARM::VLD2b16wb_fixed: 2199 case ARM::VLD2b16wb_register: 2200 case ARM::VLD2b32wb_fixed: 2201 case ARM::VLD2b32wb_register: 2202 case ARM::VLD2b8wb_fixed: 2203 case ARM::VLD2b8wb_register: 2204 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 break; 2207 default: 2208 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2209 return MCDisassembler::Fail; 2210 } 2211 2212 // Second output register 2213 switch (Inst.getOpcode()) { 2214 case ARM::VLD3d8: 2215 case ARM::VLD3d16: 2216 case ARM::VLD3d32: 2217 case ARM::VLD3d8_UPD: 2218 case ARM::VLD3d16_UPD: 2219 case ARM::VLD3d32_UPD: 2220 case ARM::VLD4d8: 2221 case ARM::VLD4d16: 2222 case ARM::VLD4d32: 2223 case ARM::VLD4d8_UPD: 2224 case ARM::VLD4d16_UPD: 2225 case ARM::VLD4d32_UPD: 2226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2227 return MCDisassembler::Fail; 2228 break; 2229 case ARM::VLD3q8: 2230 case ARM::VLD3q16: 2231 case ARM::VLD3q32: 2232 case ARM::VLD3q8_UPD: 2233 case ARM::VLD3q16_UPD: 2234 case ARM::VLD3q32_UPD: 2235 case ARM::VLD4q8: 2236 case ARM::VLD4q16: 2237 case ARM::VLD4q32: 2238 case ARM::VLD4q8_UPD: 2239 case ARM::VLD4q16_UPD: 2240 case ARM::VLD4q32_UPD: 2241 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2242 return MCDisassembler::Fail; 2243 default: 2244 break; 2245 } 2246 2247 // Third output register 2248 switch(Inst.getOpcode()) { 2249 case ARM::VLD3d8: 2250 case ARM::VLD3d16: 2251 case ARM::VLD3d32: 2252 case ARM::VLD3d8_UPD: 2253 case ARM::VLD3d16_UPD: 2254 case ARM::VLD3d32_UPD: 2255 case ARM::VLD4d8: 2256 case ARM::VLD4d16: 2257 case ARM::VLD4d32: 2258 case ARM::VLD4d8_UPD: 2259 case ARM::VLD4d16_UPD: 2260 case ARM::VLD4d32_UPD: 2261 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2262 return MCDisassembler::Fail; 2263 break; 2264 case ARM::VLD3q8: 2265 case ARM::VLD3q16: 2266 case ARM::VLD3q32: 2267 case ARM::VLD3q8_UPD: 2268 case ARM::VLD3q16_UPD: 2269 case ARM::VLD3q32_UPD: 2270 case ARM::VLD4q8: 2271 case ARM::VLD4q16: 2272 case ARM::VLD4q32: 2273 case ARM::VLD4q8_UPD: 2274 case ARM::VLD4q16_UPD: 2275 case ARM::VLD4q32_UPD: 2276 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2277 return MCDisassembler::Fail; 2278 break; 2279 default: 2280 break; 2281 } 2282 2283 // Fourth output register 2284 switch (Inst.getOpcode()) { 2285 case ARM::VLD4d8: 2286 case ARM::VLD4d16: 2287 case ARM::VLD4d32: 2288 case ARM::VLD4d8_UPD: 2289 case ARM::VLD4d16_UPD: 2290 case ARM::VLD4d32_UPD: 2291 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2292 return MCDisassembler::Fail; 2293 break; 2294 case ARM::VLD4q8: 2295 case ARM::VLD4q16: 2296 case ARM::VLD4q32: 2297 case ARM::VLD4q8_UPD: 2298 case ARM::VLD4q16_UPD: 2299 case ARM::VLD4q32_UPD: 2300 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 break; 2303 default: 2304 break; 2305 } 2306 2307 // Writeback operand 2308 switch (Inst.getOpcode()) { 2309 case ARM::VLD1d8wb_fixed: 2310 case ARM::VLD1d16wb_fixed: 2311 case ARM::VLD1d32wb_fixed: 2312 case ARM::VLD1d64wb_fixed: 2313 case ARM::VLD1d8wb_register: 2314 case ARM::VLD1d16wb_register: 2315 case ARM::VLD1d32wb_register: 2316 case ARM::VLD1d64wb_register: 2317 case ARM::VLD1q8wb_fixed: 2318 case ARM::VLD1q16wb_fixed: 2319 case ARM::VLD1q32wb_fixed: 2320 case ARM::VLD1q64wb_fixed: 2321 case ARM::VLD1q8wb_register: 2322 case ARM::VLD1q16wb_register: 2323 case ARM::VLD1q32wb_register: 2324 case ARM::VLD1q64wb_register: 2325 case ARM::VLD1d8Twb_fixed: 2326 case ARM::VLD1d8Twb_register: 2327 case ARM::VLD1d16Twb_fixed: 2328 case ARM::VLD1d16Twb_register: 2329 case ARM::VLD1d32Twb_fixed: 2330 case ARM::VLD1d32Twb_register: 2331 case ARM::VLD1d64Twb_fixed: 2332 case ARM::VLD1d64Twb_register: 2333 case ARM::VLD1d8Qwb_fixed: 2334 case ARM::VLD1d8Qwb_register: 2335 case ARM::VLD1d16Qwb_fixed: 2336 case ARM::VLD1d16Qwb_register: 2337 case ARM::VLD1d32Qwb_fixed: 2338 case ARM::VLD1d32Qwb_register: 2339 case ARM::VLD1d64Qwb_fixed: 2340 case ARM::VLD1d64Qwb_register: 2341 case ARM::VLD2d8wb_fixed: 2342 case ARM::VLD2d16wb_fixed: 2343 case ARM::VLD2d32wb_fixed: 2344 case ARM::VLD2q8wb_fixed: 2345 case ARM::VLD2q16wb_fixed: 2346 case ARM::VLD2q32wb_fixed: 2347 case ARM::VLD2d8wb_register: 2348 case ARM::VLD2d16wb_register: 2349 case ARM::VLD2d32wb_register: 2350 case ARM::VLD2q8wb_register: 2351 case ARM::VLD2q16wb_register: 2352 case ARM::VLD2q32wb_register: 2353 case ARM::VLD2b8wb_fixed: 2354 case ARM::VLD2b16wb_fixed: 2355 case ARM::VLD2b32wb_fixed: 2356 case ARM::VLD2b8wb_register: 2357 case ARM::VLD2b16wb_register: 2358 case ARM::VLD2b32wb_register: 2359 Inst.addOperand(MCOperand::CreateImm(0)); 2360 break; 2361 case ARM::VLD3d8_UPD: 2362 case ARM::VLD3d16_UPD: 2363 case ARM::VLD3d32_UPD: 2364 case ARM::VLD3q8_UPD: 2365 case ARM::VLD3q16_UPD: 2366 case ARM::VLD3q32_UPD: 2367 case ARM::VLD4d8_UPD: 2368 case ARM::VLD4d16_UPD: 2369 case ARM::VLD4d32_UPD: 2370 case ARM::VLD4q8_UPD: 2371 case ARM::VLD4q16_UPD: 2372 case ARM::VLD4q32_UPD: 2373 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2374 return MCDisassembler::Fail; 2375 break; 2376 default: 2377 break; 2378 } 2379 2380 // AddrMode6 Base (register+alignment) 2381 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2382 return MCDisassembler::Fail; 2383 2384 // AddrMode6 Offset (register) 2385 switch (Inst.getOpcode()) { 2386 default: 2387 // The below have been updated to have explicit am6offset split 2388 // between fixed and register offset. For those instructions not 2389 // yet updated, we need to add an additional reg0 operand for the 2390 // fixed variant. 2391 // 2392 // The fixed offset encodes as Rm == 0xd, so we check for that. 2393 if (Rm == 0xd) { 2394 Inst.addOperand(MCOperand::CreateReg(0)); 2395 break; 2396 } 2397 // Fall through to handle the register offset variant. 2398 case ARM::VLD1d8wb_fixed: 2399 case ARM::VLD1d16wb_fixed: 2400 case ARM::VLD1d32wb_fixed: 2401 case ARM::VLD1d64wb_fixed: 2402 case ARM::VLD1d8Twb_fixed: 2403 case ARM::VLD1d16Twb_fixed: 2404 case ARM::VLD1d32Twb_fixed: 2405 case ARM::VLD1d64Twb_fixed: 2406 case ARM::VLD1d8Qwb_fixed: 2407 case ARM::VLD1d16Qwb_fixed: 2408 case ARM::VLD1d32Qwb_fixed: 2409 case ARM::VLD1d64Qwb_fixed: 2410 case ARM::VLD1d8wb_register: 2411 case ARM::VLD1d16wb_register: 2412 case ARM::VLD1d32wb_register: 2413 case ARM::VLD1d64wb_register: 2414 case ARM::VLD1q8wb_fixed: 2415 case ARM::VLD1q16wb_fixed: 2416 case ARM::VLD1q32wb_fixed: 2417 case ARM::VLD1q64wb_fixed: 2418 case ARM::VLD1q8wb_register: 2419 case ARM::VLD1q16wb_register: 2420 case ARM::VLD1q32wb_register: 2421 case ARM::VLD1q64wb_register: 2422 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2423 // variant encodes Rm == 0xf. Anything else is a register offset post- 2424 // increment and we need to add the register operand to the instruction. 2425 if (Rm != 0xD && Rm != 0xF && 2426 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2427 return MCDisassembler::Fail; 2428 break; 2429 case ARM::VLD2d8wb_fixed: 2430 case ARM::VLD2d16wb_fixed: 2431 case ARM::VLD2d32wb_fixed: 2432 case ARM::VLD2b8wb_fixed: 2433 case ARM::VLD2b16wb_fixed: 2434 case ARM::VLD2b32wb_fixed: 2435 case ARM::VLD2q8wb_fixed: 2436 case ARM::VLD2q16wb_fixed: 2437 case ARM::VLD2q32wb_fixed: 2438 break; 2439 } 2440 2441 return S; 2442 } 2443 2444 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2445 uint64_t Address, const void *Decoder) { 2446 unsigned type = fieldFromInstruction(Insn, 8, 4); 2447 unsigned align = fieldFromInstruction(Insn, 4, 2); 2448 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2449 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2450 if (type == 10 && align == 3) return MCDisassembler::Fail; 2451 2452 unsigned load = fieldFromInstruction(Insn, 21, 1); 2453 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2454 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2455 } 2456 2457 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2458 uint64_t Address, const void *Decoder) { 2459 unsigned size = fieldFromInstruction(Insn, 6, 2); 2460 if (size == 3) return MCDisassembler::Fail; 2461 2462 unsigned type = fieldFromInstruction(Insn, 8, 4); 2463 unsigned align = fieldFromInstruction(Insn, 4, 2); 2464 if (type == 8 && align == 3) return MCDisassembler::Fail; 2465 if (type == 9 && align == 3) return MCDisassembler::Fail; 2466 2467 unsigned load = fieldFromInstruction(Insn, 21, 1); 2468 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2469 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2470 } 2471 2472 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2473 uint64_t Address, const void *Decoder) { 2474 unsigned size = fieldFromInstruction(Insn, 6, 2); 2475 if (size == 3) return MCDisassembler::Fail; 2476 2477 unsigned align = fieldFromInstruction(Insn, 4, 2); 2478 if (align & 2) return MCDisassembler::Fail; 2479 2480 unsigned load = fieldFromInstruction(Insn, 21, 1); 2481 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2482 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2483 } 2484 2485 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2486 uint64_t Address, const void *Decoder) { 2487 unsigned size = fieldFromInstruction(Insn, 6, 2); 2488 if (size == 3) return MCDisassembler::Fail; 2489 2490 unsigned load = fieldFromInstruction(Insn, 21, 1); 2491 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2492 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2493 } 2494 2495 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2496 uint64_t Address, const void *Decoder) { 2497 DecodeStatus S = MCDisassembler::Success; 2498 2499 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2500 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2501 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2502 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2503 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2504 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2505 2506 // Writeback Operand 2507 switch (Inst.getOpcode()) { 2508 case ARM::VST1d8wb_fixed: 2509 case ARM::VST1d16wb_fixed: 2510 case ARM::VST1d32wb_fixed: 2511 case ARM::VST1d64wb_fixed: 2512 case ARM::VST1d8wb_register: 2513 case ARM::VST1d16wb_register: 2514 case ARM::VST1d32wb_register: 2515 case ARM::VST1d64wb_register: 2516 case ARM::VST1q8wb_fixed: 2517 case ARM::VST1q16wb_fixed: 2518 case ARM::VST1q32wb_fixed: 2519 case ARM::VST1q64wb_fixed: 2520 case ARM::VST1q8wb_register: 2521 case ARM::VST1q16wb_register: 2522 case ARM::VST1q32wb_register: 2523 case ARM::VST1q64wb_register: 2524 case ARM::VST1d8Twb_fixed: 2525 case ARM::VST1d16Twb_fixed: 2526 case ARM::VST1d32Twb_fixed: 2527 case ARM::VST1d64Twb_fixed: 2528 case ARM::VST1d8Twb_register: 2529 case ARM::VST1d16Twb_register: 2530 case ARM::VST1d32Twb_register: 2531 case ARM::VST1d64Twb_register: 2532 case ARM::VST1d8Qwb_fixed: 2533 case ARM::VST1d16Qwb_fixed: 2534 case ARM::VST1d32Qwb_fixed: 2535 case ARM::VST1d64Qwb_fixed: 2536 case ARM::VST1d8Qwb_register: 2537 case ARM::VST1d16Qwb_register: 2538 case ARM::VST1d32Qwb_register: 2539 case ARM::VST1d64Qwb_register: 2540 case ARM::VST2d8wb_fixed: 2541 case ARM::VST2d16wb_fixed: 2542 case ARM::VST2d32wb_fixed: 2543 case ARM::VST2d8wb_register: 2544 case ARM::VST2d16wb_register: 2545 case ARM::VST2d32wb_register: 2546 case ARM::VST2q8wb_fixed: 2547 case ARM::VST2q16wb_fixed: 2548 case ARM::VST2q32wb_fixed: 2549 case ARM::VST2q8wb_register: 2550 case ARM::VST2q16wb_register: 2551 case ARM::VST2q32wb_register: 2552 case ARM::VST2b8wb_fixed: 2553 case ARM::VST2b16wb_fixed: 2554 case ARM::VST2b32wb_fixed: 2555 case ARM::VST2b8wb_register: 2556 case ARM::VST2b16wb_register: 2557 case ARM::VST2b32wb_register: 2558 if (Rm == 0xF) 2559 return MCDisassembler::Fail; 2560 Inst.addOperand(MCOperand::CreateImm(0)); 2561 break; 2562 case ARM::VST3d8_UPD: 2563 case ARM::VST3d16_UPD: 2564 case ARM::VST3d32_UPD: 2565 case ARM::VST3q8_UPD: 2566 case ARM::VST3q16_UPD: 2567 case ARM::VST3q32_UPD: 2568 case ARM::VST4d8_UPD: 2569 case ARM::VST4d16_UPD: 2570 case ARM::VST4d32_UPD: 2571 case ARM::VST4q8_UPD: 2572 case ARM::VST4q16_UPD: 2573 case ARM::VST4q32_UPD: 2574 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2575 return MCDisassembler::Fail; 2576 break; 2577 default: 2578 break; 2579 } 2580 2581 // AddrMode6 Base (register+alignment) 2582 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2583 return MCDisassembler::Fail; 2584 2585 // AddrMode6 Offset (register) 2586 switch (Inst.getOpcode()) { 2587 default: 2588 if (Rm == 0xD) 2589 Inst.addOperand(MCOperand::CreateReg(0)); 2590 else if (Rm != 0xF) { 2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 } 2594 break; 2595 case ARM::VST1d8wb_fixed: 2596 case ARM::VST1d16wb_fixed: 2597 case ARM::VST1d32wb_fixed: 2598 case ARM::VST1d64wb_fixed: 2599 case ARM::VST1q8wb_fixed: 2600 case ARM::VST1q16wb_fixed: 2601 case ARM::VST1q32wb_fixed: 2602 case ARM::VST1q64wb_fixed: 2603 case ARM::VST1d8Twb_fixed: 2604 case ARM::VST1d16Twb_fixed: 2605 case ARM::VST1d32Twb_fixed: 2606 case ARM::VST1d64Twb_fixed: 2607 case ARM::VST1d8Qwb_fixed: 2608 case ARM::VST1d16Qwb_fixed: 2609 case ARM::VST1d32Qwb_fixed: 2610 case ARM::VST1d64Qwb_fixed: 2611 case ARM::VST2d8wb_fixed: 2612 case ARM::VST2d16wb_fixed: 2613 case ARM::VST2d32wb_fixed: 2614 case ARM::VST2q8wb_fixed: 2615 case ARM::VST2q16wb_fixed: 2616 case ARM::VST2q32wb_fixed: 2617 case ARM::VST2b8wb_fixed: 2618 case ARM::VST2b16wb_fixed: 2619 case ARM::VST2b32wb_fixed: 2620 break; 2621 } 2622 2623 2624 // First input register 2625 switch (Inst.getOpcode()) { 2626 case ARM::VST1q16: 2627 case ARM::VST1q32: 2628 case ARM::VST1q64: 2629 case ARM::VST1q8: 2630 case ARM::VST1q16wb_fixed: 2631 case ARM::VST1q16wb_register: 2632 case ARM::VST1q32wb_fixed: 2633 case ARM::VST1q32wb_register: 2634 case ARM::VST1q64wb_fixed: 2635 case ARM::VST1q64wb_register: 2636 case ARM::VST1q8wb_fixed: 2637 case ARM::VST1q8wb_register: 2638 case ARM::VST2d16: 2639 case ARM::VST2d32: 2640 case ARM::VST2d8: 2641 case ARM::VST2d16wb_fixed: 2642 case ARM::VST2d16wb_register: 2643 case ARM::VST2d32wb_fixed: 2644 case ARM::VST2d32wb_register: 2645 case ARM::VST2d8wb_fixed: 2646 case ARM::VST2d8wb_register: 2647 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 break; 2650 case ARM::VST2b16: 2651 case ARM::VST2b32: 2652 case ARM::VST2b8: 2653 case ARM::VST2b16wb_fixed: 2654 case ARM::VST2b16wb_register: 2655 case ARM::VST2b32wb_fixed: 2656 case ARM::VST2b32wb_register: 2657 case ARM::VST2b8wb_fixed: 2658 case ARM::VST2b8wb_register: 2659 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2660 return MCDisassembler::Fail; 2661 break; 2662 default: 2663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2664 return MCDisassembler::Fail; 2665 } 2666 2667 // Second input register 2668 switch (Inst.getOpcode()) { 2669 case ARM::VST3d8: 2670 case ARM::VST3d16: 2671 case ARM::VST3d32: 2672 case ARM::VST3d8_UPD: 2673 case ARM::VST3d16_UPD: 2674 case ARM::VST3d32_UPD: 2675 case ARM::VST4d8: 2676 case ARM::VST4d16: 2677 case ARM::VST4d32: 2678 case ARM::VST4d8_UPD: 2679 case ARM::VST4d16_UPD: 2680 case ARM::VST4d32_UPD: 2681 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2682 return MCDisassembler::Fail; 2683 break; 2684 case ARM::VST3q8: 2685 case ARM::VST3q16: 2686 case ARM::VST3q32: 2687 case ARM::VST3q8_UPD: 2688 case ARM::VST3q16_UPD: 2689 case ARM::VST3q32_UPD: 2690 case ARM::VST4q8: 2691 case ARM::VST4q16: 2692 case ARM::VST4q32: 2693 case ARM::VST4q8_UPD: 2694 case ARM::VST4q16_UPD: 2695 case ARM::VST4q32_UPD: 2696 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 break; 2699 default: 2700 break; 2701 } 2702 2703 // Third input register 2704 switch (Inst.getOpcode()) { 2705 case ARM::VST3d8: 2706 case ARM::VST3d16: 2707 case ARM::VST3d32: 2708 case ARM::VST3d8_UPD: 2709 case ARM::VST3d16_UPD: 2710 case ARM::VST3d32_UPD: 2711 case ARM::VST4d8: 2712 case ARM::VST4d16: 2713 case ARM::VST4d32: 2714 case ARM::VST4d8_UPD: 2715 case ARM::VST4d16_UPD: 2716 case ARM::VST4d32_UPD: 2717 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 break; 2720 case ARM::VST3q8: 2721 case ARM::VST3q16: 2722 case ARM::VST3q32: 2723 case ARM::VST3q8_UPD: 2724 case ARM::VST3q16_UPD: 2725 case ARM::VST3q32_UPD: 2726 case ARM::VST4q8: 2727 case ARM::VST4q16: 2728 case ARM::VST4q32: 2729 case ARM::VST4q8_UPD: 2730 case ARM::VST4q16_UPD: 2731 case ARM::VST4q32_UPD: 2732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 // Fourth input register 2740 switch (Inst.getOpcode()) { 2741 case ARM::VST4d8: 2742 case ARM::VST4d16: 2743 case ARM::VST4d32: 2744 case ARM::VST4d8_UPD: 2745 case ARM::VST4d16_UPD: 2746 case ARM::VST4d32_UPD: 2747 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 break; 2750 case ARM::VST4q8: 2751 case ARM::VST4q16: 2752 case ARM::VST4q32: 2753 case ARM::VST4q8_UPD: 2754 case ARM::VST4q16_UPD: 2755 case ARM::VST4q32_UPD: 2756 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 break; 2759 default: 2760 break; 2761 } 2762 2763 return S; 2764 } 2765 2766 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2767 uint64_t Address, const void *Decoder) { 2768 DecodeStatus S = MCDisassembler::Success; 2769 2770 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2771 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2772 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2773 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2774 unsigned align = fieldFromInstruction(Insn, 4, 1); 2775 unsigned size = fieldFromInstruction(Insn, 6, 2); 2776 2777 if (size == 0 && align == 1) 2778 return MCDisassembler::Fail; 2779 align *= (1 << size); 2780 2781 switch (Inst.getOpcode()) { 2782 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2783 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2784 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2785 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2786 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 break; 2789 default: 2790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2791 return MCDisassembler::Fail; 2792 break; 2793 } 2794 if (Rm != 0xF) { 2795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2796 return MCDisassembler::Fail; 2797 } 2798 2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 Inst.addOperand(MCOperand::CreateImm(align)); 2802 2803 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2804 // variant encodes Rm == 0xf. Anything else is a register offset post- 2805 // increment and we need to add the register operand to the instruction. 2806 if (Rm != 0xD && Rm != 0xF && 2807 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2808 return MCDisassembler::Fail; 2809 2810 return S; 2811 } 2812 2813 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2814 uint64_t Address, const void *Decoder) { 2815 DecodeStatus S = MCDisassembler::Success; 2816 2817 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2818 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2819 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2820 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2821 unsigned align = fieldFromInstruction(Insn, 4, 1); 2822 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2823 align *= 2*size; 2824 2825 switch (Inst.getOpcode()) { 2826 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2827 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2828 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2829 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2830 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 break; 2833 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2834 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2835 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2836 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2837 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2838 return MCDisassembler::Fail; 2839 break; 2840 default: 2841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 break; 2844 } 2845 2846 if (Rm != 0xF) 2847 Inst.addOperand(MCOperand::CreateImm(0)); 2848 2849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2850 return MCDisassembler::Fail; 2851 Inst.addOperand(MCOperand::CreateImm(align)); 2852 2853 if (Rm != 0xD && Rm != 0xF) { 2854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2855 return MCDisassembler::Fail; 2856 } 2857 2858 return S; 2859 } 2860 2861 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2862 uint64_t Address, const void *Decoder) { 2863 DecodeStatus S = MCDisassembler::Success; 2864 2865 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2866 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2867 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2868 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2869 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2870 2871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2872 return MCDisassembler::Fail; 2873 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2874 return MCDisassembler::Fail; 2875 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2876 return MCDisassembler::Fail; 2877 if (Rm != 0xF) { 2878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 } 2881 2882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2883 return MCDisassembler::Fail; 2884 Inst.addOperand(MCOperand::CreateImm(0)); 2885 2886 if (Rm == 0xD) 2887 Inst.addOperand(MCOperand::CreateReg(0)); 2888 else if (Rm != 0xF) { 2889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 } 2892 2893 return S; 2894 } 2895 2896 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2897 uint64_t Address, const void *Decoder) { 2898 DecodeStatus S = MCDisassembler::Success; 2899 2900 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2901 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2902 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2903 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2904 unsigned size = fieldFromInstruction(Insn, 6, 2); 2905 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2906 unsigned align = fieldFromInstruction(Insn, 4, 1); 2907 2908 if (size == 0x3) { 2909 if (align == 0) 2910 return MCDisassembler::Fail; 2911 size = 4; 2912 align = 16; 2913 } else { 2914 if (size == 2) { 2915 size = 1 << size; 2916 align *= 8; 2917 } else { 2918 size = 1 << size; 2919 align *= 4*size; 2920 } 2921 } 2922 2923 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 if (Rm != 0xF) { 2932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2933 return MCDisassembler::Fail; 2934 } 2935 2936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 Inst.addOperand(MCOperand::CreateImm(align)); 2939 2940 if (Rm == 0xD) 2941 Inst.addOperand(MCOperand::CreateReg(0)); 2942 else if (Rm != 0xF) { 2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 } 2946 2947 return S; 2948 } 2949 2950 static DecodeStatus 2951 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2952 uint64_t Address, const void *Decoder) { 2953 DecodeStatus S = MCDisassembler::Success; 2954 2955 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2956 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2957 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2958 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2959 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2960 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2961 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2962 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2963 2964 if (Q) { 2965 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2966 return MCDisassembler::Fail; 2967 } else { 2968 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 } 2971 2972 Inst.addOperand(MCOperand::CreateImm(imm)); 2973 2974 switch (Inst.getOpcode()) { 2975 case ARM::VORRiv4i16: 2976 case ARM::VORRiv2i32: 2977 case ARM::VBICiv4i16: 2978 case ARM::VBICiv2i32: 2979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 break; 2982 case ARM::VORRiv8i16: 2983 case ARM::VORRiv4i32: 2984 case ARM::VBICiv8i16: 2985 case ARM::VBICiv4i32: 2986 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2987 return MCDisassembler::Fail; 2988 break; 2989 default: 2990 break; 2991 } 2992 2993 return S; 2994 } 2995 2996 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2997 uint64_t Address, const void *Decoder) { 2998 DecodeStatus S = MCDisassembler::Success; 2999 3000 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3001 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3002 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3003 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3004 unsigned size = fieldFromInstruction(Insn, 18, 2); 3005 3006 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3009 return MCDisassembler::Fail; 3010 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3011 3012 return S; 3013 } 3014 3015 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3016 uint64_t Address, const void *Decoder) { 3017 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3018 return MCDisassembler::Success; 3019 } 3020 3021 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3022 uint64_t Address, const void *Decoder) { 3023 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3024 return MCDisassembler::Success; 3025 } 3026 3027 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3028 uint64_t Address, const void *Decoder) { 3029 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3030 return MCDisassembler::Success; 3031 } 3032 3033 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3034 uint64_t Address, const void *Decoder) { 3035 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3036 return MCDisassembler::Success; 3037 } 3038 3039 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3040 uint64_t Address, const void *Decoder) { 3041 DecodeStatus S = MCDisassembler::Success; 3042 3043 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3044 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3045 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3046 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3047 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3048 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3049 unsigned op = fieldFromInstruction(Insn, 6, 1); 3050 3051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3052 return MCDisassembler::Fail; 3053 if (op) { 3054 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3055 return MCDisassembler::Fail; // Writeback 3056 } 3057 3058 switch (Inst.getOpcode()) { 3059 case ARM::VTBL2: 3060 case ARM::VTBX2: 3061 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3062 return MCDisassembler::Fail; 3063 break; 3064 default: 3065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 } 3068 3069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 3072 return S; 3073 } 3074 3075 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3076 uint64_t Address, const void *Decoder) { 3077 DecodeStatus S = MCDisassembler::Success; 3078 3079 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3080 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3081 3082 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 3085 switch(Inst.getOpcode()) { 3086 default: 3087 return MCDisassembler::Fail; 3088 case ARM::tADR: 3089 break; // tADR does not explicitly represent the PC as an operand. 3090 case ARM::tADDrSPi: 3091 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3092 break; 3093 } 3094 3095 Inst.addOperand(MCOperand::CreateImm(imm)); 3096 return S; 3097 } 3098 3099 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3100 uint64_t Address, const void *Decoder) { 3101 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3102 true, 2, Inst, Decoder)) 3103 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3104 return MCDisassembler::Success; 3105 } 3106 3107 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3108 uint64_t Address, const void *Decoder) { 3109 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3110 true, 4, Inst, Decoder)) 3111 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3112 return MCDisassembler::Success; 3113 } 3114 3115 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3116 uint64_t Address, const void *Decoder) { 3117 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3118 true, 2, Inst, Decoder)) 3119 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3120 return MCDisassembler::Success; 3121 } 3122 3123 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3124 uint64_t Address, const void *Decoder) { 3125 DecodeStatus S = MCDisassembler::Success; 3126 3127 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3128 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3129 3130 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3131 return MCDisassembler::Fail; 3132 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3133 return MCDisassembler::Fail; 3134 3135 return S; 3136 } 3137 3138 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3139 uint64_t Address, const void *Decoder) { 3140 DecodeStatus S = MCDisassembler::Success; 3141 3142 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3143 unsigned imm = fieldFromInstruction(Val, 3, 5); 3144 3145 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 Inst.addOperand(MCOperand::CreateImm(imm)); 3148 3149 return S; 3150 } 3151 3152 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3153 uint64_t Address, const void *Decoder) { 3154 unsigned imm = Val << 2; 3155 3156 Inst.addOperand(MCOperand::CreateImm(imm)); 3157 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3158 3159 return MCDisassembler::Success; 3160 } 3161 3162 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3163 uint64_t Address, const void *Decoder) { 3164 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3165 Inst.addOperand(MCOperand::CreateImm(Val)); 3166 3167 return MCDisassembler::Success; 3168 } 3169 3170 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3171 uint64_t Address, const void *Decoder) { 3172 DecodeStatus S = MCDisassembler::Success; 3173 3174 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3175 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3176 unsigned imm = fieldFromInstruction(Val, 0, 2); 3177 3178 // Thumb stores cannot use PC as dest register. 3179 switch (Inst.getOpcode()) { 3180 case ARM::t2STRHs: 3181 case ARM::t2STRBs: 3182 case ARM::t2STRs: 3183 if (Rn == 15) 3184 return MCDisassembler::Fail; 3185 default: 3186 break; 3187 } 3188 3189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3192 return MCDisassembler::Fail; 3193 Inst.addOperand(MCOperand::CreateImm(imm)); 3194 3195 return S; 3196 } 3197 3198 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3199 uint64_t Address, const void *Decoder) { 3200 DecodeStatus S = MCDisassembler::Success; 3201 3202 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3203 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3204 3205 if (Rn == 15) { 3206 switch (Inst.getOpcode()) { 3207 case ARM::t2LDRBs: 3208 Inst.setOpcode(ARM::t2LDRBpci); 3209 break; 3210 case ARM::t2LDRHs: 3211 Inst.setOpcode(ARM::t2LDRHpci); 3212 break; 3213 case ARM::t2LDRSHs: 3214 Inst.setOpcode(ARM::t2LDRSHpci); 3215 break; 3216 case ARM::t2LDRSBs: 3217 Inst.setOpcode(ARM::t2LDRSBpci); 3218 break; 3219 case ARM::t2LDRs: 3220 Inst.setOpcode(ARM::t2LDRpci); 3221 break; 3222 case ARM::t2PLDs: 3223 Inst.setOpcode(ARM::t2PLDpci); 3224 break; 3225 case ARM::t2PLIs: 3226 Inst.setOpcode(ARM::t2PLIpci); 3227 break; 3228 default: 3229 return MCDisassembler::Fail; 3230 } 3231 3232 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3233 } 3234 3235 if (Rt == 15) { 3236 switch (Inst.getOpcode()) { 3237 case ARM::t2LDRSHs: 3238 return MCDisassembler::Fail; 3239 case ARM::t2LDRHs: 3240 // FIXME: this instruction is only available with MP extensions, 3241 // this should be checked first but we don't have access to the 3242 // feature bits here. 3243 Inst.setOpcode(ARM::t2PLDWs); 3244 break; 3245 default: 3246 break; 3247 } 3248 } 3249 3250 switch (Inst.getOpcode()) { 3251 case ARM::t2PLDs: 3252 case ARM::t2PLDWs: 3253 case ARM::t2PLIs: 3254 break; 3255 default: 3256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3257 return MCDisassembler::Fail; 3258 } 3259 3260 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3261 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3262 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3263 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3264 return MCDisassembler::Fail; 3265 3266 return S; 3267 } 3268 3269 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3270 uint64_t Address, const void* Decoder) { 3271 DecodeStatus S = MCDisassembler::Success; 3272 3273 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3274 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3275 unsigned U = fieldFromInstruction(Insn, 9, 1); 3276 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3277 imm |= (U << 8); 3278 imm |= (Rn << 9); 3279 3280 if (Rn == 15) { 3281 switch (Inst.getOpcode()) { 3282 case ARM::t2LDRi8: 3283 Inst.setOpcode(ARM::t2LDRpci); 3284 break; 3285 case ARM::t2LDRBi8: 3286 Inst.setOpcode(ARM::t2LDRBpci); 3287 break; 3288 case ARM::t2LDRSBi8: 3289 Inst.setOpcode(ARM::t2LDRSBpci); 3290 break; 3291 case ARM::t2LDRHi8: 3292 Inst.setOpcode(ARM::t2LDRHpci); 3293 break; 3294 case ARM::t2LDRSHi8: 3295 Inst.setOpcode(ARM::t2LDRSHpci); 3296 break; 3297 case ARM::t2PLDi8: 3298 Inst.setOpcode(ARM::t2PLDpci); 3299 break; 3300 case ARM::t2PLIi8: 3301 Inst.setOpcode(ARM::t2PLIpci); 3302 break; 3303 default: 3304 return MCDisassembler::Fail; 3305 } 3306 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3307 } 3308 3309 if (Rt == 15) { 3310 switch (Inst.getOpcode()) { 3311 case ARM::t2LDRSHi8: 3312 return MCDisassembler::Fail; 3313 default: 3314 break; 3315 } 3316 } 3317 3318 switch (Inst.getOpcode()) { 3319 case ARM::t2PLDi8: 3320 case ARM::t2PLIi8: 3321 break; 3322 default: 3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 } 3326 3327 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 return S; 3330 } 3331 3332 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3333 uint64_t Address, const void* Decoder) { 3334 DecodeStatus S = MCDisassembler::Success; 3335 3336 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3337 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3338 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3339 imm |= (Rn << 13); 3340 3341 if (Rn == 15) { 3342 switch (Inst.getOpcode()) { 3343 case ARM::t2LDRi12: 3344 Inst.setOpcode(ARM::t2LDRpci); 3345 break; 3346 case ARM::t2LDRHi12: 3347 Inst.setOpcode(ARM::t2LDRHpci); 3348 break; 3349 case ARM::t2LDRSHi12: 3350 Inst.setOpcode(ARM::t2LDRSHpci); 3351 break; 3352 case ARM::t2LDRBi12: 3353 Inst.setOpcode(ARM::t2LDRBpci); 3354 break; 3355 case ARM::t2LDRSBi12: 3356 Inst.setOpcode(ARM::t2LDRSBpci); 3357 break; 3358 case ARM::t2PLDi12: 3359 Inst.setOpcode(ARM::t2PLDpci); 3360 break; 3361 case ARM::t2PLIi12: 3362 Inst.setOpcode(ARM::t2PLIpci); 3363 break; 3364 default: 3365 return MCDisassembler::Fail; 3366 } 3367 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3368 } 3369 3370 if (Rt == 15) { 3371 switch (Inst.getOpcode()) { 3372 case ARM::t2LDRSHi12: 3373 return MCDisassembler::Fail; 3374 case ARM::t2LDRHi12: 3375 Inst.setOpcode(ARM::t2PLDi12); 3376 break; 3377 default: 3378 break; 3379 } 3380 } 3381 3382 switch (Inst.getOpcode()) { 3383 case ARM::t2PLDi12: 3384 case ARM::t2PLIi12: 3385 break; 3386 default: 3387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 } 3390 3391 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 return S; 3394 } 3395 3396 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3397 uint64_t Address, const void* Decoder) { 3398 DecodeStatus S = MCDisassembler::Success; 3399 3400 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3401 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3402 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3403 imm |= (Rn << 9); 3404 3405 if (Rn == 15) { 3406 switch (Inst.getOpcode()) { 3407 case ARM::t2LDRT: 3408 Inst.setOpcode(ARM::t2LDRpci); 3409 break; 3410 case ARM::t2LDRBT: 3411 Inst.setOpcode(ARM::t2LDRBpci); 3412 break; 3413 case ARM::t2LDRHT: 3414 Inst.setOpcode(ARM::t2LDRHpci); 3415 break; 3416 case ARM::t2LDRSBT: 3417 Inst.setOpcode(ARM::t2LDRSBpci); 3418 break; 3419 case ARM::t2LDRSHT: 3420 Inst.setOpcode(ARM::t2LDRSHpci); 3421 break; 3422 default: 3423 return MCDisassembler::Fail; 3424 } 3425 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3426 } 3427 3428 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 return S; 3433 } 3434 3435 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3436 uint64_t Address, const void* Decoder) { 3437 DecodeStatus S = MCDisassembler::Success; 3438 3439 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3440 unsigned U = fieldFromInstruction(Insn, 23, 1); 3441 int imm = fieldFromInstruction(Insn, 0, 12); 3442 3443 if (Rt == 15) { 3444 switch (Inst.getOpcode()) { 3445 case ARM::t2LDRBpci: 3446 case ARM::t2LDRHpci: 3447 Inst.setOpcode(ARM::t2PLDpci); 3448 break; 3449 case ARM::t2LDRSBpci: 3450 Inst.setOpcode(ARM::t2PLIpci); 3451 break; 3452 case ARM::t2LDRSHpci: 3453 return MCDisassembler::Fail; 3454 default: 3455 break; 3456 } 3457 } 3458 3459 switch(Inst.getOpcode()) { 3460 case ARM::t2PLDpci: 3461 case ARM::t2PLIpci: 3462 break; 3463 default: 3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 } 3467 3468 if (!U) { 3469 // Special case for #-0. 3470 if (imm == 0) 3471 imm = INT32_MIN; 3472 else 3473 imm = -imm; 3474 } 3475 Inst.addOperand(MCOperand::CreateImm(imm)); 3476 3477 return S; 3478 } 3479 3480 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3481 uint64_t Address, const void *Decoder) { 3482 if (Val == 0) 3483 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3484 else { 3485 int imm = Val & 0xFF; 3486 3487 if (!(Val & 0x100)) imm *= -1; 3488 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3489 } 3490 3491 return MCDisassembler::Success; 3492 } 3493 3494 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3495 uint64_t Address, const void *Decoder) { 3496 DecodeStatus S = MCDisassembler::Success; 3497 3498 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3499 unsigned imm = fieldFromInstruction(Val, 0, 9); 3500 3501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3502 return MCDisassembler::Fail; 3503 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 3506 return S; 3507 } 3508 3509 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3510 uint64_t Address, const void *Decoder) { 3511 DecodeStatus S = MCDisassembler::Success; 3512 3513 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3514 unsigned imm = fieldFromInstruction(Val, 0, 8); 3515 3516 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3517 return MCDisassembler::Fail; 3518 3519 Inst.addOperand(MCOperand::CreateImm(imm)); 3520 3521 return S; 3522 } 3523 3524 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3525 uint64_t Address, const void *Decoder) { 3526 int imm = Val & 0xFF; 3527 if (Val == 0) 3528 imm = INT32_MIN; 3529 else if (!(Val & 0x100)) 3530 imm *= -1; 3531 Inst.addOperand(MCOperand::CreateImm(imm)); 3532 3533 return MCDisassembler::Success; 3534 } 3535 3536 3537 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3538 uint64_t Address, const void *Decoder) { 3539 DecodeStatus S = MCDisassembler::Success; 3540 3541 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3542 unsigned imm = fieldFromInstruction(Val, 0, 9); 3543 3544 // Thumb stores cannot use PC as dest register. 3545 switch (Inst.getOpcode()) { 3546 case ARM::t2STRT: 3547 case ARM::t2STRBT: 3548 case ARM::t2STRHT: 3549 case ARM::t2STRi8: 3550 case ARM::t2STRHi8: 3551 case ARM::t2STRBi8: 3552 if (Rn == 15) 3553 return MCDisassembler::Fail; 3554 break; 3555 default: 3556 break; 3557 } 3558 3559 // Some instructions always use an additive offset. 3560 switch (Inst.getOpcode()) { 3561 case ARM::t2LDRT: 3562 case ARM::t2LDRBT: 3563 case ARM::t2LDRHT: 3564 case ARM::t2LDRSBT: 3565 case ARM::t2LDRSHT: 3566 case ARM::t2STRT: 3567 case ARM::t2STRBT: 3568 case ARM::t2STRHT: 3569 imm |= 0x100; 3570 break; 3571 default: 3572 break; 3573 } 3574 3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 3580 return S; 3581 } 3582 3583 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3584 uint64_t Address, const void *Decoder) { 3585 DecodeStatus S = MCDisassembler::Success; 3586 3587 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3588 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3589 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3590 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3591 addr |= Rn << 9; 3592 unsigned load = fieldFromInstruction(Insn, 20, 1); 3593 3594 if (Rn == 15) { 3595 switch (Inst.getOpcode()) { 3596 case ARM::t2LDR_PRE: 3597 case ARM::t2LDR_POST: 3598 Inst.setOpcode(ARM::t2LDRpci); 3599 break; 3600 case ARM::t2LDRB_PRE: 3601 case ARM::t2LDRB_POST: 3602 Inst.setOpcode(ARM::t2LDRBpci); 3603 break; 3604 case ARM::t2LDRH_PRE: 3605 case ARM::t2LDRH_POST: 3606 Inst.setOpcode(ARM::t2LDRHpci); 3607 break; 3608 case ARM::t2LDRSB_PRE: 3609 case ARM::t2LDRSB_POST: 3610 if (Rt == 15) 3611 Inst.setOpcode(ARM::t2PLIpci); 3612 else 3613 Inst.setOpcode(ARM::t2LDRSBpci); 3614 break; 3615 case ARM::t2LDRSH_PRE: 3616 case ARM::t2LDRSH_POST: 3617 Inst.setOpcode(ARM::t2LDRSHpci); 3618 break; 3619 default: 3620 return MCDisassembler::Fail; 3621 } 3622 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3623 } 3624 3625 if (!load) { 3626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 } 3629 3630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 3633 if (load) { 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 } 3637 3638 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 3641 return S; 3642 } 3643 3644 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3645 uint64_t Address, const void *Decoder) { 3646 DecodeStatus S = MCDisassembler::Success; 3647 3648 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3649 unsigned imm = fieldFromInstruction(Val, 0, 12); 3650 3651 // Thumb stores cannot use PC as dest register. 3652 switch (Inst.getOpcode()) { 3653 case ARM::t2STRi12: 3654 case ARM::t2STRBi12: 3655 case ARM::t2STRHi12: 3656 if (Rn == 15) 3657 return MCDisassembler::Fail; 3658 default: 3659 break; 3660 } 3661 3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3663 return MCDisassembler::Fail; 3664 Inst.addOperand(MCOperand::CreateImm(imm)); 3665 3666 return S; 3667 } 3668 3669 3670 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3671 uint64_t Address, const void *Decoder) { 3672 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3673 3674 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3675 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3676 Inst.addOperand(MCOperand::CreateImm(imm)); 3677 3678 return MCDisassembler::Success; 3679 } 3680 3681 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3682 uint64_t Address, const void *Decoder) { 3683 DecodeStatus S = MCDisassembler::Success; 3684 3685 if (Inst.getOpcode() == ARM::tADDrSP) { 3686 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3687 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3688 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 } else if (Inst.getOpcode() == ARM::tADDspr) { 3695 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3696 3697 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3698 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3700 return MCDisassembler::Fail; 3701 } 3702 3703 return S; 3704 } 3705 3706 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3707 uint64_t Address, const void *Decoder) { 3708 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3709 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3710 3711 Inst.addOperand(MCOperand::CreateImm(imod)); 3712 Inst.addOperand(MCOperand::CreateImm(flags)); 3713 3714 return MCDisassembler::Success; 3715 } 3716 3717 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3718 uint64_t Address, const void *Decoder) { 3719 DecodeStatus S = MCDisassembler::Success; 3720 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3721 unsigned add = fieldFromInstruction(Insn, 4, 1); 3722 3723 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 Inst.addOperand(MCOperand::CreateImm(add)); 3726 3727 return S; 3728 } 3729 3730 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3731 uint64_t Address, const void *Decoder) { 3732 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3733 // Note only one trailing zero not two. Also the J1 and J2 values are from 3734 // the encoded instruction. So here change to I1 and I2 values via: 3735 // I1 = NOT(J1 EOR S); 3736 // I2 = NOT(J2 EOR S); 3737 // and build the imm32 with two trailing zeros as documented: 3738 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3739 unsigned S = (Val >> 23) & 1; 3740 unsigned J1 = (Val >> 22) & 1; 3741 unsigned J2 = (Val >> 21) & 1; 3742 unsigned I1 = !(J1 ^ S); 3743 unsigned I2 = !(J2 ^ S); 3744 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3745 int imm32 = SignExtend32<25>(tmp << 1); 3746 3747 if (!tryAddingSymbolicOperand(Address, 3748 (Address & ~2u) + imm32 + 4, 3749 true, 4, Inst, Decoder)) 3750 Inst.addOperand(MCOperand::CreateImm(imm32)); 3751 return MCDisassembler::Success; 3752 } 3753 3754 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3755 uint64_t Address, const void *Decoder) { 3756 if (Val == 0xA || Val == 0xB) 3757 return MCDisassembler::Fail; 3758 3759 Inst.addOperand(MCOperand::CreateImm(Val)); 3760 return MCDisassembler::Success; 3761 } 3762 3763 static DecodeStatus 3764 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3765 uint64_t Address, const void *Decoder) { 3766 DecodeStatus S = MCDisassembler::Success; 3767 3768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3769 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3770 3771 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3775 return MCDisassembler::Fail; 3776 return S; 3777 } 3778 3779 static DecodeStatus 3780 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3781 uint64_t Address, const void *Decoder) { 3782 DecodeStatus S = MCDisassembler::Success; 3783 3784 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3785 if (pred == 0xE || pred == 0xF) { 3786 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3787 switch (opc) { 3788 default: 3789 return MCDisassembler::Fail; 3790 case 0xf3bf8f4: 3791 Inst.setOpcode(ARM::t2DSB); 3792 break; 3793 case 0xf3bf8f5: 3794 Inst.setOpcode(ARM::t2DMB); 3795 break; 3796 case 0xf3bf8f6: 3797 Inst.setOpcode(ARM::t2ISB); 3798 break; 3799 } 3800 3801 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3802 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3803 } 3804 3805 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3806 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3807 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3808 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3809 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3810 3811 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3812 return MCDisassembler::Fail; 3813 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 3816 return S; 3817 } 3818 3819 // Decode a shifted immediate operand. These basically consist 3820 // of an 8-bit value, and a 4-bit directive that specifies either 3821 // a splat operation or a rotation. 3822 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3823 uint64_t Address, const void *Decoder) { 3824 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3825 if (ctrl == 0) { 3826 unsigned byte = fieldFromInstruction(Val, 8, 2); 3827 unsigned imm = fieldFromInstruction(Val, 0, 8); 3828 switch (byte) { 3829 case 0: 3830 Inst.addOperand(MCOperand::CreateImm(imm)); 3831 break; 3832 case 1: 3833 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3834 break; 3835 case 2: 3836 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3837 break; 3838 case 3: 3839 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3840 (imm << 8) | imm)); 3841 break; 3842 } 3843 } else { 3844 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3845 unsigned rot = fieldFromInstruction(Val, 7, 5); 3846 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3847 Inst.addOperand(MCOperand::CreateImm(imm)); 3848 } 3849 3850 return MCDisassembler::Success; 3851 } 3852 3853 static DecodeStatus 3854 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3855 uint64_t Address, const void *Decoder){ 3856 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3857 true, 2, Inst, Decoder)) 3858 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3859 return MCDisassembler::Success; 3860 } 3861 3862 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3863 uint64_t Address, const void *Decoder){ 3864 // Val is passed in as S:J1:J2:imm10:imm11 3865 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3866 // the encoded instruction. So here change to I1 and I2 values via: 3867 // I1 = NOT(J1 EOR S); 3868 // I2 = NOT(J2 EOR S); 3869 // and build the imm32 with one trailing zero as documented: 3870 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3871 unsigned S = (Val >> 23) & 1; 3872 unsigned J1 = (Val >> 22) & 1; 3873 unsigned J2 = (Val >> 21) & 1; 3874 unsigned I1 = !(J1 ^ S); 3875 unsigned I2 = !(J2 ^ S); 3876 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3877 int imm32 = SignExtend32<25>(tmp << 1); 3878 3879 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3880 true, 4, Inst, Decoder)) 3881 Inst.addOperand(MCOperand::CreateImm(imm32)); 3882 return MCDisassembler::Success; 3883 } 3884 3885 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3886 uint64_t Address, const void *Decoder) { 3887 if (Val & ~0xf) 3888 return MCDisassembler::Fail; 3889 3890 Inst.addOperand(MCOperand::CreateImm(Val)); 3891 return MCDisassembler::Success; 3892 } 3893 3894 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3895 uint64_t Address, const void *Decoder) { 3896 if (Val & ~0xf) 3897 return MCDisassembler::Fail; 3898 3899 Inst.addOperand(MCOperand::CreateImm(Val)); 3900 return MCDisassembler::Success; 3901 } 3902 3903 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3904 uint64_t Address, const void *Decoder) { 3905 if (!Val) return MCDisassembler::Fail; 3906 Inst.addOperand(MCOperand::CreateImm(Val)); 3907 return MCDisassembler::Success; 3908 } 3909 3910 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3911 uint64_t Address, const void *Decoder) { 3912 DecodeStatus S = MCDisassembler::Success; 3913 3914 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3915 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3916 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3917 3918 if (Rn == 0xF) 3919 S = MCDisassembler::SoftFail; 3920 3921 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3924 return MCDisassembler::Fail; 3925 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3926 return MCDisassembler::Fail; 3927 3928 return S; 3929 } 3930 3931 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3932 uint64_t Address, const void *Decoder){ 3933 DecodeStatus S = MCDisassembler::Success; 3934 3935 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3936 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3937 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3938 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3939 3940 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3941 return MCDisassembler::Fail; 3942 3943 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 3944 S = MCDisassembler::SoftFail; 3945 3946 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3949 return MCDisassembler::Fail; 3950 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 3953 return S; 3954 } 3955 3956 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3957 uint64_t Address, const void *Decoder) { 3958 DecodeStatus S = MCDisassembler::Success; 3959 3960 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3961 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3962 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3963 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3964 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3965 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3966 3967 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3968 3969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3970 return MCDisassembler::Fail; 3971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3972 return MCDisassembler::Fail; 3973 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3974 return MCDisassembler::Fail; 3975 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3976 return MCDisassembler::Fail; 3977 3978 return S; 3979 } 3980 3981 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3982 uint64_t Address, const void *Decoder) { 3983 DecodeStatus S = MCDisassembler::Success; 3984 3985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3986 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3987 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3988 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3989 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3990 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3991 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3992 3993 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3994 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3995 3996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3999 return MCDisassembler::Fail; 4000 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 4005 return S; 4006 } 4007 4008 4009 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4010 uint64_t Address, const void *Decoder) { 4011 DecodeStatus S = MCDisassembler::Success; 4012 4013 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4014 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4015 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4016 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4017 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4018 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4019 4020 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4021 4022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 4031 return S; 4032 } 4033 4034 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4035 uint64_t Address, const void *Decoder) { 4036 DecodeStatus S = MCDisassembler::Success; 4037 4038 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4039 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4040 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4041 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4042 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4043 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4044 4045 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4046 4047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4048 return MCDisassembler::Fail; 4049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4050 return MCDisassembler::Fail; 4051 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4052 return MCDisassembler::Fail; 4053 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4054 return MCDisassembler::Fail; 4055 4056 return S; 4057 } 4058 4059 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4060 uint64_t Address, const void *Decoder) { 4061 DecodeStatus S = MCDisassembler::Success; 4062 4063 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4064 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4065 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4066 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4067 unsigned size = fieldFromInstruction(Insn, 10, 2); 4068 4069 unsigned align = 0; 4070 unsigned index = 0; 4071 switch (size) { 4072 default: 4073 return MCDisassembler::Fail; 4074 case 0: 4075 if (fieldFromInstruction(Insn, 4, 1)) 4076 return MCDisassembler::Fail; // UNDEFINED 4077 index = fieldFromInstruction(Insn, 5, 3); 4078 break; 4079 case 1: 4080 if (fieldFromInstruction(Insn, 5, 1)) 4081 return MCDisassembler::Fail; // UNDEFINED 4082 index = fieldFromInstruction(Insn, 6, 2); 4083 if (fieldFromInstruction(Insn, 4, 1)) 4084 align = 2; 4085 break; 4086 case 2: 4087 if (fieldFromInstruction(Insn, 6, 1)) 4088 return MCDisassembler::Fail; // UNDEFINED 4089 index = fieldFromInstruction(Insn, 7, 1); 4090 4091 switch (fieldFromInstruction(Insn, 4, 2)) { 4092 case 0 : 4093 align = 0; break; 4094 case 3: 4095 align = 4; break; 4096 default: 4097 return MCDisassembler::Fail; 4098 } 4099 break; 4100 } 4101 4102 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4103 return MCDisassembler::Fail; 4104 if (Rm != 0xF) { // Writeback 4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 } 4108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4109 return MCDisassembler::Fail; 4110 Inst.addOperand(MCOperand::CreateImm(align)); 4111 if (Rm != 0xF) { 4112 if (Rm != 0xD) { 4113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 } else 4116 Inst.addOperand(MCOperand::CreateReg(0)); 4117 } 4118 4119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4120 return MCDisassembler::Fail; 4121 Inst.addOperand(MCOperand::CreateImm(index)); 4122 4123 return S; 4124 } 4125 4126 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4127 uint64_t Address, const void *Decoder) { 4128 DecodeStatus S = MCDisassembler::Success; 4129 4130 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4131 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4132 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4133 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4134 unsigned size = fieldFromInstruction(Insn, 10, 2); 4135 4136 unsigned align = 0; 4137 unsigned index = 0; 4138 switch (size) { 4139 default: 4140 return MCDisassembler::Fail; 4141 case 0: 4142 if (fieldFromInstruction(Insn, 4, 1)) 4143 return MCDisassembler::Fail; // UNDEFINED 4144 index = fieldFromInstruction(Insn, 5, 3); 4145 break; 4146 case 1: 4147 if (fieldFromInstruction(Insn, 5, 1)) 4148 return MCDisassembler::Fail; // UNDEFINED 4149 index = fieldFromInstruction(Insn, 6, 2); 4150 if (fieldFromInstruction(Insn, 4, 1)) 4151 align = 2; 4152 break; 4153 case 2: 4154 if (fieldFromInstruction(Insn, 6, 1)) 4155 return MCDisassembler::Fail; // UNDEFINED 4156 index = fieldFromInstruction(Insn, 7, 1); 4157 4158 switch (fieldFromInstruction(Insn, 4, 2)) { 4159 case 0: 4160 align = 0; break; 4161 case 3: 4162 align = 4; break; 4163 default: 4164 return MCDisassembler::Fail; 4165 } 4166 break; 4167 } 4168 4169 if (Rm != 0xF) { // Writeback 4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 } 4173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4174 return MCDisassembler::Fail; 4175 Inst.addOperand(MCOperand::CreateImm(align)); 4176 if (Rm != 0xF) { 4177 if (Rm != 0xD) { 4178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4179 return MCDisassembler::Fail; 4180 } else 4181 Inst.addOperand(MCOperand::CreateReg(0)); 4182 } 4183 4184 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 Inst.addOperand(MCOperand::CreateImm(index)); 4187 4188 return S; 4189 } 4190 4191 4192 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4193 uint64_t Address, const void *Decoder) { 4194 DecodeStatus S = MCDisassembler::Success; 4195 4196 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4197 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4198 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4199 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4200 unsigned size = fieldFromInstruction(Insn, 10, 2); 4201 4202 unsigned align = 0; 4203 unsigned index = 0; 4204 unsigned inc = 1; 4205 switch (size) { 4206 default: 4207 return MCDisassembler::Fail; 4208 case 0: 4209 index = fieldFromInstruction(Insn, 5, 3); 4210 if (fieldFromInstruction(Insn, 4, 1)) 4211 align = 2; 4212 break; 4213 case 1: 4214 index = fieldFromInstruction(Insn, 6, 2); 4215 if (fieldFromInstruction(Insn, 4, 1)) 4216 align = 4; 4217 if (fieldFromInstruction(Insn, 5, 1)) 4218 inc = 2; 4219 break; 4220 case 2: 4221 if (fieldFromInstruction(Insn, 5, 1)) 4222 return MCDisassembler::Fail; // UNDEFINED 4223 index = fieldFromInstruction(Insn, 7, 1); 4224 if (fieldFromInstruction(Insn, 4, 1) != 0) 4225 align = 8; 4226 if (fieldFromInstruction(Insn, 6, 1)) 4227 inc = 2; 4228 break; 4229 } 4230 4231 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4232 return MCDisassembler::Fail; 4233 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 if (Rm != 0xF) { // Writeback 4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 } 4239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 Inst.addOperand(MCOperand::CreateImm(align)); 4242 if (Rm != 0xF) { 4243 if (Rm != 0xD) { 4244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 } else 4247 Inst.addOperand(MCOperand::CreateReg(0)); 4248 } 4249 4250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4253 return MCDisassembler::Fail; 4254 Inst.addOperand(MCOperand::CreateImm(index)); 4255 4256 return S; 4257 } 4258 4259 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4260 uint64_t Address, const void *Decoder) { 4261 DecodeStatus S = MCDisassembler::Success; 4262 4263 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4264 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4265 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4266 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4267 unsigned size = fieldFromInstruction(Insn, 10, 2); 4268 4269 unsigned align = 0; 4270 unsigned index = 0; 4271 unsigned inc = 1; 4272 switch (size) { 4273 default: 4274 return MCDisassembler::Fail; 4275 case 0: 4276 index = fieldFromInstruction(Insn, 5, 3); 4277 if (fieldFromInstruction(Insn, 4, 1)) 4278 align = 2; 4279 break; 4280 case 1: 4281 index = fieldFromInstruction(Insn, 6, 2); 4282 if (fieldFromInstruction(Insn, 4, 1)) 4283 align = 4; 4284 if (fieldFromInstruction(Insn, 5, 1)) 4285 inc = 2; 4286 break; 4287 case 2: 4288 if (fieldFromInstruction(Insn, 5, 1)) 4289 return MCDisassembler::Fail; // UNDEFINED 4290 index = fieldFromInstruction(Insn, 7, 1); 4291 if (fieldFromInstruction(Insn, 4, 1) != 0) 4292 align = 8; 4293 if (fieldFromInstruction(Insn, 6, 1)) 4294 inc = 2; 4295 break; 4296 } 4297 4298 if (Rm != 0xF) { // Writeback 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 } 4302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4303 return MCDisassembler::Fail; 4304 Inst.addOperand(MCOperand::CreateImm(align)); 4305 if (Rm != 0xF) { 4306 if (Rm != 0xD) { 4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 } else 4310 Inst.addOperand(MCOperand::CreateReg(0)); 4311 } 4312 4313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 Inst.addOperand(MCOperand::CreateImm(index)); 4318 4319 return S; 4320 } 4321 4322 4323 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4324 uint64_t Address, const void *Decoder) { 4325 DecodeStatus S = MCDisassembler::Success; 4326 4327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4328 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4331 unsigned size = fieldFromInstruction(Insn, 10, 2); 4332 4333 unsigned align = 0; 4334 unsigned index = 0; 4335 unsigned inc = 1; 4336 switch (size) { 4337 default: 4338 return MCDisassembler::Fail; 4339 case 0: 4340 if (fieldFromInstruction(Insn, 4, 1)) 4341 return MCDisassembler::Fail; // UNDEFINED 4342 index = fieldFromInstruction(Insn, 5, 3); 4343 break; 4344 case 1: 4345 if (fieldFromInstruction(Insn, 4, 1)) 4346 return MCDisassembler::Fail; // UNDEFINED 4347 index = fieldFromInstruction(Insn, 6, 2); 4348 if (fieldFromInstruction(Insn, 5, 1)) 4349 inc = 2; 4350 break; 4351 case 2: 4352 if (fieldFromInstruction(Insn, 4, 2)) 4353 return MCDisassembler::Fail; // UNDEFINED 4354 index = fieldFromInstruction(Insn, 7, 1); 4355 if (fieldFromInstruction(Insn, 6, 1)) 4356 inc = 2; 4357 break; 4358 } 4359 4360 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4361 return MCDisassembler::Fail; 4362 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4365 return MCDisassembler::Fail; 4366 4367 if (Rm != 0xF) { // Writeback 4368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 } 4371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 Inst.addOperand(MCOperand::CreateImm(align)); 4374 if (Rm != 0xF) { 4375 if (Rm != 0xD) { 4376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4377 return MCDisassembler::Fail; 4378 } else 4379 Inst.addOperand(MCOperand::CreateReg(0)); 4380 } 4381 4382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4383 return MCDisassembler::Fail; 4384 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 Inst.addOperand(MCOperand::CreateImm(index)); 4389 4390 return S; 4391 } 4392 4393 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4394 uint64_t Address, const void *Decoder) { 4395 DecodeStatus S = MCDisassembler::Success; 4396 4397 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4398 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4399 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4400 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4401 unsigned size = fieldFromInstruction(Insn, 10, 2); 4402 4403 unsigned align = 0; 4404 unsigned index = 0; 4405 unsigned inc = 1; 4406 switch (size) { 4407 default: 4408 return MCDisassembler::Fail; 4409 case 0: 4410 if (fieldFromInstruction(Insn, 4, 1)) 4411 return MCDisassembler::Fail; // UNDEFINED 4412 index = fieldFromInstruction(Insn, 5, 3); 4413 break; 4414 case 1: 4415 if (fieldFromInstruction(Insn, 4, 1)) 4416 return MCDisassembler::Fail; // UNDEFINED 4417 index = fieldFromInstruction(Insn, 6, 2); 4418 if (fieldFromInstruction(Insn, 5, 1)) 4419 inc = 2; 4420 break; 4421 case 2: 4422 if (fieldFromInstruction(Insn, 4, 2)) 4423 return MCDisassembler::Fail; // UNDEFINED 4424 index = fieldFromInstruction(Insn, 7, 1); 4425 if (fieldFromInstruction(Insn, 6, 1)) 4426 inc = 2; 4427 break; 4428 } 4429 4430 if (Rm != 0xF) { // Writeback 4431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 } 4434 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4435 return MCDisassembler::Fail; 4436 Inst.addOperand(MCOperand::CreateImm(align)); 4437 if (Rm != 0xF) { 4438 if (Rm != 0xD) { 4439 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4440 return MCDisassembler::Fail; 4441 } else 4442 Inst.addOperand(MCOperand::CreateReg(0)); 4443 } 4444 4445 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4446 return MCDisassembler::Fail; 4447 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4450 return MCDisassembler::Fail; 4451 Inst.addOperand(MCOperand::CreateImm(index)); 4452 4453 return S; 4454 } 4455 4456 4457 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4458 uint64_t Address, const void *Decoder) { 4459 DecodeStatus S = MCDisassembler::Success; 4460 4461 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4462 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4463 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4464 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4465 unsigned size = fieldFromInstruction(Insn, 10, 2); 4466 4467 unsigned align = 0; 4468 unsigned index = 0; 4469 unsigned inc = 1; 4470 switch (size) { 4471 default: 4472 return MCDisassembler::Fail; 4473 case 0: 4474 if (fieldFromInstruction(Insn, 4, 1)) 4475 align = 4; 4476 index = fieldFromInstruction(Insn, 5, 3); 4477 break; 4478 case 1: 4479 if (fieldFromInstruction(Insn, 4, 1)) 4480 align = 8; 4481 index = fieldFromInstruction(Insn, 6, 2); 4482 if (fieldFromInstruction(Insn, 5, 1)) 4483 inc = 2; 4484 break; 4485 case 2: 4486 switch (fieldFromInstruction(Insn, 4, 2)) { 4487 case 0: 4488 align = 0; break; 4489 case 3: 4490 return MCDisassembler::Fail; 4491 default: 4492 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4493 } 4494 4495 index = fieldFromInstruction(Insn, 7, 1); 4496 if (fieldFromInstruction(Insn, 6, 1)) 4497 inc = 2; 4498 break; 4499 } 4500 4501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4502 return MCDisassembler::Fail; 4503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4504 return MCDisassembler::Fail; 4505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4506 return MCDisassembler::Fail; 4507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4508 return MCDisassembler::Fail; 4509 4510 if (Rm != 0xF) { // Writeback 4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 } 4514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4515 return MCDisassembler::Fail; 4516 Inst.addOperand(MCOperand::CreateImm(align)); 4517 if (Rm != 0xF) { 4518 if (Rm != 0xD) { 4519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4520 return MCDisassembler::Fail; 4521 } else 4522 Inst.addOperand(MCOperand::CreateReg(0)); 4523 } 4524 4525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4528 return MCDisassembler::Fail; 4529 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4530 return MCDisassembler::Fail; 4531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4532 return MCDisassembler::Fail; 4533 Inst.addOperand(MCOperand::CreateImm(index)); 4534 4535 return S; 4536 } 4537 4538 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4539 uint64_t Address, const void *Decoder) { 4540 DecodeStatus S = MCDisassembler::Success; 4541 4542 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4543 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4544 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4545 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4546 unsigned size = fieldFromInstruction(Insn, 10, 2); 4547 4548 unsigned align = 0; 4549 unsigned index = 0; 4550 unsigned inc = 1; 4551 switch (size) { 4552 default: 4553 return MCDisassembler::Fail; 4554 case 0: 4555 if (fieldFromInstruction(Insn, 4, 1)) 4556 align = 4; 4557 index = fieldFromInstruction(Insn, 5, 3); 4558 break; 4559 case 1: 4560 if (fieldFromInstruction(Insn, 4, 1)) 4561 align = 8; 4562 index = fieldFromInstruction(Insn, 6, 2); 4563 if (fieldFromInstruction(Insn, 5, 1)) 4564 inc = 2; 4565 break; 4566 case 2: 4567 switch (fieldFromInstruction(Insn, 4, 2)) { 4568 case 0: 4569 align = 0; break; 4570 case 3: 4571 return MCDisassembler::Fail; 4572 default: 4573 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4574 } 4575 4576 index = fieldFromInstruction(Insn, 7, 1); 4577 if (fieldFromInstruction(Insn, 6, 1)) 4578 inc = 2; 4579 break; 4580 } 4581 4582 if (Rm != 0xF) { // Writeback 4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4584 return MCDisassembler::Fail; 4585 } 4586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 Inst.addOperand(MCOperand::CreateImm(align)); 4589 if (Rm != 0xF) { 4590 if (Rm != 0xD) { 4591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4592 return MCDisassembler::Fail; 4593 } else 4594 Inst.addOperand(MCOperand::CreateReg(0)); 4595 } 4596 4597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4598 return MCDisassembler::Fail; 4599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4600 return MCDisassembler::Fail; 4601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4602 return MCDisassembler::Fail; 4603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4604 return MCDisassembler::Fail; 4605 Inst.addOperand(MCOperand::CreateImm(index)); 4606 4607 return S; 4608 } 4609 4610 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4611 uint64_t Address, const void *Decoder) { 4612 DecodeStatus S = MCDisassembler::Success; 4613 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4614 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4615 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4616 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4617 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4618 4619 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4620 S = MCDisassembler::SoftFail; 4621 4622 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4623 return MCDisassembler::Fail; 4624 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4627 return MCDisassembler::Fail; 4628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4629 return MCDisassembler::Fail; 4630 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4631 return MCDisassembler::Fail; 4632 4633 return S; 4634 } 4635 4636 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4637 uint64_t Address, const void *Decoder) { 4638 DecodeStatus S = MCDisassembler::Success; 4639 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4640 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4641 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4642 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4643 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4644 4645 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4646 S = MCDisassembler::SoftFail; 4647 4648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4653 return MCDisassembler::Fail; 4654 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4655 return MCDisassembler::Fail; 4656 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4657 return MCDisassembler::Fail; 4658 4659 return S; 4660 } 4661 4662 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4663 uint64_t Address, const void *Decoder) { 4664 DecodeStatus S = MCDisassembler::Success; 4665 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4666 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4667 4668 if (pred == 0xF) { 4669 pred = 0xE; 4670 S = MCDisassembler::SoftFail; 4671 } 4672 4673 if (mask == 0x0) 4674 return MCDisassembler::Fail; 4675 4676 Inst.addOperand(MCOperand::CreateImm(pred)); 4677 Inst.addOperand(MCOperand::CreateImm(mask)); 4678 return S; 4679 } 4680 4681 static DecodeStatus 4682 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4683 uint64_t Address, const void *Decoder) { 4684 DecodeStatus S = MCDisassembler::Success; 4685 4686 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4687 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4688 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4689 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4690 unsigned W = fieldFromInstruction(Insn, 21, 1); 4691 unsigned U = fieldFromInstruction(Insn, 23, 1); 4692 unsigned P = fieldFromInstruction(Insn, 24, 1); 4693 bool writeback = (W == 1) | (P == 0); 4694 4695 addr |= (U << 8) | (Rn << 9); 4696 4697 if (writeback && (Rn == Rt || Rn == Rt2)) 4698 Check(S, MCDisassembler::SoftFail); 4699 if (Rt == Rt2) 4700 Check(S, MCDisassembler::SoftFail); 4701 4702 // Rt 4703 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4704 return MCDisassembler::Fail; 4705 // Rt2 4706 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4707 return MCDisassembler::Fail; 4708 // Writeback operand 4709 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4710 return MCDisassembler::Fail; 4711 // addr 4712 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 4715 return S; 4716 } 4717 4718 static DecodeStatus 4719 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4720 uint64_t Address, const void *Decoder) { 4721 DecodeStatus S = MCDisassembler::Success; 4722 4723 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4724 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4725 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4726 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4727 unsigned W = fieldFromInstruction(Insn, 21, 1); 4728 unsigned U = fieldFromInstruction(Insn, 23, 1); 4729 unsigned P = fieldFromInstruction(Insn, 24, 1); 4730 bool writeback = (W == 1) | (P == 0); 4731 4732 addr |= (U << 8) | (Rn << 9); 4733 4734 if (writeback && (Rn == Rt || Rn == Rt2)) 4735 Check(S, MCDisassembler::SoftFail); 4736 4737 // Writeback operand 4738 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 // Rt 4741 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 // Rt2 4744 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4745 return MCDisassembler::Fail; 4746 // addr 4747 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4748 return MCDisassembler::Fail; 4749 4750 return S; 4751 } 4752 4753 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4754 uint64_t Address, const void *Decoder) { 4755 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4756 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4757 if (sign1 != sign2) return MCDisassembler::Fail; 4758 4759 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4760 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4761 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4762 Val |= sign1 << 12; 4763 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4764 4765 return MCDisassembler::Success; 4766 } 4767 4768 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4769 uint64_t Address, 4770 const void *Decoder) { 4771 DecodeStatus S = MCDisassembler::Success; 4772 4773 // Shift of "asr #32" is not allowed in Thumb2 mode. 4774 if (Val == 0x20) S = MCDisassembler::SoftFail; 4775 Inst.addOperand(MCOperand::CreateImm(Val)); 4776 return S; 4777 } 4778 4779 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4780 uint64_t Address, const void *Decoder) { 4781 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4782 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4783 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4784 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4785 4786 if (pred == 0xF) 4787 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4788 4789 DecodeStatus S = MCDisassembler::Success; 4790 4791 if (Rt == Rn || Rn == Rt2) 4792 S = MCDisassembler::SoftFail; 4793 4794 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4799 return MCDisassembler::Fail; 4800 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 4803 return S; 4804 } 4805 4806 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4807 uint64_t Address, const void *Decoder) { 4808 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4809 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4810 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4811 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4812 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4813 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4814 unsigned op = fieldFromInstruction(Insn, 5, 1); 4815 4816 DecodeStatus S = MCDisassembler::Success; 4817 4818 // VMOVv2f32 is ambiguous with these decodings. 4819 if (!(imm & 0x38) && cmode == 0xF) { 4820 if (op == 1) return MCDisassembler::Fail; 4821 Inst.setOpcode(ARM::VMOVv2f32); 4822 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4823 } 4824 4825 if (!(imm & 0x20)) return MCDisassembler::Fail; 4826 4827 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4828 return MCDisassembler::Fail; 4829 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4832 4833 return S; 4834 } 4835 4836 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4837 uint64_t Address, const void *Decoder) { 4838 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4839 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4840 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4841 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4842 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4843 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4844 unsigned op = fieldFromInstruction(Insn, 5, 1); 4845 4846 DecodeStatus S = MCDisassembler::Success; 4847 4848 // VMOVv4f32 is ambiguous with these decodings. 4849 if (!(imm & 0x38) && cmode == 0xF) { 4850 if (op == 1) return MCDisassembler::Fail; 4851 Inst.setOpcode(ARM::VMOVv4f32); 4852 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4853 } 4854 4855 if (!(imm & 0x20)) return MCDisassembler::Fail; 4856 4857 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4858 return MCDisassembler::Fail; 4859 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4860 return MCDisassembler::Fail; 4861 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4862 4863 return S; 4864 } 4865 4866 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4867 const void *Decoder) 4868 { 4869 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4870 if (Imm > 4) return MCDisassembler::Fail; 4871 Inst.addOperand(MCOperand::CreateImm(Imm)); 4872 return MCDisassembler::Success; 4873 } 4874 4875 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4876 uint64_t Address, const void *Decoder) { 4877 DecodeStatus S = MCDisassembler::Success; 4878 4879 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4880 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4881 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4882 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4883 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4884 4885 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4886 S = MCDisassembler::SoftFail; 4887 4888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 4899 return S; 4900 } 4901 4902 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4903 uint64_t Address, const void *Decoder) { 4904 4905 DecodeStatus S = MCDisassembler::Success; 4906 4907 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4908 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4909 unsigned cop = fieldFromInstruction(Val, 8, 4); 4910 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4911 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4912 4913 if ((cop & ~0x1) == 0xa) 4914 return MCDisassembler::Fail; 4915 4916 if (Rt == Rt2) 4917 S = MCDisassembler::SoftFail; 4918 4919 Inst.addOperand(MCOperand::CreateImm(cop)); 4920 Inst.addOperand(MCOperand::CreateImm(opc1)); 4921 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 Inst.addOperand(MCOperand::CreateImm(CRm)); 4926 4927 return S; 4928 } 4929 4930