1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 183 unsigned RegNo, uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 217 unsigned Insn, 218 uint64_t Adddress, 219 const void *Decoder); 220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 323 const void *Decoder); 324 325 326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 391 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 #include "ARMGenDisassemblerTables.inc" 396 397 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 398 return new ARMDisassembler(STI); 399 } 400 401 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 402 return new ThumbDisassembler(STI); 403 } 404 405 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 const MemoryObject &Region, 407 uint64_t Address, 408 raw_ostream &os, 409 raw_ostream &cs) const { 410 CommentStream = &cs; 411 412 uint8_t bytes[4]; 413 414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 416 417 // We want to read exactly 4 bytes of data. 418 if (Region.readBytes(Address, 4, bytes) == -1) { 419 Size = 0; 420 return MCDisassembler::Fail; 421 } 422 423 // Encoded as a small-endian 32-bit word in the stream. 424 uint32_t insn = (bytes[3] << 24) | 425 (bytes[2] << 16) | 426 (bytes[1] << 8) | 427 (bytes[0] << 0); 428 429 // Calling the auto-generated decoder function. 430 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 431 Address, this, STI); 432 if (result != MCDisassembler::Fail) { 433 Size = 4; 434 return result; 435 } 436 437 // VFP and NEON instructions, similarly, are shared between ARM 438 // and Thumb modes. 439 MI.clear(); 440 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 441 if (result != MCDisassembler::Fail) { 442 Size = 4; 443 return result; 444 } 445 446 MI.clear(); 447 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 448 this, STI); 449 if (result != MCDisassembler::Fail) { 450 Size = 4; 451 // Add a fake predicate operand, because we share these instruction 452 // definitions with Thumb2 where these instructions are predicable. 453 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 454 return MCDisassembler::Fail; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 460 this, STI); 461 if (result != MCDisassembler::Fail) { 462 Size = 4; 463 // Add a fake predicate operand, because we share these instruction 464 // definitions with Thumb2 where these instructions are predicable. 465 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 466 return MCDisassembler::Fail; 467 return result; 468 } 469 470 MI.clear(); 471 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 472 this, STI); 473 if (result != MCDisassembler::Fail) { 474 Size = 4; 475 // Add a fake predicate operand, because we share these instruction 476 // definitions with Thumb2 where these instructions are predicable. 477 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 478 return MCDisassembler::Fail; 479 return result; 480 } 481 482 MI.clear(); 483 484 Size = 0; 485 return MCDisassembler::Fail; 486 } 487 488 namespace llvm { 489 extern const MCInstrDesc ARMInsts[]; 490 } 491 492 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 493 /// immediate Value in the MCInst. The immediate Value has had any PC 494 /// adjustment made by the caller. If the instruction is a branch instruction 495 /// then isBranch is true, else false. If the getOpInfo() function was set as 496 /// part of the setupForSymbolicDisassembly() call then that function is called 497 /// to get any symbolic information at the Address for this instruction. If 498 /// that returns non-zero then the symbolic information it returns is used to 499 /// create an MCExpr and that is added as an operand to the MCInst. If 500 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 501 /// Value is done and if a symbol is found an MCExpr is created with that, else 502 /// an MCExpr with Value is created. This function returns true if it adds an 503 /// operand to the MCInst and false otherwise. 504 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 505 bool isBranch, uint64_t InstSize, 506 MCInst &MI, const void *Decoder) { 507 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 508 // FIXME: Does it make sense for value to be negative? 509 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 510 /* Offset */ 0, InstSize); 511 } 512 513 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 514 /// referenced by a load instruction with the base register that is the Pc. 515 /// These can often be values in a literal pool near the Address of the 516 /// instruction. The Address of the instruction and its immediate Value are 517 /// used as a possible literal pool entry. The SymbolLookUp call back will 518 /// return the name of a symbol referenced by the literal pool's entry if 519 /// the referenced address is that of a symbol. Or it will return a pointer to 520 /// a literal 'C' string if the referenced address of the literal pool's entry 521 /// is an address into a section with 'C' string literals. 522 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 523 const void *Decoder) { 524 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 525 Dis->tryAddingPcLoadReferenceComment(Value, Address); 526 } 527 528 // Thumb1 instructions don't have explicit S bits. Rather, they 529 // implicitly set CPSR. Since it's not represented in the encoding, the 530 // auto-generated decoder won't inject the CPSR operand. We need to fix 531 // that as a post-pass. 532 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 533 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 534 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 535 MCInst::iterator I = MI.begin(); 536 for (unsigned i = 0; i < NumOps; ++i, ++I) { 537 if (I == MI.end()) break; 538 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 539 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 540 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 541 return; 542 } 543 } 544 545 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 546 } 547 548 // Most Thumb instructions don't have explicit predicates in the 549 // encoding, but rather get their predicates from IT context. We need 550 // to fix up the predicate operands using this context information as a 551 // post-pass. 552 MCDisassembler::DecodeStatus 553 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 554 MCDisassembler::DecodeStatus S = Success; 555 556 // A few instructions actually have predicates encoded in them. Don't 557 // try to overwrite it if we're seeing one of those. 558 switch (MI.getOpcode()) { 559 case ARM::tBcc: 560 case ARM::t2Bcc: 561 case ARM::tCBZ: 562 case ARM::tCBNZ: 563 case ARM::tCPS: 564 case ARM::t2CPS3p: 565 case ARM::t2CPS2p: 566 case ARM::t2CPS1p: 567 case ARM::tMOVSr: 568 case ARM::tSETEND: 569 // Some instructions (mostly conditional branches) are not 570 // allowed in IT blocks. 571 if (ITBlock.instrInITBlock()) 572 S = SoftFail; 573 else 574 return Success; 575 break; 576 case ARM::tB: 577 case ARM::t2B: 578 case ARM::t2TBB: 579 case ARM::t2TBH: 580 // Some instructions (mostly unconditional branches) can 581 // only appears at the end of, or outside of, an IT. 582 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 583 S = SoftFail; 584 break; 585 default: 586 break; 587 } 588 589 // If we're in an IT block, base the predicate on that. Otherwise, 590 // assume a predicate of AL. 591 unsigned CC; 592 CC = ITBlock.getITCC(); 593 if (CC == 0xF) 594 CC = ARMCC::AL; 595 if (ITBlock.instrInITBlock()) 596 ITBlock.advanceITState(); 597 598 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 599 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 600 MCInst::iterator I = MI.begin(); 601 for (unsigned i = 0; i < NumOps; ++i, ++I) { 602 if (I == MI.end()) break; 603 if (OpInfo[i].isPredicate()) { 604 I = MI.insert(I, MCOperand::CreateImm(CC)); 605 ++I; 606 if (CC == ARMCC::AL) 607 MI.insert(I, MCOperand::CreateReg(0)); 608 else 609 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 610 return S; 611 } 612 } 613 614 I = MI.insert(I, MCOperand::CreateImm(CC)); 615 ++I; 616 if (CC == ARMCC::AL) 617 MI.insert(I, MCOperand::CreateReg(0)); 618 else 619 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 620 621 return S; 622 } 623 624 // Thumb VFP instructions are a special case. Because we share their 625 // encodings between ARM and Thumb modes, and they are predicable in ARM 626 // mode, the auto-generated decoder will give them an (incorrect) 627 // predicate operand. We need to rewrite these operands based on the IT 628 // context as a post-pass. 629 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 630 unsigned CC; 631 CC = ITBlock.getITCC(); 632 if (ITBlock.instrInITBlock()) 633 ITBlock.advanceITState(); 634 635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 636 MCInst::iterator I = MI.begin(); 637 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 638 for (unsigned i = 0; i < NumOps; ++i, ++I) { 639 if (OpInfo[i].isPredicate() ) { 640 I->setImm(CC); 641 ++I; 642 if (CC == ARMCC::AL) 643 I->setReg(0); 644 else 645 I->setReg(ARM::CPSR); 646 return; 647 } 648 } 649 } 650 651 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 652 const MemoryObject &Region, 653 uint64_t Address, 654 raw_ostream &os, 655 raw_ostream &cs) const { 656 CommentStream = &cs; 657 658 uint8_t bytes[4]; 659 660 assert((STI.getFeatureBits() & ARM::ModeThumb) && 661 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 662 663 // We want to read exactly 2 bytes of data. 664 if (Region.readBytes(Address, 2, bytes) == -1) { 665 Size = 0; 666 return MCDisassembler::Fail; 667 } 668 669 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 670 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 671 Address, this, STI); 672 if (result != MCDisassembler::Fail) { 673 Size = 2; 674 Check(result, AddThumbPredicate(MI)); 675 return result; 676 } 677 678 MI.clear(); 679 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 680 Address, this, STI); 681 if (result) { 682 Size = 2; 683 bool InITBlock = ITBlock.instrInITBlock(); 684 Check(result, AddThumbPredicate(MI)); 685 AddThumb1SBit(MI, InITBlock); 686 return result; 687 } 688 689 MI.clear(); 690 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 691 Address, this, STI); 692 if (result != MCDisassembler::Fail) { 693 Size = 2; 694 695 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 696 // the Thumb predicate. 697 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 698 result = MCDisassembler::SoftFail; 699 700 Check(result, AddThumbPredicate(MI)); 701 702 // If we find an IT instruction, we need to parse its condition 703 // code and mask operands so that we can apply them correctly 704 // to the subsequent instructions. 705 if (MI.getOpcode() == ARM::t2IT) { 706 707 unsigned Firstcond = MI.getOperand(0).getImm(); 708 unsigned Mask = MI.getOperand(1).getImm(); 709 ITBlock.setITState(Firstcond, Mask); 710 } 711 712 return result; 713 } 714 715 // We want to read exactly 4 bytes of data. 716 if (Region.readBytes(Address, 4, bytes) == -1) { 717 Size = 0; 718 return MCDisassembler::Fail; 719 } 720 721 uint32_t insn32 = (bytes[3] << 8) | 722 (bytes[2] << 0) | 723 (bytes[1] << 24) | 724 (bytes[0] << 16); 725 MI.clear(); 726 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 727 this, STI); 728 if (result != MCDisassembler::Fail) { 729 Size = 4; 730 bool InITBlock = ITBlock.instrInITBlock(); 731 Check(result, AddThumbPredicate(MI)); 732 AddThumb1SBit(MI, InITBlock); 733 return result; 734 } 735 736 MI.clear(); 737 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 738 this, STI); 739 if (result != MCDisassembler::Fail) { 740 Size = 4; 741 Check(result, AddThumbPredicate(MI)); 742 return result; 743 } 744 745 MI.clear(); 746 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 747 if (result != MCDisassembler::Fail) { 748 Size = 4; 749 UpdateThumbVFPPredicate(MI); 750 return result; 751 } 752 753 MI.clear(); 754 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 755 this, STI); 756 if (result != MCDisassembler::Fail) { 757 Size = 4; 758 Check(result, AddThumbPredicate(MI)); 759 return result; 760 } 761 762 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 763 MI.clear(); 764 uint32_t NEONLdStInsn = insn32; 765 NEONLdStInsn &= 0xF0FFFFFF; 766 NEONLdStInsn |= 0x04000000; 767 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 768 Address, this, STI); 769 if (result != MCDisassembler::Fail) { 770 Size = 4; 771 Check(result, AddThumbPredicate(MI)); 772 return result; 773 } 774 } 775 776 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 777 MI.clear(); 778 uint32_t NEONDataInsn = insn32; 779 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 780 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 781 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 782 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 783 Address, this, STI); 784 if (result != MCDisassembler::Fail) { 785 Size = 4; 786 Check(result, AddThumbPredicate(MI)); 787 return result; 788 } 789 } 790 791 Size = 0; 792 return MCDisassembler::Fail; 793 } 794 795 796 extern "C" void LLVMInitializeARMDisassembler() { 797 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 798 createARMDisassembler); 799 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 800 createThumbDisassembler); 801 } 802 803 static const uint16_t GPRDecoderTable[] = { 804 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 805 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 806 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 807 ARM::R12, ARM::SP, ARM::LR, ARM::PC 808 }; 809 810 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 811 uint64_t Address, const void *Decoder) { 812 if (RegNo > 15) 813 return MCDisassembler::Fail; 814 815 unsigned Register = GPRDecoderTable[RegNo]; 816 Inst.addOperand(MCOperand::CreateReg(Register)); 817 return MCDisassembler::Success; 818 } 819 820 static DecodeStatus 821 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = MCDisassembler::Success; 824 825 if (RegNo == 15) 826 S = MCDisassembler::SoftFail; 827 828 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 829 830 return S; 831 } 832 833 static DecodeStatus 834 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 835 uint64_t Address, const void *Decoder) { 836 DecodeStatus S = MCDisassembler::Success; 837 838 if (RegNo == 15) 839 { 840 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 841 return MCDisassembler::Success; 842 } 843 844 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 845 return S; 846 } 847 848 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 849 uint64_t Address, const void *Decoder) { 850 if (RegNo > 7) 851 return MCDisassembler::Fail; 852 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 853 } 854 855 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 856 uint64_t Address, const void *Decoder) { 857 unsigned Register = 0; 858 switch (RegNo) { 859 case 0: 860 Register = ARM::R0; 861 break; 862 case 1: 863 Register = ARM::R1; 864 break; 865 case 2: 866 Register = ARM::R2; 867 break; 868 case 3: 869 Register = ARM::R3; 870 break; 871 case 9: 872 Register = ARM::R9; 873 break; 874 case 12: 875 Register = ARM::R12; 876 break; 877 default: 878 return MCDisassembler::Fail; 879 } 880 881 Inst.addOperand(MCOperand::CreateReg(Register)); 882 return MCDisassembler::Success; 883 } 884 885 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 886 uint64_t Address, const void *Decoder) { 887 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 888 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 889 } 890 891 static const uint16_t SPRDecoderTable[] = { 892 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 893 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 894 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 895 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 896 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 897 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 898 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 899 ARM::S28, ARM::S29, ARM::S30, ARM::S31 900 }; 901 902 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 903 uint64_t Address, const void *Decoder) { 904 if (RegNo > 31) 905 return MCDisassembler::Fail; 906 907 unsigned Register = SPRDecoderTable[RegNo]; 908 Inst.addOperand(MCOperand::CreateReg(Register)); 909 return MCDisassembler::Success; 910 } 911 912 static const uint16_t DPRDecoderTable[] = { 913 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 914 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 915 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 916 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 917 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 918 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 919 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 920 ARM::D28, ARM::D29, ARM::D30, ARM::D31 921 }; 922 923 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 31) 926 return MCDisassembler::Fail; 927 928 unsigned Register = DPRDecoderTable[RegNo]; 929 Inst.addOperand(MCOperand::CreateReg(Register)); 930 return MCDisassembler::Success; 931 } 932 933 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 934 uint64_t Address, const void *Decoder) { 935 if (RegNo > 7) 936 return MCDisassembler::Fail; 937 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 938 } 939 940 static DecodeStatus 941 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) { 943 if (RegNo > 15) 944 return MCDisassembler::Fail; 945 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 946 } 947 948 static const uint16_t QPRDecoderTable[] = { 949 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 950 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 951 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 952 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 953 }; 954 955 956 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 957 uint64_t Address, const void *Decoder) { 958 if (RegNo > 31 || (RegNo & 1) != 0) 959 return MCDisassembler::Fail; 960 RegNo >>= 1; 961 962 unsigned Register = QPRDecoderTable[RegNo]; 963 Inst.addOperand(MCOperand::CreateReg(Register)); 964 return MCDisassembler::Success; 965 } 966 967 static const uint16_t DPairDecoderTable[] = { 968 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 969 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 970 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 971 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 972 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 973 ARM::Q15 974 }; 975 976 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 977 uint64_t Address, const void *Decoder) { 978 if (RegNo > 30) 979 return MCDisassembler::Fail; 980 981 unsigned Register = DPairDecoderTable[RegNo]; 982 Inst.addOperand(MCOperand::CreateReg(Register)); 983 return MCDisassembler::Success; 984 } 985 986 static const uint16_t DPairSpacedDecoderTable[] = { 987 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 988 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 989 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 990 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 991 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 992 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 993 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 994 ARM::D28_D30, ARM::D29_D31 995 }; 996 997 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 998 unsigned RegNo, 999 uint64_t Address, 1000 const void *Decoder) { 1001 if (RegNo > 29) 1002 return MCDisassembler::Fail; 1003 1004 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1005 Inst.addOperand(MCOperand::CreateReg(Register)); 1006 return MCDisassembler::Success; 1007 } 1008 1009 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1010 uint64_t Address, const void *Decoder) { 1011 if (Val == 0xF) return MCDisassembler::Fail; 1012 // AL predicate is not allowed on Thumb1 branches. 1013 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1014 return MCDisassembler::Fail; 1015 Inst.addOperand(MCOperand::CreateImm(Val)); 1016 if (Val == ARMCC::AL) { 1017 Inst.addOperand(MCOperand::CreateReg(0)); 1018 } else 1019 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1020 return MCDisassembler::Success; 1021 } 1022 1023 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1024 uint64_t Address, const void *Decoder) { 1025 if (Val) 1026 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1027 else 1028 Inst.addOperand(MCOperand::CreateReg(0)); 1029 return MCDisassembler::Success; 1030 } 1031 1032 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1033 uint64_t Address, const void *Decoder) { 1034 uint32_t imm = Val & 0xFF; 1035 uint32_t rot = (Val & 0xF00) >> 7; 1036 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1037 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1038 return MCDisassembler::Success; 1039 } 1040 1041 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1042 uint64_t Address, const void *Decoder) { 1043 DecodeStatus S = MCDisassembler::Success; 1044 1045 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1046 unsigned type = fieldFromInstruction(Val, 5, 2); 1047 unsigned imm = fieldFromInstruction(Val, 7, 5); 1048 1049 // Register-immediate 1050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1051 return MCDisassembler::Fail; 1052 1053 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1054 switch (type) { 1055 case 0: 1056 Shift = ARM_AM::lsl; 1057 break; 1058 case 1: 1059 Shift = ARM_AM::lsr; 1060 break; 1061 case 2: 1062 Shift = ARM_AM::asr; 1063 break; 1064 case 3: 1065 Shift = ARM_AM::ror; 1066 break; 1067 } 1068 1069 if (Shift == ARM_AM::ror && imm == 0) 1070 Shift = ARM_AM::rrx; 1071 1072 unsigned Op = Shift | (imm << 3); 1073 Inst.addOperand(MCOperand::CreateImm(Op)); 1074 1075 return S; 1076 } 1077 1078 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1079 uint64_t Address, const void *Decoder) { 1080 DecodeStatus S = MCDisassembler::Success; 1081 1082 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1083 unsigned type = fieldFromInstruction(Val, 5, 2); 1084 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1085 1086 // Register-register 1087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1088 return MCDisassembler::Fail; 1089 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1090 return MCDisassembler::Fail; 1091 1092 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1093 switch (type) { 1094 case 0: 1095 Shift = ARM_AM::lsl; 1096 break; 1097 case 1: 1098 Shift = ARM_AM::lsr; 1099 break; 1100 case 2: 1101 Shift = ARM_AM::asr; 1102 break; 1103 case 3: 1104 Shift = ARM_AM::ror; 1105 break; 1106 } 1107 1108 Inst.addOperand(MCOperand::CreateImm(Shift)); 1109 1110 return S; 1111 } 1112 1113 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1114 uint64_t Address, const void *Decoder) { 1115 DecodeStatus S = MCDisassembler::Success; 1116 1117 bool writebackLoad = false; 1118 unsigned writebackReg = 0; 1119 switch (Inst.getOpcode()) { 1120 default: 1121 break; 1122 case ARM::LDMIA_UPD: 1123 case ARM::LDMDB_UPD: 1124 case ARM::LDMIB_UPD: 1125 case ARM::LDMDA_UPD: 1126 case ARM::t2LDMIA_UPD: 1127 case ARM::t2LDMDB_UPD: 1128 writebackLoad = true; 1129 writebackReg = Inst.getOperand(0).getReg(); 1130 break; 1131 } 1132 1133 // Empty register lists are not allowed. 1134 if (Val == 0) return MCDisassembler::Fail; 1135 for (unsigned i = 0; i < 16; ++i) { 1136 if (Val & (1 << i)) { 1137 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1138 return MCDisassembler::Fail; 1139 // Writeback not allowed if Rn is in the target list. 1140 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1141 Check(S, MCDisassembler::SoftFail); 1142 } 1143 } 1144 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1153 unsigned regs = fieldFromInstruction(Val, 0, 8); 1154 1155 // In case of unpredictable encoding, tweak the operands. 1156 if (regs == 0 || (Vd + regs) > 32) { 1157 regs = Vd + regs > 32 ? 32 - Vd : regs; 1158 regs = std::max( 1u, regs); 1159 S = MCDisassembler::SoftFail; 1160 } 1161 1162 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 for (unsigned i = 0; i < (regs - 1); ++i) { 1165 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1166 return MCDisassembler::Fail; 1167 } 1168 1169 return S; 1170 } 1171 1172 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1173 uint64_t Address, const void *Decoder) { 1174 DecodeStatus S = MCDisassembler::Success; 1175 1176 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1177 unsigned regs = fieldFromInstruction(Val, 1, 7); 1178 1179 // In case of unpredictable encoding, tweak the operands. 1180 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1181 regs = Vd + regs > 32 ? 32 - Vd : regs; 1182 regs = std::max( 1u, regs); 1183 regs = std::min(16u, regs); 1184 S = MCDisassembler::SoftFail; 1185 } 1186 1187 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1188 return MCDisassembler::Fail; 1189 for (unsigned i = 0; i < (regs - 1); ++i) { 1190 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1191 return MCDisassembler::Fail; 1192 } 1193 1194 return S; 1195 } 1196 1197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1198 uint64_t Address, const void *Decoder) { 1199 // This operand encodes a mask of contiguous zeros between a specified MSB 1200 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1201 // the mask of all bits LSB-and-lower, and then xor them to create 1202 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1203 // create the final mask. 1204 unsigned msb = fieldFromInstruction(Val, 5, 5); 1205 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1206 1207 DecodeStatus S = MCDisassembler::Success; 1208 if (lsb > msb) { 1209 Check(S, MCDisassembler::SoftFail); 1210 // The check above will cause the warning for the "potentially undefined 1211 // instruction encoding" but we can't build a bad MCOperand value here 1212 // with a lsb > msb or else printing the MCInst will cause a crash. 1213 lsb = msb; 1214 } 1215 1216 uint32_t msb_mask = 0xFFFFFFFF; 1217 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1218 uint32_t lsb_mask = (1U << lsb) - 1; 1219 1220 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1221 return S; 1222 } 1223 1224 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1225 uint64_t Address, const void *Decoder) { 1226 DecodeStatus S = MCDisassembler::Success; 1227 1228 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1229 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1230 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1231 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1233 unsigned U = fieldFromInstruction(Insn, 23, 1); 1234 1235 switch (Inst.getOpcode()) { 1236 case ARM::LDC_OFFSET: 1237 case ARM::LDC_PRE: 1238 case ARM::LDC_POST: 1239 case ARM::LDC_OPTION: 1240 case ARM::LDCL_OFFSET: 1241 case ARM::LDCL_PRE: 1242 case ARM::LDCL_POST: 1243 case ARM::LDCL_OPTION: 1244 case ARM::STC_OFFSET: 1245 case ARM::STC_PRE: 1246 case ARM::STC_POST: 1247 case ARM::STC_OPTION: 1248 case ARM::STCL_OFFSET: 1249 case ARM::STCL_PRE: 1250 case ARM::STCL_POST: 1251 case ARM::STCL_OPTION: 1252 case ARM::t2LDC_OFFSET: 1253 case ARM::t2LDC_PRE: 1254 case ARM::t2LDC_POST: 1255 case ARM::t2LDC_OPTION: 1256 case ARM::t2LDCL_OFFSET: 1257 case ARM::t2LDCL_PRE: 1258 case ARM::t2LDCL_POST: 1259 case ARM::t2LDCL_OPTION: 1260 case ARM::t2STC_OFFSET: 1261 case ARM::t2STC_PRE: 1262 case ARM::t2STC_POST: 1263 case ARM::t2STC_OPTION: 1264 case ARM::t2STCL_OFFSET: 1265 case ARM::t2STCL_PRE: 1266 case ARM::t2STCL_POST: 1267 case ARM::t2STCL_OPTION: 1268 if (coproc == 0xA || coproc == 0xB) 1269 return MCDisassembler::Fail; 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 Inst.addOperand(MCOperand::CreateImm(coproc)); 1276 Inst.addOperand(MCOperand::CreateImm(CRd)); 1277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1278 return MCDisassembler::Fail; 1279 1280 switch (Inst.getOpcode()) { 1281 case ARM::t2LDC2_OFFSET: 1282 case ARM::t2LDC2L_OFFSET: 1283 case ARM::t2LDC2_PRE: 1284 case ARM::t2LDC2L_PRE: 1285 case ARM::t2STC2_OFFSET: 1286 case ARM::t2STC2L_OFFSET: 1287 case ARM::t2STC2_PRE: 1288 case ARM::t2STC2L_PRE: 1289 case ARM::LDC2_OFFSET: 1290 case ARM::LDC2L_OFFSET: 1291 case ARM::LDC2_PRE: 1292 case ARM::LDC2L_PRE: 1293 case ARM::STC2_OFFSET: 1294 case ARM::STC2L_OFFSET: 1295 case ARM::STC2_PRE: 1296 case ARM::STC2L_PRE: 1297 case ARM::t2LDC_OFFSET: 1298 case ARM::t2LDCL_OFFSET: 1299 case ARM::t2LDC_PRE: 1300 case ARM::t2LDCL_PRE: 1301 case ARM::t2STC_OFFSET: 1302 case ARM::t2STCL_OFFSET: 1303 case ARM::t2STC_PRE: 1304 case ARM::t2STCL_PRE: 1305 case ARM::LDC_OFFSET: 1306 case ARM::LDCL_OFFSET: 1307 case ARM::LDC_PRE: 1308 case ARM::LDCL_PRE: 1309 case ARM::STC_OFFSET: 1310 case ARM::STCL_OFFSET: 1311 case ARM::STC_PRE: 1312 case ARM::STCL_PRE: 1313 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1314 Inst.addOperand(MCOperand::CreateImm(imm)); 1315 break; 1316 case ARM::t2LDC2_POST: 1317 case ARM::t2LDC2L_POST: 1318 case ARM::t2STC2_POST: 1319 case ARM::t2STC2L_POST: 1320 case ARM::LDC2_POST: 1321 case ARM::LDC2L_POST: 1322 case ARM::STC2_POST: 1323 case ARM::STC2L_POST: 1324 case ARM::t2LDC_POST: 1325 case ARM::t2LDCL_POST: 1326 case ARM::t2STC_POST: 1327 case ARM::t2STCL_POST: 1328 case ARM::LDC_POST: 1329 case ARM::LDCL_POST: 1330 case ARM::STC_POST: 1331 case ARM::STCL_POST: 1332 imm |= U << 8; 1333 // fall through. 1334 default: 1335 // The 'option' variant doesn't encode 'U' in the immediate since 1336 // the immediate is unsigned [0,255]. 1337 Inst.addOperand(MCOperand::CreateImm(imm)); 1338 break; 1339 } 1340 1341 switch (Inst.getOpcode()) { 1342 case ARM::LDC_OFFSET: 1343 case ARM::LDC_PRE: 1344 case ARM::LDC_POST: 1345 case ARM::LDC_OPTION: 1346 case ARM::LDCL_OFFSET: 1347 case ARM::LDCL_PRE: 1348 case ARM::LDCL_POST: 1349 case ARM::LDCL_OPTION: 1350 case ARM::STC_OFFSET: 1351 case ARM::STC_PRE: 1352 case ARM::STC_POST: 1353 case ARM::STC_OPTION: 1354 case ARM::STCL_OFFSET: 1355 case ARM::STCL_PRE: 1356 case ARM::STCL_POST: 1357 case ARM::STCL_OPTION: 1358 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1359 return MCDisassembler::Fail; 1360 break; 1361 default: 1362 break; 1363 } 1364 1365 return S; 1366 } 1367 1368 static DecodeStatus 1369 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1370 uint64_t Address, const void *Decoder) { 1371 DecodeStatus S = MCDisassembler::Success; 1372 1373 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1374 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1375 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1376 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1377 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1378 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1379 unsigned P = fieldFromInstruction(Insn, 24, 1); 1380 unsigned W = fieldFromInstruction(Insn, 21, 1); 1381 1382 // On stores, the writeback operand precedes Rt. 1383 switch (Inst.getOpcode()) { 1384 case ARM::STR_POST_IMM: 1385 case ARM::STR_POST_REG: 1386 case ARM::STRB_POST_IMM: 1387 case ARM::STRB_POST_REG: 1388 case ARM::STRT_POST_REG: 1389 case ARM::STRT_POST_IMM: 1390 case ARM::STRBT_POST_REG: 1391 case ARM::STRBT_POST_IMM: 1392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1393 return MCDisassembler::Fail; 1394 break; 1395 default: 1396 break; 1397 } 1398 1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 1402 // On loads, the writeback operand comes after Rt. 1403 switch (Inst.getOpcode()) { 1404 case ARM::LDR_POST_IMM: 1405 case ARM::LDR_POST_REG: 1406 case ARM::LDRB_POST_IMM: 1407 case ARM::LDRB_POST_REG: 1408 case ARM::LDRBT_POST_REG: 1409 case ARM::LDRBT_POST_IMM: 1410 case ARM::LDRT_POST_REG: 1411 case ARM::LDRT_POST_IMM: 1412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1413 return MCDisassembler::Fail; 1414 break; 1415 default: 1416 break; 1417 } 1418 1419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1420 return MCDisassembler::Fail; 1421 1422 ARM_AM::AddrOpc Op = ARM_AM::add; 1423 if (!fieldFromInstruction(Insn, 23, 1)) 1424 Op = ARM_AM::sub; 1425 1426 bool writeback = (P == 0) || (W == 1); 1427 unsigned idx_mode = 0; 1428 if (P && writeback) 1429 idx_mode = ARMII::IndexModePre; 1430 else if (!P && writeback) 1431 idx_mode = ARMII::IndexModePost; 1432 1433 if (writeback && (Rn == 15 || Rn == Rt)) 1434 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1435 1436 if (reg) { 1437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1438 return MCDisassembler::Fail; 1439 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1440 switch( fieldFromInstruction(Insn, 5, 2)) { 1441 case 0: 1442 Opc = ARM_AM::lsl; 1443 break; 1444 case 1: 1445 Opc = ARM_AM::lsr; 1446 break; 1447 case 2: 1448 Opc = ARM_AM::asr; 1449 break; 1450 case 3: 1451 Opc = ARM_AM::ror; 1452 break; 1453 default: 1454 return MCDisassembler::Fail; 1455 } 1456 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1457 if (Opc == ARM_AM::ror && amt == 0) 1458 Opc = ARM_AM::rrx; 1459 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1460 1461 Inst.addOperand(MCOperand::CreateImm(imm)); 1462 } else { 1463 Inst.addOperand(MCOperand::CreateReg(0)); 1464 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1465 Inst.addOperand(MCOperand::CreateImm(tmp)); 1466 } 1467 1468 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1469 return MCDisassembler::Fail; 1470 1471 return S; 1472 } 1473 1474 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1475 uint64_t Address, const void *Decoder) { 1476 DecodeStatus S = MCDisassembler::Success; 1477 1478 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1479 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1480 unsigned type = fieldFromInstruction(Val, 5, 2); 1481 unsigned imm = fieldFromInstruction(Val, 7, 5); 1482 unsigned U = fieldFromInstruction(Val, 12, 1); 1483 1484 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1485 switch (type) { 1486 case 0: 1487 ShOp = ARM_AM::lsl; 1488 break; 1489 case 1: 1490 ShOp = ARM_AM::lsr; 1491 break; 1492 case 2: 1493 ShOp = ARM_AM::asr; 1494 break; 1495 case 3: 1496 ShOp = ARM_AM::ror; 1497 break; 1498 } 1499 1500 if (ShOp == ARM_AM::ror && imm == 0) 1501 ShOp = ARM_AM::rrx; 1502 1503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 unsigned shift; 1508 if (U) 1509 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1510 else 1511 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1512 Inst.addOperand(MCOperand::CreateImm(shift)); 1513 1514 return S; 1515 } 1516 1517 static DecodeStatus 1518 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1519 uint64_t Address, const void *Decoder) { 1520 DecodeStatus S = MCDisassembler::Success; 1521 1522 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1523 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1524 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1525 unsigned type = fieldFromInstruction(Insn, 22, 1); 1526 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1527 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1528 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1529 unsigned W = fieldFromInstruction(Insn, 21, 1); 1530 unsigned P = fieldFromInstruction(Insn, 24, 1); 1531 unsigned Rt2 = Rt + 1; 1532 1533 bool writeback = (W == 1) | (P == 0); 1534 1535 // For {LD,ST}RD, Rt must be even, else undefined. 1536 switch (Inst.getOpcode()) { 1537 case ARM::STRD: 1538 case ARM::STRD_PRE: 1539 case ARM::STRD_POST: 1540 case ARM::LDRD: 1541 case ARM::LDRD_PRE: 1542 case ARM::LDRD_POST: 1543 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1544 break; 1545 default: 1546 break; 1547 } 1548 switch (Inst.getOpcode()) { 1549 case ARM::STRD: 1550 case ARM::STRD_PRE: 1551 case ARM::STRD_POST: 1552 if (P == 0 && W == 1) 1553 S = MCDisassembler::SoftFail; 1554 1555 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1556 S = MCDisassembler::SoftFail; 1557 if (type && Rm == 15) 1558 S = MCDisassembler::SoftFail; 1559 if (Rt2 == 15) 1560 S = MCDisassembler::SoftFail; 1561 if (!type && fieldFromInstruction(Insn, 8, 4)) 1562 S = MCDisassembler::SoftFail; 1563 break; 1564 case ARM::STRH: 1565 case ARM::STRH_PRE: 1566 case ARM::STRH_POST: 1567 if (Rt == 15) 1568 S = MCDisassembler::SoftFail; 1569 if (writeback && (Rn == 15 || Rn == Rt)) 1570 S = MCDisassembler::SoftFail; 1571 if (!type && Rm == 15) 1572 S = MCDisassembler::SoftFail; 1573 break; 1574 case ARM::LDRD: 1575 case ARM::LDRD_PRE: 1576 case ARM::LDRD_POST: 1577 if (type && Rn == 15){ 1578 if (Rt2 == 15) 1579 S = MCDisassembler::SoftFail; 1580 break; 1581 } 1582 if (P == 0 && W == 1) 1583 S = MCDisassembler::SoftFail; 1584 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1585 S = MCDisassembler::SoftFail; 1586 if (!type && writeback && Rn == 15) 1587 S = MCDisassembler::SoftFail; 1588 if (writeback && (Rn == Rt || Rn == Rt2)) 1589 S = MCDisassembler::SoftFail; 1590 break; 1591 case ARM::LDRH: 1592 case ARM::LDRH_PRE: 1593 case ARM::LDRH_POST: 1594 if (type && Rn == 15){ 1595 if (Rt == 15) 1596 S = MCDisassembler::SoftFail; 1597 break; 1598 } 1599 if (Rt == 15) 1600 S = MCDisassembler::SoftFail; 1601 if (!type && Rm == 15) 1602 S = MCDisassembler::SoftFail; 1603 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1604 S = MCDisassembler::SoftFail; 1605 break; 1606 case ARM::LDRSH: 1607 case ARM::LDRSH_PRE: 1608 case ARM::LDRSH_POST: 1609 case ARM::LDRSB: 1610 case ARM::LDRSB_PRE: 1611 case ARM::LDRSB_POST: 1612 if (type && Rn == 15){ 1613 if (Rt == 15) 1614 S = MCDisassembler::SoftFail; 1615 break; 1616 } 1617 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1618 S = MCDisassembler::SoftFail; 1619 if (!type && (Rt == 15 || Rm == 15)) 1620 S = MCDisassembler::SoftFail; 1621 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1622 S = MCDisassembler::SoftFail; 1623 break; 1624 default: 1625 break; 1626 } 1627 1628 if (writeback) { // Writeback 1629 if (P) 1630 U |= ARMII::IndexModePre << 9; 1631 else 1632 U |= ARMII::IndexModePost << 9; 1633 1634 // On stores, the writeback operand precedes Rt. 1635 switch (Inst.getOpcode()) { 1636 case ARM::STRD: 1637 case ARM::STRD_PRE: 1638 case ARM::STRD_POST: 1639 case ARM::STRH: 1640 case ARM::STRH_PRE: 1641 case ARM::STRH_POST: 1642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1643 return MCDisassembler::Fail; 1644 break; 1645 default: 1646 break; 1647 } 1648 } 1649 1650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1651 return MCDisassembler::Fail; 1652 switch (Inst.getOpcode()) { 1653 case ARM::STRD: 1654 case ARM::STRD_PRE: 1655 case ARM::STRD_POST: 1656 case ARM::LDRD: 1657 case ARM::LDRD_PRE: 1658 case ARM::LDRD_POST: 1659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1660 return MCDisassembler::Fail; 1661 break; 1662 default: 1663 break; 1664 } 1665 1666 if (writeback) { 1667 // On loads, the writeback operand comes after Rt. 1668 switch (Inst.getOpcode()) { 1669 case ARM::LDRD: 1670 case ARM::LDRD_PRE: 1671 case ARM::LDRD_POST: 1672 case ARM::LDRH: 1673 case ARM::LDRH_PRE: 1674 case ARM::LDRH_POST: 1675 case ARM::LDRSH: 1676 case ARM::LDRSH_PRE: 1677 case ARM::LDRSH_POST: 1678 case ARM::LDRSB: 1679 case ARM::LDRSB_PRE: 1680 case ARM::LDRSB_POST: 1681 case ARM::LDRHTr: 1682 case ARM::LDRSBTr: 1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1684 return MCDisassembler::Fail; 1685 break; 1686 default: 1687 break; 1688 } 1689 } 1690 1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1692 return MCDisassembler::Fail; 1693 1694 if (type) { 1695 Inst.addOperand(MCOperand::CreateReg(0)); 1696 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1697 } else { 1698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1699 return MCDisassembler::Fail; 1700 Inst.addOperand(MCOperand::CreateImm(U)); 1701 } 1702 1703 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1704 return MCDisassembler::Fail; 1705 1706 return S; 1707 } 1708 1709 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1710 uint64_t Address, const void *Decoder) { 1711 DecodeStatus S = MCDisassembler::Success; 1712 1713 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1714 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1715 1716 switch (mode) { 1717 case 0: 1718 mode = ARM_AM::da; 1719 break; 1720 case 1: 1721 mode = ARM_AM::ia; 1722 break; 1723 case 2: 1724 mode = ARM_AM::db; 1725 break; 1726 case 3: 1727 mode = ARM_AM::ib; 1728 break; 1729 } 1730 1731 Inst.addOperand(MCOperand::CreateImm(mode)); 1732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1733 return MCDisassembler::Fail; 1734 1735 return S; 1736 } 1737 1738 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1739 uint64_t Address, const void *Decoder) { 1740 DecodeStatus S = MCDisassembler::Success; 1741 1742 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1743 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1744 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1745 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1746 1747 if (pred == 0xF) 1748 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1749 1750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1751 return MCDisassembler::Fail; 1752 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1755 return MCDisassembler::Fail; 1756 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1757 return MCDisassembler::Fail; 1758 return S; 1759 } 1760 1761 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1762 unsigned Insn, 1763 uint64_t Address, const void *Decoder) { 1764 DecodeStatus S = MCDisassembler::Success; 1765 1766 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1767 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1768 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1769 1770 if (pred == 0xF) { 1771 // Ambiguous with RFE and SRS 1772 switch (Inst.getOpcode()) { 1773 case ARM::LDMDA: 1774 Inst.setOpcode(ARM::RFEDA); 1775 break; 1776 case ARM::LDMDA_UPD: 1777 Inst.setOpcode(ARM::RFEDA_UPD); 1778 break; 1779 case ARM::LDMDB: 1780 Inst.setOpcode(ARM::RFEDB); 1781 break; 1782 case ARM::LDMDB_UPD: 1783 Inst.setOpcode(ARM::RFEDB_UPD); 1784 break; 1785 case ARM::LDMIA: 1786 Inst.setOpcode(ARM::RFEIA); 1787 break; 1788 case ARM::LDMIA_UPD: 1789 Inst.setOpcode(ARM::RFEIA_UPD); 1790 break; 1791 case ARM::LDMIB: 1792 Inst.setOpcode(ARM::RFEIB); 1793 break; 1794 case ARM::LDMIB_UPD: 1795 Inst.setOpcode(ARM::RFEIB_UPD); 1796 break; 1797 case ARM::STMDA: 1798 Inst.setOpcode(ARM::SRSDA); 1799 break; 1800 case ARM::STMDA_UPD: 1801 Inst.setOpcode(ARM::SRSDA_UPD); 1802 break; 1803 case ARM::STMDB: 1804 Inst.setOpcode(ARM::SRSDB); 1805 break; 1806 case ARM::STMDB_UPD: 1807 Inst.setOpcode(ARM::SRSDB_UPD); 1808 break; 1809 case ARM::STMIA: 1810 Inst.setOpcode(ARM::SRSIA); 1811 break; 1812 case ARM::STMIA_UPD: 1813 Inst.setOpcode(ARM::SRSIA_UPD); 1814 break; 1815 case ARM::STMIB: 1816 Inst.setOpcode(ARM::SRSIB); 1817 break; 1818 case ARM::STMIB_UPD: 1819 Inst.setOpcode(ARM::SRSIB_UPD); 1820 break; 1821 default: 1822 return MCDisassembler::Fail; 1823 } 1824 1825 // For stores (which become SRS's, the only operand is the mode. 1826 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1827 // Check SRS encoding constraints 1828 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1829 fieldFromInstruction(Insn, 20, 1) == 0)) 1830 return MCDisassembler::Fail; 1831 1832 Inst.addOperand( 1833 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1834 return S; 1835 } 1836 1837 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1838 } 1839 1840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1843 return MCDisassembler::Fail; // Tied 1844 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1845 return MCDisassembler::Fail; 1846 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1847 return MCDisassembler::Fail; 1848 1849 return S; 1850 } 1851 1852 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1853 uint64_t Address, const void *Decoder) { 1854 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1855 unsigned M = fieldFromInstruction(Insn, 17, 1); 1856 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1857 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1858 1859 DecodeStatus S = MCDisassembler::Success; 1860 1861 // This decoder is called from multiple location that do not check 1862 // the full encoding is valid before they do. 1863 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1864 fieldFromInstruction(Insn, 16, 1) != 0 || 1865 fieldFromInstruction(Insn, 20, 8) != 0x10) 1866 return MCDisassembler::Fail; 1867 1868 // imod == '01' --> UNPREDICTABLE 1869 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1870 // return failure here. The '01' imod value is unprintable, so there's 1871 // nothing useful we could do even if we returned UNPREDICTABLE. 1872 1873 if (imod == 1) return MCDisassembler::Fail; 1874 1875 if (imod && M) { 1876 Inst.setOpcode(ARM::CPS3p); 1877 Inst.addOperand(MCOperand::CreateImm(imod)); 1878 Inst.addOperand(MCOperand::CreateImm(iflags)); 1879 Inst.addOperand(MCOperand::CreateImm(mode)); 1880 } else if (imod && !M) { 1881 Inst.setOpcode(ARM::CPS2p); 1882 Inst.addOperand(MCOperand::CreateImm(imod)); 1883 Inst.addOperand(MCOperand::CreateImm(iflags)); 1884 if (mode) S = MCDisassembler::SoftFail; 1885 } else if (!imod && M) { 1886 Inst.setOpcode(ARM::CPS1p); 1887 Inst.addOperand(MCOperand::CreateImm(mode)); 1888 if (iflags) S = MCDisassembler::SoftFail; 1889 } else { 1890 // imod == '00' && M == '0' --> UNPREDICTABLE 1891 Inst.setOpcode(ARM::CPS1p); 1892 Inst.addOperand(MCOperand::CreateImm(mode)); 1893 S = MCDisassembler::SoftFail; 1894 } 1895 1896 return S; 1897 } 1898 1899 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1900 uint64_t Address, const void *Decoder) { 1901 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1902 unsigned M = fieldFromInstruction(Insn, 8, 1); 1903 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1904 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1905 1906 DecodeStatus S = MCDisassembler::Success; 1907 1908 // imod == '01' --> UNPREDICTABLE 1909 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1910 // return failure here. The '01' imod value is unprintable, so there's 1911 // nothing useful we could do even if we returned UNPREDICTABLE. 1912 1913 if (imod == 1) return MCDisassembler::Fail; 1914 1915 if (imod && M) { 1916 Inst.setOpcode(ARM::t2CPS3p); 1917 Inst.addOperand(MCOperand::CreateImm(imod)); 1918 Inst.addOperand(MCOperand::CreateImm(iflags)); 1919 Inst.addOperand(MCOperand::CreateImm(mode)); 1920 } else if (imod && !M) { 1921 Inst.setOpcode(ARM::t2CPS2p); 1922 Inst.addOperand(MCOperand::CreateImm(imod)); 1923 Inst.addOperand(MCOperand::CreateImm(iflags)); 1924 if (mode) S = MCDisassembler::SoftFail; 1925 } else if (!imod && M) { 1926 Inst.setOpcode(ARM::t2CPS1p); 1927 Inst.addOperand(MCOperand::CreateImm(mode)); 1928 if (iflags) S = MCDisassembler::SoftFail; 1929 } else { 1930 // imod == '00' && M == '0' --> this is a HINT instruction 1931 int imm = fieldFromInstruction(Insn, 0, 8); 1932 // HINT are defined only for immediate in [0..4] 1933 if(imm > 4) return MCDisassembler::Fail; 1934 Inst.setOpcode(ARM::t2HINT); 1935 Inst.addOperand(MCOperand::CreateImm(imm)); 1936 } 1937 1938 return S; 1939 } 1940 1941 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1942 uint64_t Address, const void *Decoder) { 1943 DecodeStatus S = MCDisassembler::Success; 1944 1945 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1946 unsigned imm = 0; 1947 1948 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1949 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1950 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1951 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1952 1953 if (Inst.getOpcode() == ARM::t2MOVTi16) 1954 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1955 return MCDisassembler::Fail; 1956 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1957 return MCDisassembler::Fail; 1958 1959 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1960 Inst.addOperand(MCOperand::CreateImm(imm)); 1961 1962 return S; 1963 } 1964 1965 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 DecodeStatus S = MCDisassembler::Success; 1968 1969 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1970 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1971 unsigned imm = 0; 1972 1973 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 1974 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1975 1976 if (Inst.getOpcode() == ARM::MOVTi16) 1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1978 return MCDisassembler::Fail; 1979 1980 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 1983 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1984 Inst.addOperand(MCOperand::CreateImm(imm)); 1985 1986 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1987 return MCDisassembler::Fail; 1988 1989 return S; 1990 } 1991 1992 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1993 uint64_t Address, const void *Decoder) { 1994 DecodeStatus S = MCDisassembler::Success; 1995 1996 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 1997 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 1998 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 1999 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2000 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2001 2002 if (pred == 0xF) 2003 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2004 2005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2006 return MCDisassembler::Fail; 2007 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2008 return MCDisassembler::Fail; 2009 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2012 return MCDisassembler::Fail; 2013 2014 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2015 return MCDisassembler::Fail; 2016 2017 return S; 2018 } 2019 2020 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2021 uint64_t Address, const void *Decoder) { 2022 DecodeStatus S = MCDisassembler::Success; 2023 2024 unsigned add = fieldFromInstruction(Val, 12, 1); 2025 unsigned imm = fieldFromInstruction(Val, 0, 12); 2026 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2027 2028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2029 return MCDisassembler::Fail; 2030 2031 if (!add) imm *= -1; 2032 if (imm == 0 && !add) imm = INT32_MIN; 2033 Inst.addOperand(MCOperand::CreateImm(imm)); 2034 if (Rn == 15) 2035 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2036 2037 return S; 2038 } 2039 2040 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2041 uint64_t Address, const void *Decoder) { 2042 DecodeStatus S = MCDisassembler::Success; 2043 2044 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2045 unsigned U = fieldFromInstruction(Val, 8, 1); 2046 unsigned imm = fieldFromInstruction(Val, 0, 8); 2047 2048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 2051 if (U) 2052 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2053 else 2054 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2055 2056 return S; 2057 } 2058 2059 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2060 uint64_t Address, const void *Decoder) { 2061 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2062 } 2063 2064 static DecodeStatus 2065 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2066 uint64_t Address, const void *Decoder) { 2067 DecodeStatus Status = MCDisassembler::Success; 2068 2069 // Note the J1 and J2 values are from the encoded instruction. So here 2070 // change them to I1 and I2 values via as documented: 2071 // I1 = NOT(J1 EOR S); 2072 // I2 = NOT(J2 EOR S); 2073 // and build the imm32 with one trailing zero as documented: 2074 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2075 unsigned S = fieldFromInstruction(Insn, 26, 1); 2076 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2077 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2078 unsigned I1 = !(J1 ^ S); 2079 unsigned I2 = !(J2 ^ S); 2080 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2081 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2082 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2083 int imm32 = SignExtend32<24>(tmp << 1); 2084 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2085 true, 4, Inst, Decoder)) 2086 Inst.addOperand(MCOperand::CreateImm(imm32)); 2087 2088 return Status; 2089 } 2090 2091 static DecodeStatus 2092 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2093 uint64_t Address, const void *Decoder) { 2094 DecodeStatus S = MCDisassembler::Success; 2095 2096 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2097 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2098 2099 if (pred == 0xF) { 2100 Inst.setOpcode(ARM::BLXi); 2101 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2102 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2103 true, 4, Inst, Decoder)) 2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2105 return S; 2106 } 2107 2108 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2109 true, 4, Inst, Decoder)) 2110 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 2114 return S; 2115 } 2116 2117 2118 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2119 uint64_t Address, const void *Decoder) { 2120 DecodeStatus S = MCDisassembler::Success; 2121 2122 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2123 unsigned align = fieldFromInstruction(Val, 4, 2); 2124 2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 if (!align) 2128 Inst.addOperand(MCOperand::CreateImm(0)); 2129 else 2130 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2131 2132 return S; 2133 } 2134 2135 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2136 uint64_t Address, const void *Decoder) { 2137 DecodeStatus S = MCDisassembler::Success; 2138 2139 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2140 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2141 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2142 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2143 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2144 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2145 2146 // First output register 2147 switch (Inst.getOpcode()) { 2148 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2149 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2150 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2151 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2152 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2153 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2154 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2155 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2156 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2157 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 break; 2160 case ARM::VLD2b16: 2161 case ARM::VLD2b32: 2162 case ARM::VLD2b8: 2163 case ARM::VLD2b16wb_fixed: 2164 case ARM::VLD2b16wb_register: 2165 case ARM::VLD2b32wb_fixed: 2166 case ARM::VLD2b32wb_register: 2167 case ARM::VLD2b8wb_fixed: 2168 case ARM::VLD2b8wb_register: 2169 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2170 return MCDisassembler::Fail; 2171 break; 2172 default: 2173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 } 2176 2177 // Second output register 2178 switch (Inst.getOpcode()) { 2179 case ARM::VLD3d8: 2180 case ARM::VLD3d16: 2181 case ARM::VLD3d32: 2182 case ARM::VLD3d8_UPD: 2183 case ARM::VLD3d16_UPD: 2184 case ARM::VLD3d32_UPD: 2185 case ARM::VLD4d8: 2186 case ARM::VLD4d16: 2187 case ARM::VLD4d32: 2188 case ARM::VLD4d8_UPD: 2189 case ARM::VLD4d16_UPD: 2190 case ARM::VLD4d32_UPD: 2191 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2192 return MCDisassembler::Fail; 2193 break; 2194 case ARM::VLD3q8: 2195 case ARM::VLD3q16: 2196 case ARM::VLD3q32: 2197 case ARM::VLD3q8_UPD: 2198 case ARM::VLD3q16_UPD: 2199 case ARM::VLD3q32_UPD: 2200 case ARM::VLD4q8: 2201 case ARM::VLD4q16: 2202 case ARM::VLD4q32: 2203 case ARM::VLD4q8_UPD: 2204 case ARM::VLD4q16_UPD: 2205 case ARM::VLD4q32_UPD: 2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 default: 2209 break; 2210 } 2211 2212 // Third output register 2213 switch(Inst.getOpcode()) { 2214 case ARM::VLD3d8: 2215 case ARM::VLD3d16: 2216 case ARM::VLD3d32: 2217 case ARM::VLD3d8_UPD: 2218 case ARM::VLD3d16_UPD: 2219 case ARM::VLD3d32_UPD: 2220 case ARM::VLD4d8: 2221 case ARM::VLD4d16: 2222 case ARM::VLD4d32: 2223 case ARM::VLD4d8_UPD: 2224 case ARM::VLD4d16_UPD: 2225 case ARM::VLD4d32_UPD: 2226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2227 return MCDisassembler::Fail; 2228 break; 2229 case ARM::VLD3q8: 2230 case ARM::VLD3q16: 2231 case ARM::VLD3q32: 2232 case ARM::VLD3q8_UPD: 2233 case ARM::VLD3q16_UPD: 2234 case ARM::VLD3q32_UPD: 2235 case ARM::VLD4q8: 2236 case ARM::VLD4q16: 2237 case ARM::VLD4q32: 2238 case ARM::VLD4q8_UPD: 2239 case ARM::VLD4q16_UPD: 2240 case ARM::VLD4q32_UPD: 2241 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2242 return MCDisassembler::Fail; 2243 break; 2244 default: 2245 break; 2246 } 2247 2248 // Fourth output register 2249 switch (Inst.getOpcode()) { 2250 case ARM::VLD4d8: 2251 case ARM::VLD4d16: 2252 case ARM::VLD4d32: 2253 case ARM::VLD4d8_UPD: 2254 case ARM::VLD4d16_UPD: 2255 case ARM::VLD4d32_UPD: 2256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2257 return MCDisassembler::Fail; 2258 break; 2259 case ARM::VLD4q8: 2260 case ARM::VLD4q16: 2261 case ARM::VLD4q32: 2262 case ARM::VLD4q8_UPD: 2263 case ARM::VLD4q16_UPD: 2264 case ARM::VLD4q32_UPD: 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 break; 2268 default: 2269 break; 2270 } 2271 2272 // Writeback operand 2273 switch (Inst.getOpcode()) { 2274 case ARM::VLD1d8wb_fixed: 2275 case ARM::VLD1d16wb_fixed: 2276 case ARM::VLD1d32wb_fixed: 2277 case ARM::VLD1d64wb_fixed: 2278 case ARM::VLD1d8wb_register: 2279 case ARM::VLD1d16wb_register: 2280 case ARM::VLD1d32wb_register: 2281 case ARM::VLD1d64wb_register: 2282 case ARM::VLD1q8wb_fixed: 2283 case ARM::VLD1q16wb_fixed: 2284 case ARM::VLD1q32wb_fixed: 2285 case ARM::VLD1q64wb_fixed: 2286 case ARM::VLD1q8wb_register: 2287 case ARM::VLD1q16wb_register: 2288 case ARM::VLD1q32wb_register: 2289 case ARM::VLD1q64wb_register: 2290 case ARM::VLD1d8Twb_fixed: 2291 case ARM::VLD1d8Twb_register: 2292 case ARM::VLD1d16Twb_fixed: 2293 case ARM::VLD1d16Twb_register: 2294 case ARM::VLD1d32Twb_fixed: 2295 case ARM::VLD1d32Twb_register: 2296 case ARM::VLD1d64Twb_fixed: 2297 case ARM::VLD1d64Twb_register: 2298 case ARM::VLD1d8Qwb_fixed: 2299 case ARM::VLD1d8Qwb_register: 2300 case ARM::VLD1d16Qwb_fixed: 2301 case ARM::VLD1d16Qwb_register: 2302 case ARM::VLD1d32Qwb_fixed: 2303 case ARM::VLD1d32Qwb_register: 2304 case ARM::VLD1d64Qwb_fixed: 2305 case ARM::VLD1d64Qwb_register: 2306 case ARM::VLD2d8wb_fixed: 2307 case ARM::VLD2d16wb_fixed: 2308 case ARM::VLD2d32wb_fixed: 2309 case ARM::VLD2q8wb_fixed: 2310 case ARM::VLD2q16wb_fixed: 2311 case ARM::VLD2q32wb_fixed: 2312 case ARM::VLD2d8wb_register: 2313 case ARM::VLD2d16wb_register: 2314 case ARM::VLD2d32wb_register: 2315 case ARM::VLD2q8wb_register: 2316 case ARM::VLD2q16wb_register: 2317 case ARM::VLD2q32wb_register: 2318 case ARM::VLD2b8wb_fixed: 2319 case ARM::VLD2b16wb_fixed: 2320 case ARM::VLD2b32wb_fixed: 2321 case ARM::VLD2b8wb_register: 2322 case ARM::VLD2b16wb_register: 2323 case ARM::VLD2b32wb_register: 2324 Inst.addOperand(MCOperand::CreateImm(0)); 2325 break; 2326 case ARM::VLD3d8_UPD: 2327 case ARM::VLD3d16_UPD: 2328 case ARM::VLD3d32_UPD: 2329 case ARM::VLD3q8_UPD: 2330 case ARM::VLD3q16_UPD: 2331 case ARM::VLD3q32_UPD: 2332 case ARM::VLD4d8_UPD: 2333 case ARM::VLD4d16_UPD: 2334 case ARM::VLD4d32_UPD: 2335 case ARM::VLD4q8_UPD: 2336 case ARM::VLD4q16_UPD: 2337 case ARM::VLD4q32_UPD: 2338 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2339 return MCDisassembler::Fail; 2340 break; 2341 default: 2342 break; 2343 } 2344 2345 // AddrMode6 Base (register+alignment) 2346 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2347 return MCDisassembler::Fail; 2348 2349 // AddrMode6 Offset (register) 2350 switch (Inst.getOpcode()) { 2351 default: 2352 // The below have been updated to have explicit am6offset split 2353 // between fixed and register offset. For those instructions not 2354 // yet updated, we need to add an additional reg0 operand for the 2355 // fixed variant. 2356 // 2357 // The fixed offset encodes as Rm == 0xd, so we check for that. 2358 if (Rm == 0xd) { 2359 Inst.addOperand(MCOperand::CreateReg(0)); 2360 break; 2361 } 2362 // Fall through to handle the register offset variant. 2363 case ARM::VLD1d8wb_fixed: 2364 case ARM::VLD1d16wb_fixed: 2365 case ARM::VLD1d32wb_fixed: 2366 case ARM::VLD1d64wb_fixed: 2367 case ARM::VLD1d8Twb_fixed: 2368 case ARM::VLD1d16Twb_fixed: 2369 case ARM::VLD1d32Twb_fixed: 2370 case ARM::VLD1d64Twb_fixed: 2371 case ARM::VLD1d8Qwb_fixed: 2372 case ARM::VLD1d16Qwb_fixed: 2373 case ARM::VLD1d32Qwb_fixed: 2374 case ARM::VLD1d64Qwb_fixed: 2375 case ARM::VLD1d8wb_register: 2376 case ARM::VLD1d16wb_register: 2377 case ARM::VLD1d32wb_register: 2378 case ARM::VLD1d64wb_register: 2379 case ARM::VLD1q8wb_fixed: 2380 case ARM::VLD1q16wb_fixed: 2381 case ARM::VLD1q32wb_fixed: 2382 case ARM::VLD1q64wb_fixed: 2383 case ARM::VLD1q8wb_register: 2384 case ARM::VLD1q16wb_register: 2385 case ARM::VLD1q32wb_register: 2386 case ARM::VLD1q64wb_register: 2387 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2388 // variant encodes Rm == 0xf. Anything else is a register offset post- 2389 // increment and we need to add the register operand to the instruction. 2390 if (Rm != 0xD && Rm != 0xF && 2391 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2392 return MCDisassembler::Fail; 2393 break; 2394 case ARM::VLD2d8wb_fixed: 2395 case ARM::VLD2d16wb_fixed: 2396 case ARM::VLD2d32wb_fixed: 2397 case ARM::VLD2b8wb_fixed: 2398 case ARM::VLD2b16wb_fixed: 2399 case ARM::VLD2b32wb_fixed: 2400 case ARM::VLD2q8wb_fixed: 2401 case ARM::VLD2q16wb_fixed: 2402 case ARM::VLD2q32wb_fixed: 2403 break; 2404 } 2405 2406 return S; 2407 } 2408 2409 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn, 2410 uint64_t Addr, const void* Decoder) { 2411 unsigned type = fieldFromInstruction(Insn, 8, 4); 2412 unsigned align = fieldFromInstruction(Insn, 4, 2); 2413 if(type == 7 && (align & 2)) return MCDisassembler::Fail; 2414 if(type == 10 && align == 3) return MCDisassembler::Fail; 2415 if(type == 6 && (align & 2)) return MCDisassembler::Fail; 2416 2417 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2418 } 2419 2420 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn, 2421 uint64_t Addr, const void* Decoder) { 2422 unsigned size = fieldFromInstruction(Insn, 6, 2); 2423 if(size == 3) return MCDisassembler::Fail; 2424 2425 unsigned type = fieldFromInstruction(Insn, 8, 4); 2426 unsigned align = fieldFromInstruction(Insn, 4, 2); 2427 if(type == 8 && align == 3) return MCDisassembler::Fail; 2428 if(type == 9 && align == 3) return MCDisassembler::Fail; 2429 2430 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2431 } 2432 2433 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn, 2434 uint64_t Addr, const void* Decoder) { 2435 unsigned size = fieldFromInstruction(Insn, 6, 2); 2436 if(size == 3) return MCDisassembler::Fail; 2437 2438 unsigned align = fieldFromInstruction(Insn, 4, 2); 2439 if(align & 2) return MCDisassembler::Fail; 2440 2441 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2442 } 2443 2444 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn, 2445 uint64_t Addr, const void* Decoder) { 2446 unsigned size = fieldFromInstruction(Insn, 6, 2); 2447 if(size == 3) return MCDisassembler::Fail; 2448 2449 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder); 2450 } 2451 2452 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2453 uint64_t Address, const void *Decoder) { 2454 DecodeStatus S = MCDisassembler::Success; 2455 2456 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2457 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2458 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2459 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2460 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2461 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2462 2463 // Writeback Operand 2464 switch (Inst.getOpcode()) { 2465 case ARM::VST1d8wb_fixed: 2466 case ARM::VST1d16wb_fixed: 2467 case ARM::VST1d32wb_fixed: 2468 case ARM::VST1d64wb_fixed: 2469 case ARM::VST1d8wb_register: 2470 case ARM::VST1d16wb_register: 2471 case ARM::VST1d32wb_register: 2472 case ARM::VST1d64wb_register: 2473 case ARM::VST1q8wb_fixed: 2474 case ARM::VST1q16wb_fixed: 2475 case ARM::VST1q32wb_fixed: 2476 case ARM::VST1q64wb_fixed: 2477 case ARM::VST1q8wb_register: 2478 case ARM::VST1q16wb_register: 2479 case ARM::VST1q32wb_register: 2480 case ARM::VST1q64wb_register: 2481 case ARM::VST1d8Twb_fixed: 2482 case ARM::VST1d16Twb_fixed: 2483 case ARM::VST1d32Twb_fixed: 2484 case ARM::VST1d64Twb_fixed: 2485 case ARM::VST1d8Twb_register: 2486 case ARM::VST1d16Twb_register: 2487 case ARM::VST1d32Twb_register: 2488 case ARM::VST1d64Twb_register: 2489 case ARM::VST1d8Qwb_fixed: 2490 case ARM::VST1d16Qwb_fixed: 2491 case ARM::VST1d32Qwb_fixed: 2492 case ARM::VST1d64Qwb_fixed: 2493 case ARM::VST1d8Qwb_register: 2494 case ARM::VST1d16Qwb_register: 2495 case ARM::VST1d32Qwb_register: 2496 case ARM::VST1d64Qwb_register: 2497 case ARM::VST2d8wb_fixed: 2498 case ARM::VST2d16wb_fixed: 2499 case ARM::VST2d32wb_fixed: 2500 case ARM::VST2d8wb_register: 2501 case ARM::VST2d16wb_register: 2502 case ARM::VST2d32wb_register: 2503 case ARM::VST2q8wb_fixed: 2504 case ARM::VST2q16wb_fixed: 2505 case ARM::VST2q32wb_fixed: 2506 case ARM::VST2q8wb_register: 2507 case ARM::VST2q16wb_register: 2508 case ARM::VST2q32wb_register: 2509 case ARM::VST2b8wb_fixed: 2510 case ARM::VST2b16wb_fixed: 2511 case ARM::VST2b32wb_fixed: 2512 case ARM::VST2b8wb_register: 2513 case ARM::VST2b16wb_register: 2514 case ARM::VST2b32wb_register: 2515 if (Rm == 0xF) 2516 return MCDisassembler::Fail; 2517 Inst.addOperand(MCOperand::CreateImm(0)); 2518 break; 2519 case ARM::VST3d8_UPD: 2520 case ARM::VST3d16_UPD: 2521 case ARM::VST3d32_UPD: 2522 case ARM::VST3q8_UPD: 2523 case ARM::VST3q16_UPD: 2524 case ARM::VST3q32_UPD: 2525 case ARM::VST4d8_UPD: 2526 case ARM::VST4d16_UPD: 2527 case ARM::VST4d32_UPD: 2528 case ARM::VST4q8_UPD: 2529 case ARM::VST4q16_UPD: 2530 case ARM::VST4q32_UPD: 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 break; 2534 default: 2535 break; 2536 } 2537 2538 // AddrMode6 Base (register+alignment) 2539 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2540 return MCDisassembler::Fail; 2541 2542 // AddrMode6 Offset (register) 2543 switch (Inst.getOpcode()) { 2544 default: 2545 if (Rm == 0xD) 2546 Inst.addOperand(MCOperand::CreateReg(0)); 2547 else if (Rm != 0xF) { 2548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2549 return MCDisassembler::Fail; 2550 } 2551 break; 2552 case ARM::VST1d8wb_fixed: 2553 case ARM::VST1d16wb_fixed: 2554 case ARM::VST1d32wb_fixed: 2555 case ARM::VST1d64wb_fixed: 2556 case ARM::VST1q8wb_fixed: 2557 case ARM::VST1q16wb_fixed: 2558 case ARM::VST1q32wb_fixed: 2559 case ARM::VST1q64wb_fixed: 2560 case ARM::VST1d8Twb_fixed: 2561 case ARM::VST1d16Twb_fixed: 2562 case ARM::VST1d32Twb_fixed: 2563 case ARM::VST1d64Twb_fixed: 2564 case ARM::VST1d8Qwb_fixed: 2565 case ARM::VST1d16Qwb_fixed: 2566 case ARM::VST1d32Qwb_fixed: 2567 case ARM::VST1d64Qwb_fixed: 2568 case ARM::VST2d8wb_fixed: 2569 case ARM::VST2d16wb_fixed: 2570 case ARM::VST2d32wb_fixed: 2571 case ARM::VST2q8wb_fixed: 2572 case ARM::VST2q16wb_fixed: 2573 case ARM::VST2q32wb_fixed: 2574 case ARM::VST2b8wb_fixed: 2575 case ARM::VST2b16wb_fixed: 2576 case ARM::VST2b32wb_fixed: 2577 break; 2578 } 2579 2580 2581 // First input register 2582 switch (Inst.getOpcode()) { 2583 case ARM::VST1q16: 2584 case ARM::VST1q32: 2585 case ARM::VST1q64: 2586 case ARM::VST1q8: 2587 case ARM::VST1q16wb_fixed: 2588 case ARM::VST1q16wb_register: 2589 case ARM::VST1q32wb_fixed: 2590 case ARM::VST1q32wb_register: 2591 case ARM::VST1q64wb_fixed: 2592 case ARM::VST1q64wb_register: 2593 case ARM::VST1q8wb_fixed: 2594 case ARM::VST1q8wb_register: 2595 case ARM::VST2d16: 2596 case ARM::VST2d32: 2597 case ARM::VST2d8: 2598 case ARM::VST2d16wb_fixed: 2599 case ARM::VST2d16wb_register: 2600 case ARM::VST2d32wb_fixed: 2601 case ARM::VST2d32wb_register: 2602 case ARM::VST2d8wb_fixed: 2603 case ARM::VST2d8wb_register: 2604 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 break; 2607 case ARM::VST2b16: 2608 case ARM::VST2b32: 2609 case ARM::VST2b8: 2610 case ARM::VST2b16wb_fixed: 2611 case ARM::VST2b16wb_register: 2612 case ARM::VST2b32wb_fixed: 2613 case ARM::VST2b32wb_register: 2614 case ARM::VST2b8wb_fixed: 2615 case ARM::VST2b8wb_register: 2616 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2617 return MCDisassembler::Fail; 2618 break; 2619 default: 2620 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2621 return MCDisassembler::Fail; 2622 } 2623 2624 // Second input register 2625 switch (Inst.getOpcode()) { 2626 case ARM::VST3d8: 2627 case ARM::VST3d16: 2628 case ARM::VST3d32: 2629 case ARM::VST3d8_UPD: 2630 case ARM::VST3d16_UPD: 2631 case ARM::VST3d32_UPD: 2632 case ARM::VST4d8: 2633 case ARM::VST4d16: 2634 case ARM::VST4d32: 2635 case ARM::VST4d8_UPD: 2636 case ARM::VST4d16_UPD: 2637 case ARM::VST4d32_UPD: 2638 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2639 return MCDisassembler::Fail; 2640 break; 2641 case ARM::VST3q8: 2642 case ARM::VST3q16: 2643 case ARM::VST3q32: 2644 case ARM::VST3q8_UPD: 2645 case ARM::VST3q16_UPD: 2646 case ARM::VST3q32_UPD: 2647 case ARM::VST4q8: 2648 case ARM::VST4q16: 2649 case ARM::VST4q32: 2650 case ARM::VST4q8_UPD: 2651 case ARM::VST4q16_UPD: 2652 case ARM::VST4q32_UPD: 2653 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2654 return MCDisassembler::Fail; 2655 break; 2656 default: 2657 break; 2658 } 2659 2660 // Third input register 2661 switch (Inst.getOpcode()) { 2662 case ARM::VST3d8: 2663 case ARM::VST3d16: 2664 case ARM::VST3d32: 2665 case ARM::VST3d8_UPD: 2666 case ARM::VST3d16_UPD: 2667 case ARM::VST3d32_UPD: 2668 case ARM::VST4d8: 2669 case ARM::VST4d16: 2670 case ARM::VST4d32: 2671 case ARM::VST4d8_UPD: 2672 case ARM::VST4d16_UPD: 2673 case ARM::VST4d32_UPD: 2674 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2675 return MCDisassembler::Fail; 2676 break; 2677 case ARM::VST3q8: 2678 case ARM::VST3q16: 2679 case ARM::VST3q32: 2680 case ARM::VST3q8_UPD: 2681 case ARM::VST3q16_UPD: 2682 case ARM::VST3q32_UPD: 2683 case ARM::VST4q8: 2684 case ARM::VST4q16: 2685 case ARM::VST4q32: 2686 case ARM::VST4q8_UPD: 2687 case ARM::VST4q16_UPD: 2688 case ARM::VST4q32_UPD: 2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 break; 2692 default: 2693 break; 2694 } 2695 2696 // Fourth input register 2697 switch (Inst.getOpcode()) { 2698 case ARM::VST4d8: 2699 case ARM::VST4d16: 2700 case ARM::VST4d32: 2701 case ARM::VST4d8_UPD: 2702 case ARM::VST4d16_UPD: 2703 case ARM::VST4d32_UPD: 2704 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 break; 2707 case ARM::VST4q8: 2708 case ARM::VST4q16: 2709 case ARM::VST4q32: 2710 case ARM::VST4q8_UPD: 2711 case ARM::VST4q16_UPD: 2712 case ARM::VST4q32_UPD: 2713 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 break; 2716 default: 2717 break; 2718 } 2719 2720 return S; 2721 } 2722 2723 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2724 uint64_t Address, const void *Decoder) { 2725 DecodeStatus S = MCDisassembler::Success; 2726 2727 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2728 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2729 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2730 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2731 unsigned align = fieldFromInstruction(Insn, 4, 1); 2732 unsigned size = fieldFromInstruction(Insn, 6, 2); 2733 2734 if (size == 0 && align == 1) 2735 return MCDisassembler::Fail; 2736 align *= (1 << size); 2737 2738 switch (Inst.getOpcode()) { 2739 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2740 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2741 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2742 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2743 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 break; 2746 default: 2747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 break; 2750 } 2751 if (Rm != 0xF) { 2752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 } 2755 2756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 Inst.addOperand(MCOperand::CreateImm(align)); 2759 2760 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2761 // variant encodes Rm == 0xf. Anything else is a register offset post- 2762 // increment and we need to add the register operand to the instruction. 2763 if (Rm != 0xD && Rm != 0xF && 2764 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2765 return MCDisassembler::Fail; 2766 2767 return S; 2768 } 2769 2770 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 DecodeStatus S = MCDisassembler::Success; 2773 2774 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2775 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2776 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2777 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2778 unsigned align = fieldFromInstruction(Insn, 4, 1); 2779 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2780 align *= 2*size; 2781 2782 switch (Inst.getOpcode()) { 2783 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2784 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2785 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2786 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2787 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 break; 2790 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2791 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2792 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2793 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2794 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 break; 2797 default: 2798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 break; 2801 } 2802 2803 if (Rm != 0xF) 2804 Inst.addOperand(MCOperand::CreateImm(0)); 2805 2806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2807 return MCDisassembler::Fail; 2808 Inst.addOperand(MCOperand::CreateImm(align)); 2809 2810 if (Rm != 0xD && Rm != 0xF) { 2811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 } 2814 2815 return S; 2816 } 2817 2818 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2819 uint64_t Address, const void *Decoder) { 2820 DecodeStatus S = MCDisassembler::Success; 2821 2822 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2823 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2824 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2825 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2826 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2827 2828 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2829 return MCDisassembler::Fail; 2830 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2833 return MCDisassembler::Fail; 2834 if (Rm != 0xF) { 2835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 } 2838 2839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2840 return MCDisassembler::Fail; 2841 Inst.addOperand(MCOperand::CreateImm(0)); 2842 2843 if (Rm == 0xD) 2844 Inst.addOperand(MCOperand::CreateReg(0)); 2845 else if (Rm != 0xF) { 2846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 } 2849 2850 return S; 2851 } 2852 2853 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2854 uint64_t Address, const void *Decoder) { 2855 DecodeStatus S = MCDisassembler::Success; 2856 2857 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2858 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2859 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2860 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2861 unsigned size = fieldFromInstruction(Insn, 6, 2); 2862 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2863 unsigned align = fieldFromInstruction(Insn, 4, 1); 2864 2865 if (size == 0x3) { 2866 if (align == 0) 2867 return MCDisassembler::Fail; 2868 size = 4; 2869 align = 16; 2870 } else { 2871 if (size == 2) { 2872 size = 1 << size; 2873 align *= 8; 2874 } else { 2875 size = 1 << size; 2876 align *= 4*size; 2877 } 2878 } 2879 2880 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2883 return MCDisassembler::Fail; 2884 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2885 return MCDisassembler::Fail; 2886 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2887 return MCDisassembler::Fail; 2888 if (Rm != 0xF) { 2889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 } 2892 2893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 Inst.addOperand(MCOperand::CreateImm(align)); 2896 2897 if (Rm == 0xD) 2898 Inst.addOperand(MCOperand::CreateReg(0)); 2899 else if (Rm != 0xF) { 2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2901 return MCDisassembler::Fail; 2902 } 2903 2904 return S; 2905 } 2906 2907 static DecodeStatus 2908 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2909 uint64_t Address, const void *Decoder) { 2910 DecodeStatus S = MCDisassembler::Success; 2911 2912 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2913 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2914 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2915 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2916 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2917 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2918 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2919 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2920 2921 if (Q) { 2922 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2923 return MCDisassembler::Fail; 2924 } else { 2925 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 } 2928 2929 Inst.addOperand(MCOperand::CreateImm(imm)); 2930 2931 switch (Inst.getOpcode()) { 2932 case ARM::VORRiv4i16: 2933 case ARM::VORRiv2i32: 2934 case ARM::VBICiv4i16: 2935 case ARM::VBICiv2i32: 2936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 break; 2939 case ARM::VORRiv8i16: 2940 case ARM::VORRiv4i32: 2941 case ARM::VBICiv8i16: 2942 case ARM::VBICiv4i32: 2943 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 break; 2946 default: 2947 break; 2948 } 2949 2950 return S; 2951 } 2952 2953 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 DecodeStatus S = MCDisassembler::Success; 2956 2957 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2958 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2959 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2960 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2961 unsigned size = fieldFromInstruction(Insn, 18, 2); 2962 2963 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2964 return MCDisassembler::Fail; 2965 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2966 return MCDisassembler::Fail; 2967 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2968 2969 return S; 2970 } 2971 2972 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2973 uint64_t Address, const void *Decoder) { 2974 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2975 return MCDisassembler::Success; 2976 } 2977 2978 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2979 uint64_t Address, const void *Decoder) { 2980 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2981 return MCDisassembler::Success; 2982 } 2983 2984 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2985 uint64_t Address, const void *Decoder) { 2986 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2987 return MCDisassembler::Success; 2988 } 2989 2990 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2991 uint64_t Address, const void *Decoder) { 2992 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2993 return MCDisassembler::Success; 2994 } 2995 2996 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2997 uint64_t Address, const void *Decoder) { 2998 DecodeStatus S = MCDisassembler::Success; 2999 3000 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3001 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3002 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3003 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3004 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3005 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3006 unsigned op = fieldFromInstruction(Insn, 6, 1); 3007 3008 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3009 return MCDisassembler::Fail; 3010 if (op) { 3011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3012 return MCDisassembler::Fail; // Writeback 3013 } 3014 3015 switch (Inst.getOpcode()) { 3016 case ARM::VTBL2: 3017 case ARM::VTBX2: 3018 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3019 return MCDisassembler::Fail; 3020 break; 3021 default: 3022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 } 3025 3026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 3029 return S; 3030 } 3031 3032 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3033 uint64_t Address, const void *Decoder) { 3034 DecodeStatus S = MCDisassembler::Success; 3035 3036 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3037 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3038 3039 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 3042 switch(Inst.getOpcode()) { 3043 default: 3044 return MCDisassembler::Fail; 3045 case ARM::tADR: 3046 break; // tADR does not explicitly represent the PC as an operand. 3047 case ARM::tADDrSPi: 3048 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3049 break; 3050 } 3051 3052 Inst.addOperand(MCOperand::CreateImm(imm)); 3053 return S; 3054 } 3055 3056 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3057 uint64_t Address, const void *Decoder) { 3058 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3059 true, 2, Inst, Decoder)) 3060 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3061 return MCDisassembler::Success; 3062 } 3063 3064 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3065 uint64_t Address, const void *Decoder) { 3066 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3067 true, 4, Inst, Decoder)) 3068 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3069 return MCDisassembler::Success; 3070 } 3071 3072 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3073 uint64_t Address, const void *Decoder) { 3074 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3075 true, 2, Inst, Decoder)) 3076 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3077 return MCDisassembler::Success; 3078 } 3079 3080 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3081 uint64_t Address, const void *Decoder) { 3082 DecodeStatus S = MCDisassembler::Success; 3083 3084 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3085 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3086 3087 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 3092 return S; 3093 } 3094 3095 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3096 uint64_t Address, const void *Decoder) { 3097 DecodeStatus S = MCDisassembler::Success; 3098 3099 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3100 unsigned imm = fieldFromInstruction(Val, 3, 5); 3101 3102 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 Inst.addOperand(MCOperand::CreateImm(imm)); 3105 3106 return S; 3107 } 3108 3109 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3110 uint64_t Address, const void *Decoder) { 3111 unsigned imm = Val << 2; 3112 3113 Inst.addOperand(MCOperand::CreateImm(imm)); 3114 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3115 3116 return MCDisassembler::Success; 3117 } 3118 3119 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3120 uint64_t Address, const void *Decoder) { 3121 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3122 Inst.addOperand(MCOperand::CreateImm(Val)); 3123 3124 return MCDisassembler::Success; 3125 } 3126 3127 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3128 uint64_t Address, const void *Decoder) { 3129 DecodeStatus S = MCDisassembler::Success; 3130 3131 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3132 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3133 unsigned imm = fieldFromInstruction(Val, 0, 2); 3134 3135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3136 return MCDisassembler::Fail; 3137 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3138 return MCDisassembler::Fail; 3139 Inst.addOperand(MCOperand::CreateImm(imm)); 3140 3141 return S; 3142 } 3143 3144 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3145 uint64_t Address, const void *Decoder) { 3146 DecodeStatus S = MCDisassembler::Success; 3147 3148 switch (Inst.getOpcode()) { 3149 case ARM::t2PLDs: 3150 case ARM::t2PLDWs: 3151 case ARM::t2PLIs: 3152 break; 3153 default: { 3154 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3155 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3156 return MCDisassembler::Fail; 3157 } 3158 } 3159 3160 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3161 if (Rn == 0xF) { 3162 switch (Inst.getOpcode()) { 3163 case ARM::t2LDRBs: 3164 Inst.setOpcode(ARM::t2LDRBpci); 3165 break; 3166 case ARM::t2LDRHs: 3167 Inst.setOpcode(ARM::t2LDRHpci); 3168 break; 3169 case ARM::t2LDRSHs: 3170 Inst.setOpcode(ARM::t2LDRSHpci); 3171 break; 3172 case ARM::t2LDRSBs: 3173 Inst.setOpcode(ARM::t2LDRSBpci); 3174 break; 3175 case ARM::t2PLDs: 3176 Inst.setOpcode(ARM::t2PLDi12); 3177 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3178 break; 3179 default: 3180 return MCDisassembler::Fail; 3181 } 3182 3183 int imm = fieldFromInstruction(Insn, 0, 12); 3184 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3185 Inst.addOperand(MCOperand::CreateImm(imm)); 3186 3187 return S; 3188 } 3189 3190 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3191 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3192 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3193 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 3196 return S; 3197 } 3198 3199 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3200 uint64_t Address, const void *Decoder) { 3201 if (Val == 0) 3202 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3203 else { 3204 int imm = Val & 0xFF; 3205 3206 if (!(Val & 0x100)) imm *= -1; 3207 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3208 } 3209 3210 return MCDisassembler::Success; 3211 } 3212 3213 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3214 uint64_t Address, const void *Decoder) { 3215 DecodeStatus S = MCDisassembler::Success; 3216 3217 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3218 unsigned imm = fieldFromInstruction(Val, 0, 9); 3219 3220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3223 return MCDisassembler::Fail; 3224 3225 return S; 3226 } 3227 3228 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3229 uint64_t Address, const void *Decoder) { 3230 DecodeStatus S = MCDisassembler::Success; 3231 3232 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3233 unsigned imm = fieldFromInstruction(Val, 0, 8); 3234 3235 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 3238 Inst.addOperand(MCOperand::CreateImm(imm)); 3239 3240 return S; 3241 } 3242 3243 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3244 uint64_t Address, const void *Decoder) { 3245 int imm = Val & 0xFF; 3246 if (Val == 0) 3247 imm = INT32_MIN; 3248 else if (!(Val & 0x100)) 3249 imm *= -1; 3250 Inst.addOperand(MCOperand::CreateImm(imm)); 3251 3252 return MCDisassembler::Success; 3253 } 3254 3255 3256 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3257 uint64_t Address, const void *Decoder) { 3258 DecodeStatus S = MCDisassembler::Success; 3259 3260 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3261 unsigned imm = fieldFromInstruction(Val, 0, 9); 3262 3263 // Some instructions always use an additive offset. 3264 switch (Inst.getOpcode()) { 3265 case ARM::t2LDRT: 3266 case ARM::t2LDRBT: 3267 case ARM::t2LDRHT: 3268 case ARM::t2LDRSBT: 3269 case ARM::t2LDRSHT: 3270 case ARM::t2STRT: 3271 case ARM::t2STRBT: 3272 case ARM::t2STRHT: 3273 imm |= 0x100; 3274 break; 3275 default: 3276 break; 3277 } 3278 3279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 3284 return S; 3285 } 3286 3287 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3288 uint64_t Address, const void *Decoder) { 3289 DecodeStatus S = MCDisassembler::Success; 3290 3291 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3292 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3293 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3294 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3295 addr |= Rn << 9; 3296 unsigned load = fieldFromInstruction(Insn, 20, 1); 3297 3298 if (!load) { 3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 } 3302 3303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 3306 if (load) { 3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 } 3310 3311 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3312 return MCDisassembler::Fail; 3313 3314 return S; 3315 } 3316 3317 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3318 uint64_t Address, const void *Decoder) { 3319 DecodeStatus S = MCDisassembler::Success; 3320 3321 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3322 unsigned imm = fieldFromInstruction(Val, 0, 12); 3323 3324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3325 return MCDisassembler::Fail; 3326 Inst.addOperand(MCOperand::CreateImm(imm)); 3327 3328 return S; 3329 } 3330 3331 3332 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3333 uint64_t Address, const void *Decoder) { 3334 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3335 3336 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3337 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3338 Inst.addOperand(MCOperand::CreateImm(imm)); 3339 3340 return MCDisassembler::Success; 3341 } 3342 3343 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3344 uint64_t Address, const void *Decoder) { 3345 DecodeStatus S = MCDisassembler::Success; 3346 3347 if (Inst.getOpcode() == ARM::tADDrSP) { 3348 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3349 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3350 3351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 } else if (Inst.getOpcode() == ARM::tADDspr) { 3357 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3358 3359 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3360 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 } 3364 3365 return S; 3366 } 3367 3368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3369 uint64_t Address, const void *Decoder) { 3370 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3371 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3372 3373 Inst.addOperand(MCOperand::CreateImm(imod)); 3374 Inst.addOperand(MCOperand::CreateImm(flags)); 3375 3376 return MCDisassembler::Success; 3377 } 3378 3379 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3380 uint64_t Address, const void *Decoder) { 3381 DecodeStatus S = MCDisassembler::Success; 3382 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3383 unsigned add = fieldFromInstruction(Insn, 4, 1); 3384 3385 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3386 return MCDisassembler::Fail; 3387 Inst.addOperand(MCOperand::CreateImm(add)); 3388 3389 return S; 3390 } 3391 3392 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3393 uint64_t Address, const void *Decoder) { 3394 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3395 // Note only one trailing zero not two. Also the J1 and J2 values are from 3396 // the encoded instruction. So here change to I1 and I2 values via: 3397 // I1 = NOT(J1 EOR S); 3398 // I2 = NOT(J2 EOR S); 3399 // and build the imm32 with two trailing zeros as documented: 3400 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3401 unsigned S = (Val >> 23) & 1; 3402 unsigned J1 = (Val >> 22) & 1; 3403 unsigned J2 = (Val >> 21) & 1; 3404 unsigned I1 = !(J1 ^ S); 3405 unsigned I2 = !(J2 ^ S); 3406 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3407 int imm32 = SignExtend32<25>(tmp << 1); 3408 3409 if (!tryAddingSymbolicOperand(Address, 3410 (Address & ~2u) + imm32 + 4, 3411 true, 4, Inst, Decoder)) 3412 Inst.addOperand(MCOperand::CreateImm(imm32)); 3413 return MCDisassembler::Success; 3414 } 3415 3416 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3417 uint64_t Address, const void *Decoder) { 3418 if (Val == 0xA || Val == 0xB) 3419 return MCDisassembler::Fail; 3420 3421 Inst.addOperand(MCOperand::CreateImm(Val)); 3422 return MCDisassembler::Success; 3423 } 3424 3425 static DecodeStatus 3426 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3427 uint64_t Address, const void *Decoder) { 3428 DecodeStatus S = MCDisassembler::Success; 3429 3430 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3431 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3432 3433 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3434 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3435 return MCDisassembler::Fail; 3436 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3437 return MCDisassembler::Fail; 3438 return S; 3439 } 3440 3441 static DecodeStatus 3442 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3443 uint64_t Address, const void *Decoder) { 3444 DecodeStatus S = MCDisassembler::Success; 3445 3446 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3447 if (pred == 0xE || pred == 0xF) { 3448 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3449 switch (opc) { 3450 default: 3451 return MCDisassembler::Fail; 3452 case 0xf3bf8f4: 3453 Inst.setOpcode(ARM::t2DSB); 3454 break; 3455 case 0xf3bf8f5: 3456 Inst.setOpcode(ARM::t2DMB); 3457 break; 3458 case 0xf3bf8f6: 3459 Inst.setOpcode(ARM::t2ISB); 3460 break; 3461 } 3462 3463 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3464 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3465 } 3466 3467 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3468 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3469 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3470 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3471 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3472 3473 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3474 return MCDisassembler::Fail; 3475 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 3478 return S; 3479 } 3480 3481 // Decode a shifted immediate operand. These basically consist 3482 // of an 8-bit value, and a 4-bit directive that specifies either 3483 // a splat operation or a rotation. 3484 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3485 uint64_t Address, const void *Decoder) { 3486 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3487 if (ctrl == 0) { 3488 unsigned byte = fieldFromInstruction(Val, 8, 2); 3489 unsigned imm = fieldFromInstruction(Val, 0, 8); 3490 switch (byte) { 3491 case 0: 3492 Inst.addOperand(MCOperand::CreateImm(imm)); 3493 break; 3494 case 1: 3495 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3496 break; 3497 case 2: 3498 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3499 break; 3500 case 3: 3501 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3502 (imm << 8) | imm)); 3503 break; 3504 } 3505 } else { 3506 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3507 unsigned rot = fieldFromInstruction(Val, 7, 5); 3508 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3509 Inst.addOperand(MCOperand::CreateImm(imm)); 3510 } 3511 3512 return MCDisassembler::Success; 3513 } 3514 3515 static DecodeStatus 3516 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3517 uint64_t Address, const void *Decoder){ 3518 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3519 true, 2, Inst, Decoder)) 3520 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3521 return MCDisassembler::Success; 3522 } 3523 3524 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3525 uint64_t Address, const void *Decoder){ 3526 // Val is passed in as S:J1:J2:imm10:imm11 3527 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3528 // the encoded instruction. So here change to I1 and I2 values via: 3529 // I1 = NOT(J1 EOR S); 3530 // I2 = NOT(J2 EOR S); 3531 // and build the imm32 with one trailing zero as documented: 3532 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3533 unsigned S = (Val >> 23) & 1; 3534 unsigned J1 = (Val >> 22) & 1; 3535 unsigned J2 = (Val >> 21) & 1; 3536 unsigned I1 = !(J1 ^ S); 3537 unsigned I2 = !(J2 ^ S); 3538 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3539 int imm32 = SignExtend32<25>(tmp << 1); 3540 3541 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3542 true, 4, Inst, Decoder)) 3543 Inst.addOperand(MCOperand::CreateImm(imm32)); 3544 return MCDisassembler::Success; 3545 } 3546 3547 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3548 uint64_t Address, const void *Decoder) { 3549 if (Val & ~0xf) 3550 return MCDisassembler::Fail; 3551 3552 Inst.addOperand(MCOperand::CreateImm(Val)); 3553 return MCDisassembler::Success; 3554 } 3555 3556 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3557 uint64_t Address, const void *Decoder) { 3558 if (!Val) return MCDisassembler::Fail; 3559 Inst.addOperand(MCOperand::CreateImm(Val)); 3560 return MCDisassembler::Success; 3561 } 3562 3563 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3564 uint64_t Address, const void *Decoder) { 3565 DecodeStatus S = MCDisassembler::Success; 3566 3567 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3568 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3569 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3570 3571 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3572 3573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3580 return MCDisassembler::Fail; 3581 3582 return S; 3583 } 3584 3585 3586 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3587 uint64_t Address, const void *Decoder){ 3588 DecodeStatus S = MCDisassembler::Success; 3589 3590 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3591 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3592 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3593 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3594 3595 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 3598 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3599 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3600 3601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 3610 return S; 3611 } 3612 3613 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3614 uint64_t Address, const void *Decoder) { 3615 DecodeStatus S = MCDisassembler::Success; 3616 3617 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3618 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3619 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3620 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3621 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3622 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3623 3624 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3625 3626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3629 return MCDisassembler::Fail; 3630 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3633 return MCDisassembler::Fail; 3634 3635 return S; 3636 } 3637 3638 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3639 uint64_t Address, const void *Decoder) { 3640 DecodeStatus S = MCDisassembler::Success; 3641 3642 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3643 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3644 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3645 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3646 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3647 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3648 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3649 3650 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3651 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3652 3653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3654 return MCDisassembler::Fail; 3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3656 return MCDisassembler::Fail; 3657 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3658 return MCDisassembler::Fail; 3659 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 3662 return S; 3663 } 3664 3665 3666 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3667 uint64_t Address, const void *Decoder) { 3668 DecodeStatus S = MCDisassembler::Success; 3669 3670 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3671 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3672 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3673 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3674 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3675 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3676 3677 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3678 3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3682 return MCDisassembler::Fail; 3683 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3684 return MCDisassembler::Fail; 3685 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 3688 return S; 3689 } 3690 3691 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3692 uint64_t Address, const void *Decoder) { 3693 DecodeStatus S = MCDisassembler::Success; 3694 3695 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3696 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3697 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3698 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3699 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3700 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3701 3702 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3703 3704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3707 return MCDisassembler::Fail; 3708 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 3713 return S; 3714 } 3715 3716 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3717 uint64_t Address, const void *Decoder) { 3718 DecodeStatus S = MCDisassembler::Success; 3719 3720 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3721 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3722 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3723 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3724 unsigned size = fieldFromInstruction(Insn, 10, 2); 3725 3726 unsigned align = 0; 3727 unsigned index = 0; 3728 switch (size) { 3729 default: 3730 return MCDisassembler::Fail; 3731 case 0: 3732 if (fieldFromInstruction(Insn, 4, 1)) 3733 return MCDisassembler::Fail; // UNDEFINED 3734 index = fieldFromInstruction(Insn, 5, 3); 3735 break; 3736 case 1: 3737 if (fieldFromInstruction(Insn, 5, 1)) 3738 return MCDisassembler::Fail; // UNDEFINED 3739 index = fieldFromInstruction(Insn, 6, 2); 3740 if (fieldFromInstruction(Insn, 4, 1)) 3741 align = 2; 3742 break; 3743 case 2: 3744 if (fieldFromInstruction(Insn, 6, 1)) 3745 return MCDisassembler::Fail; // UNDEFINED 3746 index = fieldFromInstruction(Insn, 7, 1); 3747 3748 switch (fieldFromInstruction(Insn, 4, 2)) { 3749 case 0 : 3750 align = 0; break; 3751 case 3: 3752 align = 4; break; 3753 default: 3754 return MCDisassembler::Fail; 3755 } 3756 break; 3757 } 3758 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 if (Rm != 0xF) { // Writeback 3762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3763 return MCDisassembler::Fail; 3764 } 3765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3766 return MCDisassembler::Fail; 3767 Inst.addOperand(MCOperand::CreateImm(align)); 3768 if (Rm != 0xF) { 3769 if (Rm != 0xD) { 3770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 } else 3773 Inst.addOperand(MCOperand::CreateReg(0)); 3774 } 3775 3776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3777 return MCDisassembler::Fail; 3778 Inst.addOperand(MCOperand::CreateImm(index)); 3779 3780 return S; 3781 } 3782 3783 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3784 uint64_t Address, const void *Decoder) { 3785 DecodeStatus S = MCDisassembler::Success; 3786 3787 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3788 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3789 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3790 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3791 unsigned size = fieldFromInstruction(Insn, 10, 2); 3792 3793 unsigned align = 0; 3794 unsigned index = 0; 3795 switch (size) { 3796 default: 3797 return MCDisassembler::Fail; 3798 case 0: 3799 if (fieldFromInstruction(Insn, 4, 1)) 3800 return MCDisassembler::Fail; // UNDEFINED 3801 index = fieldFromInstruction(Insn, 5, 3); 3802 break; 3803 case 1: 3804 if (fieldFromInstruction(Insn, 5, 1)) 3805 return MCDisassembler::Fail; // UNDEFINED 3806 index = fieldFromInstruction(Insn, 6, 2); 3807 if (fieldFromInstruction(Insn, 4, 1)) 3808 align = 2; 3809 break; 3810 case 2: 3811 if (fieldFromInstruction(Insn, 6, 1)) 3812 return MCDisassembler::Fail; // UNDEFINED 3813 index = fieldFromInstruction(Insn, 7, 1); 3814 3815 switch (fieldFromInstruction(Insn, 4, 2)) { 3816 case 0: 3817 align = 0; break; 3818 case 3: 3819 align = 4; break; 3820 default: 3821 return MCDisassembler::Fail; 3822 } 3823 break; 3824 } 3825 3826 if (Rm != 0xF) { // Writeback 3827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3828 return MCDisassembler::Fail; 3829 } 3830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 Inst.addOperand(MCOperand::CreateImm(align)); 3833 if (Rm != 0xF) { 3834 if (Rm != 0xD) { 3835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 } else 3838 Inst.addOperand(MCOperand::CreateReg(0)); 3839 } 3840 3841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3842 return MCDisassembler::Fail; 3843 Inst.addOperand(MCOperand::CreateImm(index)); 3844 3845 return S; 3846 } 3847 3848 3849 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3850 uint64_t Address, const void *Decoder) { 3851 DecodeStatus S = MCDisassembler::Success; 3852 3853 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3854 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3855 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3856 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3857 unsigned size = fieldFromInstruction(Insn, 10, 2); 3858 3859 unsigned align = 0; 3860 unsigned index = 0; 3861 unsigned inc = 1; 3862 switch (size) { 3863 default: 3864 return MCDisassembler::Fail; 3865 case 0: 3866 index = fieldFromInstruction(Insn, 5, 3); 3867 if (fieldFromInstruction(Insn, 4, 1)) 3868 align = 2; 3869 break; 3870 case 1: 3871 index = fieldFromInstruction(Insn, 6, 2); 3872 if (fieldFromInstruction(Insn, 4, 1)) 3873 align = 4; 3874 if (fieldFromInstruction(Insn, 5, 1)) 3875 inc = 2; 3876 break; 3877 case 2: 3878 if (fieldFromInstruction(Insn, 5, 1)) 3879 return MCDisassembler::Fail; // UNDEFINED 3880 index = fieldFromInstruction(Insn, 7, 1); 3881 if (fieldFromInstruction(Insn, 4, 1) != 0) 3882 align = 8; 3883 if (fieldFromInstruction(Insn, 6, 1)) 3884 inc = 2; 3885 break; 3886 } 3887 3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 if (Rm != 0xF) { // Writeback 3893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3894 return MCDisassembler::Fail; 3895 } 3896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 Inst.addOperand(MCOperand::CreateImm(align)); 3899 if (Rm != 0xF) { 3900 if (Rm != 0xD) { 3901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 } else 3904 Inst.addOperand(MCOperand::CreateReg(0)); 3905 } 3906 3907 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3908 return MCDisassembler::Fail; 3909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3910 return MCDisassembler::Fail; 3911 Inst.addOperand(MCOperand::CreateImm(index)); 3912 3913 return S; 3914 } 3915 3916 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3917 uint64_t Address, const void *Decoder) { 3918 DecodeStatus S = MCDisassembler::Success; 3919 3920 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3921 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3922 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3923 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3924 unsigned size = fieldFromInstruction(Insn, 10, 2); 3925 3926 unsigned align = 0; 3927 unsigned index = 0; 3928 unsigned inc = 1; 3929 switch (size) { 3930 default: 3931 return MCDisassembler::Fail; 3932 case 0: 3933 index = fieldFromInstruction(Insn, 5, 3); 3934 if (fieldFromInstruction(Insn, 4, 1)) 3935 align = 2; 3936 break; 3937 case 1: 3938 index = fieldFromInstruction(Insn, 6, 2); 3939 if (fieldFromInstruction(Insn, 4, 1)) 3940 align = 4; 3941 if (fieldFromInstruction(Insn, 5, 1)) 3942 inc = 2; 3943 break; 3944 case 2: 3945 if (fieldFromInstruction(Insn, 5, 1)) 3946 return MCDisassembler::Fail; // UNDEFINED 3947 index = fieldFromInstruction(Insn, 7, 1); 3948 if (fieldFromInstruction(Insn, 4, 1) != 0) 3949 align = 8; 3950 if (fieldFromInstruction(Insn, 6, 1)) 3951 inc = 2; 3952 break; 3953 } 3954 3955 if (Rm != 0xF) { // Writeback 3956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3957 return MCDisassembler::Fail; 3958 } 3959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 Inst.addOperand(MCOperand::CreateImm(align)); 3962 if (Rm != 0xF) { 3963 if (Rm != 0xD) { 3964 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3965 return MCDisassembler::Fail; 3966 } else 3967 Inst.addOperand(MCOperand::CreateReg(0)); 3968 } 3969 3970 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3971 return MCDisassembler::Fail; 3972 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3973 return MCDisassembler::Fail; 3974 Inst.addOperand(MCOperand::CreateImm(index)); 3975 3976 return S; 3977 } 3978 3979 3980 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3981 uint64_t Address, const void *Decoder) { 3982 DecodeStatus S = MCDisassembler::Success; 3983 3984 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3985 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3986 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3987 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3988 unsigned size = fieldFromInstruction(Insn, 10, 2); 3989 3990 unsigned align = 0; 3991 unsigned index = 0; 3992 unsigned inc = 1; 3993 switch (size) { 3994 default: 3995 return MCDisassembler::Fail; 3996 case 0: 3997 if (fieldFromInstruction(Insn, 4, 1)) 3998 return MCDisassembler::Fail; // UNDEFINED 3999 index = fieldFromInstruction(Insn, 5, 3); 4000 break; 4001 case 1: 4002 if (fieldFromInstruction(Insn, 4, 1)) 4003 return MCDisassembler::Fail; // UNDEFINED 4004 index = fieldFromInstruction(Insn, 6, 2); 4005 if (fieldFromInstruction(Insn, 5, 1)) 4006 inc = 2; 4007 break; 4008 case 2: 4009 if (fieldFromInstruction(Insn, 4, 2)) 4010 return MCDisassembler::Fail; // UNDEFINED 4011 index = fieldFromInstruction(Insn, 7, 1); 4012 if (fieldFromInstruction(Insn, 6, 1)) 4013 inc = 2; 4014 break; 4015 } 4016 4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 4024 if (Rm != 0xF) { // Writeback 4025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 } 4028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 Inst.addOperand(MCOperand::CreateImm(align)); 4031 if (Rm != 0xF) { 4032 if (Rm != 0xD) { 4033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 } else 4036 Inst.addOperand(MCOperand::CreateReg(0)); 4037 } 4038 4039 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4040 return MCDisassembler::Fail; 4041 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4042 return MCDisassembler::Fail; 4043 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4044 return MCDisassembler::Fail; 4045 Inst.addOperand(MCOperand::CreateImm(index)); 4046 4047 return S; 4048 } 4049 4050 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4051 uint64_t Address, const void *Decoder) { 4052 DecodeStatus S = MCDisassembler::Success; 4053 4054 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4055 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4056 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4057 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4058 unsigned size = fieldFromInstruction(Insn, 10, 2); 4059 4060 unsigned align = 0; 4061 unsigned index = 0; 4062 unsigned inc = 1; 4063 switch (size) { 4064 default: 4065 return MCDisassembler::Fail; 4066 case 0: 4067 if (fieldFromInstruction(Insn, 4, 1)) 4068 return MCDisassembler::Fail; // UNDEFINED 4069 index = fieldFromInstruction(Insn, 5, 3); 4070 break; 4071 case 1: 4072 if (fieldFromInstruction(Insn, 4, 1)) 4073 return MCDisassembler::Fail; // UNDEFINED 4074 index = fieldFromInstruction(Insn, 6, 2); 4075 if (fieldFromInstruction(Insn, 5, 1)) 4076 inc = 2; 4077 break; 4078 case 2: 4079 if (fieldFromInstruction(Insn, 4, 2)) 4080 return MCDisassembler::Fail; // UNDEFINED 4081 index = fieldFromInstruction(Insn, 7, 1); 4082 if (fieldFromInstruction(Insn, 6, 1)) 4083 inc = 2; 4084 break; 4085 } 4086 4087 if (Rm != 0xF) { // Writeback 4088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4089 return MCDisassembler::Fail; 4090 } 4091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4092 return MCDisassembler::Fail; 4093 Inst.addOperand(MCOperand::CreateImm(align)); 4094 if (Rm != 0xF) { 4095 if (Rm != 0xD) { 4096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4097 return MCDisassembler::Fail; 4098 } else 4099 Inst.addOperand(MCOperand::CreateReg(0)); 4100 } 4101 4102 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4103 return MCDisassembler::Fail; 4104 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4105 return MCDisassembler::Fail; 4106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4107 return MCDisassembler::Fail; 4108 Inst.addOperand(MCOperand::CreateImm(index)); 4109 4110 return S; 4111 } 4112 4113 4114 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4115 uint64_t Address, const void *Decoder) { 4116 DecodeStatus S = MCDisassembler::Success; 4117 4118 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4119 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4120 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4121 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4122 unsigned size = fieldFromInstruction(Insn, 10, 2); 4123 4124 unsigned align = 0; 4125 unsigned index = 0; 4126 unsigned inc = 1; 4127 switch (size) { 4128 default: 4129 return MCDisassembler::Fail; 4130 case 0: 4131 if (fieldFromInstruction(Insn, 4, 1)) 4132 align = 4; 4133 index = fieldFromInstruction(Insn, 5, 3); 4134 break; 4135 case 1: 4136 if (fieldFromInstruction(Insn, 4, 1)) 4137 align = 8; 4138 index = fieldFromInstruction(Insn, 6, 2); 4139 if (fieldFromInstruction(Insn, 5, 1)) 4140 inc = 2; 4141 break; 4142 case 2: 4143 switch (fieldFromInstruction(Insn, 4, 2)) { 4144 case 0: 4145 align = 0; break; 4146 case 3: 4147 return MCDisassembler::Fail; 4148 default: 4149 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4150 } 4151 4152 index = fieldFromInstruction(Insn, 7, 1); 4153 if (fieldFromInstruction(Insn, 6, 1)) 4154 inc = 2; 4155 break; 4156 } 4157 4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4161 return MCDisassembler::Fail; 4162 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4163 return MCDisassembler::Fail; 4164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4165 return MCDisassembler::Fail; 4166 4167 if (Rm != 0xF) { // Writeback 4168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4169 return MCDisassembler::Fail; 4170 } 4171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4172 return MCDisassembler::Fail; 4173 Inst.addOperand(MCOperand::CreateImm(align)); 4174 if (Rm != 0xF) { 4175 if (Rm != 0xD) { 4176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4177 return MCDisassembler::Fail; 4178 } else 4179 Inst.addOperand(MCOperand::CreateReg(0)); 4180 } 4181 4182 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4189 return MCDisassembler::Fail; 4190 Inst.addOperand(MCOperand::CreateImm(index)); 4191 4192 return S; 4193 } 4194 4195 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4196 uint64_t Address, const void *Decoder) { 4197 DecodeStatus S = MCDisassembler::Success; 4198 4199 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4200 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4201 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4202 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4203 unsigned size = fieldFromInstruction(Insn, 10, 2); 4204 4205 unsigned align = 0; 4206 unsigned index = 0; 4207 unsigned inc = 1; 4208 switch (size) { 4209 default: 4210 return MCDisassembler::Fail; 4211 case 0: 4212 if (fieldFromInstruction(Insn, 4, 1)) 4213 align = 4; 4214 index = fieldFromInstruction(Insn, 5, 3); 4215 break; 4216 case 1: 4217 if (fieldFromInstruction(Insn, 4, 1)) 4218 align = 8; 4219 index = fieldFromInstruction(Insn, 6, 2); 4220 if (fieldFromInstruction(Insn, 5, 1)) 4221 inc = 2; 4222 break; 4223 case 2: 4224 switch (fieldFromInstruction(Insn, 4, 2)) { 4225 case 0: 4226 align = 0; break; 4227 case 3: 4228 return MCDisassembler::Fail; 4229 default: 4230 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4231 } 4232 4233 index = fieldFromInstruction(Insn, 7, 1); 4234 if (fieldFromInstruction(Insn, 6, 1)) 4235 inc = 2; 4236 break; 4237 } 4238 4239 if (Rm != 0xF) { // Writeback 4240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 } 4243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 Inst.addOperand(MCOperand::CreateImm(align)); 4246 if (Rm != 0xF) { 4247 if (Rm != 0xD) { 4248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 } else 4251 Inst.addOperand(MCOperand::CreateReg(0)); 4252 } 4253 4254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4255 return MCDisassembler::Fail; 4256 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4257 return MCDisassembler::Fail; 4258 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4259 return MCDisassembler::Fail; 4260 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4261 return MCDisassembler::Fail; 4262 Inst.addOperand(MCOperand::CreateImm(index)); 4263 4264 return S; 4265 } 4266 4267 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4268 uint64_t Address, const void *Decoder) { 4269 DecodeStatus S = MCDisassembler::Success; 4270 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4271 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4272 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4273 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4274 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4275 4276 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4277 S = MCDisassembler::SoftFail; 4278 4279 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4280 return MCDisassembler::Fail; 4281 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4282 return MCDisassembler::Fail; 4283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4284 return MCDisassembler::Fail; 4285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4286 return MCDisassembler::Fail; 4287 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4288 return MCDisassembler::Fail; 4289 4290 return S; 4291 } 4292 4293 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4294 uint64_t Address, const void *Decoder) { 4295 DecodeStatus S = MCDisassembler::Success; 4296 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4297 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4298 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4299 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4300 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4301 4302 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4303 S = MCDisassembler::SoftFail; 4304 4305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4310 return MCDisassembler::Fail; 4311 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4312 return MCDisassembler::Fail; 4313 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 4316 return S; 4317 } 4318 4319 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4320 uint64_t Address, const void *Decoder) { 4321 DecodeStatus S = MCDisassembler::Success; 4322 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4323 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4324 4325 if (pred == 0xF) { 4326 pred = 0xE; 4327 S = MCDisassembler::SoftFail; 4328 } 4329 4330 if (mask == 0x0) { 4331 mask |= 0x8; 4332 S = MCDisassembler::SoftFail; 4333 } 4334 4335 Inst.addOperand(MCOperand::CreateImm(pred)); 4336 Inst.addOperand(MCOperand::CreateImm(mask)); 4337 return S; 4338 } 4339 4340 static DecodeStatus 4341 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4342 uint64_t Address, const void *Decoder) { 4343 DecodeStatus S = MCDisassembler::Success; 4344 4345 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4346 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4347 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4348 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4349 unsigned W = fieldFromInstruction(Insn, 21, 1); 4350 unsigned U = fieldFromInstruction(Insn, 23, 1); 4351 unsigned P = fieldFromInstruction(Insn, 24, 1); 4352 bool writeback = (W == 1) | (P == 0); 4353 4354 addr |= (U << 8) | (Rn << 9); 4355 4356 if (writeback && (Rn == Rt || Rn == Rt2)) 4357 Check(S, MCDisassembler::SoftFail); 4358 if (Rt == Rt2) 4359 Check(S, MCDisassembler::SoftFail); 4360 4361 // Rt 4362 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 // Rt2 4365 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 // Writeback operand 4368 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 // addr 4371 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 4374 return S; 4375 } 4376 4377 static DecodeStatus 4378 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4379 uint64_t Address, const void *Decoder) { 4380 DecodeStatus S = MCDisassembler::Success; 4381 4382 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4383 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4384 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4385 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4386 unsigned W = fieldFromInstruction(Insn, 21, 1); 4387 unsigned U = fieldFromInstruction(Insn, 23, 1); 4388 unsigned P = fieldFromInstruction(Insn, 24, 1); 4389 bool writeback = (W == 1) | (P == 0); 4390 4391 addr |= (U << 8) | (Rn << 9); 4392 4393 if (writeback && (Rn == Rt || Rn == Rt2)) 4394 Check(S, MCDisassembler::SoftFail); 4395 4396 // Writeback operand 4397 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4398 return MCDisassembler::Fail; 4399 // Rt 4400 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 // Rt2 4403 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4404 return MCDisassembler::Fail; 4405 // addr 4406 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4407 return MCDisassembler::Fail; 4408 4409 return S; 4410 } 4411 4412 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4413 uint64_t Address, const void *Decoder) { 4414 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4415 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4416 if (sign1 != sign2) return MCDisassembler::Fail; 4417 4418 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4419 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4420 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4421 Val |= sign1 << 12; 4422 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4423 4424 return MCDisassembler::Success; 4425 } 4426 4427 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4428 uint64_t Address, 4429 const void *Decoder) { 4430 DecodeStatus S = MCDisassembler::Success; 4431 4432 // Shift of "asr #32" is not allowed in Thumb2 mode. 4433 if (Val == 0x20) S = MCDisassembler::SoftFail; 4434 Inst.addOperand(MCOperand::CreateImm(Val)); 4435 return S; 4436 } 4437 4438 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4439 uint64_t Address, const void *Decoder) { 4440 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4441 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4443 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4444 4445 if (pred == 0xF) 4446 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4447 4448 DecodeStatus S = MCDisassembler::Success; 4449 4450 if (Rt == Rn || Rn == Rt2) 4451 S = MCDisassembler::SoftFail; 4452 4453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4454 return MCDisassembler::Fail; 4455 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4456 return MCDisassembler::Fail; 4457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4458 return MCDisassembler::Fail; 4459 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4460 return MCDisassembler::Fail; 4461 4462 return S; 4463 } 4464 4465 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4466 uint64_t Address, const void *Decoder) { 4467 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4468 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4469 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4470 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4471 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4472 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4473 unsigned op = fieldFromInstruction(Insn, 5, 1); 4474 4475 DecodeStatus S = MCDisassembler::Success; 4476 4477 // VMOVv2f32 is ambiguous with these decodings. 4478 if (!(imm & 0x38) && cmode == 0xF) { 4479 if (op == 1) return MCDisassembler::Fail; 4480 Inst.setOpcode(ARM::VMOVv2f32); 4481 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4482 } 4483 4484 if (!(imm & 0x20)) return MCDisassembler::Fail; 4485 4486 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4487 return MCDisassembler::Fail; 4488 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4489 return MCDisassembler::Fail; 4490 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4491 4492 return S; 4493 } 4494 4495 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4496 uint64_t Address, const void *Decoder) { 4497 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4498 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4499 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4500 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4501 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4502 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4503 unsigned op = fieldFromInstruction(Insn, 5, 1); 4504 4505 DecodeStatus S = MCDisassembler::Success; 4506 4507 // VMOVv4f32 is ambiguous with these decodings. 4508 if (!(imm & 0x38) && cmode == 0xF) { 4509 if (op == 1) return MCDisassembler::Fail; 4510 Inst.setOpcode(ARM::VMOVv4f32); 4511 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4512 } 4513 4514 if (!(imm & 0x20)) return MCDisassembler::Fail; 4515 4516 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4517 return MCDisassembler::Fail; 4518 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4519 return MCDisassembler::Fail; 4520 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4521 4522 return S; 4523 } 4524 4525 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4526 const void *Decoder) 4527 { 4528 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4529 if (Imm > 4) return MCDisassembler::Fail; 4530 Inst.addOperand(MCOperand::CreateImm(Imm)); 4531 return MCDisassembler::Success; 4532 } 4533 4534 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4535 uint64_t Address, const void *Decoder) { 4536 DecodeStatus S = MCDisassembler::Success; 4537 4538 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4539 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4540 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4541 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4542 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4543 4544 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4545 S = MCDisassembler::SoftFail; 4546 4547 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4550 return MCDisassembler::Fail; 4551 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4552 return MCDisassembler::Fail; 4553 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4554 return MCDisassembler::Fail; 4555 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4556 return MCDisassembler::Fail; 4557 4558 return S; 4559 } 4560 4561 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4562 uint64_t Address, const void *Decoder) { 4563 4564 DecodeStatus S = MCDisassembler::Success; 4565 4566 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4567 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4568 unsigned cop = fieldFromInstruction(Val, 8, 4); 4569 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4570 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4571 4572 if ((cop & ~0x1) == 0xa) 4573 return MCDisassembler::Fail; 4574 4575 if (Rt == Rt2) 4576 S = MCDisassembler::SoftFail; 4577 4578 Inst.addOperand(MCOperand::CreateImm(cop)); 4579 Inst.addOperand(MCOperand::CreateImm(opc1)); 4580 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4581 return MCDisassembler::Fail; 4582 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 Inst.addOperand(MCOperand::CreateImm(CRm)); 4585 4586 return S; 4587 } 4588 4589