[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)

In accordance with https://github.com/llvm/llvm-project/issues/123569

In order to keep the patch at reasonable size, this

[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)

In accordance with https://github.com/llvm/llvm-project/issues/123569

In order to keep the patch at reasonable size, this PR only covers for
the llvm subproject, unittests excluded.

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[TargetLowering] Return Align from getByValTypeAlignment (NFC) (#119233)

[GlobalISel] Remove unused includes (NFC) (#115429)

Identified with misc-include-cleaner.

[llvm] Replace uses of Type::getPointerTo() (NFC) (#110163)

Replace uses of `Type::getPointerTo()` which is to be removed.

---------

Co-authored-by: Nikita Popov <github@npopov.com>

[CodeGen] Construct SmallVector with ArrayRef (NFC) (#101841)

[AArch64][PAC] Lower direct authenticated calls to ptrauth constants. (#97664)

This tries to turn indirect ptrauth calls into direct calls, using
`ConstantPtrAuth::isKnownEquivalent` to compare the

[AArch64][PAC] Lower direct authenticated calls to ptrauth constants. (#97664)

This tries to turn indirect ptrauth calls into direct calls, using
`ConstantPtrAuth::isKnownEquivalent` to compare the `ConstantPtrAuth`
target with the ptrauth call bundle.

This should be straightforward, other than the somewhat awkward GISel
handling, which has a handshake between CallLowering and IRTranslator to
elide the ptrauth when possible.

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[GlobalISel] Fix formatting in CallLowering.cpp. NFC

[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)

Similar to https://github.com/llvm/llvm-project/pull/96902, this adds
`getDataLayout()` helpers to Function and GlobalValue, re

[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)

Similar to https://github.com/llvm/llvm-project/pull/96902, this adds
`getDataLayout()` helpers to Function and GlobalValue, replacing the
current `getParent()->getDataLayout()` pattern.

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[GlobalISel] Add support for lowering byref attribute



Reviewers: nikic, spaits, arsenm

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/96733

[GISel][RISCV]Implement indirect parameter passing (#95429)

Some targets like RISC-V pass scalars wider than 2×XLEN bits by
reference, so those arguments are replaced in the argument list with an

[GISel][RISCV]Implement indirect parameter passing (#95429)

Some targets like RISC-V pass scalars wider than 2×XLEN bits by
reference, so those arguments are replaced in the argument list with an
address (See RISC-V ABIs Specification 1.0 section 2.1).

This commit implements this indirect parameter passing in GlobalISel.

---------

Co-authored-by: Gabor Spaits <Gabor.Spaits@hightec-rt.com>

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[GlobalISel] Allow more illegal vector types in params/returns. (#95514)

This helps some of the testing of illegal types, allowing us to pass
them into and out of functions.

The AMD tests no lon

[GlobalISel] Allow more illegal vector types in params/returns. (#95514)

This helps some of the testing of illegal types, allowing us to pass
them into and out of functions.

The AMD tests no longer fail, but I am unsure whether they are correct.
They fail later on in the pipeline for GISel, and during lowering ret
for SDAG.

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[AArch64][PAC] Lower authenticated calls with ptrauth bundles. (#85736)

This adds codegen support for the "ptrauth" operand bundles, which can
be used to augment indirect calls with the equivalent

[AArch64][PAC] Lower authenticated calls with ptrauth bundles. (#85736)

This adds codegen support for the "ptrauth" operand bundles, which can
be used to augment indirect calls with the equivalent of an
`@llvm.ptrauth.auth` intrinsic call on the call target (possibly
preceded by an `@llvm.ptrauth.blend` on the auth discriminator if
applicable.)

This allows the generation of combined authenticating calls
on AArch64 (in the BLRA* PAuth instructions), while avoiding
the raw just-authenticated function pointer from being
exposed to attackers.

This is done by threading a PtrAuthInfo descriptor through
the call lowering infrastructure, eventually selecting a BLRA
pseudo. The pseudo encapsulates the safe discriminator
computation, which together with the real BLRA* call get emitted
in late pseudo expansion in AsmPrinter.

Note that this also applies to the other forms of indirect calls,
notably invokes, rvmarker, and tail calls. Tail-calls in particular
bring some additional complexity, with the intersecting register
constraints of BTI and PAC discriminator computation.
However this doesn't currently support PAuth_LR tail-call variants.

This also adopts an x8+ allocation order for GPR64noip, matching
GPR64.

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[GlobalISel] convergence control tokens and intrinsics (#67006)

[GlobalISel] Implement convergence control tokens and intrinsics in GMIR

In the IR translator, convert the LLVM token type to LLT::

[GlobalISel] convergence control tokens and intrinsics (#67006)

[GlobalISel] Implement convergence control tokens and intrinsics in GMIR

In the IR translator, convert the LLVM token type to LLT::token(), which is an
alias for the s0 type. These show up as implicit uses on convergent operations.

Differential Revision: https://reviews.llvm.org/D158147

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[AArch64] Implement -fno-plt for SelectionDAG/GlobalISel

Clang sets the nonlazybind attribute for certain ObjC features. The
AArch64 SelectionDAG implementation for non-intrinsic calls
(46e36f0953aa

[AArch64] Implement -fno-plt for SelectionDAG/GlobalISel

Clang sets the nonlazybind attribute for certain ObjC features. The
AArch64 SelectionDAG implementation for non-intrinsic calls
(46e36f0953aabb5e5cd00ed8d296d60f9f71b424) is behind a cl option.

GCC implements -fno-plt for a few ELF targets. In Clang, -fno-plt also
sets the nonlazybind attribute. For SelectionDAG, make the cl option not
affect ELF so that non-intrinsic calls to a dso_preemptable function use
GOT. Adjust AArch64TargetLowering::LowerCall to handle intrinsic calls.

For FastISel, change `fastLowerCall` to bail out when a call is due to
-fno-plt.

For GlobalISel, handle non-intrinsic calls in CallLowering::lowerCall
and intrinsic calls in AArch64CallLowering::lowerCall (where the
target-independent CallLowering::lowerCall is not called).
The GlobalISel test in `call-rv-marker.ll` is therefore updated.

Note: the current -fno-plt -fpic implementation does not use GOT for a
preemptable function.

Link: #78275

Pull Request: https://github.com/llvm/llvm-project/pull/78890

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[GlobalISel] Fix a check that aligned tail call is lowered (#82016)

Despite of a valid tail call opportunity, backends still may not
generate a tail call or such lowering is not implemented yet.

[GlobalISel] Fix a check that aligned tail call is lowered (#82016)

Despite of a valid tail call opportunity, backends still may not
generate a tail call or such lowering is not implemented yet.

Check that lowering has happened instead of its possibility when
generating G_ASSERT_ALIGN.

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[GISEL] More accounting for scalable vectors when operating on LLTs (#80372)

This is stacked on by #80377 and #80378

[GlobalISel] Fix buildCopyFromRegs for split vectors (#77448)

Fixes #77055

[GlobalISel] Revise 'assignCustomValue' interface (#77824)

- Previously, 'assignCustomValue' requests the number of assigned VAs
minus 1 is returned and treats 0 as the assignment failure. However,

[GlobalISel] Revise 'assignCustomValue' interface (#77824)

- Previously, 'assignCustomValue' requests the number of assigned VAs
minus 1 is returned and treats 0 as the assignment failure. However,
under that arrangment, we cannot tell a successful *single* VA custom
assignment from the failure case.
- This change requests that 'assignCustomValue' just return the number
of all VAs assigned, including the first WA so that it won't be ambigous
to tell the failure case from the single VA custom assignment.

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[GlobalISel] Always direct-call IFuncs and Aliases (#74902)

This is safe because for both cases, the use must be in the same TU as the definition, and they cannot be forward declared.

[RISCV][GISEL] Add support for lowerFormalArguments that contain scalable vector types (#70882)

Scalable vector types from LLVM IR can be lowered to scalable vector
types in MIR according to the RI

[RISCV][GISEL] Add support for lowerFormalArguments that contain scalable vector types (#70882)

Scalable vector types from LLVM IR can be lowered to scalable vector
types in MIR according to the RISCVAssignFn.

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[GISel] Make assignValueToReg take CCValAssign by const reference. (#70086)

This was previously passed by value. It used to be passed by non-const
reference, but it was changed to value in D110610.

[GISel] Make assignValueToReg take CCValAssign by const reference. (#70086)

This was previously passed by value. It used to be passed by non-const
reference, but it was changed to value in D110610. I'm not sure why.

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[GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC (#69810)

Previously they were passed by non-const reference. No in tree target
modifies the values.

This makes it possible

[GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC (#69810)

Previously they were passed by non-const reference. No in tree target
modifies the values.

This makes it possible to call assignValueToAddress from
assignCustomValue without a const_cast. For example in this patch
https://github.com/llvm/llvm-project/pull/69138.

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[NFC] Replace uses of Type::getPointerTo

Replace some uses of `Type::getPointerTo` via 2 ways
* Remove entirely if it's only used to support an unnecessary bitcast
(remove the bitcast as well).
*

[NFC] Replace uses of Type::getPointerTo

Replace some uses of `Type::getPointerTo` via 2 ways
* Remove entirely if it's only used to support an unnecessary bitcast
(remove the bitcast as well).
* Replace with `PointerType::get`/`PointerType::getUnqual`

NFC opaque pointer clean-up effort.

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[GlobalISel] introduce MIFlag::NoConvergent

Some opcodes in MIR are defined to be convergent by the target by setting
IsConvergent in the corresponding TD file. For example, in AMDGPU, the opcodes
G

[GlobalISel] introduce MIFlag::NoConvergent

Some opcodes in MIR are defined to be convergent by the target by setting
IsConvergent in the corresponding TD file. For example, in AMDGPU, the opcodes
G_SI_CALL and G_INTRINSIC* are marked as convergent. But this is too
conservative, since calls to functions that do not execute convergent operations
should not be marked convergent. This information is available in LLVM IR.

The new flag MIFlag::NoConvergent now allows the IR translator to mark an
instruction as not performing any convergent operations. It is relevant only on
occurrences of opcodes that are marked isConvergent in the target.

Differential Revision: https://reviews.llvm.org/D157475

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[GlobalISel] Handle ptr size != index size in IRTranslator, CodeGenPrepare

While the original motivation for this patch (address space 7 on
AMDGPU) has been reworked and is not presently planned to

[GlobalISel] Handle ptr size != index size in IRTranslator, CodeGenPrepare

While the original motivation for this patch (address space 7 on
AMDGPU) has been reworked and is not presently planned to reach IR
translation, the incorrect (by the spec) handling of index offset
width in IR translation and CodeGenPrepare is likely to trip someone
- possibly future AMD, since we have a p7:160:256:256:32 now, so we
convert to the other API now.

Reviewed By: aemerson, arsenm

Differential Revision: https://reviews.llvm.org/D143526

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