Name Date Size #Lines LOC

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osdep_raw/H16-Jul-2024-7756

osdep_rte/H29-Jan-2025-7049

READMEH A D16-Jul-20241.4 KiB4734

ifpga_api.cH A D16-Jul-202411.1 KiB476356

ifpga_api.hH A D16-Jul-2024894 3018

ifpga_compat.hH A D16-Jul-20241.6 KiB5436

ifpga_defines.hH A D16-Jul-202441.4 KiB1,7651,306

ifpga_enumerate.cH A D16-Jul-202425.8 KiB1,139879

ifpga_enumerate.hH A D16-Jul-2024345 157

ifpga_feature_dev.cH A D16-Jul-202410.1 KiB414295

ifpga_feature_dev.hH A D16-Jul-20246.3 KiB229174

ifpga_fme.cH A D16-Jul-202439.1 KiB1,6691,291

ifpga_fme_dperf.cH A D16-Jul-20247.2 KiB302227

ifpga_fme_error.cH A D16-Jul-20249.9 KiB414319

ifpga_fme_iperf.cH A D16-Jul-202420.1 KiB716577

ifpga_fme_pr.cH A D16-Jul-20248.5 KiB358266

ifpga_fme_rsu.cH A D16-Jul-20249.7 KiB447381

ifpga_hw.hH A D16-Jul-20243.2 KiB155118

ifpga_port.cH A D16-Jul-20249.7 KiB430314

ifpga_port_error.cH A D16-Jul-20243.8 KiB164122

ifpga_sec_mgr.cH A D16-Jul-202413.9 KiB640547

ifpga_sec_mgr.hH A D16-Jul-20242.6 KiB9465

meson.buildH A D16-Jul-20241.1 KiB4439

opae_at24_eeprom.cH A D16-Jul-20241.4 KiB8866

opae_at24_eeprom.hH A D16-Jul-2024406 157

opae_debug.cH A D16-Jul-20242.9 KiB10381

opae_debug.hH A D16-Jul-2024522 2012

opae_eth_group.cH A D16-Jul-20246.4 KiB317227

opae_eth_group.hH A D16-Jul-20242.1 KiB10382

opae_hw_api.cH A D16-Jul-202424.3 KiB1,093608

opae_hw_api.hH A D29-Jan-202512.1 KiB

opae_i2c.cH A D16-Jul-202411 KiB514388

opae_i2c.hH A D16-Jul-20244.3 KiB133107

opae_ifpga_hw_api.cH A D16-Jul-20242.9 KiB146100

opae_ifpga_hw_api.hH A D16-Jul-202411.8 KiB283208

opae_intel_max10.cH A D29-Jan-202534 KiB

opae_intel_max10.hH A D16-Jul-202416.2 KiB557459

opae_osdep.hH A D29-Jan-20253.6 KiB

opae_spi.cH A D16-Jul-20246.5 KiB316247

opae_spi.hH A D16-Jul-20245.5 KiB179157

opae_spi_transaction.cH A D29-Jan-202511.3 KiB

README

1..
2
3/* SPDX-License-Identifier: BSD-3-Clause
4 * Copyright(c) 2010-2018 Intel Corporation
5 */
6
7Intel iFPGA driver
8==================
9
10This directory contains source code of Intel FPGA driver released by
11the team which develops Intel FPGA Open Programmable Acceleration Engine (OPAE).
12The directory of base/ contains the original source package. The base code
13currently supports Intel FPGA solutions including integrated solution (Intel(R)
14Xeon(R) CPU with FPGAs) and discrete solution (Intel(R) Programmable Acceleration
15Card with Intel(R) Arria(R) 10 FPGA) and it could be extended to support more FPGA
16devices in the future.
17
18Please refer to [1][2] for more introduction on OPAE and Intel FPGAs.
19
20[1] https://01.org/OPAE
21[2] https://www.altera.com/solutions/acceleration-hub/overview.html
22
23
24Updating the driver
25===================
26
27NOTE: The source code in this directory should not be modified apart from
28the following file(s):
29
30	osdep_raw/osdep_generic.h
31	osdep_rte/osdep_generic.h
32
33
34New Features
35==================
36
372019-03:
38Support Intel FPGA PAC N3000 card.
39Some features added in this version:
401. Store private features in FME and Port list.
412. Add eth group devices driver.
423. Add altera SPI master driver and Intel MAX10 device driver.
434. Add Altera I2C master driver and AT24 eeprom driver.
445. Add Device Tree support to get the configuration from card.
456. Instruding and exposing APIs to DPDK PMD to access networking
46functionality.
47