1*473c88f9SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2*473c88f9SBruce Richardson * Copyright(c) 2010-2018 Intel Corporation
3*473c88f9SBruce Richardson */
4*473c88f9SBruce Richardson
5*473c88f9SBruce Richardson #include "opae_ifpga_hw_api.h"
6*473c88f9SBruce Richardson #include "ifpga_api.h"
7*473c88f9SBruce Richardson
opae_manager_ifpga_get_prop(struct opae_manager * mgr,struct feature_prop * prop)8*473c88f9SBruce Richardson int opae_manager_ifpga_get_prop(struct opae_manager *mgr,
9*473c88f9SBruce Richardson struct feature_prop *prop)
10*473c88f9SBruce Richardson {
11*473c88f9SBruce Richardson struct ifpga_fme_hw *fme;
12*473c88f9SBruce Richardson
13*473c88f9SBruce Richardson if (!mgr || !mgr->data)
14*473c88f9SBruce Richardson return -EINVAL;
15*473c88f9SBruce Richardson
16*473c88f9SBruce Richardson fme = mgr->data;
17*473c88f9SBruce Richardson
18*473c88f9SBruce Richardson return ifpga_get_prop(fme->parent, FEATURE_FIU_ID_FME, 0, prop);
19*473c88f9SBruce Richardson }
20*473c88f9SBruce Richardson
opae_manager_ifpga_set_prop(struct opae_manager * mgr,struct feature_prop * prop)21*473c88f9SBruce Richardson int opae_manager_ifpga_set_prop(struct opae_manager *mgr,
22*473c88f9SBruce Richardson struct feature_prop *prop)
23*473c88f9SBruce Richardson {
24*473c88f9SBruce Richardson struct ifpga_fme_hw *fme;
25*473c88f9SBruce Richardson
26*473c88f9SBruce Richardson if (!mgr || !mgr->data)
27*473c88f9SBruce Richardson return -EINVAL;
28*473c88f9SBruce Richardson
29*473c88f9SBruce Richardson fme = mgr->data;
30*473c88f9SBruce Richardson
31*473c88f9SBruce Richardson return ifpga_set_prop(fme->parent, FEATURE_FIU_ID_FME, 0, prop);
32*473c88f9SBruce Richardson }
33*473c88f9SBruce Richardson
opae_manager_ifpga_get_info(struct opae_manager * mgr,struct fpga_fme_info * fme_info)34*473c88f9SBruce Richardson int opae_manager_ifpga_get_info(struct opae_manager *mgr,
35*473c88f9SBruce Richardson struct fpga_fme_info *fme_info)
36*473c88f9SBruce Richardson {
37*473c88f9SBruce Richardson struct ifpga_fme_hw *fme;
38*473c88f9SBruce Richardson
39*473c88f9SBruce Richardson if (!mgr || !mgr->data || !fme_info)
40*473c88f9SBruce Richardson return -EINVAL;
41*473c88f9SBruce Richardson
42*473c88f9SBruce Richardson fme = mgr->data;
43*473c88f9SBruce Richardson
44*473c88f9SBruce Richardson spinlock_lock(&fme->lock);
45*473c88f9SBruce Richardson fme_info->capability = fme->capability;
46*473c88f9SBruce Richardson spinlock_unlock(&fme->lock);
47*473c88f9SBruce Richardson
48*473c88f9SBruce Richardson return 0;
49*473c88f9SBruce Richardson }
50*473c88f9SBruce Richardson
opae_manager_ifpga_set_err_irq(struct opae_manager * mgr,struct fpga_fme_err_irq_set * err_irq_set)51*473c88f9SBruce Richardson int opae_manager_ifpga_set_err_irq(struct opae_manager *mgr,
52*473c88f9SBruce Richardson struct fpga_fme_err_irq_set *err_irq_set)
53*473c88f9SBruce Richardson {
54*473c88f9SBruce Richardson struct ifpga_fme_hw *fme;
55*473c88f9SBruce Richardson
56*473c88f9SBruce Richardson if (!mgr || !mgr->data)
57*473c88f9SBruce Richardson return -EINVAL;
58*473c88f9SBruce Richardson
59*473c88f9SBruce Richardson fme = mgr->data;
60*473c88f9SBruce Richardson
61*473c88f9SBruce Richardson return ifpga_set_irq(fme->parent, FEATURE_FIU_ID_FME, 0,
62*473c88f9SBruce Richardson IFPGA_FME_FEATURE_ID_GLOBAL_ERR, err_irq_set);
63*473c88f9SBruce Richardson }
64*473c88f9SBruce Richardson
opae_bridge_ifpga_get_prop(struct opae_bridge * br,struct feature_prop * prop)65*473c88f9SBruce Richardson int opae_bridge_ifpga_get_prop(struct opae_bridge *br,
66*473c88f9SBruce Richardson struct feature_prop *prop)
67*473c88f9SBruce Richardson {
68*473c88f9SBruce Richardson struct ifpga_port_hw *port;
69*473c88f9SBruce Richardson
70*473c88f9SBruce Richardson if (!br || !br->data)
71*473c88f9SBruce Richardson return -EINVAL;
72*473c88f9SBruce Richardson
73*473c88f9SBruce Richardson port = br->data;
74*473c88f9SBruce Richardson
75*473c88f9SBruce Richardson return ifpga_get_prop(port->parent, FEATURE_FIU_ID_PORT,
76*473c88f9SBruce Richardson port->port_id, prop);
77*473c88f9SBruce Richardson }
78*473c88f9SBruce Richardson
opae_bridge_ifpga_set_prop(struct opae_bridge * br,struct feature_prop * prop)79*473c88f9SBruce Richardson int opae_bridge_ifpga_set_prop(struct opae_bridge *br,
80*473c88f9SBruce Richardson struct feature_prop *prop)
81*473c88f9SBruce Richardson {
82*473c88f9SBruce Richardson struct ifpga_port_hw *port;
83*473c88f9SBruce Richardson
84*473c88f9SBruce Richardson if (!br || !br->data)
85*473c88f9SBruce Richardson return -EINVAL;
86*473c88f9SBruce Richardson
87*473c88f9SBruce Richardson port = br->data;
88*473c88f9SBruce Richardson
89*473c88f9SBruce Richardson return ifpga_set_prop(port->parent, FEATURE_FIU_ID_PORT,
90*473c88f9SBruce Richardson port->port_id, prop);
91*473c88f9SBruce Richardson }
92*473c88f9SBruce Richardson
opae_bridge_ifpga_get_info(struct opae_bridge * br,struct fpga_port_info * port_info)93*473c88f9SBruce Richardson int opae_bridge_ifpga_get_info(struct opae_bridge *br,
94*473c88f9SBruce Richardson struct fpga_port_info *port_info)
95*473c88f9SBruce Richardson {
96*473c88f9SBruce Richardson struct ifpga_port_hw *port;
97*473c88f9SBruce Richardson
98*473c88f9SBruce Richardson if (!br || !br->data || !port_info)
99*473c88f9SBruce Richardson return -EINVAL;
100*473c88f9SBruce Richardson
101*473c88f9SBruce Richardson port = br->data;
102*473c88f9SBruce Richardson
103*473c88f9SBruce Richardson spinlock_lock(&port->lock);
104*473c88f9SBruce Richardson port_info->capability = port->capability;
105*473c88f9SBruce Richardson port_info->num_uafu_irqs = port->num_uafu_irqs;
106*473c88f9SBruce Richardson spinlock_unlock(&port->lock);
107*473c88f9SBruce Richardson
108*473c88f9SBruce Richardson return 0;
109*473c88f9SBruce Richardson }
110*473c88f9SBruce Richardson
opae_bridge_ifpga_get_region_info(struct opae_bridge * br,struct fpga_port_region_info * info)111*473c88f9SBruce Richardson int opae_bridge_ifpga_get_region_info(struct opae_bridge *br,
112*473c88f9SBruce Richardson struct fpga_port_region_info *info)
113*473c88f9SBruce Richardson {
114*473c88f9SBruce Richardson struct ifpga_port_hw *port;
115*473c88f9SBruce Richardson
116*473c88f9SBruce Richardson if (!br || !br->data || !info)
117*473c88f9SBruce Richardson return -EINVAL;
118*473c88f9SBruce Richardson
119*473c88f9SBruce Richardson /* Only support STP region now */
120*473c88f9SBruce Richardson if (info->index != PORT_REGION_INDEX_STP)
121*473c88f9SBruce Richardson return -EINVAL;
122*473c88f9SBruce Richardson
123*473c88f9SBruce Richardson port = br->data;
124*473c88f9SBruce Richardson
125*473c88f9SBruce Richardson spinlock_lock(&port->lock);
126*473c88f9SBruce Richardson info->addr = port->stp_addr;
127*473c88f9SBruce Richardson info->size = port->stp_size;
128*473c88f9SBruce Richardson spinlock_unlock(&port->lock);
129*473c88f9SBruce Richardson
130*473c88f9SBruce Richardson return 0;
131*473c88f9SBruce Richardson }
132*473c88f9SBruce Richardson
opae_bridge_ifpga_set_err_irq(struct opae_bridge * br,struct fpga_port_err_irq_set * err_irq_set)133*473c88f9SBruce Richardson int opae_bridge_ifpga_set_err_irq(struct opae_bridge *br,
134*473c88f9SBruce Richardson struct fpga_port_err_irq_set *err_irq_set)
135*473c88f9SBruce Richardson {
136*473c88f9SBruce Richardson struct ifpga_port_hw *port;
137*473c88f9SBruce Richardson
138*473c88f9SBruce Richardson if (!br || !br->data)
139*473c88f9SBruce Richardson return -EINVAL;
140*473c88f9SBruce Richardson
141*473c88f9SBruce Richardson port = br->data;
142*473c88f9SBruce Richardson
143*473c88f9SBruce Richardson return ifpga_set_irq(port->parent, FEATURE_FIU_ID_PORT, port->port_id,
144*473c88f9SBruce Richardson IFPGA_PORT_FEATURE_ID_ERROR, err_irq_set);
145*473c88f9SBruce Richardson }
146