1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
3 */
4
5 #include "opae_ifpga_hw_api.h"
6 #include "ifpga_api.h"
7
opae_manager_ifpga_get_prop(struct opae_manager * mgr,struct feature_prop * prop)8 int opae_manager_ifpga_get_prop(struct opae_manager *mgr,
9 struct feature_prop *prop)
10 {
11 struct ifpga_fme_hw *fme;
12
13 if (!mgr || !mgr->data)
14 return -EINVAL;
15
16 fme = mgr->data;
17
18 return ifpga_get_prop(fme->parent, FEATURE_FIU_ID_FME, 0, prop);
19 }
20
opae_manager_ifpga_set_prop(struct opae_manager * mgr,struct feature_prop * prop)21 int opae_manager_ifpga_set_prop(struct opae_manager *mgr,
22 struct feature_prop *prop)
23 {
24 struct ifpga_fme_hw *fme;
25
26 if (!mgr || !mgr->data)
27 return -EINVAL;
28
29 fme = mgr->data;
30
31 return ifpga_set_prop(fme->parent, FEATURE_FIU_ID_FME, 0, prop);
32 }
33
opae_manager_ifpga_get_info(struct opae_manager * mgr,struct fpga_fme_info * fme_info)34 int opae_manager_ifpga_get_info(struct opae_manager *mgr,
35 struct fpga_fme_info *fme_info)
36 {
37 struct ifpga_fme_hw *fme;
38
39 if (!mgr || !mgr->data || !fme_info)
40 return -EINVAL;
41
42 fme = mgr->data;
43
44 spinlock_lock(&fme->lock);
45 fme_info->capability = fme->capability;
46 spinlock_unlock(&fme->lock);
47
48 return 0;
49 }
50
opae_manager_ifpga_set_err_irq(struct opae_manager * mgr,struct fpga_fme_err_irq_set * err_irq_set)51 int opae_manager_ifpga_set_err_irq(struct opae_manager *mgr,
52 struct fpga_fme_err_irq_set *err_irq_set)
53 {
54 struct ifpga_fme_hw *fme;
55
56 if (!mgr || !mgr->data)
57 return -EINVAL;
58
59 fme = mgr->data;
60
61 return ifpga_set_irq(fme->parent, FEATURE_FIU_ID_FME, 0,
62 IFPGA_FME_FEATURE_ID_GLOBAL_ERR, err_irq_set);
63 }
64
opae_bridge_ifpga_get_prop(struct opae_bridge * br,struct feature_prop * prop)65 int opae_bridge_ifpga_get_prop(struct opae_bridge *br,
66 struct feature_prop *prop)
67 {
68 struct ifpga_port_hw *port;
69
70 if (!br || !br->data)
71 return -EINVAL;
72
73 port = br->data;
74
75 return ifpga_get_prop(port->parent, FEATURE_FIU_ID_PORT,
76 port->port_id, prop);
77 }
78
opae_bridge_ifpga_set_prop(struct opae_bridge * br,struct feature_prop * prop)79 int opae_bridge_ifpga_set_prop(struct opae_bridge *br,
80 struct feature_prop *prop)
81 {
82 struct ifpga_port_hw *port;
83
84 if (!br || !br->data)
85 return -EINVAL;
86
87 port = br->data;
88
89 return ifpga_set_prop(port->parent, FEATURE_FIU_ID_PORT,
90 port->port_id, prop);
91 }
92
opae_bridge_ifpga_get_info(struct opae_bridge * br,struct fpga_port_info * port_info)93 int opae_bridge_ifpga_get_info(struct opae_bridge *br,
94 struct fpga_port_info *port_info)
95 {
96 struct ifpga_port_hw *port;
97
98 if (!br || !br->data || !port_info)
99 return -EINVAL;
100
101 port = br->data;
102
103 spinlock_lock(&port->lock);
104 port_info->capability = port->capability;
105 port_info->num_uafu_irqs = port->num_uafu_irqs;
106 spinlock_unlock(&port->lock);
107
108 return 0;
109 }
110
opae_bridge_ifpga_get_region_info(struct opae_bridge * br,struct fpga_port_region_info * info)111 int opae_bridge_ifpga_get_region_info(struct opae_bridge *br,
112 struct fpga_port_region_info *info)
113 {
114 struct ifpga_port_hw *port;
115
116 if (!br || !br->data || !info)
117 return -EINVAL;
118
119 /* Only support STP region now */
120 if (info->index != PORT_REGION_INDEX_STP)
121 return -EINVAL;
122
123 port = br->data;
124
125 spinlock_lock(&port->lock);
126 info->addr = port->stp_addr;
127 info->size = port->stp_size;
128 spinlock_unlock(&port->lock);
129
130 return 0;
131 }
132
opae_bridge_ifpga_set_err_irq(struct opae_bridge * br,struct fpga_port_err_irq_set * err_irq_set)133 int opae_bridge_ifpga_set_err_irq(struct opae_bridge *br,
134 struct fpga_port_err_irq_set *err_irq_set)
135 {
136 struct ifpga_port_hw *port;
137
138 if (!br || !br->data)
139 return -EINVAL;
140
141 port = br->data;
142
143 return ifpga_set_irq(port->parent, FEATURE_FIU_ID_PORT, port->port_id,
144 IFPGA_PORT_FEATURE_ID_ERROR, err_irq_set);
145 }
146