1*a05bd1b4SWei Huang /* SPDX-License-Identifier: BSD-3-Clause 2*a05bd1b4SWei Huang * Copyright(c) 2020 Intel Corporation 3*a05bd1b4SWei Huang */ 4*a05bd1b4SWei Huang 5*a05bd1b4SWei Huang #ifndef _IFPGA_FME_RSU_H_ 6*a05bd1b4SWei Huang #define _IFPGA_FME_RSU_H_ 7*a05bd1b4SWei Huang 8*a05bd1b4SWei Huang 9*a05bd1b4SWei Huang #include "ifpga_hw.h" 10*a05bd1b4SWei Huang 11*a05bd1b4SWei Huang #define IFPGA_N3000_VID 0x8086 12*a05bd1b4SWei Huang #define IFPGA_N3000_DID 0x0b30 13*a05bd1b4SWei Huang 14*a05bd1b4SWei Huang #define IFPGA_BOOT_TYPE_FPGA 0 15*a05bd1b4SWei Huang #define IFPGA_BOOT_TYPE_BMC 1 16*a05bd1b4SWei Huang 17*a05bd1b4SWei Huang #define IFPGA_BOOT_PAGE_FACTORY 0 18*a05bd1b4SWei Huang #define IFPGA_BOOT_PAGE_USER 1 19*a05bd1b4SWei Huang 20*a05bd1b4SWei Huang #define IFPGA_RSU_DATA_BLK_SIZE 32768 21*a05bd1b4SWei Huang #define IFPGA_RSU_START_RETRY 120 22*a05bd1b4SWei Huang #define IFPGA_RSU_WRITE_RETRY 10 23*a05bd1b4SWei Huang #define IFPGA_RSU_CANCEL_RETRY 30 24*a05bd1b4SWei Huang 25*a05bd1b4SWei Huang #define IFPGA_N3000_COPY_SPEED 42700 26*a05bd1b4SWei Huang 27*a05bd1b4SWei Huang /* status */ 28*a05bd1b4SWei Huang #define IFPGA_RSU_IDLE 0 29*a05bd1b4SWei Huang #define IFPGA_RSU_PREPARE 1 30*a05bd1b4SWei Huang #define IFPGA_RSU_READY 2 31*a05bd1b4SWei Huang #define IFPGA_RSU_COPYING 3 32*a05bd1b4SWei Huang #define IFPGA_RSU_REBOOT 4 33*a05bd1b4SWei Huang 34*a05bd1b4SWei Huang #define IFPGA_RSU_GET_STAT(v) (((v) >> 16) & 0xffff) 35*a05bd1b4SWei Huang #define IFPGA_RSU_GET_PROG(v) ((v) & 0xffff) 36*a05bd1b4SWei Huang #define IFPGA_RSU_STATUS(s, p) ((((s) << 16) & 0xffff0000) | ((p) & 0xffff)) 37*a05bd1b4SWei Huang 38*a05bd1b4SWei Huang /* control */ 39*a05bd1b4SWei Huang #define IFPGA_RSU_ABORT 1 40*a05bd1b4SWei Huang 41*a05bd1b4SWei Huang #define IFPGA_DUAL_CFG_CTRL0 0x200020 42*a05bd1b4SWei Huang #define IFPGA_DUAL_CFG_CTRL1 0x200024 43*a05bd1b4SWei Huang 44*a05bd1b4SWei Huang #define IFPGA_SEC_START_INTERVAL_MS 100 45*a05bd1b4SWei Huang #define IFPGA_SEC_START_TIMEOUT_MS 20000 46*a05bd1b4SWei Huang #define IFPGA_NIOS_HANDSHAKE_INTERVAL_MS 100 47*a05bd1b4SWei Huang #define IFPGA_NIOS_HANDSHAKE_TIMEOUT_MS 5000 48*a05bd1b4SWei Huang 49*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_HW_ERROR -1 50*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_TIMEOUT -2 51*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_CANCELED -3 52*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_BUSY -4 53*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_INVALID_SIZE -5 54*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_RW_ERROR -6 55*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_WEAROUT -7 56*a05bd1b4SWei Huang #define IFPGA_RSU_ERR_FILE_READ -8 57*a05bd1b4SWei Huang 58*a05bd1b4SWei Huang struct ifpga_sec_mgr; 59*a05bd1b4SWei Huang 60*a05bd1b4SWei Huang struct ifpga_sec_ops { 61*a05bd1b4SWei Huang int (*prepare)(struct ifpga_sec_mgr *smgr); 62*a05bd1b4SWei Huang int (*write_blk)(struct ifpga_sec_mgr *smgr, char *buf, uint32_t offset, 63*a05bd1b4SWei Huang uint32_t size); 64*a05bd1b4SWei Huang int (*write_done)(struct ifpga_sec_mgr *smgr); 65*a05bd1b4SWei Huang int (*check_complete)(struct ifpga_sec_mgr *smgr); 66*a05bd1b4SWei Huang int (*reload)(struct ifpga_sec_mgr *smgr, int type, int page); 67*a05bd1b4SWei Huang int (*cancel)(struct ifpga_sec_mgr *smgr); 68*a05bd1b4SWei Huang void (*cleanup)(struct ifpga_sec_mgr *smgr); 69*a05bd1b4SWei Huang u64 (*get_hw_errinfo)(struct ifpga_sec_mgr *smgr); 70*a05bd1b4SWei Huang }; 71*a05bd1b4SWei Huang 72*a05bd1b4SWei Huang struct ifpga_sec_mgr { 73*a05bd1b4SWei Huang struct ifpga_fme_hw *fme; 74*a05bd1b4SWei Huang struct intel_max10_device *max10_dev; 75*a05bd1b4SWei Huang unsigned int rsu_length; 76*a05bd1b4SWei Huang /* number of bytes that copied from staging area to working area 77*a05bd1b4SWei Huang * in one second, which is calculated by experiment 78*a05bd1b4SWei Huang */ 79*a05bd1b4SWei Huang unsigned int copy_speed; 80*a05bd1b4SWei Huang unsigned int *rsu_control; 81*a05bd1b4SWei Huang unsigned int *rsu_status; 82*a05bd1b4SWei Huang const struct ifpga_sec_ops *ops; 83*a05bd1b4SWei Huang }; 84*a05bd1b4SWei Huang 85*a05bd1b4SWei Huang int init_sec_mgr(struct ifpga_fme_hw *fme); 86*a05bd1b4SWei Huang void release_sec_mgr(struct ifpga_fme_hw *fme); 87*a05bd1b4SWei Huang int fpga_update_flash(struct ifpga_fme_hw *fme, const char *image, 88*a05bd1b4SWei Huang uint64_t *status); 89*a05bd1b4SWei Huang int fpga_stop_flash_update(struct ifpga_fme_hw *fme, int force); 90*a05bd1b4SWei Huang int fpga_reload(struct ifpga_fme_hw *fme, int type, int page); 91*a05bd1b4SWei Huang 92*a05bd1b4SWei Huang 93*a05bd1b4SWei Huang #endif /* _IFPGA_FME_RSU_H_ */ 94