Add SDNode ordering to inlined asm and VA functions.

llvm-svn: 91876

Adding more assignment of ordering to SDNodes. This time in the "call" and
generic copy functions.

llvm-svn: 91872

Add ordering of SDNodes to LowerCallTo.

llvm-svn: 91866

Now add ordering to SDNodes created by the massive intrinsic lowering function.

llvm-svn: 91863

To make things interesting, I added MORE code to set the ordering of
SDNodes. This time in the load/store and limited-precision code.

llvm-svn: 91860

Add more plumbing to assign ordering to SDNodes. Have the "getValue" method
assign the ordering when called. Combine some of the ordering assignments to
keep things simple.

llvm-svn: 91857

More ordering plumbing. This time for GEP. I need to remember to assign
orderings to values returned by getValue().

llvm-svn: 91850

Another incremental check-in for assigning ordering to SDNodes. This time for
shuffle and insert vector.

llvm-svn: 91847

Assign ordering to more instructions. Incremental check-in.

llvm-svn: 91846

- Add a bit more plumbing assigning an order to SDNodes.
- Modify the "dump" method to emit the order of an SDNode.

llvm-svn: 91845

First wave of plumbing for assigning an ordering to SDNodes. This takes care of
a lot of the branching instructions.

llvm-svn: 91838

Changes from review:

- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
doesn't conflate construction with storage.

Changes from review:

- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.

This isn't used yet, so there should be no functional changes.

llvm-svn: 91727

show more ...

Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers)

Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.

llvm-svn: 91649

show more ...

Fix a comment grammaro.

llvm-svn: 91584

Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good.

llvm-svn: 91560

Revert "Initial work on disabling the scheduler. This is a work in progress, and
this", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.

llvm-svn: 91533

Initial work on disabling the scheduler. This is a work in progress, and this
stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothes

Initial work on disabling the scheduler. This is a work in progress, and this
stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.

The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.

llvm-svn: 91392

show more ...

Fix the result type of SELECT nodes lowered from Select instructions with
aggregate return values. This fixes PR5754.

llvm-svn: 91145

Rename SelectionDAGLowering to SelectionDAGBuilder, and rename
SelectionDAGBuild.cpp to SelectionDAGBuilder.cpp.

llvm-svn: 89681