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/freebsd-src/sys/conf/
H A Dfiles.riscv1 cddl/dev/dtrace/riscv/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}"
2 cddl/dev/dtrace/riscv/dtrace_isa.c optional dtrace compile-with "${DTRACE_C}"
3 cddl/dev/dtrace/riscv/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}"
4 cddl/dev/dtrace/riscv/instr_size.c optional dtrace compile-with "${DTRACE_C}"
5 cddl/dev/fbt/riscv/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
40 riscv/riscv/aplic.c standard
41 riscv/riscv/autoconf.c standard
42 riscv/risc
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/freebsd-src/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2042-cpus.dtsi257 compatible = "thead,c920", "riscv";
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
272 mmu-type = "riscv,sv39";
275 compatible = "riscv,cpu-intc";
282 compatible = "thead,c920", "riscv";
284 riscv,isa = "rv64imafdc";
285 riscv,isa-base = "rv64i";
286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp35 #include "RISCV.h"
45 #define DEBUG_TYPE "riscv-opt-w-instrs"
52 static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
55 static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
96 unsigned MCOpcode = RISCV::getRVVMCOpcode(MI.getOpcode()); in vectorPseudoHasAllNBitUsers()
112 RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW); in hasAllNBitUsers()
154 case RISCV::ADDIW: in hasAllNBitUsers()
155 case RISCV::ADDW: in hasAllNBitUsers()
156 case RISCV::DIVUW: in hasAllNBitUsers()
157 case RISCV in hasAllNBitUsers()
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H A DRISCVExpandPseudoInsts.cpp15 #include "RISCV.h"
108 case RISCV::PseudoRV32ZdinxSD: in expandMI()
110 case RISCV::PseudoRV32ZdinxLD: in expandMI()
112 case RISCV::PseudoCCMOVGPRNoX0: in expandMI()
113 case RISCV::PseudoCCMOVGPR: in expandMI()
114 case RISCV::PseudoCCADD: in expandMI()
115 case RISCV::PseudoCCSUB: in expandMI()
116 case RISCV::PseudoCCAND: in expandMI()
117 case RISCV::PseudoCCOR: in expandMI()
118 case RISCV in expandMI()
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H A DRISCVInstrInfo.cpp15 #include "RISCV.h"
48 "riscv-prefer-whole-register-move", cl::init(false), cl::Hidden,
52 "riscv-force-machine-combiner-strategy", cl::Hidden,
63 using namespace RISCV;
70 namespace llvm::RISCV { in RISCVInstrInfo()
75 } // end namespace llvm::RISCV in getNop()
78 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), in getNop()
83 return MCInstBuilder(RISCV::C_NOP); in isLoadFromStackSlot()
84 return MCInstBuilder(RISCV in isLoadFromStackSlot()
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H A DRISCVRegisterInfo.cpp14 #include "RISCV.h"
33 static cl::opt<bool> DisableCostPerUse("riscv-disable-cost-per-use",
36 DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
41 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
42 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
43 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
44 static_assert(RISCV
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H A DRISCVAsmPrinter.cpp19 #include "RISCV.h"
53 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
133 MII->getOpcode() == RISCV::DBG_VALUE || in LowerSTACKMAP()
168 RISCVMatInt::generateMCInstSeq(CallTarget, *STI, RISCV::X1, Seq); in LowerSTATEPOINT()
173 bool Compressed = EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR) in LowerSTATEPOINT()
174 .addReg(RISCV::X1) in LowerSTATEPOINT()
175 .addReg(RISCV::X1) in LowerSTATEPOINT()
183 MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp)); in EmitToStreamer()
215 MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp)); in emitNTLHint()
219 EmitToStreamer(OutStreamer, MCInstBuilder(RISCV in emitNTLHint()
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H A DRISCVExpandAtomicPseudoInsts.cpp16 #include "RISCV.h"
114 case RISCV::PseudoAtomicLoadNand32: in expandMI()
117 case RISCV::PseudoAtomicLoadNand64: in expandMI()
120 case RISCV::PseudoMaskedAtomicSwap32: in expandMI()
123 case RISCV::PseudoMaskedAtomicLoadAdd32: in expandMI()
125 case RISCV::PseudoMaskedAtomicLoadSub32: in expandMI()
127 case RISCV::PseudoMaskedAtomicLoadNand32: in expandMI()
130 case RISCV::PseudoMaskedAtomicLoadMax32: in expandMI()
133 case RISCV::PseudoMaskedAtomicLoadMin32: in expandMI()
136 case RISCV::PseudoMaskedAtomicLoadUMax32: in expandMI()
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H A DRISCVMergeBaseOffset.cpp14 #include "RISCV.h"
24 #define DEBUG_TYPE "riscv-merge-base-offset"
87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC && in INITIALIZE_PASS()
88 Hi.getOpcode() != RISCV::PseudoMovAddr) in INITIALIZE_PASS()
93 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; in INITIALIZE_PASS()
101 if (Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
111 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
116 if (Hi.getOpcode() == RISCV::LUI || Hi.getOpcode() == RISCV in INITIALIZE_PASS()
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H A DRISCVISelDAGToDAG.cpp28 #define DEBUG_TYPE "riscv-isel"
32 "riscv-use-rematerializable-movimm", cl::Hidden,
37 namespace llvm::RISCV { namespace
47 } // namespace llvm::RISCV
67 SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT()); in PreprocessISelDAG()
114 CurDAG->getRegister(RISCV::X0, MVT::i64), in PreprocessISelDAG()
177 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT); in selectImmSeq()
187 CurDAG->getRegister(RISCV::X0, VT)); in selectImmSeq()
211 CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT, in selectImm()
228 CurDAG->getMachineNode(RISCV in selectImm()
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H A DRISCVMakeCompressible.cpp68 #include "RISCV.h"
77 #define DEBUG_TYPE "riscv-make-compressible"
94 INITIALIZE_PASS(RISCVMakeCompressibleOpt, "riscv-make-compressible",
102 case RISCV::LBU: in log2LdstWidth()
103 case RISCV::SB: in log2LdstWidth()
105 case RISCV::LH: in log2LdstWidth()
106 case RISCV::LHU: in log2LdstWidth()
107 case RISCV::SH: in log2LdstWidth()
109 case RISCV::LW: in log2LdstWidth()
110 case RISCV in log2LdstWidth()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp126 if (MI.getOpcode() == RISCV::PseudoTAIL) { in expandFunctionCall()
128 Ra = RISCV::X6; in expandFunctionCall()
131 if (STI.hasFeature(RISCV::FeatureStdExtZicfilp)) in expandFunctionCall()
132 Ra = RISCV::X7; in expandFunctionCall()
133 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { in expandFunctionCall()
136 } else if (MI.getOpcode() == RISCV::PseudoCALL) { in expandFunctionCall()
138 Ra = RISCV::X1; in expandFunctionCall()
139 } else if (MI.getOpcode() == RISCV::PseudoJump) { in expandFunctionCall()
150 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); in expandFunctionCall()
154 if (MI.getOpcode() == RISCV in expandFunctionCall()
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H A DRISCVELFObjectWriter.cpp68 case RISCV::fixup_riscv_pcrel_hi20: in getRelocType()
70 case RISCV::fixup_riscv_pcrel_lo12_i: in getRelocType()
72 case RISCV::fixup_riscv_pcrel_lo12_s: in getRelocType()
74 case RISCV::fixup_riscv_got_hi20: in getRelocType()
76 case RISCV::fixup_riscv_tls_got_hi20: in getRelocType()
78 case RISCV::fixup_riscv_tls_gd_hi20: in getRelocType()
80 case RISCV::fixup_riscv_tlsdesc_hi20: in getRelocType()
82 case RISCV::fixup_riscv_tlsdesc_load_lo12: in getRelocType()
84 case RISCV::fixup_riscv_tlsdesc_add_lo12: in getRelocType()
86 case RISCV::fixup_riscv_tlsdesc_call: in getRelocType()
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H A DRISCVMatInt.cpp25 case RISCV::SLLI: in getInstSeqCost()
26 case RISCV::SRLI: in getInstSeqCost()
29 case RISCV::ADDI: in getInstSeqCost()
30 case RISCV::ADDIW: in getInstSeqCost()
31 case RISCV::LUI: in getInstSeqCost()
51 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in generateInstSeqImpl()
54 if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) && in generateInstSeqImpl()
56 Res.emplace_back(RISCV::BSETI, Log2_64(Val)); in generateInstSeqImpl()
72 Res.emplace_back(RISCV::LUI, Hi20); in generateInstSeqImpl()
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV in generateInstSeqImpl()
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H A DRISCVAsmBackend.cpp30 static cl::opt<bool> RelaxBranches("riscv-asm-relax-branches", cl::init(true),
36 "riscv-uleb128-reloc", cl::init(true), cl::Hidden,
44 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" in getFixupKind()
95 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds, in getFixupKindInfo()
131 case RISCV::fixup_riscv_got_hi20: in shouldForceRelocation()
132 case RISCV::fixup_riscv_tls_got_hi20: in shouldForceRelocation()
133 case RISCV::fixup_riscv_tls_gd_hi20: in shouldForceRelocation()
134 case RISCV::fixup_riscv_tlsdesc_hi20: in shouldForceRelocation()
138 return STI->hasFeature(RISCV::FeatureRelax) || ForceRelocs; in shouldForceRelocation()
160 case RISCV in fixupNeedsRelaxationAdvanced()
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H A DRISCVMCTargetDesc.cpp48 using namespace RISCV; in createRISCVMCInstrInfo()
65 InitRISCVMCRegisterInfo(X, RISCV::X1); in createRISCVMCAsmInfo()
74 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); in createRISCVMCObjectFileInfo()
130 return Reg >= RISCV::X0 && Reg <= RISCV::X31; in setGPRState()
134 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg"); in setGPRState()
135 return Reg - RISCV::X1; in setGPRState()
139 if (Reg == RISCV::X0) in setGPRState()
153 if (Reg == RISCV::X0) in getGPRState()
192 case RISCV in evaluateBranch()
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/freebsd-src/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
31 const: riscv
34 riscv,isa:
39 https://riscv.org/specifications/
43 Notably, riscv,isa was defined prior to the creation of the
48 insensitive, letters in the riscv,isa string must be all
54 riscv,isa-base:
62 riscv,isa-extensions:
116 encoding") of the riscv-v-spec.
129 request #42 from riscv/jhause
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H A Dcpus.yaml4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
53 - const: riscv
59 - const: riscv
60 - const: riscv # Simulator only
70 https://riscv.org/specifications/
73 - riscv,sv32
74 - riscv,sv39
75 - riscv,sv48
76 - riscv,sv57
77 - riscv,non
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp28 #define DEBUG_TYPE "riscv-disassembler"
74 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE); in DecodeGPRRegisterClass()
79 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRX1X5RegisterClass()
87 MCRegister Reg = RISCV::X0 + RegNo;
88 if (Reg != RISCV::X1 && Reg != RISCV::X5) in DecodeFPR16RegisterClass()
101 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR32RegisterClass()
112 MCRegister Reg = RISCV::F0_F + RegNo; in DecodeFPR32CRegisterClass()
123 MCRegister Reg = RISCV::F8_F + RegNo; in DecodeFPR64RegisterClass()
134 MCRegister Reg = RISCV in DecodeFPR64CRegisterClass()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp16 #include "RISCV.h"
21 #define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
26 const llvm::StringRef RISCVLMULInstrument::DESC_NAME = "RISCV-LMUL";
51 const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW"; in isDataValid()
105 if (Inst.getOpcode() == RISCV::VSETVLI || in createInstrument()
106 Inst.getOpcode() == RISCV::VSETIVLI) { in createInstrument()
172 case RISCV::VLM_V: in createInstruments()
173 case RISCV::VSM_V: in createInstruments()
174 case RISCV::VLE8_V: in createInstruments()
175 case RISCV in createInstruments()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp26 namespace RISCV {
107 } // namespace RISCV in getRegBankFromRegClass()
121 case RISCV::GPRRegClassID: in getFPValueMapping()
122 case RISCV::GPRF16RegClassID: in getFPValueMapping()
123 case RISCV::GPRF32RegClassID: in getFPValueMapping()
124 case RISCV::GPRNoX0RegClassID: in getFPValueMapping()
125 case RISCV::GPRNoX0X2RegClassID:
126 case RISCV::GPRJALRRegClassID:
127 case RISCV::GPRJALRNonX7RegClassID:
128 case RISCV
25 namespace RISCV { global() namespace
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H A DRISCVInstructionSelector.cpp28 #define DEBUG_TYPE "riscv-isel"
218 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectShiftMask()
219 unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB; in selectShiftMask()
222 .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg}); in selectShiftMask()
229 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
232 .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) in selectSHXADDOp()
278 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
281 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
290 Register DstReg = MRI.createVirtualRegister(&RISCV in selectSHXADDOp()
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/freebsd-src/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/perf/
H A Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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