Lines Matching full:riscv
19 #include "RISCV.h"
53 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
133 MII->getOpcode() == RISCV::DBG_VALUE ||
168 RISCVMatInt::generateMCInstSeq(CallTarget, *STI, RISCV::X1, Seq);
173 bool Compressed = EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR)
174 .addReg(RISCV::X1)
175 .addReg(RISCV::X1)
183 MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp));
215 MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp));
219 EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JAL)
220 .addReg(RISCV::X1)
225 EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR)
226 .addReg(RISCV::X1)
276 Hint.setOpcode(RISCV::C_ADD_HINT);
278 Hint.setOpcode(RISCV::ADD);
280 Hint.addOperand(MCOperand::createReg(RISCV::X0));
281 Hint.addOperand(MCOperand::createReg(RISCV::X0));
282 Hint.addOperand(MCOperand::createReg(RISCV::X2 + NontemporalMode));
299 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
302 case RISCV::KCFI_CHECK:
305 case RISCV::PseudoRVVInitUndefM1:
306 case RISCV::PseudoRVVInitUndefM2:
307 case RISCV::PseudoRVVInitUndefM4:
308 case RISCV::PseudoRVVInitUndefM8:
339 OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
452 if (auto *MD = dyn_cast_or_null<MDNode>(M.getModuleFlag("riscv-isa"))) {
520 std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" +
527 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));
542 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
543 unsigned NextReg = RISCV::X28;
553 if (Reg > RISCV::X31)
557 if (AddrReg == RISCV::X0) {
560 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI)
562 .addReg(RISCV::X0)
576 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::LW)
589 MCInstBuilder(RISCV::LUI).addReg(ScratchRegs[1]).addImm(Hi20));
593 MCInstBuilder((STI->hasFeature(RISCV::Feature64Bit) && Hi20)
594 ? RISCV::ADDIW
595 : RISCV::ADDI)
604 MCInstBuilder(RISCV::BEQ)
611 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::EBREAK));
658 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8),
660 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI)
661 .addReg(RISCV::X6)
662 .addReg(RISCV::X6)
666 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADD)
667 .addReg(RISCV::X6)
668 .addReg(RISCV::X5)
669 .addReg(RISCV::X6),
672 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
676 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56),
681 MCInstBuilder(RISCV::BNE)
682 .addReg(RISCV::X7)
683 .addReg(RISCV::X6)
689 OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR)
690 .addReg(RISCV::X0)
691 .addReg(RISCV::X1)
696 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
697 .addReg(RISCV::X28)
698 .addReg(RISCV::X0)
703 MCInstBuilder(RISCV::BGEU)
704 .addReg(RISCV::X6)
705 .addReg(RISCV::X28)
710 MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),
714 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
715 .addReg(RISCV::X28)
716 .addReg(RISCV::X28)
720 MCInstBuilder(RISCV::BGE)
721 .addReg(RISCV::X28)
722 .addReg(RISCV::X6)
727 MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),
730 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
733 MCInstBuilder(RISCV::BEQ)
734 .addReg(RISCV::X6)
735 .addReg(RISCV::X7)
776 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
777 .addReg(RISCV::X2)
778 .addReg(RISCV::X2)
783 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
784 .addReg(RISCV::X10)
785 .addReg(RISCV::X2)
789 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
790 .addReg(RISCV::X11)
791 .addReg(RISCV::X2)
797 MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 *
802 MCInstBuilder(RISCV::SD).addReg(RISCV::X1).addReg(RISCV::X2).addImm(1 *
805 if (Reg != RISCV::X10)
806 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
807 .addReg(RISCV::X10)
812 MCInstBuilder(RISCV::ADDI)
813 .addReg(RISCV::X11)
814 .addReg(RISCV::X0)
818 OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
971 bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
998 if (RISCV::VRM2RegClass.contains(Reg) ||
999 RISCV::VRM4RegClass.contains(Reg) ||
1000 RISCV::VRM8RegClass.contains(Reg)) {
1001 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1003 } else if (RISCV::FPR16RegClass.contains(Reg)) {
1005 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
1007 } else if (RISCV::FPR64RegClass.contains(Reg)) {
1008 Reg = TRI->getSubReg(Reg, RISCV::sub_32);
1010 } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
1011 RISCV::VRN2M2RegClass.contains(Reg) ||
1012 RISCV::VRN2M4RegClass.contains(Reg) ||
1013 RISCV::VRN3M1RegClass.contains(Reg) ||
1014 RISCV::VRN3M2RegClass.contains(Reg) ||
1015 RISCV::VRN4M1RegClass.contains(Reg) ||
1016 RISCV::VRN4M2RegClass.contains(Reg) ||
1017 RISCV::VRN5M1RegClass.contains(Reg) ||
1018 RISCV::VRN6M1RegClass.contains(Reg) ||
1019 RISCV::VRN7M1RegClass.contains(Reg) ||
1020 RISCV::VRN8M1RegClass.contains(Reg)) {
1021 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1040 RISCV::VMV0RegClassID &&
1042 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));