Lines Matching full:riscv
28 #define DEBUG_TYPE "riscv-isel"
218 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
219 unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB;
222 .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg});
229 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
232 .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg})
278 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
281 .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
290 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
293 .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
329 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
332 .buildInstr(RISCV::SRLIW, {DstReg}, {RegY})
368 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
371 .buildInstr(RISCV::SLLI, {DstReg}, {RegX})
451 RHS = RISCV::X0;
465 RHS = RISCV::X0;
474 LHS = RISCV::X0;
581 Register GPRReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
585 unsigned Opcode = Size == 64 ? RISCV::FMV_D_X
586 : Size == 32 ? RISCV::FMV_W_X
587 : RISCV::FMV_H_X;
595 Register GPRRegHigh = MRI.createVirtualRegister(&RISCV::GPRRegClass);
596 Register GPRRegLow = MRI.createVirtualRegister(&RISCV::GPRRegClass);
603 RISCV::BuildPairF64Pseudo, {DstReg}, {GPRRegLow, GPRRegHigh});
647 MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {MI.getOperand(2)})
653 auto ADD = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass},
658 unsigned LdOpc = EntrySize == 8 ? RISCV::LD : RISCV::LW;
660 MIB.buildInstr(LdOpc, {&RISCV::GPRRegClass}, {ADD.getReg(0)})
672 Dest = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass},
679 MIB.buildInstr(RISCV::PseudoBRIND, {}, {Dest.getReg(0)}).addImm(0);
687 MI.setDesc(TII.get(RISCV::PseudoBRIND));
696 MI.setDesc(TII.get(RISCV::ADDI));
736 MI.setDesc(TII.get(RISCV::BuildPairF64Pseudo));
752 MI.setDesc(TII.get(RISCV::SplitF64Pseudo));
764 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID));
848 if (RB.getID() == RISCV::GPRBRegBankID) {
850 return &RISCV::GPRRegClass;
853 if (RB.getID() == RISCV::FPRBRegBankID) {
855 return &RISCV::FPR16RegClass;
857 return &RISCV::FPR32RegClass;
859 return &RISCV::FPR64RegClass;
862 if (RB.getID() == RISCV::VRBRegBankID) {
864 return &RISCV::VRRegClass;
867 return &RISCV::VRM2RegClass;
870 return &RISCV::VRM4RegClass;
873 return &RISCV::VRM8RegClass;
881 return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::GPRBRegBankID;
886 return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::FPRBRegBankID;
910 MI.setDesc(TII.get(RISCV::COPY));
938 MIB.buildCopy(DstReg, Register(RISCV::X0));
939 RBI.constrainGenericRegister(DstReg, RISCV::GPRRegClass, MRI);
945 Register SrcReg = RISCV::X0;
949 ? MRI.createVirtualRegister(&RISCV::GPRRegClass)
963 {SrcReg, Register(RISCV::X0)});
1007 MI.setDesc(TII.get(RISCV::PseudoLLA));
1022 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {})
1043 Register AddrHiDest = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1044 MachineInstr *AddrHi = MIB.buildInstr(RISCV::LUI, {AddrHiDest}, {})
1050 auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest})
1076 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {})
1090 MI.setDesc(TII.get(RISCV::PseudoLLA));
1111 MIB.buildInstr(RISCV::ADDIW, {Dst.getReg()}, {Src.getReg()}).addImm(0U);
1131 unsigned Opc = RISCV::Select_GPR_Using_CC_GPR;
1132 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) {
1134 Opc = Size == 32 ? RISCV::Select_FPR32_Using_CC_GPR
1135 : RISCV::Select_FPR64_Using_CC_GPR;
1156 return Size == 16 ? RISCV::FLT_H : Size == 32 ? RISCV::FLT_S : RISCV::FLT_D;
1158 return Size == 16 ? RISCV::FLE_H : Size == 32 ? RISCV::FLE_S : RISCV::FLE_D;
1160 return Size == 16 ? RISCV::FEQ_H : Size == 32 ? RISCV::FEQ_S : RISCV::FEQ_D;
1220 TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1228 {&RISCV::GPRRegClass}, {LHS, RHS});
1232 {&RISCV::GPRRegClass}, {RHS, LHS});
1236 TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1238 MIB.buildInstr(RISCV::OR, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)});
1246 {&RISCV::GPRRegClass}, {LHS, LHS});
1250 {&RISCV::GPRRegClass}, {RHS, RHS});
1254 TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1256 MIB.buildInstr(RISCV::AND, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)});
1264 auto Xor = MIB.buildInstr(RISCV::XORI, {DstReg}, {TmpReg}).addImm(1);
1282 MIB.buildInstr(RISCV::FENCE, {}, {})
1309 MIB.buildInstr(RISCV::FENCE_TSO, {}, {});
1327 MIB.buildInstr(RISCV::FENCE, {}, {}).addImm(Pred).addImm(Succ);