| /llvm-project/mlir/lib/Dialect/GPU/Transforms/ |
| H A D | ParallelLoopMapper.cpp | 36 // Verify that each processor is mapped to only once. in setMappingAttr()
37 llvm::DenseSet<gpu::Processor> specifiedMappings; in setMappingAttr()
39 gpu::Processor processor = dimAttr.getProcessor(); in setMappingAttr() local
40 if (processor != gpu::Processor::Sequential && in setMappingAttr()
41 specifiedMappings.count(processor)) in setMappingAttr()
43 "invalid mapping multiple loops to same processor"); in setMappingAttr()
44 specifiedMappings.insert(processor); in setMappingAttr()
74 static Processor getHardwareIdForMapping(MappingLevel level, int dimension) { in getHardwareIdForMapping()
77 return Processor::Sequential; in getHardwareIdForMapping()
82 return Processor::BlockX; in getHardwareIdForMapping()
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|
| /llvm-project/clang/lib/Basic/ |
| H A D | TargetID.cpp | 40 llvm::StringRef Processor) { in getAllPossibleTargetIDFeatures()
43 return getAllPossibleAMDGPUTargetIDFeatures(T, Processor); in getAllPossibleTargetIDFeatures()
47 /// Returns canonical processor name or empty string if \p Processor is invalid. in getCanonicalProcessorName()
49 llvm::StringRef Processor) { in getCanonicalProcessorName()
51 return llvm::AMDGPU::getCanonicalArchName(T, Processor); in getCanonicalProcessorName()
52 return Processor; in getCanonicalProcessorName()
61 // Parse a target ID with format checking only. Do not check whether processor
62 // name or features are valid for the processor.
64 // A target ID is a processor nam
39 getAllPossibleTargetIDFeatures(const llvm::Triple & T,llvm::StringRef Processor) getAllPossibleTargetIDFeatures() argument
48 getCanonicalProcessorName(const llvm::Triple & T,llvm::StringRef Processor) getCanonicalProcessorName() argument
69 llvm::StringRef Processor; parseTargetIDWithFormatCheckingOnly() local
113 llvm::StringRef Processor = getCanonicalProcessorName(T, *OptionalProcessor); parseTargetID() local
130 getCanonicalTargetID(llvm::StringRef Processor,const llvm::StringMap<bool> & Features) getCanonicalTargetID() argument
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| /llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | ResourceManager.h | 10 /// The classes here represent processor resource units and their management
27 /// Used to notify the internal state of a processor resource.
29 /// A processor resource is available if it is not reserved, and there are
30 /// available slots in the buffer. A processor resource is unavailable if it
31 /// is either reserved, or the associated buffer is full. A processor resource
55 /// Selects a processor resource unit from a ReadyMask.
58 /// Called by the ResourceManager when a processor resource group, or a
59 /// processor resource with multiple units has become unavailable.
65 /// Default resource allocation strategy used by processor resource groups and
66 /// processor resource
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| /llvm-project/mlir/test/Dialect/GPU/ |
| H A D | mapping.mlir | 20 // CHECK: {mapping = [#gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0)…
21 // CHECK-SAME: #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0)…
22 // CHECK: {mapping = [#gpu.loop_dim_map<processor = block_x, map = (d0) -> (d0), bound = (d0) …
23 // CHECK-SAME: #gpu.loop_dim_map<processor = block_y, map = (d0) -> (d0), bound = (d0) …
49 // CHECK: {mapping = [#gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
50 // CHECK-SAME: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
51 // CHECK-SAME: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
52 // CHECK-SAME: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
53 // CHECK: {mapping = [#gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0)…
54 // CHECK-SAME: #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0)…
[all …]
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600Processors.td | 1 //===-- R600Processors.td - R600 Processor definitions --------------------===//
70 def : Processor<"r600", R600_VLIW5_Itin,
74 def : Processor<"r630", R600_VLIW5_Itin,
78 def : Processor<"rs880", R600_VLIW5_Itin,
82 def : Processor<"rv670", R600_VLIW5_Itin,
90 def : Processor<"rv710", R600_VLIW5_Itin,
94 def : Processor<"rv730", R600_VLIW5_Itin,
98 def : Processor<"rv770", R600_VLIW5_Itin,
106 def : Processor<"cedar", R600_VLIW5_Itin,
111 def : Processor<"cypres
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| /llvm-project/clang/include/clang/Basic/ |
| H A D | TargetID.h | 20 /// Get all feature strings that can be used in target ID for \p Processor.
21 /// Target ID is a processor name with optional feature strings
23 /// gfx908:xnack+:sramecc-. Each processor have a limited
27 llvm::StringRef Processor);
29 /// Get processor name from target ID.
30 /// Returns canonical processor name or empty if the processor name is invalid.
34 /// Parse a target ID to get processor and feature map.
35 /// Returns canonicalized processor name or std::nullopt if the target ID is
45 /// Returns canonical target ID, assuming \p Processor is canonical and all
47 std::string getCanonicalTargetID(llvm::StringRef Processor,
|
| /llvm-project/llvm/unittests/TargetParser/ |
| H A D | Host.cpp | 35 processor : 0 in TEST()
36 model name : ARMv7 Processor rev 10 (v7l) in TEST()
45 processor : 1 in TEST()
46 model name : ARMv7 Processor rev 10 (v7l) in TEST()
152 Processor : AArch64 Processor rev 3 (aarch64) in TEST()
153 processor : 0 in TEST()
154 processor : 1 in TEST()
155 processor : 2 in TEST()
156 processor in TEST()
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| /llvm-project/compiler-rt/lib/tsan/rtl/ |
| H A D | tsan_rtl_proc.cpp | 20 Processor *ProcCreate() { in ProcCreate()
21 void *mem = InternalAlloc(sizeof(Processor)); in ProcCreate()
22 internal_memset(mem, 0, sizeof(Processor)); in ProcCreate()
23 Processor *proc = new(mem) Processor; in ProcCreate()
33 void ProcDestroy(Processor *proc) { in ProcDestroy()
41 proc->~Processor(); in ProcDestroy()
45 void ProcWire(Processor *proc, ThreadState *thr) { in ProcWire()
52 void ProcUnwire(Processor *proc, ThreadState *thr) { in ProcUnwire()
|
| /llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | ELF.h | 9 // This header contains common, non-processor-specific data structures and
70 Elf32_Word e_flags; // Processor-specific flags
123 ET_LOPROC = 0xff00, // Beginning of processor-specific codes
124 ET_HIPROC = 0xffff // Processor-specific
169 EM_IA_64 = 50, // Intel IA-64 processor architecture
175 EM_NCPU = 56, // Sony nCPU embedded RISC processor
177 EM_STARCORE = 58, // Motorola Star*Core processor
178 EM_ME16 = 59, // Toyota ME16 processor
179 EM_ST100 = 60, // STMicroelectronics ST100 processor
180 EM_TINYJ = 61, // Advanced Logic Corp. TinyJ embedded processor famil
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenSchedule.h | 113 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
117 /// subtargets. ProcIndices contains 0 for any processor.
120 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
129 /// itinerary class. Each inherits the processor index from the ItinRW record
138 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
148 // InstRWs processor indices. Filled in inferFromInstRWs
185 /// A processor register file.
187 /// This class describes a processor register file. Register file information is
209 // Processor model.
213 // ModelDef is NULL for inferred Models. This happens when a processor define
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| /llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | BottleneckAnalysis.h | 13 /// identify problematic data dependencies and processor resource interferences.
62 /// and edges of the graph represent data dependencies or processor resource
99 // Resource pressure distribution. There is an element for every processor
103 // Each processor resource is associated with a so-called processor resource
104 // mask. This vector allows to correlate processor resource IDs with processor
105 // resource masks. There is exactly one element per each processor resource
109 // Maps processor resource state indices (returned by calls to
110 // `getResourceStateIndex(Mask)` to processor resourc
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| H A D | SummaryView.h | 60 // For each processor resource, this vector stores the cumulative number of
64 // Each processor resource is associated with a so-called processor resource
65 // mask. This vector allows to correlate processor resource IDs with processor
66 // resource masks. There is exactly one element per each processor resource
70 // Used to map resource indices to actual processor resource IDs.
|
| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | Sparc.td | 121 : Processor<Name, NoItineraries, Features, TuneFeatures>;
164 def : Processor<"leon2", LEON2Itineraries,
168 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
169 def : Processor<"at697e", LEON2Itineraries,
173 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
174 def : Processor<"at697f", LEON2Itineraries,
179 def : Processor<"leon3", LEON3Itineraries,
182 // LEON 3 FT (UT699). Provides features for the UT699 processor
184 def : Processor<"ut699", LEON3Itineraries,
187 // LEON3 FT (GR712RC). Provides features for the GR712RC processor
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| /llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSchedule.td | 27 // processor resources and latency with each SchedReadWrite type.
105 // A processor may only implement part of published ISA, due to either new ISA
109 // For a processor which doesn't support some feature(s), the schedule model
132 // Define a kind of processor resource that may be common across
136 // Define a number of interchangeable processor resources. NumUnits
185 // SchedModel ties these units to a processor for any stand-alone defs
195 // Subtargets typically define processor resource kind and number of
249 // SchedModel ties these resources to a processor.
264 // Allow a processor to mark some scheduling classes as unsupported
267 // Allow a processor to mark some scheduling classes as single-issue.
[all …]
|
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMProcessors.td | 2 : Processor<Name, NoItineraries, Features>;
5 // ARM Processor subtarget features.
114 // model, but one of similar/previous processor. These should be fixed.
149 def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
150 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
154 def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m,
156 def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m,
158 def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m,
160 def : Processor<"sc000", ARMV6Itineraries, [ARMv6m,
163 def : Processor<"arm1176j
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| /llvm-project/mlir/lib/Conversion/SCFToGPU/ |
| H A D | SCFToGPU.cpp | 356 static bool isMappedToProcessor(gpu::Processor processor) { in isMappedToProcessor() argument
357 return processor != gpu::Processor::Sequential; in isMappedToProcessor()
360 static unsigned getLaunchOpArgumentNum(gpu::Processor processor) { in getLaunchOpArgumentNum() argument
361 switch (processor) { in getLaunchOpArgumentNum()
362 case gpu::Processor::BlockX: in getLaunchOpArgumentNum()
364 case gpu::Processor::BlockY: in getLaunchOpArgumentNum()
366 case gpu::Processor in getLaunchOpArgumentNum()
405 processParallelLoop(ParallelOp parallelOp,gpu::LaunchOp launchOp,IRMapping & cloningMap,SmallVectorImpl<Operation * > & worklist,DenseMap<gpu::Processor,Value> & bounds,PatternRewriter & rewriter) processParallelLoop() argument
443 gpu::Processor processor = annotation.getProcessor(); processParallelLoop() local
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| /llvm-project/clang/lib/Headers/ |
| H A D | mwaitxintrin.h | 21 /// the processor in the monitor event pending state. Data stored in the
22 /// monitored address range causes the processor to exit the pending state.
41 /// Used with the \c MONITORX instruction to wait while the processor is in
43 /// range, or an interrupt, causes the processor to exit the pending state.
51 /// processor.
53 /// Optional hints for the monitoring state, which can vary by processor.
|
| /llvm-project/llvm/test/tools/llvm-readobj/ELF/ |
| H A D | file-header-machine-types.test | 121 … llvm-readelf --file-headers %t.ncpu.o | FileCheck %s -DMACHINE="Sony nCPU embedded RISC processor"
127 …: llvm-readelf --file-headers %t.starcore.o | FileCheck %s -DMACHINE="Motorola Star*Core processor"
130 # RUN: llvm-readelf --file-headers %t.me16.o | FileCheck %s -DMACHINE="Toyota ME16 processor"
133 …lvm-readelf --file-headers %t.st100.o | FileCheck %s -DMACHINE="STMicroelectronics ST100 processor"
136 … --file-headers %t.tinyj.o | FileCheck %s -DMACHINE="Advanced Logic Corp. TinyJ embedded processor"
142 # RUN: llvm-readelf --file-headers %t.pdsp.o | FileCheck %s -DMACHINE="Sony DSP processor"
181 …f --file-headers %t.cris.o | FileCheck %s -DMACHINE="Axis Communications 32-bit embedded processor"
187 …lvm-readelf --file-headers %t.firepath.o | FileCheck %s -DMACHINE="Element 14 64-bit DSP processor"
190 …N: llvm-readelf --file-headers %t.zsp.o | FileCheck %s -DMACHINE="LSI Logic's 16-bit DSP processor"
193 …elf --file-headers %t.mmix.o | FileCheck %s -DMACHINE="Donald Knuth's educational 64-bit processor"
[all …]
|
| /llvm-project/llvm/include/llvm/MCA/ |
| H A D | Support.h | 73 /// Populates vector Masks with processor resource masks.
75 /// The number of bits set in a mask depends on the processor resource type.
76 /// Each processor resource mask has at least one bit set. For groups, the
79 /// identify processor resources that are part of the group.
87 /// ResourceAB is a processor resource group containing ResourceA and ResourceB.
101 assert(Mask && "Processor Resource Mask cannot be zero!"); in getResourceStateIndex()
105 /// Compute the reciprocal block throughput from a set of processor resource
|
| /llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 59 // Each processor has a SchedClassDesc table with an entry for each
303 // Begin processor name table. in FeatureKeyValues()
308 Records.getAllDerivedDefinitions("Processor");
316 for (const Record *Processor : ProcessorList) { in CPUKeyValues()
317 StringRef Name = Processor->getValueAsString("Name"); in CPUKeyValues()
330 // End processor name table. in CPUKeyValues()
342 // Gather and sort processor information in CPUKeyValues()
344 Records.getAllDerivedDefinitions("Processor"); in CPUKeyValues()
350 // which does the duplicate processor check.
352 // Begin processor tabl
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| /llvm-project/clang-tools-extra/test/clang-tidy/checkers/cert/ |
| H A D | env33-c.c | 10 // It is permissible to check for the presence of a command processor. in f()
14 …// CHECK-MESSAGES: :[[@LINE-1]]:3: warning: calling 'system' uses a command processor [cert-env33-… in f()
17 // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: calling 'popen' uses a command processor in f()
19 // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: calling '_popen' uses a command processor in f()
|
| /llvm-project/llvm/utils/release/ |
| H A D | bump-version.py | 14 class Processor: class
67 class CMakeProcessor(Processor):
104 class GNIProcessor(Processor):
122 class LitProcessor(Processor):
135 class LibCXXProcessor(Processor):
207 for f, processor in files_to_update:
208 processor.process_file(source_root / Path(f), version)
|
| /llvm-project/mlir/include/mlir/Dialect/GPU/IR/ |
| H A D | ParallelLoopMapperAttr.td | 28 def ProcessorEnum : I64EnumAttr<"Processor", "processor for loop mapping", [
35 // processor: the hardware id to map to.
43 EnumParameter<ProcessorEnum>:$processor,
52 "parallel loop to processor mapping attribute">;
|
| /llvm-project/llvm/test/tools/llvm-objcopy/ELF/ |
| H A D | common-symbol.test | 63 #CHECK-NEXT: Section: Processor Specific (0xFF00)
72 #CHECK-NEXT: Section: Processor Specific (0xFF01)
81 #CHECK-NEXT: Section: Processor Specific (0xFF02)
90 #CHECK-NEXT: Section: Processor Specific (0xFF03)
99 #CHECK-NEXT: Section: Processor Specific (0xFF04)
|
| /llvm-project/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 124 errs() << format(" %-*s - Select the %s processor.\n", MaxCPULen, in Help()
162 errs() << "Use -mcpu or -mtune to specify the target's processor.\n" in getFeatures()
197 errs() << "'" << CPU << "' is not a recognized processor for this target" in getFeatures()
198 << " (ignoring processor)\n"; in getFeatures()
210 errs() << "'" << TuneCPU << "' is not a recognized processor for this " in InitMCProcessorInfo()
211 << "target (ignoring processor)\n"; in InitMCProcessorInfo()
332 "Processor machine model table is not sorted"); in getInstrItineraryForCPU()
340 << "' is not a recognized processor for this target" in getEnabledProcessorFeatures()
341 << " (ignoring processor)\n"; in getEnabledProcessorFeatures()
344 assert(CPUEntry->SchedModel && "Missing processor SchedMode in getEnabledProcessorFeatures()
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