Lines Matching full:processor
59 // Each processor has a SchedClassDesc table with an entry for each
303 // Begin processor name table.
308 Records.getAllDerivedDefinitions("Processor");
316 for (const Record *Processor : ProcessorList) {
317 StringRef Name = Processor->getValueAsString("Name");
330 // End processor name table.
342 // Gather and sort processor information
344 Records.getAllDerivedDefinitions("Processor");
350 // which does the duplicate processor check.
352 // Begin processor table.
357 for (const Record *Processor : ProcessorList) {
358 StringRef Name = Processor->getValueAsString("Name");
359 ConstRecVec FeatureList = Processor->getValueAsListOfDefs("Features");
361 Processor->getValueAsListOfDefs("TuneFeatures");
373 SchedModels.getModelForProc(Processor).ModelName;
377 // End processor table.
475 // Multiple processor models may share an itinerary record. Emit it once.
537 // If this processor defines no itineraries, then leave the itinerary list
644 // EmitProcessorData - Generate data for processor itineraries that were
646 // Itineraries for each processor. The Itinerary lists are indexed on
651 // Multiple processor models may share an itinerary record. Emit it once.
654 // For each processor's machine model
665 // Get the itinerary list for the processor.
677 // Begin processor itinerary table
691 // End processor itinerary table
699 // value defined in the C++ header. The Record is null if the processor does not
843 // Now generate a table for the extra processor info.
913 // Find the WriteRes Record that defines processor resources for this
920 // specifies a set of processor resources.
936 "defined for processor " +
944 // Check this processor's list of write resources.
957 "alias on processor " +
963 // TODO: If ProcModel has a base model (previous generation processor),
967 Twine("Processor does not define resources for ") +
973 /// Find the ReadAdvance record for the given SchedRead on this processor or
982 // Check this processor's list of aliases for SchedRead.
995 "defined for processor " +
1003 // Check this processor's ReadAdvanceList.
1017 "processor " +
1023 // TODO: If ProcModel has a base model (previous generation processor),
1027 Twine("Processor does not define resources for ") +
1033 // Expand an explicit list of processor resources into a full list of implied
1051 PrintFatalError(SubDef->getLoc(), "Processor resource group "
1081 // Generate the SchedClass table for this processor and update global
1082 // tables. Must be called for each processor in order.
1117 // Determine if the SchedClass is actually reachable on this processor. If
1118 // not don't try to locate the processor resources, it will fail.
1146 // Check this processor's itinerary class resources.
1440 // Emit a SchedClass table for each processor.
1484 // For each processor model.
1486 // Emit extra processor info if available.
1489 // Emit processor resource table.
1497 // Begin processor itinerary properties
1525 OS << " " << PM.Index << ", // Processor ID\n";
1545 OS << " nullptr // No extra processor descriptor\n";
1580 // Emit the processor machine model
1721 // defined by the processor models of this target.
1740 // Emit a guard on the processor ID.
1749 // Now emit transitions associated with processor PI.
1761 // for a given processor.