xref: /llvm-project/llvm/lib/Target/Sparc/Sparc.td (revision aca971d336d9c7650120fc0fd6dfe58866408216) 
1//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17include "llvm/TableGen/SearchableTable.td"
18
19//===----------------------------------------------------------------------===//
20// SPARC Subtarget features.
21//
22
23def FeatureSoftMulDiv
24  : SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true",
25                     "Use software emulation for integer multiply and divide">;
26
27def FeatureNoFSMULD
28  : SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true",
29                     "Disable the fsmuld instruction.">;
30def FeatureNoFMULS
31  : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true",
32                     "Disable the fmuls instruction.">;
33
34def FeatureV9
35  : SubtargetFeature<"v9", "IsV9", "true",
36                     "Enable SPARC-V9 instructions">;
37def FeatureV8Plus
38  : SubtargetFeature<"v8plus", "IsV8Plus", "true",
39                     "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code">;
40def FeatureV8Deprecated
41  : SubtargetFeature<"deprecated-v8", "UseV8DeprecatedInsts", "true",
42                     "Enable deprecated V8 instructions in V9 mode">;
43def FeatureVIS
44  : SubtargetFeature<"vis", "IsVIS", "true",
45                     "Enable UltraSPARC Visual Instruction Set extensions">;
46def FeatureVIS2
47  : SubtargetFeature<"vis2", "IsVIS2", "true",
48                     "Enable Visual Instruction Set extensions II">;
49def FeatureVIS3
50  : SubtargetFeature<"vis3", "IsVIS3", "true",
51                     "Enable Visual Instruction Set extensions III">;
52def FeatureLeon
53  : SubtargetFeature<"leon", "IsLeon", "true",
54                     "Enable LEON extensions">;
55def FeaturePWRPSR
56  : SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true",
57                     "Enable the PWRPSR instruction">;
58
59def FeatureHardQuad
60  : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
61                     "Enable quad-word floating point instructions">;
62
63def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
64                               "Use the popc (population count) instruction">;
65
66def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
67                              "Use software emulation for floating point">;
68
69//===----------------------------------------------------------------------===//
70// SPARC Subtarget tuning features.
71//
72
73def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true",
74                                    "rd %pc, %XX is slow", [FeatureV9]>;
75
76//==== Features added predmoninantly for LEON subtarget support
77include "LeonFeatures.td"
78
79//==== Register allocation tweaks needed by some low-level software
80foreach i = 1 ... 7  in
81    def FeatureReserveG#i : SubtargetFeature<"reserve-g"#i, "ReserveRegister["#i#" + SP::G0]", "true",
82                                             "Reserve G"#i#", making it unavailable as a GPR">;
83foreach i = 0 ... 5 in
84    def FeatureReserveO#i : SubtargetFeature<"reserve-o"#i, "ReserveRegister["#i#" + SP::O0]", "true",
85                                             "Reserve O"#i#", making it unavailable as a GPR">;
86foreach i = 0 ... 7 in
87    def FeatureReserveL#i : SubtargetFeature<"reserve-l"#i, "ReserveRegister["#i#" + SP::L0]", "true",
88                                             "Reserve L"#i#", making it unavailable as a GPR">;
89foreach i = 0 ... 5 in
90    def FeatureReserveI#i : SubtargetFeature<"reserve-i"#i, "ReserveRegister["#i#" + SP::I0]", "true",
91                                             "Reserve I"#i#", making it unavailable as a GPR">;
92
93//===----------------------------------------------------------------------===//
94// Register File, Calling Conv, Instruction Descriptions
95//===----------------------------------------------------------------------===//
96
97include "SparcASITags.td"
98include "SparcPrefetchTags.td"
99include "SparcRegisterInfo.td"
100include "SparcCallingConv.td"
101include "SparcSchedule.td"
102include "SparcInstrInfo.td"
103
104def SparcInstrInfo : InstrInfo;
105
106def SparcAsmParser : AsmParser {
107  let ShouldEmitMatchRegisterAltName = true;
108  let AllowDuplicateRegisterNames = true;
109}
110
111def SparcAsmParserVariant : AsmParserVariant {
112  let RegisterPrefix = "%";
113}
114
115//===----------------------------------------------------------------------===//
116// SPARC processors supported.
117//===----------------------------------------------------------------------===//
118
119class Proc<string Name, list<SubtargetFeature> Features,
120           list<SubtargetFeature> TuneFeatures = []>
121 : Processor<Name, NoItineraries, Features, TuneFeatures>;
122
123def : Proc<"generic",         []>;
124def : Proc<"v7",              [FeatureSoftMulDiv, FeatureNoFSMULD]>;
125def : Proc<"v8",              []>;
126def : Proc<"supersparc",      []>;
127def : Proc<"sparclite",       []>;
128def : Proc<"f934",            []>;
129def : Proc<"hypersparc",      []>;
130def : Proc<"sparclite86x",    []>;
131def : Proc<"sparclet",        []>;
132def : Proc<"tsc701",          []>;
133def : Proc<"myriad2",         [FeatureLeon, LeonCASA]>;
134def : Proc<"myriad2.1",       [FeatureLeon, LeonCASA]>;
135def : Proc<"myriad2.2",       [FeatureLeon, LeonCASA]>;
136def : Proc<"myriad2.3",       [FeatureLeon, LeonCASA]>;
137def : Proc<"ma2100",          [FeatureLeon, LeonCASA]>;
138def : Proc<"ma2150",          [FeatureLeon, LeonCASA]>;
139def : Proc<"ma2155",          [FeatureLeon, LeonCASA]>;
140def : Proc<"ma2450",          [FeatureLeon, LeonCASA]>;
141def : Proc<"ma2455",          [FeatureLeon, LeonCASA]>;
142def : Proc<"ma2x5x",          [FeatureLeon, LeonCASA]>;
143def : Proc<"ma2080",          [FeatureLeon, LeonCASA]>;
144def : Proc<"ma2085",          [FeatureLeon, LeonCASA]>;
145def : Proc<"ma2480",          [FeatureLeon, LeonCASA]>;
146def : Proc<"ma2485",          [FeatureLeon, LeonCASA]>;
147def : Proc<"ma2x8x",          [FeatureLeon, LeonCASA]>;
148def : Proc<"v9",              [FeatureV9]>;
149def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated, FeatureVIS],
150                              [TuneSlowRDPC]>;
151def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated, FeatureVIS,
152                               FeatureVIS2],
153                              [TuneSlowRDPC]>;
154def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated, FeatureVIS,
155                               FeatureVIS2]>;
156def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
157                               FeatureVIS, FeatureVIS2]>;
158def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
159                               FeatureVIS, FeatureVIS2]>;
160def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
161                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
162
163// LEON 2 FT generic
164def : Processor<"leon2", LEON2Itineraries,
165                [FeatureLeon]>;
166
167// LEON 2 FT (AT697E)
168// TO DO: Place-holder: Processor specific features will be added *very* soon here.
169def : Processor<"at697e", LEON2Itineraries,
170                [FeatureLeon, InsertNOPLoad]>;
171
172// LEON 2 FT (AT697F)
173// TO DO: Place-holder: Processor specific features will be added *very* soon here.
174def : Processor<"at697f", LEON2Itineraries,
175                [FeatureLeon, InsertNOPLoad]>;
176
177
178// LEON 3 FT generic
179def : Processor<"leon3", LEON3Itineraries,
180                [FeatureLeon, UMACSMACSupport]>;
181
182// LEON 3 FT (UT699). Provides features for the UT699 processor
183// - covers all the erratum fixes for LEON3, but does not support the CASA instruction.
184def : Processor<"ut699", LEON3Itineraries,
185                [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>;
186
187// LEON3 FT (GR712RC). Provides features for the GR712RC processor.
188// - covers all the erratum fixed for LEON3 and support for the CASA instruction.
189def : Processor<"gr712rc", LEON3Itineraries,
190                [FeatureLeon, LeonCASA]>;
191
192// LEON 4 FT generic
193def : Processor<"leon4", LEON4Itineraries,
194                [FeatureLeon, UMACSMACSupport, LeonCASA]>;
195
196// LEON 4 FT (GR740)
197// TO DO: Place-holder: Processor specific features will be added *very* soon here.
198def : Processor<"gr740", LEON4Itineraries,
199                [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter,
200                 FeaturePWRPSR]>;
201
202//===----------------------------------------------------------------------===//
203// Declare the target which we are implementing
204//===----------------------------------------------------------------------===//
205
206def SparcAsmWriter : AsmWriter {
207  string AsmWriterClassName  = "InstPrinter";
208  int PassSubtarget = 1;
209  int Variant = 0;
210}
211
212def Sparc : Target {
213  // Pull in Instruction Info:
214  let InstructionSet = SparcInstrInfo;
215  let AssemblyParsers  = [SparcAsmParser];
216  let AssemblyParserVariants = [SparcAsmParserVariant];
217  let AssemblyWriters = [SparcAsmWriter];
218  let AllowRegisterRenaming = 1;
219}
220