Lines Matching full:processor

27 // processor resources and latency with each SchedReadWrite type.
105   // A processor may only implement part of published ISA, due to either new ISA
109   // For a processor which doesn't support some feature(s), the schedule model
132 // Define a kind of processor resource that may be common across
136 // Define a number of interchangeable processor resources. NumUnits
185 // SchedModel ties these units to a processor for any stand-alone defs
195 // Subtargets typically define processor resource kind and number of
249 // SchedModel ties these resources to a processor.
264   // Allow a processor to mark some scheduling classes as unsupported
267   // Allow a processor to mark some scheduling classes as single-issue.
280 // defined by the subtarget, and maps the SchedWrite to processor
285 // them to processor resources in one place. Then ItinRW can map
299 // against the processor's IssueWidth limit. If an instruction can
323 // SchedModel ties these resources to a processor.
327   // Allow a processor to mark some scheduling classes as unsupported
333 // A processor may define a ReadAdvance associated with a SchedRead
436 // SchedModel ties this opcode mapping to a processor.
449 // SchedModel ties this ItineraryClass mapping to a processor.
456 // Alias a target-defined SchedReadWrite to a processor specific
462 // and ties this SchedAlias mapping to a processor.
469 // Allow the definition of processor register files for register renaming
472 // Each processor register file declares:
498 // Otherwise, the processor keeps it (as well as any other different part
575 // Base class for Load/StoreQueue.  It is used to identify processor resources