Lines Matching full:processor

113 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
117 /// subtargets. ProcIndices contains 0 for any processor.
120 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
129 /// itinerary class. Each inherits the processor index from the ItinRW record
138   // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
148   // InstRWs processor indices. Filled in inferFromInstRWs
185 /// A processor register file.
187 /// This class describes a processor register file. Register file information is
209 // Processor model.
213 // ModelDef is NULL for inferred Models. This happens when a processor defines
214 // an itinerary but no machine model. If the processor defines neither a machine
222 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
232   // This list is empty if the Processor has no value for Itineraries.
237   // This list is empty if no ItinRW refers to this Processor.
241   // This list is empty if the Processor has no UnsupportedFeatures.
244   // All read/write resources associated with this processor.
257   // Per-operand machine model resources associated with this processor.
306 /// Each processor can use a (potentially different) InstructionEquivalenceClass
309 /// contributed by a different processor).
322 /// processor model that sees XORrr as a zero-idiom, and that specifies the same
332 /// same for all processor models.
334   llvm::APInt ProcModelMask; // A set of processor model indices.
440   // List of unique processor models.
443   // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
518   // Iterate over the unique processor models.
600   // Initialize a new processor model if it is unique.